Freescale Semiconductor Advance Information Document Number: MPC17533 Rev. 3.0, 7/2006 0.7 A 6.8 V Dual H-Bridge Motor Driver 17533 The 17533 is a monolithic dual H-Bridge power IC ideal for portable electronic applications containing bipolar stepper motors and/or brush DC-motors (e.g., cameras and disk drive head positioners). The 17533 operates from 2.0 V to 6.8 V, with independent control of each H-Bridge via parallel MCU interface (3.0 V- and 5.0 V-compatible logic). The device features built-in shoot-through current protection and an undervoltage shutdown function. The 17533 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The 17533 has a low total RDS(ON) of 1.2 Ω (max @ 25°C). The 17533’s low output resistance and high slew rates provide efficient drive for many types of micromotors. Features • Low Total RDS(ON) 0.8 Ω (Typ), 1.2 Ω (Max) @ 25°C • Output Current 0.7 A (DC), 1.4 A (Peak) • Shoot-Through Current Protection Circuit • 3.0 V/ 5.0 V CMOS-Compatible Inputs • PWM Control Input Frequency up to 200 kHz • Built-In 2-Channel H-Bridge Driver • Low Power Consumption • Undervoltage Detection and Shutdown Circuit • Pb-Free Packaging Designated by Suffix Code EV EV SUFFIX (Pb-FREE) 98ASA10614D 16-PIN VMFP ORDERING INFORMATION Device Temperature Range (TA) Package MPC17533EV/EL -20°C to 65°C 16 VMFP 5.0 V 5.0 V 13 V H-BRIDGE MOTOR DRIVER 17533 VDD VG VM OUT1A OUT1B MCU IN1A IN1B IN2A IN2B OE OUT2A OUT2B N S Bipolar Step Motor GND Figure 1. 17533 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM VG LowVoltage Shutdown VDD VM1 IN1A OUT1A H-Bridge 1 OUT1B IN1B VDD PGND1 OE Control Logic Level Shifter Predriver VM2 IN2A OUT2A H-Bridge 2 OUT2B IN2B PGND2 LGND Figure 2. 17533 Simplified Internal Block Diagram 17533 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS OUT1A 1 16 PGND2 VM1 2 15 OUT2A IN1A 3 14 IN2A IN1B 4 13 IN2B VDD 5 12 VG OE 6 11 VM2 LGND 7 10 OUT2B OUT1B 8 9 PGND1 Figure 3. 17533 Pin Connections Table 1. PIN Function Description Pin Pin Name Formal Name Definition 1 OUT1A H-Bridge Output 1A 2 VM1 Motor Drive Power Supply 1 3 IN1A Logic Input Control 1A Logic input control of OUT1A (refer to Table 5, Truth Table, page 7). 4 IN1B Logic Input Control 1B Logic input control of OUT1B (refer to Table 5, Truth Table, page 7). 5 VDD Logic Supply 6 OE Output Enable Logic output Enable control of H-Bridges (Low = True). 7 LGND Logic Ground Low-current logic signal ground. 8 OUT1B H-Bridge Output 1B Output B of H-Bridge channel 1. 9 PGND1 Power Ground 1 10 OUT2B H-Bridge Output 2B 11 VM2 Motor Drive Power Supply 2 12 VG 13 IN2B Logic Input Control 2B Logic input control of OUT2B (refer to Table 5, Truth Table, page 7). 14 IN2A Logic Input Control 2A Logic input control of OUT2A (refer to Table 5, Truth Table, page 7). 15 OUT2A H-Bridge Output 2A 16 PGND2 Power Ground 2 Output A of H-Bridge channel 1. Positive power source connection for H-Bridge 1 (Motor Drive Power Supply). Control circuit power supply pin. High-current power ground 1. Output B of H-Bridge channel 2. Positive power source connection for H-Bridge 2 (Motor Drive Power Supply). Gate Driver Circuit Voltage Input Input pin for the gate drive voltage. Output A of H-Bridge channel 2. High-current power ground 2. 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit Motor Supply Voltage VM -0.5 to 8.0 V Gate Driver Circuit Power Supply Voltage VG -0.5 to 14 V Logic Supply Voltage VDD -0.5 to 7.0 V Signal Input Voltage VIN -0.5 to VDD + 0.5 V IO 0.7 IOPK 1.4 Human Body Model VESD1 ±1500 Machine Model VESD2 ± 200 Operating Junction Temperature TJ -55 to 150 °C Operating Ambient Temperature TA -20 to 65 °C TSTG -55 to 150 °C RθJA 150 °C/W PD 830 mW TSOLDER 260 °C Driver Output Current A Continuous Peak (1) ESD Voltage (2) V Storage Temperature Range Thermal Resistance Power Dissipation (3) (4) Pin Soldering Temperature (5) Notes 1. TA = 25°C. 10 ms pulse at 200 ms intervals. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 3. 4. Mounted on 37 mm x 50 mm x 1.6 mm glass epoxy board mount. TA = 25°C. 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 17533 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Motor Supply Voltage VM 2.0 5.0 6.8 V Logic Supply Voltage VDD 2.7 5.0 5.7 V – – 1.0 – – 20 – – 150 – – 3.0 VG – – 0.7 VDD DET 1.5 2.0 2.5 RDS(ON) – 0.8 1.2 RDS(ON)2 – – 1.5 VG 12 13 13.5 V VIN 0 – VDD V High-Level Input Voltage VIH VDD x 0.7 – – V Low-Level Input Voltage VIL – – VDD x 0.3 V High-Level Input Current IIH – – 1.0 µA IIL -1.0 – – µA IIL-OE – 50 100 µA POWER µA Quiescent Power Supply Current IQ Driver Circuit Power Supply Current I Logic Supply Current (6) Gate Driver Circuit Power Supply Current Operating Power Supply Current Logic Supply Current (7) Gate Driver Circuit Power Supply Current (8) Low VDD Detection Voltage (9) M QVDD I QVG IV I mA DD Ω Driver Output ON Resistance Source + Sink at IO = 0.7 A(10) VG = 9.5 V, VM = 5.0 V, TA = 25°C(11) V GATE DRIVE Gate Drive Circuit Power Supply Voltage CONTROL LOGIC Logic Input Voltage Logic Inputs (2.7 V < VDD < 5.7 V) Low-Level Input Current OE Pin Input Current Low Notes 6. IQVDD includes the current to predriver circuit. 7. IV 8. At fIN = 20 kHz. 9. Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When gate voltage VG is applied from an external source, VG = 7.5 V. 10. 11. DD includes the current to predriver circuit at fIN = 100 kHz. The total H-Bridge ON resistance when VG is 13V. Increased RDS(ON) value as the result of a reduced VG value of 9.5 V. 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Characteristic Symbol Min Typ Max Unit f IN – – 200 kHz tR – – 1.0 µs tF – INPUT Pulse Input Frequency Input Pulse Rise Time (12) Input Pulse Fall Time (14) (13) – 1.0 (13) µs OUTPUT Propagation Delay Time (15) µs t PLH t PHL Turn-ON Time Turn-OFF Time Low-Voltage Detection Notes 12. 13. 14. 15. 16. Time(16) tV DD DET – 0.1 0.5 – 0.1 0.5 – – 10 ms Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. Load of Output is 8.0 Ω resistance. see figure 4 See figure 5. 17533 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS VDDDETon IN1, IN2, OE 50% 2.5 V VDDDEToff VDD 50% 1.5 V tPLH tPHL t VDDDET 90% 90% OUTA, OUTB t VDDDET 0% (<1.0 µA) IM 10% Figure 4. tPLH, tPHL, and tPZH Timing Figure 5. Low-Voltage Detection Timing Diagram Table 5. Truth Table INPUT OUTPUT OE IN1A IN2A IN1B IN2B OUT1A OUT2A OUT1B OUT2B L L L L L L H L H L L L H L H L H H Z Z H X X Z Z H = High. L = Low. Z = High impedance. X = Don’t care. OE pin is pulled up to VDD with internal resistance. 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 7 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 17533 is a monolithic dual H-Bridge ideal for portable electronic applications to control bipolar stepper motors and brush DC motors such as those found in camera len assemblies, camera shutters, optical disk drives, etc. The 17533 operates from 2.0 V to 6.8 V, with independent control of each H-Bridge via parallel MCU interface (3.0 Vand 5.0 V-compatible I/O). The device features built-in shootthrough current protection and undervoltage shutdown. The 17533 has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). The MOSFETs comprising the output bridge have a total source + sink RDS(ON) ≤ 1.2 Ω. The 17533 can simultaneously drive two brush DC motors or, as shown in the simplified application diagram on page 1, one bipolar stepper motor. The drivers are designed to be PWM’ed at frequencies up to 200 kHz. FUNCTIONAL PIN DESCRIPTION LOGIC SUPPLY (VDD) The VDD pin carries the logic supply voltage and current into the logic sections of the IC. VDD has an undervoltage threshold. If the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input control pins. LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND IN2B) These logic input pins control each H-Bridge output (e.g., IN1A logic HIGH = OUT1A HIGH, etc.). However, if all inputs are taken HIGH, the outputs bridges are both tri-stated (refer to Table 5, Truth Table, page 7). OUTPUT ENABLE (OE) The OE pin is a LOW = TRUE enable input. When OE = HIGH, all H-Bridge outputs (OUT1A, OUT1B, OUT2A, and OUT2B) are tri-stated (high-impedance), regardless of logic inputs (IN1A, IN1B, IN2A, and IN2B) states. OUTPUT A AND B OF H-BRIDGE CHANNEL 1 AND 2 (OUT1A, OUT1B, OUT2A, AND OUT2B) These pins provide connection to the outputs of each of the internal H-Bridges (see Figure 2, 17533 Simplified Internal Block Diagram, page 2). MOTOR DRIVE POWER SUPPLY (VM1 AND VM2) The VM pins carry the main supply voltage and current into the power sections of the IC. This supply then becomes controlled and/or modulated by the IC as it delivers the power to the loads attached between the output pins. All VM pins must be connected together on the printed circuit board. GATE DRIVER CIRCUIT VOLTAGE INPUT (VG) The VG pin is the input pin for the gate drive voltage. POWER GROUND (PGND) Power ground pins. They must be tied together on the PCB. LOGIC GROUND (LGND) Logic ground pin. 17533 8 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS INTRODUCTION TYPICAL APPLICATIONS INTRODUCTION Figure 6 shows a typical application for the 17533. When applying the gate voltage to the VG pin from an external source, be sure to connect it via a resistor equal to, or greater than, RG = VG / 0.02 Ω. Care must be taken to provide sufficient gate-source voltage for the high-side MOSFETs when VM >> VDD (e.g., VM = 5.0 V, VDD = 3.0 V), in order to ensure full enhancement of the high-side MOSFET channels. 5.0 V 17533 VDD VG < 14 V VM OUT1A RG > VG /0.02 Ω VG RG 0.01 µF OUT1B IN1A IN1B IN2A IN2B MCU OE OUT2A OUT2B GND Figure 6. 17533 Typical Application Diagram CEMF SNUBBING TECHNIQUES PCB LAYOUT Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commuting currents in inductive loads. Typical practice is to provide snubbing of voltage transients by placing a zener or a capacitor at the supply pin (VM) (see Figure 7). When designing the printed circuit board (PCB), connect sufficient capacitance between power supply and ground pins to ensure proper filtering from transients. For all highcurrent paths, use wide copper traces and shortest possible distances. 5.0 V 5.0 V 17533 VDD VM 5.0 V 5.0 V 17533 VDD VM OUT OUT OUT OUT OUT OUT OUT GND OUT GND Figure 7. CEMF Snubbing Techniques 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 9 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A number listed below. EV (Pb-FREE) SUFFIX 16-LEAD VMFP PLASTIC PACKAGE 98ASA10614D ISSUE B 17533 10 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY REVISION DATE 2.0 5/2006 3.0 7/2006 DESCRIPTION OF CHANGES • • • • • Converted to Freescale format Added Revision History page Updated to the prevailing form and style Corrected device isometric drawing on page 1 Added RoHS compliance 17533 Analog Integrated Circuit Device Data Freescale Semiconductor 11 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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