FREESCALE MC68HC05J3

MC68HC05J3/D
MC68HC05J3
TECHNICAL DATA
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MC68HC05J3
TECHNICAL
DATA
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INTRODUCTION
1
MODES OF OPERATION AND PIN DESCRIPTIONS
2
MEMORY AND REGISTERS
3
INPUT/OUTPUT PORTS
4
CORE TIMER
5
16-BIT PROGRAMMABLE TIMER
6
RESETS AND INTERRUPTS
7
CPU CORE AND INSTRUCTION SET
8
ELECTRICAL SPECIFICATIONS
9
MECHANICAL DATA
10
ORDERING INFORMATION
11
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1
INTRODUCTION
2
MODES OF OPERATION AND PIN DESCRIPTIONS
3
MEMORY AND REGISTERS
4
INPUT/OUTPUT PORTS
5
CORE TIMER
6
16-BIT PROGRAMMABLE TIMER
7
RESETS AND INTERRUPTS
8
CPU CORE AND INSTRUCTION SET
9
ELECTRICAL SPECIFICATIONS
10
MECHANICAL DATA
11
ORDERING INFORMATION
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MC68HC05J3
High-density Complementary
Metal Oxide Semiconductor
(HCMOS) Microcomputer Unit
2
3
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5
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All Trade Marks recognized. This document contains information on new products. Specifications and information herein are
subject to change without notice.
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All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the
Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part
of a contract (with the exception of the contents of this Notice). A copy of Motorola’s Terms & Conditions of Supply is available
on request.
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All
operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed,
intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office.
This document supersedes any earlier documentation relating to the products referred to herein. The information contained
in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.
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© MOTOROLA LTD., 1996
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TABLE OF CONTENTS
Paragraph
Number
TITLE
Page
Number
1
INTRODUCTION
1.1
1.2
Features.................................................................................................................1-1
MC68HC05J3 mask options ..................................................................................1-2
2
MODES OF OPERATION AND
PIN DESCRIPTIONS
2.1
Modes of operation ................................................................................................2-1
2.1.1
Single chip mode .............................................................................................2-1
2.1.2
RAM bootloader mode .....................................................................................2-2
2.2
Pin descriptions .....................................................................................................2-3
2.2.1
VDD and VSS ..................................................................................................2-3
2.2.2
IRQ ..................................................................................................................2-4
2.2.3
OSC1, OSC2 ...................................................................................................2-4
2.2.3.1
Crystal ........................................................................................................2-4
2.2.3.2
Ceramic resonator......................................................................................2-4
2.2.3.3
RC network.................................................................................................2-4
2.2.3.4
External clock .............................................................................................2-6
2.2.4
RESET.............................................................................................................2-6
2.2.5
PA0–PA7 ..........................................................................................................2-6
2.2.6
PB0–PB5 .........................................................................................................2-6
2.3
Low power modes..................................................................................................2-7
2.3.1
STOP ...............................................................................................................2-7
2.3.2
WAIT ................................................................................................................2-7
3
MEMORY AND REGISTERS
3.1
3.2
3.3
Registers ...............................................................................................................3-1
RAM.......................................................................................................................3-1
Non-volatile memory (NVM) ..................................................................................3-1
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Paragraph
Number
TITLE
Page
Number
4
INPUT/OUTPUT PORTS
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.5
Input/output programming .....................................................................................4-1
Port A.....................................................................................................................4-2
Port B.....................................................................................................................4-2
Port registers .........................................................................................................4-4
Port A data register (PORTA)...........................................................................4-4
Port B data register (PORTB) ..........................................................................4-4
Port B configuration register (CONFB) ............................................................4-4
Data direction register A (DDRA).....................................................................4-5
Data direction register B (DDRB).....................................................................4-5
Other port considerations ......................................................................................4-6
5
CORE TIMER
5.1
5.2
5.3
5.3.1
5.3.2
5.4
5.5
Real time interrupts (RTI) ......................................................................................5-2
Computer operating properly (COP) watchdog timer ............................................5-2
Core timer registers ...............................................................................................5-3
Core timer control and status register (CTCSR)..............................................5-3
Core timer counter register (CTCR).................................................................5-4
Core timer during WAIT .........................................................................................5-5
Core timer during STOP ........................................................................................5-5
6
16-BIT PROGRAMMABLE TIMER
6.1
Counter..................................................................................................................6-3
6.1.1
Counter high register
Counter low register
Alternate counter high register
Alternate counter low register ..........................................................................6-3
6.2
Timer functions ......................................................................................................6-4
6.2.1
Timer control register – TCR............................................................................6-4
6.2.2
Timer status register – TSR .............................................................................6-5
6.2.3
Input capture function ......................................................................................6-6
6.2.4
Input capture high register
Input capture low register ................................................................................6-6
6.2.5
Output compare function .................................................................................6-7
6.2.6
Output compare high register
Output compare low register............................................................................6-7
6.3
Timer during WAIT mode.......................................................................................6-8
6.4
Timer during STOP mode......................................................................................6-8
6.5
Timer state diagrams.............................................................................................6-9
TPG
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Paragraph
Number
TITLE
Page
Number
7
RESETS AND INTERRUPTS
7.1
7.1.1
7.1.2
7.1.3
7.2
7.3
7.3.1
7.4
7.5
7.5.1
7.5.2
7.5.3
7.6
Resets ...................................................................................................................7-1
Power-on reset .................................................................................................7-2
RESET pin .......................................................................................................7-2
Computer operating properly (COP) reset .......................................................7-2
Functions affected by reset....................................................................................7-3
Interrupts ...............................................................................................................7-3
Interrupt priorities .............................................................................................7-4
Non-maskable software interrupt (SWI).................................................................7-6
Maskable hardware interrupts ...............................................................................7-6
External interrupt (IRQ or keyboard)................................................................7-6
Core timer interrupts ........................................................................................7-6
16-bit timer interrupts .......................................................................................7-7
Hardware controlled interrupt sequence................................................................7-7
8
CPU CORE AND INSTRUCTION SET
8.1
Registers ...............................................................................................................8-1
8.1.1
Accumulator (A) ...............................................................................................8-2
8.1.2
Index register (X)..............................................................................................8-2
8.1.3
Program counter (PC) ......................................................................................8-2
8.1.4
Stack pointer (SP) ............................................................................................8-2
8.1.5
Condition code register (CCR).........................................................................8-2
8.2
Instruction set ........................................................................................................8-3
8.2.1
Register/memory Instructions ..........................................................................8-4
8.2.2
Branch instructions ..........................................................................................8-4
8.2.3
Bit manipulation instructions ............................................................................8-4
8.2.4
Read/modify/write instructions .........................................................................8-4
8.2.5
Control instructions ..........................................................................................8-4
8.2.6
Tables...............................................................................................................8-4
8.3
Addressing modes .................................................................................................8-11
8.3.1
Inherent............................................................................................................8-11
8.3.2
Immediate ........................................................................................................8-11
8.3.3
Direct................................................................................................................8-11
8.3.4
Extended..........................................................................................................8-12
8.3.5
Indexed, no offset.............................................................................................8-12
8.3.6
Indexed, 8-bit offset..........................................................................................8-12
8.3.7
Indexed, 16-bit offset........................................................................................8-12
8.3.8
Relative ............................................................................................................8-13
8.3.9
Bit set/clear ......................................................................................................8-13
8.3.10
Bit test and branch ...........................................................................................8-13
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Paragraph
Number
TITLE
Page
Number
9
ELECTRICAL SPECIFICATIONS
9.1
9.2
9.3
9.4
Maximum ratings ...................................................................................................9-1
Thermal characteristics and power considerations ...............................................9-2
DC electrical characteristics ..................................................................................9-3
AC electrical characteristics ..................................................................................9-5
10
MECHANICAL DATA
11
ORDERING INFORMATION
11.1
11.2
11.3
EPROMS .............................................................................................................11-1
Verification media ................................................................................................11-2
ROM verification units (RVU)...............................................................................11-2
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LIST OF FIGURES
Figure
Number
1-1
2-1
2-2
2-3
2-4
3-1
4-1
4-2
4-3
5-1
6-1
6-2
6-3
6-4
6-5
7-1
7-2
8-1
8-2
9-1
9-2
10-1
10-2
10-3
10-4
TITLE
Page
Number
MC68HC05J3 block diagram..................................................................................1-2
RAM bootloader circuit ...........................................................................................2-2
20-pin SOIC/DIP single chip and bootloader mode pin assignments.....................2-3
Oscillator connections ............................................................................................2-5
STOP and WAIT flowcharts ....................................................................................2-8
Memory map of the MC68HC05J3.........................................................................3-2
Standard I/O port structure.....................................................................................4-2
Port B keyboard interrupt function ..........................................................................4-3
Port logic levels.......................................................................................................4-6
Core timer block diagram........................................................................................5-1
16-bit programmable timer block diagram ..............................................................6-2
Timer state timing diagram for reset .......................................................................6-9
Timer state timing diagram for input capture ..........................................................6-9
Timer state timing diagram for output compare ......................................................6-10
Timer state timing diagram for timer overflow.........................................................6-10
Reset timing diagram..............................................................................................7-1
Interrupt flow chart..................................................................................................7-5
Programming model ...............................................................................................8-1
Stacking order ........................................................................................................8-1
Equivalent test load ................................................................................................9-2
External interrupt timing .........................................................................................9-6
20-pin SOIC pinout ...............................................................................................10-1
20-pin PDIP pinout ...............................................................................................10-1
20-pin SOIC mechanical dimensions ...................................................................10-2
20-pin PDIP mechanical dimensions....................................................................10-3
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LIST OF TABLES
Table
Number
2-1
2-2
3-1
4-1
5-1
7-1
7-2
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
9-1
9-2
9-3
9-4
9-5
9-6
11-1
TITLE
Page
Number
MC68HC05J3 operating mode entry conditions.....................................................2-1
RAM bootloader mode jump vectors ......................................................................2-3
Register outline.......................................................................................................3-3
I/O pin states ..........................................................................................................4-2
Example RTI periods ..............................................................................................5-4
Effect of RESET, POR, STOP and WAIT................................................................7-3
Interrupt priorities ...................................................................................................7-4
MUL instruction.......................................................................................................8-5
Register/memory instructions.................................................................................8-5
Branch instructions .................................................................................................8-6
Bit manipulation instructions...................................................................................8-6
Read/modify/write instructions ...............................................................................8-7
Control instructions.................................................................................................8-7
Instruction set (1 of 2).............................................................................................8-8
Instruction set (2 of 2).............................................................................................8-9
M68HC05 opcode map...........................................................................................8-10
Maximum ratings ....................................................................................................9-1
Package thermal characteristics.............................................................................9-2
DC electrical characteristics for 5V operation.........................................................9-3
DC electrical characteristics for 3.3V operation......................................................9-4
AC electrical characteristics for 5V operation .........................................................9-5
AC electrical characteristics for 3.3V operation ......................................................9-6
MC order numbers................................................................................................11-1
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1
INTRODUCTION
The MC68HC05J3, with 2kbytes of ROM is a member of the Motorola M68HC05 family of
HCMOS 8-bit single chip microcomputers. Based on the industry-standard M68HC05 CPU core
and its familiar, efficient instruction set, this device provides a cost effective, low pin-count
microcomputer solution suitable for use in a wide variety of application areas, including car body
electronics. The keyboard interrupt function, which shares 4 I/O lines of port B, provides a simple
interface to keypads, switches and other similar input media. In addition, the port pins are capable
of sinking a current of 8mA at 0.8V and can therefore be used to drive certain LED’s.
1.1
Features
•
Fully static design featuring the industry standard M68HC05 core
•
On-chip oscillator with crystal, resistor, external clock or ceramic resonator connection
•
2048 bytes of User ROM
•
128 bytes of RAM
•
Power saving STOP and WAIT modes
•
16-bit programmable timer with input capture and output compare functions
•
8-bit multi-purpose timer
•
Real time interrupt circuit
•
Computer operating properly watchdog timer (mask option)
•
Interrupt request input (IRQ), plus four on-chip hardware interrupt sources
•
Keyboard interrupt feature on four port B input/output lines
•
One 8-bit and one 6-bit parallel I/O port (two lines on port B are shared with the 16-bit timer)
•
All port pins are capable of sinking a current of 8mA at 0.8V
•
Available in 20-pin plastic SOIC and 20-pin plastic DIL packages
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128 bytes
RAM
240 bytes
self-check ROM
Keyboard
Interrupt
RESET
8-bit timer and COP
watchdog system
16-bit timer
KI0
KI1
KI2
K!3
TCMP
TCAP
Port B
2048 bytes
User ROM
(plus 16 bytes user vectors)
Port A
1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
IRQ
OSC2
OSC1
Oscillator and divide by 2
M68HC05
CPU
VDD
VSS
Figure 1-1 MC68HC05J3 block diagram
1.2
MC68HC05J3 mask options
There are four mask options on the MC68HC05J3 which are programmed during manufacture and
therefore must be specified on the order form: IRQ sensitivity (edge sensitive or edge-and-level
sensitive), COP watchdog enable/disable, STOP instruction enable/disable and RC or crystal
clock selection.
TPG
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2
MODES OF OPERATION AND
PIN DESCRIPTIONS
2.1
Modes of operation
The MC68HC05J3 has two modes of operation, single chip and RAM bootloader mode. Table 2-1
shows the conditions required to enter each mode on the rising edge of RESET.
Table 2-1 MC68HC05J3 operating mode entry conditions
IRQ
TCAP PA3
VSS to VDD x
x Single chip
1
0
1.8VDD
RAM bootloader
1
1
x = don’t care
RESET
2.1.1
Mode
Jump to RAM ($0081)
Load RAM & execute ($0081)
Single chip mode
This is the normal operating mode of the MC68HC05J3. In this mode the device functions as a
self-contained microcomputer (MCU) with all on-board peripherals, including the 8-bit I/O port (A)
and the 6-bit I/O port (B), available to the user. All address and data activity occurs within the MCU.
Single chip mode is entered on the rising edge of RESET if the voltage level on the IRQ pin is
within the normal operating range.
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2.1.2
2
RAM bootloader mode
The RAM bootloader mode for the MC68HC05J3 allows the user to run a program in RAM. To
make use of this feature a circuit board should be constructed as shown in Figure 2-1. It is then
possible, by correctly configuring TCAP and PA3, to load a user program into RAM and then to
execute it.
1.8 VDD
4.7KΩ
IRQ
10MΩ
OSC1
PA0
RXD
VDD
4.0MHz
OSC2
20pF
20pF
VDD
TCAP
VDD
PA3
100KΩ
RESET
100nF
VSS
MC68HC05J3
PA3
Function
0 Jump to RAM ($0081)
1 Load RAM & execute ($0081)
All resistors are 10 kΩ unless otherwise specified
Figure 2-1 RAM bootloader circuit
The RAM bootloader is selected when the device is put into bootloader mode with TCAP held high.
If PA3 is low, the program counter is set to $0081 and a previously loaded RAM program can be
executed. If PA3 is high at reset a program is serially loaded from PA0 into the RAM and executed
from $0081, once the last byte has been received.
The first byte to be loaded is the count byte which must contain the total number of bytes to be
transferred, including the count byte itself. Therefore, for a program length of $30, the count should
equal $31. The maximum program size including the count byte is 124 bytes ($7C), since four
bytes must be left for the stack during download.
TPG
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MODES OF OPERATION AND PIN DESCRIPTIONS
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Providing the oscillator is running at 4MHz, the serial data format is 9600 baud, low start bit, 8
data bits, high stop bit. The data is in hexadecimal form, not ASCII.
In the RAM bootloader mode all interrupt vectors are mapped to pseudo-vectors in RAM (refer to
Table 2-2). This allows programmers to use their own service-routine addresses. Each
pseudo-vector is allowed three bytes of space, rather than the two bytes for normal vectors,
because an explicit jump (JMP) opcode is needed to cause the desired jump to the user’s
service-routine address.
2
Table 2-2 RAM bootloader mode jump vectors
Address
Pseudo-vector
0084 Software interrupt
0087 IRQ interrupt
008A Core timer interrupt
008D Input capture
0090 Output compare interrupt
0093 Timer overflow interrupt
2.2
Pin descriptions
OSC1
OSC2
TCAP/PB5
TCMP/PB4
PB3
PB2
PB1
PB0
VDD
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
IRQ
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Figure 2-2 20-pin SOIC/DIP single chip and bootloader mode pin assignments
2.2.1
VDD and VSS
Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS
is ground.
It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These
short rise and fall times place very high short-duration current demands on the power supply. To
prevent noise problems, special care must be taken to provide good power supply bypassing at
the MCU. Bypass capacitors should have good high-frequency characteristics and be as close to
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the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are
loaded.
2.2.2
IRQ
This is an input-only pin for external interrupt sources. Interrupt triggering can be selected to be edge
sensitive or edge-and-level sensitive (see Section 1.2). The IRQ pin contains an internal Schmitt
trigger as part of its input to improve noise immunity.
2.2.3
OSC1, OSC2
These pins provide control input for an on-chip oscillator circuit. A crystal, ceramic resonator,
resistor or external clock signal connected to these pins supplies the oscillator clock. The oscillator
frequency (fOSC) is divided by two to give the internal bus frequency (fOP).
2.2.3.1
Crystal
The circuit shown in Figure 2-3(a) is recommended when using either a crystal or a ceramic
resonator. Figure 2-3(e) provides the recommended capacitance and feedback resistance values.
The internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal
resonator in the frequency range specified for fosc (see Table 9-5 and Table 9-6). Use of an
external CMOS oscillator is recommended when crystals outside the specified ranges are to be
used. The crystal and associated components should be mounted as close as possible to the input
pins to minimise output distortion and start-up stabilization time. The manufacturer of the
particular crystal being considered should be consulted for specific information.
2.2.3.2
Ceramic resonator
A ceramic resonator may be used instead of a crystal in cost sensitive applications. The circuit
shown in Figure 2-3(a) is recommended when using either a crystal or a ceramic resonator.
Figure 2-3(e) lists the recommended capacitance and feedback resistance values. The
manufacturer of the particular ceramic resonator being considered should be consulted for
specific information.
2.2.3.3
RC network
With this option, a resistor is connected to the oscillator pins as shown in Figure 2-3(c). The overall
accuracy of the RC oscillator is approximately ±25% (contact factory for more accurate details).
TPG
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MODES OF OPERATION AND PIN DESCRIPTIONS
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MCU
OSC1
L
OSC2
C1
2
RS
OSC1
OSC2
RP
C0
COSC1
COSC2
(b) Crystal equivalent circuit
(a) Crystal/ceramic resonator
oscillator connections
MCU
MCU
OSC1
OSC1
OSC2
OSC2
R
(c) RC oscillator connections
RS(max)
C0
C1
COSC1
COSC2
RP
Q
Crystal
2MHz 4MHz
400
75
5
7
8
12
15 – 40 15 – 30
15 – 30 15 – 25
10
10
30 000 40 000
OSC1
OSC2
External
clock
NC
(d) External clock source connections
Unit
Ω
pF
ƒF
pF
pF
MΩ
—
Ceramic resonator
2 – 4MHz
Unit
RS(typ)
10
Ω
C0
40
pF
C1
4.3
pF
COSC1
30
pF
COSC2
30
pF
1 – 10
MΩ
RP
Q
1250
—
(e) Crystal and ceramic resonator parameters
Figure 2-3 Oscillator connections
TPG
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2.2.3.4
2
External clock
An external clock should be applied to the OSC1 input, with the OSC2 pin left unconnected, as
shown in Figure 2-3(d). The tOXOV specification (see Table 9-5 and Table 9-6) does not apply
when using an external clock input. The equivalent specification of the external clock source
should be used in lieu of tOXOV.
2.2.4
RESET
This active low input-only pin is used to reset the MCU. Applying a logic zero to this pin forces the
device to a known start-up state. An external RC-circuit can be connected to this pin to generate
a power-on-reset (POR) if required. In this case, the time constant must be great enough to allow
the oscillator circuit to stabilise. This input has an internal Schmitt trigger to improve noise
immunity.
2.2.5
PA0–PA7
These 8 I/O lines comprise ports A. The state of any pin is software programmable, and all the
pins are configured as inputs during power-on or reset.
2.2.6
PB0–PB5
These six pins comprise port B. The state of any pin is software programmable, and all the pins
are configured as inputs during power-on or reset. In addition to their normal I/O functions, pins
PB0–PB3 can be used to generate a keyboard interrupt when configured as an input while PB4
is shared with the output compare function (TCMP) of the programmable timer and PB5 with the
input capture function (TCAP) (see Section 4.3). PB0–PB5 contain an internal Schmitt trigger as
part of their input to improve noise immunity.
TPG
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2.3
Low power modes
2
2.3.1
STOP
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off, halting all internal processing, including timer (and COP watchdog
timer) operation.
During STOP mode, the core timer interrupt flags (CTOF and RTIF) and interrupt enable bits
(CTOFE and RTIE) in the CTCSR, the timer flags for the 16-bit timer in the TSR register and the
interrupt enable bits in the TCR register are cleared by internal hardware. This removes any
pending timer interrupt requests and disables any further timer interrupts. The timer prescaler is
cleared. The I-bit in the CCR is cleared to enable external interrupts. All other registers, the
remaining bits in the CTCSR, and memory contents remain unaltered. All input/output lines
remain unchanged. The processor can be brought out of STOP mode only by an external interrupt,
a keyboard interrupt, if enabled, or a reset (see Figure 2-4).
2.3.2
WAIT
The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode
consumes more power than STOP mode. All CPU action is suspended, but the 16-bit timer and
the core timer remain active. An external or keyboard interrupt or an interrupt from either of the
timers, if enabled, will cause the MCU to exit WAIT mode.
During WAIT mode, the I-bit in the CCR is cleared to enable interrupts. All other registers, memory
and input/output lines remain in their previous state. The 16-bit timer or the core timer interrupts
may be enabled to allow a periodic exit from WAIT mode. See Figure 2-4.
TPG
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2
STOP
WAIT
Stop oscillator
and all clocks;
clear I-mask
Oscillator active;
stop processing;
clear I-mask
Reset
?
Reset
?
No
No
Yes
No
Yes
Any
external, keyboard,
16-bit or core timer
interrupt
?
Any
external or
keyboard interrupt
?
Yes
No
Yes
Turn on oscillator;
wait tPORL for
stabilization
Restart
processor
clocks
Fetch
interrupt or reset
vector
Fetch
interrupt or reset
vector
Figure 2-4 STOP and WAIT flowcharts
TPG
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3
3
MEMORY AND REGISTERS
The MC68HC05J3 has a 4 kbyte memory map consisting of registers (for I/O, control and status),
User RAM, User ROM, bootloader ROM and reset and interrupt vectors as shown in Figure 3-1.
3.1
Registers
All the I/O, control and status registers of the MC68HC05J3 are contained within the first 32-byte
block of the memory map, as detailed in Table 3-1.
3.2
RAM
The User RAM consists of 128 bytes of memory, from $0080 to $00FF. This is shared with a
64-byte stack area. The stack begins at $00FF and may extend down to $00C0.
Note:
Using the stack area for data storage or temporary work locations requires care to prevent
the data from being overwritten due to stacking from an interrupt or subroutine call.
3.3
Non-volatile memory (NVM)
The NVM consists of 2048 bytes of ROM (MC68HC05J3) from $0700 to $0EFF, 240 bytes of
bootloader ROM and 16 bytes of user vectors ($0FF0 to $0FFF).
TPG
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MC68HC05J3
Registers
$0000
Port A data (PORTA)
Port B data (PORTB)
I/O
(32 bytes)
3
$0020
Port A data direction (DDRA)
Port B data direction (DDRB)
Port B configuration (CONFB)
Core timer control & status (CTCSR)
Core timer counter (CTCR)
$0080
$00C0
$00FF
$0100
RAM
(128 bytes)
Stack
$06FF
$0700
User ROM
(2048 bytes)
Timer control (TCR)
Timer status (TSR)
Input capture high (ICH)
Input capture low (ICL)
Output compare high (OCH)
Output compare low (OCL)
Timer counter high (TCH)
Timer counter low (TCL)
Alternate counter high (TCH)
Alternate counter low (TCL)
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$0F00
$0F01
Bootloader
ROM
$0FEF
$0FF0
Reserved
User vectors
(16 bytes)
$0FFF
Figure 3-1 Memory map of the MC68HC05J3
TPG
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Table 3-1 Register outline
Register Name
Address bit 7
Port A data (PORTA)
Port B data (PORTB)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$0000
$0001
State on
Reset
Undefined
0
0
Undefined
$0002
Reserved
3
$0003
Port A data direction (DDRA)
$0004
Port B data direction (DDRB)
$0005
Reserved
$0006
0000 0000
0
Port B configuration (CONFB)
$0007
KSF
Core timer control/status (CTCSR)
$0008
CTOF
Core timer counter (CTCR)
0
KIE
0000 0000
TCAP TCMP
0
0
0
0
0000 0000
RTIF CTOFE RTIE
0
0
RT1
RT0
uu00 0011
$0009
Undefined
$000A
$000B
$000C
$000D
Reserved
$000E
$000F
$0010
$0011
Timer control (TCR)
$0012
ICIE
OCIE
TOIE
0
0
0
IEDG
OCF
TOF
0
0
0
0
OLV
0000 00u0
0
uuu0 0000
Timer status (TSR)
$0013
ICF
Input capture high (ICH)
$0014
(bit 15)
(bit 8) Undefined
(bit 15)
(bit 8) Undefined
(bit 15)
(bit 8) 1111 1111
Alternate counter high (ACH)
$001A (bit 15)
(bit 8) 1111 1111
Alternate counter low (ACL)
$001B
Reserved
$001C
to
$0EFF
Reserved
$0F00
Input capture low (ICL)
$0015
Output compare high (OCH)
$0016
Output compare low (OCL)
$0017
Timer counter high (TCH)
$0018
Timer counter low (TCL)
Undefined
Undefined
$0019
1111 1100
1111 1100
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4
INPUT/OUTPUT PORTS
4
In single chip mode, the MC68HC05J3 has a total of 14 I/O lines, arranged as one 8-bit port (A)
and one 6-bit port (B). Each I/O line is individually programmable as either input or output, under
the software control of the data direction registers. Four of the port B pins can be configured to
respond to keyboard interrupts, while the other two are shared with the timer subsystem. The port
B configuration register provides the control for all pins of port B.
To avoid glitches on the output pins, data should be written to the I/O port data register before
writing ones to the corresponding data direction register bits to set the pins to output mode.
4.1
Input/output programming
The bidirectional port lines may be programmed as inputs or outputs under software control. The
direction of each pin is determined by the state of the corresponding bit in the port data direction
register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if
its corresponding DDR bit is set. A pin is configured as an input if its corresponding DDR bit is
cleared.
At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. The data
direction registers can be written to or read by the MCU. During the programmed output state, a
read of the data register actually reads the value of the output data buffer and not the I/O pin. The
operation of the standard port hardware is shown schematically in Figure 4-1.
This is further summarized in Table 4-1, which shows the effect of reading from, or writing to an
I/O pin in various circumstances. Note that the read/write signal shown is internal and not available
to the user.
TPG
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INPUT/OUTPUT PORTS
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M68HC05 internal connections
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Data direction
register bit
DDRn
Latched data
register bit
DATA
Output
buffer
O/P
data
buffer
Input
buffer
I/O
pin
DDRn
DATA
I/O Pin

Output 
1
0
0
1
1
1


0
0
tristate
0
1
tristate
Input
Figure 4-1 Standard I/O port structure
Table 4-1 I/O pin states
R/W
0
0
1
1
4.2
DDRn
0
1
0
1
Action of MCU write to/read of data bit
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch, and output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in output mode. The output data latch is read.
Port A
This port is a standard M68HC05 bidirectional I/O port, comprising a data register and a data
direction register.
Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode.
4.3
Port B
In addition to the standard port functions, this 6-bit port has a programmable keyboard interrupt
feature on pins PB0–PB3 and shares two pins (PB4 and PB5) with the timer subsystem. On reset,
this port is configured as a standard I/O port, comprising a data register and a data direction
register.
TPG
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Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode.
Provided that the interrupt mask bit of the condition code register is cleared, the keyboard interrupt
facility is enabled by setting the keyboard interrupt enable bit (KIE) in the port B configuration
register at location $07. The configuration register is described in Section 4.4.3.
Pins configured as output do not contribute to the wired-or interrupt. The structure of the port pins
is shown diagrammatically in Figure 4-2. When a low-to-high transition is detected on any of these
port pins, a keyboard interrupt request is generated and the port B interrupt status flag (KSF) is
set. The address of the interrupt service routine is specified by the contents of memory locations
$0FFA and $0FFB. Since this interrupt vector is shared with the IRQ external interrupt function,
the interrupt service routine should check KSF to determine the interrupt source. KSF can be
cleared by accessing the port B data register. The keyboard interrupt is edge sensitive. Care must
be taken to allow adequate time for switch debounce before clearing the flag.
4
A keyboard interrupt will force the MCU out of STOP or WAIT mode.
IRQ
PB3
+
DDRB3
PB2
+
DDRB2
&
PB1
+
&
&
Edge
detect
Internal
interrupt
DDRB1
PB0
+
DDRB0
KIE
Figure 4-2 Port B keyboard interrupt function
TPG
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4.4
Port registers
The following sections explain in detail the individual bits in the data and control registers
associated with the ports.
4.4.1
Port A data register (PORTA)
4
Address
Port A data (PORTA)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$0000
State
on reset
Undefined
Each bit can be configured as input or output via the corresponding data direction bit in the port
A data direction register (DDRA).
The state of the bits in the port data register following reset is undefined.
4.4.2
Port B data register (PORTB)
Port B data (PORTB)
Address
bit 7
bit 6
$0001
0
0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Undefined
In addition to the normal port functions, port B is equipped with a keyboard interrupt capability as
described in Section 4.3. Two of the port pins (PB4 and PB5) are shared with the TCMP and TCAP
pins respectively. These functions are controlled using the port B configuration register.
4.4.3
Port B configuration register (CONFB)
Port B configuration (CONFB)
Address
bit 7
bit 6
$0007
KSF
KIE
bit 5
bit 4
TCAP TCMP
bit 3
bit 2
bit 1
bit 0
State
on reset
0
0
0
0
0000 0000
Reset clears this register, thus returning all port B pins to normal I/O lines.
KSF — Keyboard interrupt status flag
1 (set)
–
0 (clear) –
Keyboard interrupt has occurred.
No keyboard interrupt has occurred.
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KIE — Keyboard interrupt enable
1 (set)
–
0 (clear) –
Keyboard interrupt enabled on port B.
Keyboard interrupt disabled.
TCAP — Timer input capture function
1 (set)
–
0 (clear) –
PB5 acts as the TCAP input to the 16-bit timer. The pin is forced to
an input state regardless of the data direction bit.
4
PB5 functions as a normal I/O pin.
TCMP — Timer output compare function
1 (set)
–
0 (clear) –
PB4 acts as the TCMP output for the 16-bit timer. The pin is forced to
an output state regardless of the data direction bit.
PB4 functions as a normal I/O pin.
Bits 3–0 are not implemented on the configuration register and always read zero. Writing to these
bits has no meaning or effect.
4.4.4
Data direction register A (DDRA)
Address
Port A data direction (DDRA)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$0004
State
on reset
0000 0000
Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ configures the corresponding port pin as an input.
Reset clears these registers, thus configuring all pins as inputs.
4.4.5
Data direction register B (DDRB)
Port B data direction (DDRB)
Address
bit 7
bit 6
$0005
0
0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
0000 0000
Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ configures the corresponding port pin as an input.
Reset clears these registers, thus configuring all pins as inputs.
TPG
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4.5
Other port considerations
All output ports can emulate ‘open-drain’ outputs. This is achieved by writing a zero to the relevant
output port latch. By toggling the corresponding data direction bit, the port pin will either be an
output zero or tri-state (an input). This is shown diagrammatically in Figure 4-3.
4
When using a port pin as an ‘open-drain’ output, certain precautions must be taken in the user
software. If a read-modify-write instruction is used on a port where the ‘open-drain’ is assigned
and the pin at this time is programmed as an input, it will read it as a ‘one’. The read-modify-write
instruction will then write this ‘one’ into the output data latch on the next cycle. This would cause
the ‘open-drain’ pin not to output a ‘zero’ when desired.
Note:
‘Open-drain’ outputs should not be pulled above VDD.
Read buffer output
(a)
A
Y
Data direction register bit DDRn
DDRn
1
1
0
0
A
0
1
0
1
Y
0
1
tri state
tri state





Normal operation – tri state
1
1
0
0
0
1
0
1
low
—
high
high





‘Open-drain’
(b)
VDD
VDD
Px0
‘Open-drain’ output
(c)
DDRx, bit 0 = 0
Portx, bit 0 = 0
DDRx, bit 0 = 0
Portx, bit 0 = 0
Figure 4-3 Port logic levels
TPG
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5
CORE TIMER
The MC68HC05J3 has a 15-stage ripple counter called the core timer (CTIMER). Features of this
timer are: timer overflow; power-on reset (POR); real time interrupt (RTI), with four selectable
interrupt rates; and a computer operating properly (COP) watchdog timer.
5
Internal bus
8
Internal processor clock
fOP
$09 CTCR
(Core timer counter)
fOP / 22
8
fOP
(÷4)
/ 210
7-bit counter
Overflow
detect
circuit
fOP / 217
fOP / 214
COP
clear
RTI select circuit
$08 CTCSR
(Core timer control & status)
8
CTOF RTIF CTOFE RTIE
0
0
RT1
RT0
COP watchdog
timer
(÷8)
Interrupt circuit
To
reset
logic
To interrupt logic
Figure 5-1 Core timer block diagram
TPG
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As shown in Figure 5-1, the timer is driven by the internal bus clock divided by four with a fixed
prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be
read by the CPU at any time, by accessing the CTIMER counter register (CTCR) at address $09.
A timer overflow function is implemented on the last stage of this counter, giving a possible
interrupt at the rate of fOP/1024. (The POR signal (tPORL) is also derived from this register, at
fOP/4064.) The counter register circuit is followed by four more stages, with the resulting clock
(fOP/16384) driving the real time interrupt circuit. The RTI circuit consists of three divider stages
with a 1-of-4 selector. The output of the RTI circuit is further divided by 8 to drive the COP
watchdog timer circuit. The RTI rate selector bits, and the RTI and CTIMER overflow enable bits
and flags, are located in the CTIMER control and status register (CTCSR) at location $08.
5
CTOF (core timer overflow flag) is a clearable, read-only status bit and is set when the 8-bit ripple
counter rolls over from $FF to $00. A CPU interrupt request will be generated if CTOFE is set.
Clearing the CTOF is done by writing a ‘0’ to it. Writing a ‘1’ to CTOF has no effect on the bit’s
value. Reset clears CTOF.
When CTOFE (core timer overflow enable) is set, a CPU interrupt request is generated when the
CTOF bit is set. Reset clears CTOFE.
The core timer counter register (CTCR) is a read-only register that contains the current value of
the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP/4 and can
be used for various functions including a software input capture. Extended time periods can be
attained using the CTIMER overflow function to increment a temporary RAM storage location
thereby simulating a 16-bit (or more) counter.
The power-on cycle clears the entire counter chain and begins clocking the counter. After tPORL
cycles, the power-on reset circuit is released, which again clears the counter chain and allows the
device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up
from zero and normal device operation will begin. When RESET is asserted at any time during
operation (other than POR), the counter chain will be cleared.
5.1
Real time interrupts (RTI)
The real time interrupt circuit consists of a three stage divider and a 1-of-4 selector. The clock
frequency that drives the RTI circuit is fOP/214 (or fOP/16384), with three additional divider stages,
giving a maximum interrupt period of 4 seconds at a bus frequency (fOP) of 32kHz. Register details
are given in Section 5.3.
5.2
Computer operating properly (COP) watchdog timer
The COP watchdog timer function is implemented by taking the output of the RTI circuit and
further dividing it by eight, as shown in Figure 5-1. Note that the minimum COP timeout period is
seven times the RTI period. This is because the COP will be cleared asynchronously with respect
TPG
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to the value in the core timer counter register/RTI divider, hence the actual COP timeout period
will vary between 7x and 8x the RTI period.
The COP function is a mask option, enabled or disabled during device manufacture.
If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched.
COP timeout is prevented by writing a ‘0’ to bit 0 of address $0FF0. When the COP is cleared, only
the final divide-by-eight stage is cleared (see Figure 5-1).
5.3
Core timer registers
5.3.1
Core timer control and status register (CTCSR)
Core timer control/status (CTCSR)
Address
bit 7
bit 6
$0008
CTOF
bit 5
bit 4
5
bit 3
bit 2
bit 1
bit 0
State
on reset
0
0
RT1
RT0
uu00 0011
RTIF CTOFE RTIE
CTOF — Core timer overflow
1 (set)
–
0 (clear) –
Core timer overflow has occurred.
No core timer overflow interrupt has been generated.
This bit is set when the core timer counter register rolls over from $FF to $00; an interrupt request
will be generated if CTOFE is set. When set, the bit may be cleared by writing a ‘0’ to it.
RTIF — Real time interrupt flag
1 (set)
–
0 (clear) –
A real time interrupt has occurred.
No real time interrupt has been generated.
This bit is set when the output of the chosen stage becomes active; an interrupt request will be
generated if RTIE is set. When set, the bit may be cleared by writing a ‘0’ to it.
CTOFE — Core timer overflow enable
1 (set)
–
Core timer overflow interrupt is enabled.
0 (clear) –
Core timer overflow interrupt is disabled.
Setting this bit enables the core timer overflow interrupt. A CPU interrupt request will then be
generated whenever the CTOF bit becomes set. Clearing this bit disables the core timer overflow
interrupt capability.
TPG
MC68HC05J3
CORE TIMER
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RTIE — Real time interrupt enable
1 (set)
–
Real time interrupt is enabled.
0 (clear) –
Real time interrupt is disabled.
Setting this bit enables the real time interrupt. A CPU interrupt request will then be generated
whenever the RTIF bit becomes set. Clearing this bit disables the real time interrupt capability.
RT1:RT0 — Real time interrupt rate select
5
These two bits select one of four taps from the real time interrupt circuitry. Reset sets both RT0
and RT1 to one, selecting the lowest periodic rate and therefore the maximum time in which to
alter them if necessary. The COP reset times are also determined by these two bits. Care should
be taken when altering RT0 and RT1 if a timeout is imminent, or the timeout period is uncertain.
If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be
missed or an additional one could be generated. To avoid problems, the COP should be cleared
before changing the RTI taps. See Table 5-1 for some example RTI periods.
Table 5-1 Example RTI periods
RT1 RT0
0
0
1
1
5.3.2
0
1
0
1
Division
ratio
214
215
216
217
Bus frequency
fOP = 2 MHz
Minimum
RTI
COP
period
period
8.2ms
57.3ms
16.4ms
114.7ms
32.8ms
229.4ms
65.5ms
458.8ms
Core timer counter register (CTCR)
Address
Core timer counter (CTCR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$0009
The core timer counter register is a read-only register, which contains the current value of the 8-bit
ripple counter at the beginning of the timer chain. Reset clears this register.
TPG
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CORE TIMER
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5.4
Core timer during WAIT
The CPU clock halts during the WAIT mode, but the core timer remains active. If the CTIMER
interrupts are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
5.5
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt
or an external reset, the internal oscillator will restart, followed by an internal processor
stabilization delay (tPORL). The timer is then cleared and operation resumes.
5
TPG
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CORE TIMER
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5
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
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6
16-BIT PROGRAMMABLE TIMER
The programmable timer on the MC68HC05J3 consists of a 16-bit read-only free-running counter,
with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. Selected
input edges cause the current counter value to be latched into a 16-bit input capture register so
that software can later read this value to determine when the edge occurred. When the free
running counter value matches the value in the output compare registers, the programmed pin
action takes place. Refer to Figure 6-1 for a block diagram of the timer. The input capture and
output compare functions can only be enabled by setting bit 4 and bit 5 of the port B configuration
register as described in Section 4.4.3.
6
The timer has a 16-bit architecture, hence each specific functional segment is represented by two
8-bit registers. These registers contain the high and low byte of that functional segment. Accessing
the low byte of a specific timer function allows full control of that function; however, an access of
the high byte inhibits that specific timer function until the low byte is also accessed.
Note:
The I-bit in the CCR should be set while manipulating both the high and low byte register
of a specific timer function to ensure that an interrupt does not occur.
TPG
MC68HC05J3
16-BIT PROGRAMMABLE TIMER
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Internal bus
8
Internal
processor
clock
High
byte
Low
byte
Output
compare
register
6
8-bit
buffer
High
byte
fOP
$16
(÷4)
$17
16-bit
free-running
counter
$18
Alternate
counter
register
$1A
Output
compare
circuit
High
byte
Low byte
Low
byte
$14
Input
capture
register
$19
$15
$1B
Overflow
detect
circuit
Edge
detect
circuit
Output level
register
CLK
ICF
OCF
TOF
D C Q
$13 TSR
(Timer status register)
ICIE
OCIE TOIE
0
0
0
IEDG
OLV
RESET
$12 TCR
(Timer control register)
Interrupt circuit
TCMP
(Output level)
TCAP
(Input edge)
Figure 6-1 16-bit programmable timer block diagram
TPG
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6.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter, or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2µs if the internal bus clock is 2MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
6.1.1
Counter high register
Counter low register
Alternate counter high register
Alternate counter low register
bit 7
$0018
(bit 15)
(bit 8) 1111 1111
Alternate counter high (ACH)
$001A (bit 15)
(bit 8) 1111 1111
Alternate counter low (ACL)
$001B
Timer counter high (TCH)
Timer counter low (TCL)
bit 6
bit 5
bit 4
bit 3
bit 2
$0019
bit 1
bit 0
State
on reset
Address
6
1111 1100
1111 1100
The double-byte, free-running counter can be read from either of two locations, the counter
register at $18 – $19 or the alternate counter register at $1A – $1B. A read from only the less
significant byte (LSB) of the free-running counter, $19 or $1B, receives the count value at the time
of the read. If a read of the free-running counter or alternate counter register first addresses the
more significant byte (MSB), $18 or $1A, the LSB is transferred to a buffer. This buffer value
remains fixed after the first MSB read, even if the user reads the MSB several times. This buffer is
accessed when reading the free-running counter or alternate counter register LSB and thus
completes a read sequence of the total counter value. In reading either the free-running counter
or alternate counter register, if the MSB is read, the LSB must also be read to complete the
sequence. If the timer overflow flag (TOF) is set when the counter register LSB is read, then a read
of the TSR will clear the flag.
The alternate counter register differs from the counter register only in that a read of the LSB does
not clear TOF. Therefore, to avoid the possibility of missing timer overflow interrupts due to clearing
of TOF, the alternate counter register should be used where this is a critical issue.
The free-running counter is set to $FFFC during reset and is always a read-only register. During
a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator
start-up delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-four
prescaler, the value in the free-running counter repeats every 262 144 internal bus clock cycles.
TOF is set when the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE
is set.
TPG
MC68HC05J3
16-BIT PROGRAMMABLE TIMER
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Bits 8 – 15 — MSB of counter/alternate counter register
A read of only the more significant byte (MSB) transfers the LSB to a buffer, which remains fixed
after the first MSB read, until the LSB is also read.
Bits 0 – 7 — LSB of counter/alternate counter register
A read of only the less significant byte (LSB) receives the count value at the time of reading.
6.2
Timer functions
The 16-bit programmable timer is monitored and controlled by a group of ten registers, full details
of which are contained in the following paragraphs. An explanation of the timer functions is
also given.
6
6.2.1
Timer control register – TCR
The timer control register at location $12 is used to enable the input capture (ICIE), output
compare (OCIE), and timer overflow (TOIE) interrupt enable functions as well as selecting input
edge sensitivity (IEDG) and output level polarity (OLV).
Timer control (TCR)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0012
ICIE
OCIE
TOIE
0
0
0
IEDG
OLV
0000 00u0
ICIE — Input capture interrupt enable
1 (set)
–
Input capture interrupt enabled.
0 (clear) –
Input capture interrupt disabled.
OCIE — Output compare interrupt enable
1 (set)
–
Output compare interrupt enabled.
0 (clear) –
Output compare interrupt disabled.
TOIE — Timer overflow interrupt enable
1 (set)
–
Timer overflow interrupt enabled.
0 (clear) –
Timer overflow interrupt disabled.
TPG
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IEDG — Input edge
1 (set)
–
TCAP is positive-going edge sensitive.
0 (clear) –
TCAP is negative-going edge sensitive.
When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running
counter value to the input capture register. When clear, a negative-going edge triggers the transfer.
OLV — Output level
1 (set)
–
A high output level will appear on the TCMP pin.
0 (clear) –
A low output level will appear on the TCMP pin.
When OLV is set, a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP pin. When clear, it will be a low level that
will appear on the TCMP pin.
6
6.2.2
Timer status register – TSR
The Timer Status register ($13) contains the status bits for the above three interrupt conditions —
ICF, OCF, TOF.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
Timer status (TSR)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0013
ICF
OCF
TOF
0
0
0
0
0
uuu0 0000
ICF — Input capture flag
1 (set)
–
0 (clear) –
A valid input capture has occurred.
No input capture has occurred.
This bit is set when the selected polarity of edge is detected by the input capture edge detector;
an input capture interrupt will be generated, if ICIE is set. ICF is cleared by reading the TSR and
then the input capture low register at $15.
TPG
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16-BIT PROGRAMMABLE TIMER
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OCF — Output compare flag
1 (set)
–
0 (clear) –
A valid output compare has occurred.
No output compare has occurred.
This bit is set when the output compare register contents match those of the free-running counter;
an output compare interrupt will be generated, if OCIE is set. OCF is cleared by reading the TSR
and then the output compare low register at $17.
TOF — Timer overflow flag
1 (set)
–
0 (clear) –
Timer overflow has occurred.
No timer overflow has occurred.
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt
will occur, if TOIE is set. TOF is cleared by reading the TSR and the counter low register, $19.
6
When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
1) the timer status register is read or written when TOF is set and
2) the LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
6.2.3
Input capture function
‘Input capture’ is a technique whereby an external signal (connected to the TCAP pin) is used to
trigger a read of the free-running counter. In this way it is possible to relate the timing of an external
signal to the internal counter value, and hence to elapsed time.
6.2.4
Input capture high register
Input capture low register
Address
bit 7
Input capture high (ICH)
$0014
(bit 15)
Input capture low (ICL)
$0015
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
(bit 8) Undefined
Undefined
The two 8-bit registers that make up the 16-bit input capture register are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector senses a valid
TPG
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transition. The level transition that triggers the counter transfer is defined by the input edge bit
(IEDG). The most significant 8 bits are stored in the input capture high register at $14, the least
significant in the input capture low register at $15.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronisation. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register on each valid signal transition whether the input capture flag (ICF) is set or clear.
The input capture register always contains the free-running counter value that corresponds to the
most recent input capture. After a read of the input capture register MSB ($14), the counter
transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time used in the
input capture software routine and its interaction with the main program to determine the minimum
pulse period. A read of the input capture register LSB ($15) does not inhibit the free-running
counter transfer since the two actions occur on opposite edges of the internal bus clock.
The contents of the input capture register are undefined following reset.
6.2.5
6
Output compare function
‘Output compare’ is a technique that may be used, for example, to generate an output waveform,
or to signal when a specific time period has elapsed, by presetting the output compare register to
the appropriate value.
6.2.6
Output compare high register
Output compare low register
Address
bit 7
Output compare high (OCH)
$0016
(bit 15)
Output compare low (OCL)
$0017
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
(bit 8) Undefined
Undefined
The 16-bit output compare register is made up of two 8-bit registers at locations $16 (MSB) and
$17 (LSB). The contents of the output compare register are continually compared with the
contents of the free-running counter and, if a match is found, the output compare flag (OCF) in the
timer status register is set and the output level (OLV) bit clocked to the output level register. The
output compare register values and the output level bit should be changed after each successful
comparison to establish a new elapsed timeout. An interrupt can also accompany a successful
output compare provided the corresponding interrupt enable bit (OCIE) is set. (The free-running
counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register containing the MSB ($16), the output
compare function is inhibited until the LSB ($17) is also written. The user must write both bytes
TPG
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16-BIT PROGRAMMABLE TIMER
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(locations) if the MSB is written first. A write made only to the LSB will not inhibit the compare
function. The processor can write to either byte of the output compare register without affecting
the other byte. The output level (OLV) bit is clocked to the output level register whether the output
compare flag (OCF) is set or clear. The minimum time required to update the output compare
register is a function of the program rather than the internal hardware. Because the output
compare flag and the output compare register are not defined at power on, and not affected by
reset, care must be taken when initialising output compare functions with software. The following
procedure is recommended:
1) write to output compare high to inhibit further compares;
2) read the timer status register to clear OCF (if set);
3) write to output compare low to enable the output compare function.
6
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
6.3
Timer during WAIT mode
In WAIT mode all CPU action is suspended, but the programmable timer continues counting. An
interrupt from an input capture, an output compare or a timer overflow, if enabled, will cause the
processor to exit WAIT mode.
6.4
Timer during STOP mode
In the STOP mode all MCU clocks are stopped, hence the timer stops counting. If STOP is exited
by an interrupt the counter retains the last count value. If the device is reset, then the counter is
forced to $FFFC. During STOP, if at least one valid input capture edge occurs at the TCAP pin, the
input capture detect circuit is armed. This does not set any timer flags nor wake up the MCU. When
the MCU does wake up, however, there is an active input capture flag and data from the first valid
edge that occurred during the STOP period. If the device is reset to exit STOP mode, then no input
capture flag or data remains, even if a valid input capture edge occurred.
6.5
Timer state diagrams
The relationships between the internal clock signals, the counter contents and the status of the
flag bits are shown in the following diagrams. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
TPG
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Internal
processor clock
Internal
reset
Internal
timer clocks
 T00
 T01

 T10
 T11
16-bit
counter
$FFFC
$FFFD
$FFFE
$FFFF
External reset
or end of POR
Note:
The counter and timer control registers are the only ones affected by power-on or external reset.
6
Figure 6-2 Timer state timing diagram for reset
Internal
processor clock
Internal
timer clocks
 T00
 T01
 T10

 T11
16-bit
counter
$F124
$F125
$F126
}
}
}
Input
edge
$F123
}
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Internal
capture latch
Input capture
register
$????
$F124
Input capture
flag
Note:
If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then
the input capture flag will be set during the next T11 state.
Figure 6-3 Timer state timing diagram for input capture
TPG
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16-BIT PROGRAMMABLE TIMER
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Internal
processor clock
Internal
timer clocks
 T00
 T01

 T10
 T11
16-bit
counter
$F456
$F457
$F458
$F459
(Note 1)
Output compare
register
CPU writes $F457
(Note 1)
Compare register
latch
6
(Note 2)
Output compare
flag and TCMP
Note:
$F457
(1) The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state
T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.
(2) The output compare flag is set at the timer state T11 that follows the comparison match ($F457 in this
example).
Figure 6-4 Timer state timing diagram for output compare
Internal
processor clock
Internal
timer clocks
 T00
 T01

 T10
 T11
16-bit
counter
$FFFF
$0000
$0001
$0002
Timer overflow
flag
Note:
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared
by a read of the timer status register during the internal processor clock high time, followed by a read
of the counter low register.
Figure 6-5 Timer state timing diagram for timer overflow
TPG
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7
RESETS AND INTERRUPTS
7.1
Resets
The MC68HC05J3 can be reset in three ways: by the initial power-on reset function, by an active
low input to the RESET pin and by a COP watchdog reset, if the watchdog timer is enabled. Any
of these resets will cause the program to go to its starting address, specified by the contents of
memory locations $0FFE and $0FFF, and cause the interrupt mask of the condition code register
to be set.
7
tVDDR
VDD
VDD threshold (1-2V typical)
tOXOV
OSC1
tPORL
tCYC
Internal
processor clock
RESET
Internal
address bus
Internal
data bus
tRL (or tDOGL)
(Internal power-on reset)
0FFE 0FFE 0FFE 0FFE 0FFF
New
PC
0FFE 0FFE 0FFE 0FFE
Reset sequence
New
PCH
(External hardware reset)
0FFF
New
PC
New
PCL
Op
code
Reset sequence
New
PCL
Op
code
Program
execution
begins
New
PCH
Program
execution
begins
Figure 7-1 Reset timing diagram
TPG
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7.1.1
Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high. The user must ensure that the voltage
on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed.
If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached
the specified minimum operating voltage. This may be accomplished by connecting an external
RC-circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be
great enough (at least 100ms) to allow the oscillator circuit to stabilize.
7.1.2
7
RESET pin
When the oscillator is running in a stable state, the MCU is reset when a logic zero is applied to
the RESET input for a minimum period of 1.5 machine cycles (tCYC). This pin contains an internal
Schmitt trigger as part of its input to improve noise immunity. When the RESET pin goes high, the
MCU will resume operation on the following cycle.
7.1.3
Computer operating properly (COP) reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a
specific time by a program reset sequence.
Note:
COP timeout is prevented by periodically writing a ‘0’ to bit 0 of address $0FF0.
If the COP watchdog timer is allowed to timeout, an internal reset is generated to reset the MCU.
Because the internal reset signal is used, the MCU comes out of a COP reset in the same
operating mode it was in when the COP timeout was generated.
The COP reset function is enabled or disabled by a mask option (see Section 1.2).
TPG
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7.2
Functions affected by reset
When processing stops within the MCU for any reason, i.e. power-on reset, external reset or the
execution of a STOP or WAIT instruction, various internal functions of the MCU are affected.
Table 7-1 shows the resulting action of any type of system reset, but not necessarily in the order
in which they occur.
Table 7-1 Effect of RESET, POR, STOP and WAIT
Function/effect
16-bit timer prescaler set to zero
16-bit timer counter set to $FFFC
All timer enable bits cleared (disable)
Data direction registers cleared (inputs)
Stack pointer set to $00FF
Force internal address bus to restart
Vector $0FFE, $0FFF
Interrupt mask bit (I-bit in CCR) set
Interrupt mask bit (I-bit in CCR) cleared
Reset STOP latch
Reset IRQ latch
Reset WAIT latch
Oscillator disabled for 4064 cycles
Timer clock cleared
Watchdog counter reset
7.3
RESET
x
x
x
x
x
x
x
x
x
x
x
x
POR
x
x
x
x
x
x
x
x
x
x
x
x
x
x
WAIT
x
x
STOP
x
x
x
x
7
Interrupts
The MCU can be interrupted by four different sources, three maskable hardware interrupts and
one non-maskable software interrupt:
•
External signal on the IRQ pin
•
Core timer
•
16-bit programmable timer
•
Software interrupt instruction (SWI)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction (ReTurn from Interrupt) causes the
register contents to be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the interrupt mask bit (I-bit) will be cleared providing the
corresponding enable bit stored on the stack is zero, i.e. the interrupt is disabled.
TPG
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RESETS AND INTERRUPTS
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Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
Note:
Power-on or external reset clear all interrupt enable bits thus preventing interrupts
during the reset sequence.
7.3.1
Interrupt priorities
Each potential interrupt source is assigned a priority which means that if more than one interrupt
is pending at the same time, the processor will service the one with the highest priority first. For
example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
7
Table 7-2 shows the relative priority of all the possible interrupt sources. Figure 7-2 shows
the interrupt processing flow.
Table 7-2 Interrupt priorities
Source
Register
Reset
—
Software interrupt (SWI)
—
External interrupt (IRQ)/
—
keyboard interrupt
CONFB
Core timer
CTCSR
16-bit timer – input capture
TSR
16-bit timer – output compare
TSR
16-bit timer – overflow
TSR
Reserved
—
Flags
—
—
—
PTBIF
CTOF, RTIF
ICF
OCF
TOF
—
Vector address
$0FFE, $0FFF
$0FFC, $0FFD
Priority
highest
$0FFA, $0FFB
$0FF8, $0FF9
$0FF6, $1FF7
$0FF4, $0FF5
$0FF2, $0FF3
$0FF0, $0FF1
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Reset
Yes
Is I-bit set?
No
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IRQ/keyboard
interrupt?
Yes
Clear IRQ request
latch
No
Core timer
interrupt?
Stack
PC, X, A, CC
Yes
Set I-bit
No
16-bit timer
interrupt?
Load PC from:
IRQ/key:
$0FFA-$0FFB
Core timer: $0FF8-$0FF9
Timer IC:
$1FF6-$1FF7
Timer OC: $1FF4-$1FF5
Timer OVF: $1FF2-$1FF3
No
Fetch next
instruction
SWI
instruction?
7
Yes
Yes
No
RTI
instruction?
Yes
Restore registers from
stack:
CC, A, X, PC
No
Execute instruction
Figure 7-2 Interrupt flow chart
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7.4
Non-maskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specified by
the contents of memory locations $0FFC and $0FFD.
7.5
Maskable hardware interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note:
7
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the
I-bit is cleared.
7.5.1
External interrupt (IRQ or keyboard)
These external interrupt sources will vector to the same interrupt service routine, whose start
address is contained in memory locations $0FFA and $0FFB. IRQ can be selected to be either
edge sensitive or edge-and-level sensitive. Further details of the keyboard interrupt facility can be
found in Section 4.3.
7.5.2
Core timer interrupts
There are two core timer interrupt flags that cause an interrupt whenever an interrupt is enabled
and its flag becomes set (RTIF and CTOF). The interrupt flags and enable bits are located in the
core timer control and status register (CTCSR). These interrupts vector to the same interrupt
service routine, whose start address is contained in memory locations $0FF8 and $0FF9. Full
details of the core timer can be found in Section 5.
To make use of the real time interrupt, the RTIE bit must first be set. The RTIF bit will then be set
after the specified number of counts.
To make use of the core timer overflow interrupt, the CTOFE bit must first be set. The CTOF bit
will then be set when the core timer counter register overflows from $FF to $00.
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7.5.3
16-bit timer interrupts
There are three different timer interrupt flags (ICF, OCF and TOF) that will cause a timer interrupt
whenever they are set and enabled. These three interrupt flags are found in the three most
significant bits of the timer status register (TSR) at location $13. ICF will vector to the service
routine defined by $0FF6 - $0FF7, OCF will vector to the service routine defined by $0FF4 - $0FF5
and TOF will vector to the service routine defined by $0FF2 - $0FF3 as shown in Table 7-2.
There are three corresponding enable bits; ICIE, OCIE and TOIE which are located in the timer
control register (TCR) at address $12. Full details of the programmable timer can be found in
Section 6.
7.6
Hardware controlled interrupt sequence
The following three functions; reset, STOP and WAIT, are not in the strictest sense interrupts.
However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in
Figure 2-4.
RESET: A reset condition causes the program to vector to its starting address, which is contained
in memory locations $1FFE (MSB) and $1FFF (LSB). The I-bit in the condition code
register is also set, to disable interrupts.
STOP:
The STOP instruction causes the oscillator to be turned off and the processor to ‘sleep’
until an external interrupt (IRQ) or a keyboard interrupt occurs or the device is reset.
WAIT:
The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks
running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt
(IRQ or keyboard) or a timer interrupt. There are no special WAIT vectors for these
individual interrupts.
7
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8
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the
addressing modes of the MC68HC05J3.
8.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 8-1. The interrupt
stacking order is shown in Figure 8-2.
7
0
7
0
7
0
Accumulator
8
Index register
15
Program counter
15
7
0
0 0 0 0 0 0 0 0 1 1
7
0
1 1 1 H I N Z C
Stack pointer
Condition code register
Carry / borrow
Zero
Negative
Interrupt mask
Half carry
Figure 8-1 Programming model
Increasing
memory
address
Unstack
Stack
0
Condition code register
Accumulator
Index register
Program counter high
Program counter low
Interrupt
7
Return
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Decreasing
memory
address
Figure 8-2 Stacking order
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8.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of
arithmetic calculations or data manipulations.
8.1.2
Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to
create an effective address. The index register may also be used as a temporary storage area.
8.1.3
Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
8.1.4
8
Stack pointer (SP)
The stack pointer is a 16-bit register, which contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to
location $00FF. The stack pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011. These
ten bits are appended to the six least significant register bits to produce an address within the
range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64
locations are exceeded, the stack pointer wraps around and overwrites the previously stored
information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
8.1.5
Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just
executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually
tested by a program, and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
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Half carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
When this bit is set all maskable interrupts are masked. If an interrupt occurs while this bit is set,
the interrupt is latched and remains pending until the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero.
Carry/borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred
during the last arithmetic operation. This bit is also affected during bit test and branch instructions
and during shifts and rotates.
8.2
8
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as
follows:
–
Register/memory
–
Read/modify/write
–
Branch
–
Bit manipulation
–
Control
The following paragraphs briefly explain each type. All the instructions within a given type are
presented in individual tables.
This MCU uses all the instructions available in the M146805 CMOS family plus one more: the
unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents
of the accumulator (A) and the index register (X). The high-order product is then stored in the
index register and the low-order product is stored in the accumulator. A detailed definition of the
MUL instruction is shown in Table 8-1.
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8.2.1
Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the
index register. The second operand is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register
operand. Refer to Table 8-2 for a complete list of register/memory instructions.
8.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no
operation is performed. Branch instructions are two-byte instructions. Refer to Table 8-3.
8.2.3
8
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space
(page 0). All port data and data direction registers, timer and serial interface registers,
control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature
allows the software to test and branch on the state of any bit within these locations. The bit set, bit
clear, bit test and branch functions are all implemented with single instructions. For the test and
branch instructions, the value of the bit tested is also placed in the carry bit of the condition code
register. Refer to Table 8-4.
8.2.4
Read/modify/write instructions
These instructions read a memory location or a register, modify or test its contents, and write the
modified value back to memory or to the register. The test for negative or zero (TST) instruction is
an exception to this sequence of reading, modifying and writing, since it does not modify the value.
Refer to Table 8-5 for a complete list of read/modify/write instructions.
8.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation
during program execution. Refer to Table 8-6 for a complete list of control instructions.
8.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical
listing of all the instructions (see Table 8-7 and Table 8-8), and an opcode map for the instruction
set of the M68HC05 MCU family (see Table 8-9).
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Table 8-1 MUL instruction
X:A ← X*A
Multiplies the eight bits in the index register by the eight
Description bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
H : Cleared
I : Not affected
Condition
N : Not affected
codes
Z : Not affected
C : Cleared
Source
MUL
Addressing mode
Cycles
Bytes
Opcode
Form
Inherent
11
1
$42
Operation
Table 8-2 Register/memory instructions
Addressing modes
Indexed
(no
offset)
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Indexed
(16-bit
offset)
Opcode
Indexed
(8-bit
offset)
# Cycles
Extended
# Bytes
Direct
Opcode
Immediate
Mnemonic
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Load A from memory
LDA
A6
2
2
B6
2
3
C6
3
4
F6
1
3
E6
2
4
D6
3
5
Load X from memory
LDX
AE
2
2
BE
2
3
CE
3
4
FE
1
3
EE
2
4
DE
3
5
Store A in memory
STA
B7
2
4
C7
3
5
F7
1
4
E7
2
5
D7
3
6
6
Function
Store X in memory
STX
BF
2
4
CF
3
5
FF
1
4
EF
2
5
DF
3
Add memory to A
ADD
AB
2
2
BB
2
3
CB
3
4
FB
1
3
EB
2
4
DB
3
5
Add memory and carry to A
ADC
A9
2
2
B9
2
3
C9
3
4
F9
1
3
E9
2
4
D9
3
5
Subtract memory
SUB
A0
2
2
B0
2
3
C0
3
4
F0
1
3
E0
2
4
D0
3
5
Subtract memory from A
with borrow
SBC
A2
2
2
B2
2
3
C2
3
4
F2
1
3
E2
2
4
D2
3
5
AND memory with A
AND
A4
2
2
B4
2
3
C4
3
4
F4
1
3
E4
2
4
D4
3
5
OR memory with A
ORA
AA
2
2
BA
2
3
CA
3
4
FA
1
3
EA
2
4
DA
3
5
Exclusive OR memory with A
EOR
A8
2
2
B8
2
3
C8
3
4
F8
1
3
E8
2
4
D8
3
5
Arithmetic compare A
with memory
CMP
A1
2
2
B1
2
3
C1
3
4
F1
1
3
E1
2
4
D1
3
5
Arithmetic compare X
with memory
B3
2
3
C3
3
4
F3
1
3
E3
2
4
D3
3
5
CPX
A3
2
2
Bit test memory with A
(logical compare)
BIT
A5
2
2
B5
2
3
C5
3
4
F5
1
3
E5
2
4
D5
3
5
Jump unconditional
JMP
BC
2
2
CC
3
3
FC
1
2
EC
2
3
DC
3
4
Jump to subroutine
JSR
BD
2
5
CD
3
6
FD
1
5
ED
2
6
DD
3
7
8
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Table 8-3 Branch instructions
Function
Branch always
Branch never
Branch if higher
Branch if lower or same
Branch if carry clear
(Branch if higher or same)
Branch if carry set
(Branch if lower)
Branch if not equal
Branch if equal
Branch if half carry clear
Branch if half carry set
Branch if plus
Branch if minus
Branch if interrupt mask bit is clear
Branch if interrupt mask bit is set
Branch if interrupt line is low
Branch if interrupt line is high
Branch to subroutine
8
Mnemonic
BRA
BRN
BHI
BLS
BCC
(BHS)
BCS
(BLO)
BNE
BEQ
BHCC
BHCS
BPL
BMI
BMC
BMS
BIL
BIH
BSR
Relative addressing mode
Opcode # Bytes # Cycles
20
2
3
21
2
3
22
2
3
23
2
3
24
2
3
24
2
3
25
2
3
25
2
3
26
2
3
27
2
3
28
2
3
29
2
3
2A
2
3
2B
2
3
2C
2
3
2D
2
3
2E
2
3
2F
2
3
AD
2
6
Table 8-4 Bit manipulation instructions
Function
Branch if bit n is set
Branch if bit n is clear
Set bit n
Clear bit n
Mnemonic
BRSET n (n=0–7)
BRCLR n (n=0–7)
BSET n (n=0–7)
BCLR n (n=0–7)
Addressing Modes
Bit set/clear
Bit test and branch
Opcode # Bytes # Cycles Opcode # Bytes # Cycles
2•n
3
5
01+2•n
3
5
10+2•n
2
5
11+2•n
2
5
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Table 8-5 Read/modify/write instructions
Addressing modes
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Indexed
(8-bit
offset)
# Cycles
Increment
Decrement
Clear
Complement
Negate (two’s complement)
Rotate left through carry
Rotate right through carry
Logical shift left
Logical shift right
Arithmetic shift right
Test for negative or zero
Multiply
Indexed
(no
offset)
Direct
# Bytes
Function
Inherent
(X)
Opcode
Inherent
(A)
Mnemonic
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INC
DEC
CLR
COM
NEG
ROL
ROR
LSL
LSR
ASR
TST
MUL
4C
4A
4F
43
40
49
46
48
44
47
4D
42
1
1
1
1
1
1
1
1
1
1
1
1
3 5C
3 5A
3 5F
3 53
3 50
3 59
3 56
3 58
3 54
3 57
3 5D
11
1
1
1
1
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
3
3C
3A
3F
33
30
39
36
38
34
37
3D
2
2
2
2
2
2
2
2
2
2
2
5
5
5
5
5
5
5
5
5
5
4
7C
7A
7F
73
70
79
76
78
74
77
7D
1
1
1
1
1
1
1
1
1
1
1
5
5
5
5
5
5
5
5
5
5
4
6C
6A
6F
63
60
69
66
68
64
67
6D
2
2
2
2
2
2
2
2
2
2
2
6
6
6
6
6
6
6
6
6
6
5
8
Table 8-6 Control instructions
Function
Transfer A to X
Transfer X to A
Set carry bit
Clear carry bit
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-operation
Stop
Wait
Mnemonic
TAX
TXA
SEC
CLC
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
Inherent addressing mode
Opcode # Bytes # Cycles
97
1
2
9F
1
2
99
1
2
98
1
2
9B
1
2
9A
1
2
83
1
10
81
1
6
80
1
9
9C
1
2
9D
1
2
8E
1
2
8F
1
2
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Table 8-7 Instruction set (1 of 2)
Mnemonic
INH
IMM
DIR
Addressing modes
EXT REL IX
IX1
IX2
BSC BTB
H
◊
◊
ADC
ADD
AND
8
Condition codes
I
N Z C
•
◊ ◊ ◊
•
◊ ◊ ◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
CLR
CMP
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
◊
◊
◊
•
•
•
•
•
•
•
•
•
•
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
◊
◊
◊
◊
•
•
•
•
•
•
•
•
•
•
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
◊
•
◊
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
◊
◊
•
•
0
•
•
◊
Condition code symbols
Address mode abbreviations
◊
Tested and set if true,
cleared otherwise
Interrupt mask
•
Not affected
Negate (sign bit)
?
Load CCR from stack
Z
Zero
0
Cleared
C
Carry/borrow
1
Set
H
Half carry (from bit 3)
BSC Bit set/clear
IMM
Immediate
BTB
Bit test & branch
IX
Indexed (no offset)
I
DIR
Direct
IX1
Indexed, 1 byte offset
N
EXT
Extended
IX2
Indexed, 2 byte offset
INH
Inherent
REL
Relative
Not implemented
TPG
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Table 8-8 Instruction set (2 of 2)
Mnemonic
INH
IMM
DIR
Addressing modes
EXT REL IX
IX1
IX2
BSC BTB
H
COM
Condition codes
I
N Z C
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•
CPX
DEC
EOR
INC
JMP
JSR
LDA
LDX
LSL
LSR
MUL
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
1
•
0
•
•
1
•
•
•
0
◊
◊
◊
◊
◊
•
•
◊
◊
◊
0
•
◊
•
◊
◊
◊
•
?
•
◊
•
•
◊
•
◊
◊
•
•
◊
•
•
◊
◊
◊
◊
◊
•
•
◊
◊
◊
◊
•
◊
•
◊
◊
◊
•
?
•
◊
•
•
◊
•
◊
◊
•
•
◊
•
•
1
◊
•
•
•
•
•
•
•
◊
◊
0
◊
•
•
◊
◊
•
?
•
◊
1
•
•
•
•
◊
•
•
•
•
•
8
Condition code symbols
Address mode abbreviations
◊
Tested and set if true,
cleared otherwise
Interrupt mask
•
Not affected
Negate (sign bit)
?
Load CCR from stack
Z
Zero
0
Cleared
C
Carry/borrow
1
Set
H
Half carry (from bit 3)
BSC Bit set/clear
IMM
Immediate
BTB
Bit test & branch
IX
Indexed (no offset)
I
DIR
Direct
IX1
Indexed, 1 byte offset
N
EXT
Extended
IX2
Indexed, 2 byte offset
INH
Inherent
REL
Relative
Not implemented
TPG
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MOTOROLA
8-9
64
MOTOROLA
8-10
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
High
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
BRCLR7
BRSET7
BRCLR6
BRSET6
BRCLR5
BRSET5
BRCLR4
BRSET4
BRCLR3
BRSET3
BRCLR2
BRSET2
BRCLR1
BRSET1
BTB 2
5
BRCLR0
3
5
BTB 2
5
BRSET0
3
BSC 2
BCLR7
BSC 2
5
BSET7
BSC 2
5
BCLR6
BSC 2
5
BSC 2
5
BSET6
BCLR5
BSC 2
5
BSC 2
5
BSET5
BCLR4
BSC 2
5
BSC 2
5
BSET4
BCLR3
BSC 2
5
BSC 2
5
BSET3
BCLR2
BSC 2
5
BSC 2
5
BSET2
BCLR1
BSC 2
5
BSET1
BSC 2
5
BCLR0
5
BSC 2
5
BSET0
BIH
BIL
BMS
BMC
BMI
REL 2
REL
3
REL 2
3
REL 2
3
REL
3
REL 2
3
REL 2
3
REL 2
3
REL 2
3
REL 2
3
REL
3
REL 2
3
REL 2
3
REL
3
REL
3
BHCS
BPL
3
REL 2
3
BHCC
BEQ
BNE
BCS
BCC
BLS
BHI
BRN
BRA
BSC
BTB
DIR
EXT
INH
IMM
Bit set/clear
Bit test and branch
Direct
Extended
Inherent
Immediate
IX
IX1
IX2
REL
A
X
Abbreviations for address modes and registers
Low
Branch
REL
2
0010
CLR
TST
INC
DEC
ROL
LSL
ASR
ROR
LSR
COM
NEG
DIR
3
0011
5
CLRA
TSTA
INCA
INH 1
3
INH 1
INH 1
3
3
INH 1
INH 1
3
INH 1
3
INH 1
3
DECA
ROLA
LSLA
ASRA
INH 1
3
3
INH 1
INH 1
3
RORA
LSRA
11
INH
3
COMA
MUL
3
INH 1
NEGA
CLRX
TSTX
INCX
INH 2
3
INH 2
INH 2
3
3
INH 2
INH 2
3
DECX
ROLX
INH 2
3
INH 2
3
ASRX
INH 2
3
3
INH 2
RORX
LSLX
3
INH 2
3
COMX
LSRX
3
INH 2
NEGX
CLR
TST
INC
DEC
ROL
LSL
ASR
ROR
LSR
COM
NEG
Read/modify/write
INH
IX1
5
6
0101
0110
Indexed (no offset)
Indexed, 1 byte (8-bit) offset
Indexed, 2 byte (16-bit) offset
Relative
Accumulator
Index register
DIR 1
5
DIR 1
DIR 1
4
5
DIR 1
DIR 1
5
DIR 1
5
DIR 1
5
DIR 1
5
5
DIR 1
DIR 1
5
5
1
DIR 1
INH
4
0100
6
IX1 1
6
IX1 1
IX1 1
5
6
IX1 1
IX1 1
6
IX1 1
6
IX1 1
6
IX1 1
6
6
IX1 1
IX1 1
6
6
IX1 1
CLR
TST
INC
DEC
ROL
LSL
ASR
ROR
LSR
COM
NEG
IX
7
0111
5
1
WAIT
STOP
SWI
RTS
RTI
1
1
1
1
1
1
1
INH 1
INH
2
2
INH
10
INH
INH
6
9
Control
Not implemented
IX 1
5
IX
IX
4
5
IX
IX
5
IX
5
IX
5
IX
5
5
IX
IX 1
5
5
1
IX 1
INH
8
1000
8
Bit manipulation
BTB
BSC
0
1
0000
0001
TXA
NOP
RSP
SEI
CLI
SEC
CLC
TAX
INH
9
1001
INH
2
2
INH 2
INH
2
INH 2
2
INH 2
2
INH 2
2
INH 2
2
INH
2
2
2
2
2
2
2
2
2
LDX
BSR
ADD
ORA
ADC
EOR
LDA
BIT
AND
CPX
SBC
CMP
SUB
IMM
A
1010
2
2
6
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
3
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Bytes
1
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
SUB
F
1111
EXT 3
EXT 3
5
EXT 3
4
EXT 3
6
EXT 3
3
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
5
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
4
IX
3
5
0
0000
IX2 2
IX2 2
6
IX2 2
5
IX2 2
7
IX2 2
4
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
6
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
IX1
E
1110
Address mode
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
Register/memory
EXT
IX2
C
D
1100
1101
Cycles
DIR 3
DIR 3
4
DIR 3
3
DIR 3
5
DIR 3
2
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
4
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
Mnemonic
Legend
2
IMM 2
REL 2
2
2
IMM 2
IMM 2
2
IMM 2
2
IMM 2
2
2
IMM 2
IMM 2
2
IMM 2
2
IMM 2
2
IMM 2
2
IMM 2
2
IMM 2
2
DIR
B
1011
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4
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
High
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Low
Opcode in binary
Opcode in hexadecimal
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
IX1 1
3
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
5
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX
F
1111
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Table 8-9 M68HC05 opcode map
TPG
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8.3
Addressing modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for
all situations. The various indexed addressing modes make it possible to locate data tables, code
conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are
single byte instructions; the longest instructions (three bytes) enable access to tables throughout
memory. Short absolute (direct) and long absolute (extended) addressing are also included. One
or two byte direct addressing instructions access all data bytes in most applications. Extended
addressing permits jump instructions to reach all memory locations.
The term ‘effective address’ (EA) is used in describing the various addressing modes. The
effective address is defined as the address from which the argument for an instruction is fetched
or stored. The ten addressing modes of the processor are described below. Parentheses are used
to indicate ‘contents of’ the location or register referred to. For example, (PC) indicates the
contents of the location pointed to by the PC (program counter). An arrow indicates ‘is replaced
by’ and a colon indicates concatenation of two bytes. For additional details and graphical
illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/
Microprocessor User's Manual or to the M68HC05 Applications Guide.
8.3.1
Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is
contained in the opcode. Operations specifying only the index register or accumulator, as well as
the control instruction, with no other arguments are included in this mode. These instructions are
one byte long.
8.3.2
8
Immediate
In the immediate addressing mode, the operand is contained in the byte immediately following the
opcode. The immediate addressing mode is used to access constants that do not change during
program execution (e.g. a constant used to initialize a loop counter).
EA = PC+1; PC ← PC+2
8.3.3
Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte
following the opcode byte. Direct addressing allows the user to directly address the lowest 256
bytes in memory with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
TPG
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8.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode byte. Instructions with extended addressing mode are capable of
referencing arguments anywhere in memory with a single three-byte instruction. When using the
Motorola assembler, the user need not specify whether an instruction uses direct or extended
addressing. The assembler automatically selects the short form of the instruction.
EA = (PC+1):(PC+2); PC ← PC+3
Address bus high ← (PC+1); Address bus low ← (PC+2)
8.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in
the 8-bit index register. This addressing mode can access the first 256 memory locations. These
instructions are only one byte long. This mode is often used to move a pointer through a table or
to hold the address of a frequently referenced RAM or I/O location.
EA = X; PC ← PC+1
Address bus high ← 0; Address bus low ← X
8
8.3.6
Indexed, 8-bit offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the
operand can be located anywhere within the lowest 511 memory locations. This addressing mode
is useful for selecting the mth element in an n element table.
EA = X+(PC+1); PC ← PC+2
Address bus high ← K; Address bus low ← X+(PC+1)
where K = the carry from the addition of X and (PC+1)
8.3.7
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address
mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola
assembler determines the shortest form of indexed addressing.
EA = X+[(PC+1):(PC+2)]; PC ← PC+3
Address bus high ← (PC+1)+K; Address bus low ← X+(PC+2)
where K = the carry from the addition of X and (PC+2)
TPG
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8.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the
contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only
if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of
relative addressing is from –126 to +129 from the opcode address. The programmer need not
calculate the offset when using the Motorola assembler, since it calculates the proper offset and
checks to see that it is within the span of the branch.
EA = PC+2+(PC+1); PC ← EA if branch taken;
otherwise EA = PC ← PC+2
8.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte
following the opcode specifies the address of the byte in which the specified bit is to be set or
cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively
set or cleared with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
8.3.10
8
Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative
addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The
address of the byte to be tested is in the single byte immediately following the opcode byte (EA1).
The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set
or cleared in the specified memory location. This single three-byte instruction allows the program
to branch based on the condition of any readable bit in the first 256 locations of memory. The span
of branch is from –125 to +130 from the opcode address. The state of the tested bit is also
transferred to the carry bit of the condition code register.
EA1 = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
EA2 = PC+3+(PC+2); PC ← EA2 if branch taken;
otherwise PC ← PC+3
TPG
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8
TPG
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9
ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications and associated timing information for the
MC68HC05J3.
9.1
Maximum ratings
Table 9-1 Maximum ratings
Rating
Supply voltage(1)
Input voltage
–ports, OSC1, RESET
Input voltage
– IRQ (bootloader mode)
Operating temperature range
Storage temperature range
Current drain per pin (excluding VDD and VSS)
–Source(2)
–Sink(3)
Symbol
VDD
Unit
V
TSTG
Value
– 0.3 to +7.0
VSS – 0.3 to
VDD + 0.5
VSS – 0.3 to
1.8 x VDD + 0.3
TL to TH
0 to +70
– 65 to +150
ID
IS
25
8
mA
mA
VIN
VIN
TA
V
9
V
°C
°C
(1) All voltages are with respect to VSS.
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
(3) Applicable to PA0–7 and PB0–5; maximum 45mA per device.
Note:
This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given
in the maximum ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either VSS or VDD.
TPG
MC68HC05J3
ELECTRICAL SPECIFICATIONS
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9.2
Thermal characteristics and power considerations
The average chip junction temperature, TJ, in degrees Celsius can be obtained from the following
equation:
T J = T A + ( P D • θ JA )
[1]
where:
TA = Ambient temperature (°C)
θJA = Package thermal resistance, junction-to-ambient (°C/W)
PD = PINT + PI/O (W)
PINT = Internal chip power = IDD • VDD (W)
PI/O = Power dissipation on input and output pins (User determined)
An approximate relationship between PD and TJ (if PI/O is neglected) is:
K
P D = ---------------------T J + 273
[2]
Solving equations [1] and [2] for K gives:
K = P D • ( T A + 273 ) + θ JA • P D2
9
[3]
where K is a constant for a particular part. K can be determined by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained for any value of TA
by solving the above equations. The package thermal characteristics are shown in Table 9-2.
Table 9-2 Package thermal characteristics
Characteristics
Thermal resistance
– 20-pin SOIC package
– 20-pin DIL package
Symbol
Value
Unit
θJA
θJA
60
60
°C/W
°C/W
VDD = 4.5 V
Pins
PA0–7, PB0–5
R1
3.26kΩ
R2
2.38kΩ
C
50pF
R2
Test
point
C
R1
Figure 9-1 Equivalent test load
TPG
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9.3
DC electrical characteristics
Table 9-3 DC electrical characteristics for 5V operation
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH
Characteristic(1)
Symbol
Output high voltage (ILOAD = – 25 µA)
VOH
Output low voltage (ILOAD = +25 µA)
VOL
Output high voltage (ILOAD = – 0.8 mA)
VOH
PA0–7, PB0–5
Output low voltage (ILOAD = +1.6 mA)
VOL
PA0–7, PB0–5
Output low voltage (ILOAD = +8 mA)
VOL
PA0–7, PB0–5
Input high voltage
VIH
PA0–7, PB0–5, OSC1, IRQ, RESET
Input low voltage
VIL
PA0–7, PB0–5, OSC1, IRQ, RESET
Supply current(3)
IDD
RUN (at 2.1 MHz bus frequency)
WAIT (at 2.1 MHz bus frequency)
STOP (oscillators off, 0 to 70°)
I/O ports high-Z leakage current
IOZ
PA0–7, PB0–5
Inputs high-Z leakage current
IOZ
IRQ, RESET, OSC1
Capacitance
Ports (as input or output)
COUT
IRQ, RESET
CIN
Min
VDD – 0.1
—
Typ(2)
—
—
Max
—
0.1
Unit
V
V
VDD – 0.8
VDD – 0.1
—
V
—
0.2
0.4
V
—
0.4
0.8
V
0.7VDD
—
VDD
V
VSS
—
0.2VDD
V
—
—
—
5.0
2.5
1
10
4
100
mA
mA
µA
—
—
±10
µA
—
—
±1
µA
—
—
—
—
12
TBD
pF
pF
9
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the
transient switching currents inherent in CMOS designs (see Section 2.2.1).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2 MHz); all inputs
0.2V from rail; no DC loads; maximum load on outputs 50pF (except OSC2 load 20pF).
WAIT IDD: only the timer system active; current varies linearly with the OSC2 capacitance.
WAIT and STOP IDD: all ports configured as inputs; VIL = 0.2V and VIH = VDD – 0.2V.
STOP IDD: measured with OSC1 = VDD.
TPG
MC68HC05J3
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Table 9-4 DC electrical characteristics for 3.3V operation
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH
Characteristic(1)
Symbol
Output high voltage (ILOAD = – 25 µA)
VOH
Output high voltage (ILOAD = + 25 µA)
VOH
Output high voltage (ILOAD = – 0.2 mA)
VOH
PA0–7, PB0–5
Output low voltage (ILOAD = +0.4 mA)
VOL
PA0–7, PB0–5
Output low voltage (ILOAD = +4 mA)
VOL
PA0–7, PB0–5
Input high voltage
VIH
PA0–7, PB0–5, OSC1, IRQ, RESET
Input low voltage
VIL
PA0–7, PB0–5, OSC1, IRQ, RESET
Supply current(3)
IDD
RUN (at 1.05 MHz bus frequency)
WAIT (at 1.05 MHz bus frequency)
STOP (oscillators off, 0 to 70°)
I/O ports high-Z leakage current
IOZ
PA0–7, PB0–5
Inputs high-Z leakage current
IOZ
IRQ, RESET, OSC1
Capacitance
Ports (as input or output)
COUT
IRQ, RESET
CIN
9
Min
VDD – 0.1
—
Typ(2)
—
—
Max
—
0.1
Unit
V
V
VDD – 0.3
VDD – 0.3
—
V
—
0.2
0.3
V
—
0.4
0.5
V
0.7VDD
—
VDD
V
VSS
—
0.2VDD
V
—
—
—
2.0
1.0
1
5
2
50
mA
mA
µA
—
—
±10
µA
—
—
±1
µA
—
—
—
—
12
TBD
pF
pF
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the
transient switching currents inherent in CMOS designs (see Section 2.2.1).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.1MHz); all inputs
0.2V from rail; no DC loads; maximum load on outputs 50pF (except OSC2 load 20pF).
WAIT IDD: only the timer system active; current varies linearly with the OSC2 capacitance.
WAIT and STOP IDD: all ports configured as inputs; VIL = 0.2V and VIH = VDD – 0.2V.
STOP IDD: measured with OSC1 = VDD.
TPG
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9.4
AC electrical characteristics
Table 9-5 AC electrical characteristics for 5V operation
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH
Characteristic
Symbol
Frequency of operation
Crystal
fOSC
External clock
fOSC
Internal operating frequency
Crystal (fOSC /2)
fOP
External clock (fOSC /2)
fOP
Processor cycle time
tCYC
Ceramic resonator start-up time
tOXOV
Ceramic resonator STOP recovery start-up time
tILCH
OSC1 pulse width
tOH, tOL
RESET pulse width
tRL
16-bit timer
Resolution(1)
tRESL
Input capture pulse width
tTLTH
Input capture pulse period
tTLTL
Power-on reset delay
tPORL
Interrupt pulse width low (edge-triggered)
tILIH
Interrupt pulse period (see Figure 9-2)
tILIL
Min
Max
Unit
—
dc
4.2
4.2
MHz
MHz
—
dc
480
—
—
90
1.5
2.1
2.1
—
10
10
—
—
MHz
MHz
ns
ms
ms
ns
tCYC
—
250
4
—
—
4064
—
—
tCYC
ns
tCYC
tCYC
ns
tCYC
(2)
4064
125
(3)
(1) Since the 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in
determining the timer resolution.
9
(2) The minimum period tTLTL should not be less than the number of cycles it takes to execute the capture
interrupt service routine plus 24 tCYC.
(3) The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt
service routine plus 21 tCYC.
TPG
MC68HC05J3
ELECTRICAL SPECIFICATIONS
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Table 9-6 AC electrical characteristics for 3.3V operation
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH
Characteristic
Symbol
Frequency of operation
Crystal
fOSC
External clock
fOSC
Internal operating frequency
Crystal (fOSC /2)
fOP
External clock (fOSC /2)
fOP
Processor cycle time
tCYC
Ceramic resonator start-up time
tOXOV
Ceramic resonator STOP recovery start-up time
tILCH
OSC1 pulse width
tOH, tOL
RESET pulse width
tRL
16-bit timer
Resolution(1)
tRESL
Input capture pulse width
tTLTH
Input capture pulse period
tTLTL
Power-on reset delay
tPORL
Interrupt pulse width low (edge-triggered)
tILIH
Interrupt pulse period (see Figure 9-2)
tILIL
Min
Max
Unit
—
dc
2.1
2.1
MHz
MHz
—
dc
1000
—
—
200
1.5
1.05
1.05
—
20
20
—
—
MHz
MHz
ns
ms
ms
ns
tCYC
—
500
4
—
—
4064
—
—
tCYC
ns
tCYC
tCYC
ns
tCYC
(2)
4064
250
(3)
(1) Since the 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in
determining the timer resolution.
(2) The minimum period tTLTL should not be less than the number of cycles it takes to execute the capture
interrupt service routine plus 24 tCYC.
(3) The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt
service routine plus 21 tCYC.
9
IRQ
tILIH
tILIL
Edge-sensitive trigger — The minimum tILIH is either 125ns (V DD =5V) or 250ns (V DD =3.3V). The minimum period
tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 tCYC.
Edge and level sensitive trigger — If IRQ remains low after the initial interrupt is serviced, the MCU recognises the
interrupt until the IRQ line returns to a high level.
Figure 9-2 External interrupt timing
TPG
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MECHANICAL DATA
The MC68HC05J3 is available in both 20-pin SOIC and 20-pin PDIP packages.
OSC1
OSC2
TCAP/PB5
TCMP/PB4
PB3
PB2
PB1
PB0
VDD
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
IRQ
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Figure 10-1 20-pin SOIC pinout
OSC1
OSC2
TCAP/PB5
TCMP/PB4
PB3
PB2
PB1
PB0
VDD
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
IRQ
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
10
Figure 10-2 20-pin PDIP pinout
TPG
MC68HC05J3
MECHANICAL DATA
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–A–
–B–
Case 751D-03
P
0.25
M B M
10 PL
1
R x 45°
G
J
C
0.25
Dim.
A
B
C
D
F
G
M
Min.
Max.
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
10
Seating
plane
K
D 20 PL
T B S
–T–
F
A S
Notes
1.
2.
3.
4.
5.
M
Dimensions ‘A’ and ‘B’ are datums and ‘T’ is a datum surface.
Dimensioning and tolerancing per ANSI Y14.5M, 1982.
All dimensions in mm.
Dimensions ‘A’ and ‘B’ do not include mould protrusion.
Maximum mould protrusion is 0.15 mm per side.
Dim.
J
K
M
P
R
—
Min.
0.25
0.10
0°
10.05
0.25
—
Max.
0.32
0.25
7°
10.55
0.75
—
Figure 10-3 20-pin SOIC mechanical dimensions
TPG
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A
B
Case 738-03
1
G
L
N
C
K
M
E
F
J
D
Seating
plane
Dim.
A
B
C
D
E
F
Min.
Max.
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
Notes
1. All dimensions in mm.
2. Positional tolerance of leads (‘D’) shall be within 0.25 mm at
maximum material condition, in relation to seating plane and to
each other.
3. Dimension ‘L’ is to centre of leads when formed parallel.
4. Dimension ‘B’ does not include mould protrusion.
Dim.
G
J
K
L
M
N
Min.
Max.
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0°
15°
0.51
1.01
10
Figure 10-4 20-pin PDIP mechanical dimensions
TPG
MC68HC05J3
MECHANICAL DATA
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MECHANICAL DATA
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ORDERING INFORMATION
This section describes the information needed to order the MC68HC05J3.
To initiate a ROM pattern for the MCU, it is necessary to contact your local field service office, local
sales person or Motorola representative. Please note that you will need to supply details such as:
mask option selections; temperature range; oscillator frequency; package type; electrical test
requirements; and device marking details so that an order can be processed, and a customer
specific part number allocated. Refer to Table 11-1 for appropriate part numbers.
Table 11-1 MC order numbers
Device title
Package type
20-pin plastic PDIP
MC68HC05J3
20-pin SOIC
11.1
Temperature
0 to +70°C
–40 to + 85°C
0 to +70°C
–40 to + 85°C
Part number
MC68HC05J3P
MC68HC05J3CP
MC68HC05J3DW
MC68HC05J3CDW
EPROMS
A 4 kbyte EPROM programmed with the customer’s software (positive logic for address and data)
should be submitted for pattern generation. All unused bytes should be programmed to $00.
11
The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed.
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MC68HC05J3
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11.2
Verification media
All original pattern media (EPROMs) are filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and returned with a listing verification form.
The listing should be thoroughly checked and the verification form completed, signed and returned
to Motorola. The signed verification form constitutes the contractual agreement for creation of the
custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from
the data file used to create the custom mask, to aid in the verification process.
11.3
ROM verification units (RVU)
Ten MCUs containing the customer’s ROM pattern will be provided for program verification. These
units will have been made using the custom mask but are for ROM verification only. For
expediency, they are usually unmarked and are tested only at room temperature (25°C) and at
5 Volts. These RVUs are included in the mask charge and are not production parts. They are
neither backed nor guaranteed by Motorola Quality Assurance.
11
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GLOSSARY
This section contains abbreviations and specialist words used in this data
sheet and throughout the industry. Further information on many of the terms
may be gleaned from Motorola’s M68HC11 Reference Manual,
M68HC11RM/AD, or from a variety of standard electronics text books.
$xxxx
The digits following the ‘$’ are in hexadecimal format.
%xxxx
The digits following the ‘%’ are in binary format.
A/D, ADC
Analog-to-digital (converter).
Bootstrap mode
In this mode the device automatically loads its internal memory from an
external source on reset and then allows this program to be executed.
Byte
Eight bits.
CCR
Condition codes register; an integral part of the CPU.
CERQUAD
A ceramic package type, principally used for EPROM and high temperature
devices.
Clear
‘0’ — the logic zero state; the opposite of ‘set’.
CMOS
Complementary metal oxide semiconductor. A semiconductor technology
chosen for its low power consumption and good noise immunity.
COP
Computer operating properly. aka ‘watchdog’. This circuit is used to detect
device runaway and provide a means for restoring correct operation.
CPU
Central processing unit.
D/A, DAC
Digital-to-analog (converter).
EEPROM
Electrically erasable programmable read only memory. aka ‘EEROM’.
EPROM
Erasable programmable read only memory. This type of memory requires
exposure to ultra-violet wavelengths in order to erase previous data. aka
‘PROM’.
ESD
Electrostatic discharge.
Expanded mode
In this mode the internal address and data bus lines are connected to
external pins. This enables the device to be used in much more complex
systems, where there is a need for external memory for example.
TPG
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GLOSSARY
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EVS
Evaluation system. One of the range of platforms provided by Motorola for
evaluation and emulation of their devices.
HCMOS
High-density complementary metal oxide semiconductor. A semiconductor
technology chosen for its low power consumption and good noise immunity.
I/O
Input/output; used to describe a bidirectional pin or function.
Input capture
(IC) This is a function provided by the timing system, whereby an external
event is ‘captured’ by storing the value of a counter at the instant the event
is detected.
Interrupt
This refers to an asynchronous external event and the handling of it by the
MCU. The external event is detected by the MCU and causes a
predetermined action to occur.
IRQ
Interrupt request. The overline indicates that this is an active-low signal
format.
K byte
A kilo-byte (of memory); 1024 bytes.
LCD
Liquid crystal display.
LSB
Least significant byte.
M68HC05
Motorola’s family of 8-bit MCUs.
MCU
Microcontroller unit.
MI BUS
Motorola interconnect bus. A single wire, medium speed serial
communications protocol.
MSB
Most significant byte.
Nibble
Half a byte; four bits.
NRZ
Non-return to zero.
Opcode
The opcode is a byte which identifies the particular instruction and operating
mode to the CPU.
Operand
The operand is a byte containing information the CPU needs to execute a
particular instruction.
Output compare
(OC) This is a function provided by the timing system, whereby an external
event is generated when an internal counter value matches a predefined
value.
PLCC
Plastic leaded chip carrier package.
PLL
Phase-locked loop circuit. This provides a method of frequency
multiplication, to enable the use of a low frequency crystal in a high
frequency circuit.
Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are
permanently connected to either ground or VDD.
G
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PWM
Pulse width modulation. This term is used to describe a technique where the
width of the high and low periods of a waveform is varied, usually to enable
a representation of an analog value.
QFP
Quad flat pack package.
RAM
Random access memory. Fast read and write, but contents are lost when
the power is removed.
RFI
Radio frequency interference.
RTI
Real-time interrupt.
ROM
Read-only memory. This type of memory is programmed during device
manufacture and cannot subsequently be altered.
RS-232C
A standard serial communications protocol.
SAR
Successive approximation register.
SCI
Serial communications interface.
Set
‘1’ — the logic one state; the opposite of ‘clear’.
Silicon glen
An area in the central belt of Scotland, so called because of the
concentration of semiconductor manufacturers and users found there.
Single chip mode
In this mode the device functions as a self contained unit, requiring only I/O
devices to complete a system.
SPI
Serial peripheral interface.
Test mode
This mode is intended for factory testing.
TTL
Transistor-transistor logic.
UART
Universal asynchronous receiver transmitter.
VCO
Voltage controlled oscillator.
Watchdog
see ‘COP’.
Wired-OR
A means of connecting outputs together such that the resulting composite
output state is the logical OR of the state of the individual outputs.
Word
Two bytes; 16 bits.
XIRQ
Non-maskable interrupt request. The overline indicates that this has an
active-low signal format.
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INTRODUCTION
1
MODES OF OPERATION AND PIN DESCRIPTIONS
2
MEMORY AND REGISTERS
3
INPUT/OUTPUT PORTS
4
CORE TIMER
5
16-BIT PROGRAMMABLE TIMER
6
RESETS AND INTERRUPTS
7
CPU CORE AND INSTRUCTION SET
8
ELECTRICAL SPECIFICATIONS
9
MECHANICAL DATA
10
ORDERING INFORMATION
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1
INTRODUCTION
2
MODES OF OPERATION AND PIN DESCRIPTIONS
3
MEMORY AND REGISTERS
4
INPUT/OUTPUT PORTS
5
CORE TIMER
6
16-BIT PROGRAMMABLE TIMER
7
RESETS AND INTERRUPTS
8
CPU CORE AND INSTRUCTION SET
9
ELECTRICAL SPECIFICATIONS
10
MECHANICAL DATA
11
ORDERING INFORMATION
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