Freescale Semiconductor, Inc. Order this document by MC68L300EC16/D MC68L300 Technical Supplement 16.78 MHz Electrical Characteristics Freescale Semiconductor, Inc... Devices in the M68300 Modular Microcontroller Family are built up from a selection of standard functional modules. The MC68331 and MC68332 contain the same central processing unit (CPU32) and system integration module (SIM), and thus have similar electrical characteristics. M68300 devices that operate at 3.3 volts are now available. This publication contains electrical characteristics that supplement the MC68331 User's Manual (MC68331UM/AD) and the MC68332 User's Manual (MC68332UM/AD). MC68L331 and MC68L332 are currently offered for operation in external clock mode only. Enhanced versions of the MC68331 and MC68332 will offer extended VDD operating range, PLL, 5 volt tolerant I/O, and higher frequency. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc... Maximum Ratings .................................................................................................................................3 MC68L331 Typical Ratings ...................................................................................................................3 MC68L332 Typical Ratings ...................................................................................................................4 Thermal Characteristics ........................................................................................................................4 16.78 MHz DC Characteristics ..............................................................................................................5 16.78 MHz AC Timing ...........................................................................................................................7 Background Debugging Mode Timing .................................................................................................17 ECLK Bus Timing ................................................................................................................................18 QSPI Timing ........................................................................................................................................19 Time Processor Unit Timing ................................................................................................................22 General-Purpose Timer AC Characteristics ........................................................................................23 2 For More Information On This Product, Go to: www.freescale.com MC68L300 MC68L300EC16/D Freescale Semiconductor, Inc. Table 1 Maximum Ratings Freescale Semiconductor, Inc... Num Rating Symbol Value Unit 1 Supply Voltage1,2,3 VDD – 0.3 to + 6.5 V 2 Input Voltage 1,2,3,4,5,7 VIN – 0.3 to + 6.5 V 3 Instantaneous Maximum Current Single Pin Limit (all pins)1,3,5,6 ID 25 mA 4 Operating Maximum Current Digital Input Disruptive Current3,5,6,7,8 VNEGCLMAP ≅ – 0.3 V VPOSCLAMP ≅ VDD + 0.3 Iid – 500 to 500 µA 5 Operating Temperature Range C Suffix TA TL to TH – 40 to 85 °C 6 Storage Temperature Range Tstg – 55 to 150 °C NOTES: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3. This parameter is periodically sampled rather than 100% tested. 4. All pins except TSC. 5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current. 7. All functional non-supply pins are internally clamped to VSS. All functional pins except EXTAL and XFC are internally clamped to VDD. 8. Total input current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. Table 2 MC68L331 Typical Ratings Num Rating Symbol Value Unit VDD 3.3 V Operating Temperature TA 25 °C 3 VDD Supply Current RUN LPSTOP, External clock, max fsys IDD 38 1.0 mA mA 4 Clock Synthesizer Operating Voltage VDDSYN 3.3 V 5 VDDSYN Supply Current External Clock, maximum fsys IDDSYN 1.5 mA 6 RAM Standby Current Normal RAM operation Standby operation ISB 3.0 10 µA µA 7 Power Dissipation PD 125.0 mW 1 Supply Voltage 2 MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. Table 3 MC68L332 Typical Ratings Freescale Semiconductor, Inc... Num Rating Symbol Value Unit VDD 3.3 V 1 Supply Voltage 2 Operating Temperature TA 25 °C 3 VDD Supply Current RUN LPSTOP, External clock, max fsys IDD 45 1.0 mA mA 4 Clock Synthesizer Operating Voltage VDDSYN 3.3 V 5 VDDSYN Supply Current External Clock, maximum fsys IDDSYN 2.0 mA 6 RAM Standby Current Normal RAM operation Standby operation ISB 3.0 10 µA µA 7 Power Dissipation PD 148.0 mW Table 4 Thermal Characteristics Num Rating Symbol Thermal Resistance Plastic 132-Pin Surface Mount ΘJA Plastic 144-Pin Surface Mount The average chip-junction temperature (TJ) in C can be obtained from: T = T + ( P × Θ ) (1) 1 J A D Value Unit 38 49 °C/W JA where: TA = Ambient Temperature, °C ΘJA= Package Thermal Resistance, Junction-to-Ambient, °C/W PD = PINT + PI/O PINT= IDD × VDD, Watts — Chip Internal Power PI/O= Power Dissipation on Input and Output Pins — User Determined For most applications PI/O < PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: P = K ÷ ( T + 273°C ) (2) D J Solving equations 1 and 2 for K gives: K = P D + ( T A + 273°C ) + Θ JA × P D 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. 4 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 5 16.78 MHz DC Characteristics (VDD and VDDSYN = 3.0 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH) Num Characteristic Symbol 1 Input High Voltage VIH 2 Input Low Voltage VIL 3 Input Hysteresis1 VHYS Input Leakage Current 2 Iin 4 Vin = VDD or VSS Input-only pins High Impedance (Off-State) Leakage Current2 IOZ 5 Vin = VDD or VSS All input/output and output pins CMOS Output High Voltage2, 3 VOH 6 IOH = –10.0 µA Group 1, 2, 4 input/output and all output pins CMOS Output Low Voltage2 VOL 7 IOL = 10.0 µA Group 1, 2, 4 input/output and all output pins Output High Voltage2, 3 VOH 8 IOH = –0.4 mA Group 1, 2, 4 input/output and all output pins Output Low Voltage2 IOL = 0.8 mA Group 1 I/O pins CLKOUT, FREEZE/QUOT, IPIPE/DSO 9 VOL IOL = 2.6 mA Group 2 and group 4 I/O pins, CSBOOT, BG/CS1 IOL = 6.0 mA Group 3 10 Three State Control Input High Voltage VIHTSC Data Bus Mode Select Pull-up Current 4 Vin = VIL IMSP 11 Vin = VIH MC68331 VDD Supply Current5 Run IDD 12A LPSTOP, external clock input = max fsys MC68332 VDD Supply Current5 Run IDD 12B LPSTOP, external clock input = max fsys 13 Clock Synthesizer Operating Voltage VDDSYN 2.5 µA –2.5 2.5 µA VDD –0.2 — V — 0.2 V VDD –0.5 — V — — — 2.4 (VDD) 0.4 0.4 0.4 9.1 V — –8 –95 — µA — — 49 2 mA mA — — 3.0 56 2 3.6 mA mA V 3 mA 0.0 2.7 VDD 3.6 V — — — 10 3 50 µA mA µA PD PD — — 187 212 mW mW Cin — — 10 20 pF — — — — 90 100 100 100 VDDSYN Supply Current External Clock, maximum fsys IDDSYN 15 MC68332 RAM Standby Voltage Specified VDD applied VDD = VSS VSB 16 Transient condition Standby operation VSB – 0.5 V ≥ VDD ≥ VSS + 0.5 V MC68L300EC16/D ISB VDD < VSS + 0.5 V 17A MC68331 Power Dissipation8 17B MC68332 Power Dissipation Input Capacitance2, 9 All input-only pins 18 All input/output pins Load Capacitance2 Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE Group 2 I/O Pins and CSBOOT, BG/CS 19 Group 3 I/O Pins Group 4 I/O Pins Max Unit VDD + 0.3 V V 0.2 (VDD) — V –2.5 14 MC68332 RAM Standby Current6, 7 Normal RAM operation VDD > VSB – 0.5 V Min 0.7 (VDD) VSS – 0.3 0.5 CL For More Information On This Product, Go to: www.freescale.com — V pF 5 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES: 1. Applies to: QSM pins IRQ[7:1], RESET, EXTAL, TSC, RMC, BKPT/DSCLK, IFETCH/DSI 2. Input-Only Pins: TSC, BKPT/DSCLK, RXD Output-Only Pins: CSBOOT, BG/CS, CLKOUT, FREEZE/QUOT, IPIPE/DSO Input/Output Pins: Group 1: DATA[15:0], IFETCH/DSI Group 2: ADDR[23:19]/CS[10:6], FC[2:0]/CS[5:3], DSACK[1:0], AVEC, RMC, DS, AS, SIZ[1:0] IRQ[7:1], MODCLK, ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2, PCS[3:1], PCS0/SS, TXD Group 3: HALT, RESET Group 4: MISO, MOSI, SCK 3. Does not apply to HALT and RESET because they are open drain pins. Does not apply to Port QS[7:0] (TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode. 4. Current measured at maximum system clock frequency. 5. Total operating current is the sum of the appropriate VDD supply and VDDSYN supply current. 6. When VSB is more than 0.3V greater than VDD, current flows between the VSTBY and VDD pins, which causes standby current to increase toward the maximum condition specification. System noise on the VDD and VSTBY pin can contribute to this condition. 7. The SRAM module will not switch into standby mode as long as VSB does not exceed VDD by more than 0.5 volts. The SRAM array cannot be accessed while the module is in standby mode. 8. Power dissipation measured at specified system clock frequency. Power dissipation can be calculated using the expression: PD = 3.6V (IDDSYN + IDD) 9. Input capacitance is periodically sampled rather than 100% tested. 6 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 6 16.78 MHz AC Timing (VDD and VDDSYN = 3.0 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH)1 Num F1 1 1A 1B 2, 3 2A, 3A 2B, 3B 4, 5 4A, 5A 4B, 5B 6 7 8 9 9A 9C 11 12 12A 13 14 14A 14B 15 16 17 18 20 21 22 23 24 25 26 27 27A 28 29 29A 30 30A 31 33 35 37 39 39A 46 Characteristic Frequency of Operation Clock Period ECLK Period External Clock Input Period2 Clock Pulse Width ECLK Pulse Width External Clock Input High/Low Time2 CLKOUT Rise and Fall Time Rise and Fall Time (All outputs except CLKOUT) External Clock Input Rise and Fall Time Clock High to ADDR, FC, RMC, SIZ Valid Clock High to ADDR, Data, FC, RMC,SIZ High Impedance Clock High to ADDR, FC, RMC, SIZ Invalid Clock Low to AS, DS, CS Asserted AS to DS or CS Asserted (Read)3 Clock Low to IFETCH, IPIPE Asserted ADDR, FC, RMC, SIZ Valid to AS, CS, (and DS Read) Asserted Clock Low to AS, DS, CS Negated Clock Low to IFETCH, IPIPE Negated AS, DS, CS Negated to ADDR, FC, SIZ Invalid (Address Hold) AS, CS (and DS Read) Width Asserted DS, CS Width Asserted (Write) AS, CS (and DS Read) Width Asserted (Fast Cycle) AS, DS, CS Width Negated4 Clock High to AS, DS, R/W High Impedance AS, DS, CS Negated to R/W High Clock High to R/W High Clock High to R/W Low R/W High to AS, CS Asserted R/W Low to DS, CS Asserted (Write) Clock High to Data Out Valid Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) DS, CS Negated to Data Out Invalid (Data Out Hold) Data Out Valid to DS, CS Asserted (Write) Data In Valid to Clock Low (Data Setup) Late BERR, HALT Asserted to Clock Low (Setup Time) AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated DS, CS Negated to Data In Invalid (Data In Hold)5 DS, CS Negated to Data In High Impedance5, 6 CLKOUT Low to Data In Invalid (Fast Cycle Hold)5 CLKOUT Low to Data In High Impedance5 DSACK[1:0] Asserted to Data In Valid7 Clock Low to BG Asserted/Negated BR Asserted to BG Asserted (RMC not Asserted)8 BGACK Asserted to BG Negated BG Width Negated BG Width Asserted R/W Width Asserted (Write or Read) MC68L300EC16/D Symbol fsys tcyc tEcyc tXcyc tCW tECW tXCHL tCrf trf tXCrf tCHAV tCHAZx tCHAZn tCLSA tSTSA tCLIA tAVSA tCLSN tCLIN tSNAI tSWA tSWAW tSWDW tSN tCHSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO tDVASN tSNDOI tDVSA tDICL tBELCL tSNDN tSNDI tSHDI tCLDI tCLDH tDADI tCLBAN tBRAGA tGAGN tGH tGA tRWA For More Information On This Product, Go to: www.freescale.com Min — 59.6 476 59.6 24 236 29.8 — — — 0 0 0 0 –15 2 15 2 2 15 100 45 40 40 — 15 0 0 15 70 — 15 15 15 5 20 0 0 — 10 — — — 1 1 2 1 150 Max Unit 16.78 MHz — ns — ns — ns — ns — ns — ns 7 ns 8 ns 4 ns 29 ns 59 ns — ns 25 ns 15 ns 22 ns — ns 29 ns 29 ns — ns — ns — ns — ns — ns 59 ns — ns 29 ns 29 ns — ns — ns 29 ns — ns — ns — ns — ns — ns 80 ns — ns 55 ns — ns 90 ns 50 ns 29 ns — tcyc 2 tcyc — tcyc — tcyc — ns 7 Freescale Semiconductor, Inc. Table 6 16.78 MHz AC Timing (Continued) (VDD and VDDSYN = 3.0 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH)1 Num 46A 47A Freescale Semiconductor, Inc... 47B 48 53 54 55 70 71 72 73 74 75 76 77 78 Characteristic R/W Width Asserted (Fast Write or Read Cycle) Asynchronous Input Setup Time BR, BGACK, DSACK[1:0], BERR, AVEC, HALT Asynchronous Input Hold Time DSACK[1:0] Asserted to BERR, HALT Asserted9 Data Out Hold from Clock High Clock High to Data Out High Impedance R/W Asserted to Data Bus Impedance Change Clock Low to Data Bus Driven (Show Cycle) Data Setup Time to Clock Low (Show Cycle) Data Hold from Clock Low (Show Cycle) BKPT Input Setup Time BKPT Input Hold Time Mode Select Setup Time Mode Select Hold Time RESET Assertion Time10 RESET Rise Time11,12 Symbol tRWAS Min 90 Max — Unit ns tAIST 5 — ns tAIHT tDABA tDOCH tCHDH tRADC tSCLDD tSCLDS tSCLDH tBKST tBKHT tMSS tMSH tRSTA tRSTR 15 — 0 — 40 0 15 10 15 10 20 0 4 — — 30 — 28 — 29 — — — — — — — 10 ns ns ns ns ns ns ns ns ns ns tcyc ns tcyc tcyc NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable tXcyc period is reduced when the duty cycle of the external clock varies. The relationship between external clock input duty cycle and minimum tXcyc is expressed: Minimum tXcyc period = minimum tXCHL / (50% – external clock input duty cycle tolerance). 3. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside the limits shown in specification 9. 4. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles. 5. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads. The user is free to use either hold time. 6. Maximum value is equal to (tcyc / 2) + 25 ns. 7. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle. 8. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles of the current operand transfer are complete. 9. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification 47A). 10. After external RESET negation is detected, a short transition period (approximately 2) tcyc elapses, then the SIM drives RESET low for 512 tcyc. 11. External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles. 12. External logic must pull RESET high during this period in order for normal MCU operation to begin. 8 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. 1 2 4 3 CLKOUT 5 68300 CLKOUT TIM Freescale Semiconductor, Inc... Figure 1 CLKOUT Output Timing Diagram 1B 2B 4B 3B EXTAL 5B NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% VDD. PULSE WIDTH SHOWN WITH RESPECT TO 50% VDD. 68300 EXT CLK INPUT TIM Figure 2 External Clock Input Timing Diagram 1A 2A 4A 3A ECLK 5A NOTE: TIMING SHOWN WITH RESPECT TO 20% AND 70% VDD. 68300 ECLK OUTPUT TIM Figure 3 ECLK Output Timing Diagram MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 CLKOUT 8 6 ADDR[23:20] FC[2:0] SIZ[1:0] 11 15 14 AS 13 Freescale Semiconductor, Inc... 9 DS 9A 12 CS 17 18 20 21 R/W 46 DSACK0 47A 28 DSACK1 29 31 DATA[15:0] 27 29A BERR 48 27A HALT 9C 12A 12A IFETCH 73 74 BKPT 47A 47B ASYNCHRONOUS INPUTS 68300 RD CYC TIM Figure 4 Read Cycle Timing Diagram 10 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 CLKOUT 6 8 ADDR[23:20] FC[2:0] SIZ[1:0] 11 15 14 AS 13 Freescale Semiconductor, Inc... 9 DS 21 9 12 CS 20 22 14A 17 R/W 46 DSACK0 47A 28 DSACK1 55 25 DATA[15:0] 23 26 54 53 BERR 48 27A HALT 74 73 BKPT 68300 WR CYC TIM Figure 5 Write Cycle Timing Diagram MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 11 Freescale Semiconductor, Inc. S0 S1 S4 S5 S0 CLKOUT 8 6 ADDR[23:0] FC[2:0] SIZ[1:0] 14B AS 12 9 Freescale Semiconductor, Inc... DS CS 20 18 46A R/W 30 27 30A DATA[15:0] 29A 73 29 BKPT 74 68300 FAST RD CYC TIM Figure 6 Fast Termination Read Cycle Timing Diagram 12 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. S0 S1 S4 S5 S0 CLKOUT 6 8 ADDR[23:0] FC[2:0] SIZ[1:0] 14B AS 9 12 Freescale Semiconductor, Inc... DS CS 46A 20 R/W 23 24 18 DATA[15:0] 73 25 BKPT 74 68300 FAST WR CYC TIM Figure 7 Fast Termination Write Cycle Timing Diagram MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 S98 A5 A5 A2 CLKOUT ADDR[23:0] 7 DATA[15:0] AS 16 Freescale Semiconductor, Inc... DS R/W DSACK0 DSACK1 47A BR 39A 35 BG 33 33 BGACK 37 68300 BUS ARB TIM Figure 8 Bus Arbitration Timing Diagram — Active Bus Case 14 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. A0 A5 A5 A2 A3 A0 CLKOUT ADDR[23:0] DATA[15:0] AS 47A 47A BR Freescale Semiconductor, Inc... 35 37 BG 33 47A 33 BGACK 68300 BUS ARB TIM IDLE Figure 9 Bus Arbitration Timing Diagram — Idle Bus Case S0 S41 S42 S43 S0 S1 S2 CLKOUT 6 8 ADDR[23:0] 18 R/W 20 AS 9 12 15 DS 71 70 72 DATA[15:0] 73 74 BKPT SHOW CYCLE START OF EXTERNAL CYCLE NOTE: Show cycles can stretch during clock phase S42 when bus accesses take longer than two cycles due to IMB module wait-state insertion. 68300 SHW CYC TIM Figure 10 Show Cycle Timing Diagram MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKOUT 6 8 6 ADDR[23:0] FC[2:0] SIZ[1:0] 14 11 11 14 13 AS 15 Freescale Semiconductor, Inc... 9 9 DS 9 17 17 21 12 21 12 CS 20 18 18 14A 46 R/W 46 29 25 55 DATA[15:0] 27 29A 53 23 54 68300 CHIP SEL TIM Figure 11 Chip-Select Timing Diagram 77 78 RESET 75 DATA[15:0] 76 68300 RST/MODE SEL TIM Figure 12 Reset and Mode Select Timing Diagram 16 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. Table 7 Background Debugging Mode Timing (VDD and VDDSYN = 3.0 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH)1 Freescale Semiconductor, Inc... Num Characteristic Symbol Min Max Unit B0 DSI Input Setup Time tDSISU 15 — ns B1 DSI Input Hold Time tDSIH 10 — ns B2 DSCLK Setup Time tDSCSU 15 — ns B3 DSCLK Hold Time tDSCH 10 — ns B4 DSO Delay Time B5 DSCLK Cycle Time B6 CLKOUT Low to FREEZE Asserted/Negated B7 CLKOUT High to IFETCH High Impedance B8 CLKOUT High to IFETCH Valid B9 DSCLK Low Time tDSOD — 25 ns tDSCCYC 2 — tcyc tFRZAN — 50 ns tIPZ — 50 ns tIP — 50 ns tDSCLO 1 — tcyc NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. CLKOUT FREEZE B3 B2 BKPT/DSCLK B9 B5 B1 B0 IFETCH/DSI B4 IPIPE/DSO 68300 BKGD DBM SER COM TIM Figure 13 BDM Serial Communication Timing Diagram CLKOUT B6 FREEZE B7 B6 IFETCH/DSI B8 68300 BDM FRZ TIM Figure 14 BDM Freeze Assertion Timing Diagram MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 17 Freescale Semiconductor, Inc. Table 8 ECLK Bus Timing (VDD and VDDSYN = 3.0 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH)1 Freescale Semiconductor, Inc... Num Characteristic Symbol Valid2 Min Max Unit E1 ECLK Low to Address tEAD — 60 ns E2 ECLK Low to Address Hold tEAH 15 — ns E3 ECLK Low to CS Valid (CS Delay) tECSD — 150 ns E4 ECLK Low to CS Hold tECSH 15 — ns E5 CS Negated Width tECSN 30 — ns E6 Read Data Setup Time tEDSR 30 — ns E7 Read Data Hold Time tEDHR 5 — ns E8 ECLK Low to Data High Impedance tEDHZ — 60 ns E9 CS Negated to Data Hold (Read) tECDH 0 — ns E10 CS Negated to Data High Impedance tECDZ — 1 tcyc E11 ECLK Low to Data Valid (Write) tEDDW — 2 tcyc E12 ECLK Low to Data Hold (Write) tEDHW 15 — ns (Read)3 E13 Address Access Time tEACC 386 — ns E14 Chip-Select Access Time (Read)4 tEACS 296 — ns E15 Address Setup Time tEAS 1/2 — tcyc NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low. 3. Address access time = tEcyc – tEAD – tEDSR. 4. Chip select access time = tEcyc – tECSD – tEDSR. CLKOUT 2A 3A ECLK 1A R/W E1 E2 ADDR[23:0] E3 E14 E5 E4 E6 CS E15 E9 E13 DATA[15:0] READ WRITE E7 E8 E11 DATA[15:0] E10 WRITE E12 68300 E CYCLE TIM Figure 15 ECLK Timing Diagram 18 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. Table 9 QSPI Timing (VDD and VDDSYN = 3.0 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH , 100 pF load on all QSPI pins)1 Freescale Semiconductor, Inc... Num Function Symbol Min Max Unit fop DC DC 1/4 1/4 fsys fsys 1 Operating Frequency Master Slave 2 Cycle Time Master Slave tqcyc 4 4 510 — tcyc tcyc 3 Enable Lead Time Master Slave tlead 2 2 128 — tcyc tcyc 4 Enable Lag Time Master Slave tlag — 2 1/2 — SCK tcyc 5 Clock (SCK) High or Low Time Master Slave2 tsw 2 tcyc – 60 2 tcyc – n 255 tcyc — ns ns 6 Sequential Transfer Delay Master Slave (Does Not Require Deselect) ttd 17 13 8192 — tcyc tcyc 7 Data Setup Time (Inputs) Master Slave tsu 30 20 — — ns ns 8 Data Hold Time (Inputs) Master Slave thi 0 20 — — ns ns 9 Slave Access Time ta — 1 tcyc 10 Slave MISO Disable Time tdis — 2 tcyc 11 Data Valid (after SCK Edge) Master Slave tv — — 50 50 ns ns 12 Data Hold Time (Outputs) Master Slave tho 0 0 — — ns ns 13 Rise Time Input Output tri tro — — 2 30 µs ns 14 Fall Time Input Output tfi tfo — — 2 30 µs ns NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. For high time, n = External SCK rise time; for low time, n = External SCK fall time. MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 19 Freescale Semiconductor, Inc. 3 2 PCS[3:0] OUTPUT 5 13 12 SCK CPOL=0 OUTPUT 4 1 SCK CPOL=1 OUTPUT 6 12 4 13 7 Freescale Semiconductor, Inc... MISO INPUT MSB IN DATA LSB IN 11 MOSI OUTPUT MSB OUT PD MSB IN 10 DATA LSB OUT PORT DATA 13 MSB OUT 12 68300 QSPI MAST CPHA0 Figure 16 QSPI Timing — Master, CPHA = 0 3 2 PCS[3:0] OUTPUT 5 13 12 1 SCK CPOL=0 OUTPUT 4 1 7 SCK CPOL=1 OUTPUT 12 4 13 6 MISO INPUT DATA MSB IN 11 MOSI OUTPUT MSB OUT PORT DATA 13 LSB IN MSB 10 DATA LSB OUT PORT DATA MSB 12 68300 QSPI MAST CPHA1 Figure 17 QSPI Timing — Master, CPHA = 1 20 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. 3 2 SS INPUT 5 13 12 SCK CPOL=0 INPUT 4 1 SCK CPOL=1 INPUT 12 4 Freescale Semiconductor, Inc... 8 MISO OUTPUT 13 MSB OUT 11 10 11 DATA 9 LSB OUT PD MSB OUT 13 7 6 MOSI INPUT MSB IN DATA LSB IN MSB IN 68300 QSPI SLV CPHA0 Figure 18 QSPI Timing — Slave, CPHA = 0 SS INPUT 5 1 13 4 12 SCK CPOL=0 INPUT 4 2 3 SCK CPOL=1 INPUT 12 13 10 10 8 MISO OUTPUT PD MSB OUT 9 11 DATA SLAVE LSB OUT PD 12 7 6 MOSI INPUT MSB IN DATA LSB IN 68300 QSPI SLV CPHA1 Figure 19 QSPI Timing — Slave, CPHA = 1 MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 21 Freescale Semiconductor, Inc. Table 10 Time Processor Unit Timing (VDD and VDDA = 3.0 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH)1 Num Parameter Valid2, 3, 4 1 CLKOUT High to TPU Output Channel 2 CLKOUT High to TPU Output Channel Hold 3 TPU Input Channel Pulse Width Symbol Min Max Unit tCHTOV 2 23 ns tCHTOH 0 20 ns tTIPW 4 — tcyc Freescale Semiconductor, Inc... NOTES: 1. AC Timing is shown with respect to 20% VDD and 70% VDD levels. 2. Timing not valid for external T2CLK input. 3. Maximum load capacitance for CLKOUT pin is 90 pF. 4. Maximum load capacitance for TPU output pins is 100 pF. CLKOUT 2 1 TPU OUTPUT TPU INPUT 3 TPU I/O TIM Figure 20 TPU Timing Diagram 22 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. Table 11 General-Purpose Timer AC Characteristics Freescale Semiconductor, Inc... Num Parameter Symbol Min Max Unit 1 Operating Frequency Fclock 0 16.77 MHz 2 PCLK Frequency Fpclk 0 1/4 Fclock MHz 3 Pulse Width Input Capture PWtim 2/Fclock — — 4 PWM Resolution — 2/Fclock — — 5 IC/OC Resolution — 4/Fclock — — 6 PCLK Width (PWM) — 4/Fclock — — 7 PCLK Width (IC/OC) — 4/Fclock — — 8 PAI Pulse Width — 2/Fclock — — PHI1* EXT PIN A B NOTE: 1. A = Input signal after the synchronizer 2. B = “A” after the digital filter 3. *PHI1 is the same frequency as system clock; however, it does not have the same timing. Figure 21 Input Signal Conditioner Timing MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 23 Freescale Semiconductor, Inc. PHI1* PAEN EXT PIN (PAI) Freescale Semiconductor, Inc... A B PACNT $FF $00 PAIF PAOVF NOTE: 1. 2. 3. 4. 5. A = PAI signal after the synchronizer B = “A” after the digital filter *PHI1 is the same frequency as system clock; however, it does not have the same timing. The external leading edge causes the pulse accumulator to increment and the PAIF flag to be set. The counter transition from $FF to $00 causes the PAOVF flag to be set. Figure 22 Pulse Accumulator — Event Counting Mode (Leading Edge) 24 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. PHI1* PHI1*/4 PAEN Freescale Semiconductor, Inc... EXT PIN (PAI) A B $77 PACNT $78 PAIF NOTE: 1. 2. 3. 4. 5. A = PAI signal after the synchronizer B = “A” after the digital filter PHI1*/4 clocks PACNT when GT-PAIF is asserted. PAIF is asserted when PAI is negated. *PHI1 has the same frequency as the system clock; however, it does not have the same timing. Figure 23 Pulse Accumulator — Gated Mode (Count While Pin High) MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 25 Freescale Semiconductor, Inc. PHI1* PHI1*/4 EXT PIN (PAI) Freescale Semiconductor, Inc... TCNT $FFFE $FFFF $0000 $77 PACNT $78 NOTE: 1. TCNT counts as a result of PHI1*/4; PACNT counts when TCNT overflows from $FFFF to $0000 and the conditioned PAI signal is asserted. 2. *PHI1 has the same frequency as the system clock; however, it does not have the same timing. Figure 24 Pulse Accumulator — Using TOF as Gated Mode Clock PHI1* PHI1*/2 PWMCNT (7:0) $FF $00 $01 $02 EXT PIN (PMWx) NOTE: 1. *PAI1 is the same frequency as the system clock; however, it does not have the same timing. 2. When the counter rolls over from $FF to $00, the PWM pin is set to logic level one. 3. When the counter equals the PWM register, the PWM pin is cleared to a logic level zero. Figure 25 PWMx (PWMx Register = 01, Fast Mode) 26 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. PHI1* COMPARE/ CAPTURE CLOCK OCx COMPARE REGISTER Freescale Semiconductor, Inc... TCNT $0102 $0101 $0102 $0103 OCx MATCH OCxF EXT PIN (OCx) NOTE: 1. When the TCNT matches the OCx compare register, the OCxF flag is set followed by the OCx pin changing state. 2. *PAI1 is the same frequency as the system clock; however, it does not have the same timing. Figure 26 Output Compare (Toggle Pin State) MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 27 Freescale Semiconductor, Inc. PHI1* COMPARE/ CAPTURE CLOCK TCNT $0101 $0102 Freescale Semiconductor, Inc... ICx EXTERNAL PIN CONDITIONED INPUT ICx CAPTURE REGISTER $0102 ICxF NOTE: 1. The conditioned input signal causes the current value of the TCNT to be latched by the ICx capture register. The ICxF flag is set at the same time. 2. *PAI1 is the same frequency as the system clock; however, it does not have the same timing. Figure 27 Input Capture (Capture on Rising Edge) 28 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. BUS STATES PHI1* PDDRx EXTERNAL PIN (INPUT) Freescale Semiconductor, Inc... CONDITIONED INPUT PDRx INTERNAL DATA BUS NEW DATA IMB READ CYCLE (READ BIT AS 1) IMB READ CYCLE (READ BIT AS 1) IMB READ CYCLE (READ BIT AS 0) NOTE: 1. *PAI1 is the same frequency as the system clock; however, it does not have the same timing. Figure 28 General-Purpose Input MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 29 Freescale Semiconductor, Inc. BUS STATES B1 B2 B3 B4 B1 B2 B3 B4 B1 B2 B3 B4 B1 B2 B3 B4 PHI1* INTERNAL DATA BUS PDR Freescale Semiconductor, Inc... PDRx EXTERNAL PIN (OUTPUT) CONDITIONED INPUT ICx COMPARE REGISTER $0102 PDDRX 0 TCNT $0101 IMB WRITE CYCLE $0102 IMB WRITE CYCLE NOTE: 1. *PAI1 is the same frequency as the system clock; however, it does not have the same timing. 2. When the bit value is driven on the pin, the input circuit sees the signal. After it is conditioned it causes the contents of the TCNT to be latched into the ICx compare register. Figure 29 General-Purpose Output (Causes Input Capture) 30 For More Information On This Product, Go to: www.freescale.com MC68L300EC16/D Freescale Semiconductor, Inc. BUS STATES B1 B2 B3 B4 B1 B2 B3 B4 B1 B2 B3 B4 B1 B2 B3 B4 PHI1* COMPARE/ CAPTURE CLOCK TCNT $0101 Freescale Semiconductor, Inc... TOCx $0102 $0103 $AOF3 FOCx OCxF (NOT SET) EXTERNAL PIN (OCx) IMB WRITE CYCLE NOTE: 1. *PAI1 is the same frequency as the system clock; however, it does not have the same timing. Figure 30 Force Compare (CLEAR) MC68L300EC16/D For More Information On This Product, Go to: www.freescale.com 31 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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