Features • CPU32+ Processor (4.5 MIPS at 25 MHz) • • • • • • • • • • • • • • • – 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32) – Background Debug Mode – Byte-misaligned Addressing Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits) Up to 32 Address Lines (At Least 28 Always Available) Complete Static Design (0 - 25 MHz Operation) Slave Mode to Disable CPU32+ (Allows Use with External Processors) – Multiple QUICCs Can Share One System Bus (One Master) – TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and Intelligent Peripheral (22 MIPS at 25 MHz) – Peripheral Device of TSPC603e (see DC415/D note) Four General-purpose Timers – Superset of MC68302 Timers – Four 16-bit Timers or Two 32-bit Timers – Gate Mode Can Enable/Disable Counting Two Independent DMAs (IDMAs) System Integration Module (SIM60) Communications Processor Module (CPM) Four Baud Rate Generators Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full 10 Mbps Support) Two SMC VCC = +5V ± 5% fmax = 25 MHz and 33 MHz Military Temperature Range: -55°C < TC < +125°C PD = 1.4 W at 25 MHz; 5.25V 2 W at 33 MHz; 5.25V 32-bit Quad Integrated Communication Controller TS68EN360 Description The TS68EN360 QUad Integrated Communication Controller (QUICC™) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications activities. The QUICC (pronounced “quick”) can be described as a next-generation TS68302 with higher performance in all areas of device operation, increased flexibility, major extensions in capability, and higher integration. The term “quad” comes from the fact that there are four serial communications controllers (SCCs) on the device; however, there are actually seven serial channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI). Screening/Quality This product is manufactured in full compliance with: • MIL-STD-883 (class B) • QML (class Q) • or according to Atmel standards Rev. 2113A–HIREL–03/02 1 R suffix PGA 241 Ceramic Pin Grid Array Cavity Up A suffix CERQUAD 240 Ceramic Leaded Chip Carrier Cavity Down Introduction QUICC Architecture Overview The QUICC is 32-bit controller that is an extension of other members of the TS68300 family. Like other members of the TS68300 family, the QUICC incorporates the intermodule bus (IMB). The TS68302 is an exception, having an 68000 bus on chip. The IMB provides a common interface for all modules of the TS68300 family, which allows the development of new devices more quickly by using the library of existing modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first device to implement this option. The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each module utilizes the 32-bit IMB. The TS68EN360 QUICC block diagram is shown in Figure 1. Figure 1. QUICC Block Diagram SIM 60 CPU32+ CORE SYSTEM PROTECTION JTAG PERIODIC TIMER BREAKPOINT LOGIC CLOCK GENERATION DRAM CONTROLLER OTHER FEATURES AND CHIP SELECTS EXTERNAL BUS INTERFACE IMB (32 BIT) SYSTEM I/F CPM COMMUNICATIONS PROCESSOR 2.5-KBYTE DUAL-PORT RAM RISC CONTROLLER TWO IDMAs FOURTEEN SERIAL DMAs SEVEN SERIAL CHANNELS 2 INTERRUPT CONTROLLER TIMER SLOT ASSIGNER FOUR GENERALPURPOSE TIMERS OTHER FEATURES TS68EN360 2113A–HIREL–03/02 TS68EN360 Pin Assignments Figure 2. 241-lead Pin Grid Array (PGA) T PA15 PA12 PA9 PA6 PA3 PA2 PB17 PB15 PB12 PB11 PA13 PA10 PA7 PA5 PA1 PB8 PB5 PB2 PC11 PC9 PC6 PC5 PC2 PB7 PB4 PB1 PC10 PC7 PC3 PC1 IRQ2 IRQ3 IRQ1 S D2 D0 PB16 PB13 PB10 D4 D3 D1 PA14 PA11 PA8 PA4 PA0 PB14 PB9 PB6 PB3 PB0 PC8 PC4 PC0 D7 D6 D5 GND GND GND Vcc Vcc GND GND Vcc Vcc GND GND GND IRQ5 BERR RESETS D10 D9 D8 GND Vcc GND Vcc GND GND HALT RMC PERR D13 D12 D11 GND GND GND GND AVEC TDO D16 D15 D14 GND Vcc D19 D18 D17 Vcc GND TRST BKPT IRQ6 R Q P NC N TMS M TD1 TCK RESETH L K CLKO2 Vcc GND Vccclk TS68EN360 GNDclk Vcc Vcc IRQ4 BGACK BG GND GND IFETCH NC1 (BOTTOM VIEW) J CLKO1 D20 D22 GND Vcc BR H D21 D23 D25 GND GNDs2 NC2 BCLRO OE D24 D26 D28 Vcc D27 D29 D31 GND D30 FC3 FC0 A31 Vccsyn GNDsyn FC2 FC1 A30 XFC Vcc GND GND Vcc Vcc GND GND GND GND Vcc GND CAS0 SIZ1 A29 EXTAL MODCK1 A27 A23 A20 A17 A14 A8 A4 A0 CS7 CS4 CS1 CAS3 FREEZE DS SIZ0 A28 MODCK0 GND A25 A22 A19 A16 A13 A10 A7 A5 A1 IRQ7 CS5 CS2 G Vcc IPIPE0 AS IPIPE1 F GND Vcc GND PRTY2 PRTY1 PRTY0 E GND Vcc GNDs1 Vcc NC3 DSACK1 PRTY3 D R/W DSACK0 C B CAS2 CAS1 A 1 Note: XTAL NC4 A26 A24 A21 A18 A15 A12 A11 A9 A6 A3 A2 TRIS CS6 CS3 CS0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin P9 “NC” is for guide purposes only. 3 2113A–HIREL–03/02 CS0 CS1 CS2 CS3 Vcc GND CS4 CS5 CS6 CS7 IRQ7 TRIS A0 A1 GND A2 A3 Vcc A4 A5 GND A6 A7 Vcc GND A8 A9 GND A10 A11 Vcc A12 A13 GND A14 A15 A16 A17 A18 GND A19 A20 A21 Vcc A22 A23 A24 GND A25 A26 A27 NC4 GND MODCK1 MODCK0 XTAL EXTAL GNDsyn XFC Vccsyn Figure 3. 240-lead Cerquad GNDs1 CAS3 CAS2 Vcc CAS1 GND CAS0 FREEZE DS GND R/W NC3 Vcc DSACK0 GND DSACK1 GND PRTY3 PRTY2 GND Vcc PRTY1 PRTY0 IPIPE0 AS GNDs2 IPIPE1 Vcc NC2 BCLRO GND OE IFETCH NC1 BR Vcc GND BG BGACK Vcc IRQ4 IRQ6 GND BKPT RESETH TRST TCK TMS TDI TDO PERR GND AVEC RMC Vcc RESETS HALT GND BERR IRQ1 180 181 170 160 150 140 130 121 120 190 110 200 100 TS68EN360 (TOP VIEW) 210 90 220 80 230 70 PIN ONE INDICATOR 240 61 10 20 30 40 50 60 IRQ5 IRQ3 IRQ2 PC0 PC1 PC2 GND PC3 PC4 PC5 PC6 Vcc PC7 PC8 PC9 PC10 GND PC11 PB0 PB1 PB2 PB3 PB4 PB5 PB6 GND PB7 PB8 PB9 PB10 Vcc PB11 PB12 PB13 PB14 GND PB15 PB16 PB17 PA0 GND Vcc PA1 PA2 PA3 PA4 GND PA5 PA6 PA7 PA8 Vcc PA9 PA10 PA11 PA12 GND PA13 PA14 PA15 1 A28 A29 GND A30 A31 Vcc SIZ0 SIZ1 FC0 GND FC1 FC2 FC3 Vcc GND D31 D30 D29 GND D28 D27 D26 Vcc D25 D24 D23 GND D22 D21 D20 CLKO1 Vccclk GNDclk CLKO2 D19 D18 D17 GND D16 D15 Vcc D14 D13 D12 GND D11 D10 D9 D8 D7 GND D6 D5 Vcc D4 D3 D2 GND D1 D0 4 TS68EN360 2113A–HIREL–03/02 TS68EN360 Signal Description Functional Signal Group Figure 4. QUICC Functional Signal Groups ADDRESS BUS A27±A0 A31±A28/WE0±WE3 FC2±FC0/TM2±TM0 FC3/TT0 PORT A DATA BUS RXD1/PA0 TXD1/PA1 D31±D16 RXD2/PA2 TXD2/PA3 D15±D0 PRTY1±PRTY2/IOUT1±IOUT2 PRTY2/IOUT0/RQOUT L1TXDB/RXD3/PA4 L1RXDB/TXD3/PA5 PRTY3/16BM BUS CONTROL SIZ0 SIZ1 DSACK0/TBI DSACK1/TA L1TXDA/RXD4/PA6 L1RXDA/TXD4/PA7 TIMERs/SCCs/SIs/CLOCKs/BRG TIN1/L1RCLKA/BRGO1/CLK1/PA8 BRGCLK1/TOUT1/CLK2/PA9 R/W AS DS/TT1 OE/AMUX TIN2/L1TCLKA/BRGO2/CLK3/PA10 TOUT2/CLK4/PA11 TIN3/BRGO3/CLK5/PA12 BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13 TIN4/BRGO4/CLK7/PA14 L1TCLKB/TOUT4/CLK8/PA15 PORT B (PIP) RRJCT1/SPISEL/PB0 RSTRT2/SPICLK/PB1 RRJCT2/SPIMOSI(SPITXD)/PB2 BRGO4/SPIMISO(SPIRXD)/PB3 DREQ1/BRGO1/PB4 DACK1/BRGO2/PB5 DONE1/SMTXD1/PB6 DONE2/SMRXD1/PB7 DREQ2/SMSYN1/PB8 DACK2/SMSYN2/PB9 L1CLKOB/SMTXD2/PB10 L1CLKOA/SMRXD2/PB11 L1ST1/RTS1/PB12 L1ST2/RTS2/PB13 L1ST3/L1RQB/RTS3/PB14 L1ST4/L1RQA/RTS4/PB15 STRBO/BRGO3/PB16 STRBI/RSTRT1/PB17 PORT C (INTERRUPT PARALLEL I/O) L1ST1/RTS1/PC0 L1ST2/RTS2/PC1 L1ST3/L1RQB/RTS3/PC2 L1ST4/L1RQA/RTS4/PC3 CTS1/PC4 TGATE1/CD1/PC5 CTS2/PC6 TGATE2/CD2/PC7 SDACK2/L1TSYNCB/CTS3/PC8 L1RSYNCB/CD3/PC9 SDACK1/L1TSYNCA/CTS4/PC10 L1RSYNCA/CD4/PC11 BUS ARBITRATION RMC/CONFIG0/LOCK BR BG BGACK/BB BCLRO/CONFIG1/RAS2DD SYSTEM CONTROL RESETH RESETS HALT BERR/TEA QUICC TS68360 240 PINS PERR INTERRUPT CONTROL IRQ1/OUT0/RQOUT IRQ4/OUT1 IRQ6/OUT2 IRQ2,3,5,7 AVEC/IACK5/AVECO MEMORY CONTROLLER CS6±CS0/RAS6±RAS0 CS/RAS7/IACK7 CAS3±CAS0/IACK6,3,2,1 TEST TRIS/TS BKPT/BKPT0/DSCLK FREEZE/CONFIG2/MBARE IPIPE1/RAS1DD/BCLRI IPIPE0/BADD2/DSO IFETCH/BADD3/DSI TCK TMS TDI TDO TRST CLOCK XTAL EXTAL XFC MODCK1±MODCK0 CLKO2±CLKO1 5 2113A–HIREL–03/02 Signal Index Table 1. System Bus Signal Index (Normal Operation) Group Signal Name Mnemonic Address Address Bus A27-A0 Data Parity A31-A28 WE3-WE0 Upper four bits of address bus (I/O), or byte write enable signals (O) for accesses to external memory or peripherals. Function Codes FC3-FC0 Identifies the processor state and the address space of the current bus cycle. (I/O) Data Bus 31 - 16 D31-D16 Upper 16-bit data bus used to transfer byte or word data. Used in 16-bit bus mode. (I/O) Data Bus 15 - 0 D15-D0 Lower 16-bit data bus used to transfer 3-byte or long-word data. (I/O) Not used in 16-bit bus mode. Parity 3/16BM Bus Arbitration PRTY2-PRTY0 Parity signals for byte writes/reads from/to external memory module. (I/O) PRTY3/16BM Parity signals for byte writes/reads from/to external memory module or defines 16-bit bus mode. (I/O) Parity Error PERR Indicates a parity error during a read cycle. (O) Chip Select Row Address Select 7 Interrupt Acknowledge 7 CS RAS7 IACK7 Enables peripherals or DRAMs at programmed addresses (O) or interrupt level 7 acknowledge line. (O) Chip Select 6-0 Row Address Select 6-0 CS6-CS0 RAS6-RAS0 Enables peripherals or DRAMs at programmed addresses. (O) Column Address Select 3 - 0/Interrupt Acknowledge 1, 2, 3, 6 CAS3-CAS0/ IACK6,3,2,1 DRAM column address select or interrupt level acknowledge lines. (O) Bus Request BR Indicates that an external device requires bus mastership. (I) Bus Grant BG Indicates that the current bus cycle is complete and the QUICC has relinquished the bus. (O) Bus Grand Acknowledge BGACK Read-Modify-Write Cycle Initial Configuration 0 RMC CONFIG0 Bus Clear Out/Initial Configuration 1/Row Address Select 2 Double-Drive 6 Lower 27 bits of address bus. (I/O) Address Bus/Byte Write Enables Parity 2 - 0 Memory Controller Function BCLRO/CONFIG1/ RAS2DD Indicates that an external device has assumed bus mastership. (I) Identifies the bus cycle as part of an indivisible read-modify-write operation (I/O) or initial QUICC configuration select. (I) Indicates that an internal device requires the external bus (Open-Drain O) or initial QUICC configuration select (I) or row address select 2 double-drive output. (O) TS68EN360 2113A–HIREL–03/02 TS68EN360 Table 1. System Bus Signal Index (Normal Operation) (Continued) Group Signal Name Mnemonic Bus Control Data and Size Acknowledge DSACK1 - DSACK0 Address Strobe AS Indicates that a valid address is on the address bus. (I/O) Data Strobe DS During a read cycle, DS indicates that an external device should place valid data on the data bus. During a write cycle, DS indicates that valid data is on the data bus. (I/O) SIZ1-SIZ0 Indicates the number of bytes remaining to be transferred for this cycle. (I/O) Size Read/Write Interrupt Control Clock and Test Provides asynchronous data transfer acknowledgement and dynamic bus sizing (open-drain I/O but driven high before three-stated). Indicates the direction of data transfer on the bus. (I/O) Output Enable Address Multiplex OE/AMUX Active during a read cycle indicates that an external device should place valid data on the data bus (O) or provides a strobe for external address multiplexing in DRAM accesses if internal multiplexing is not used. (O) Interrupt Request Level 7-1 IRQ7-IRQ1 Provides external interrupt requests to the CPU32+ at priority levels 7-1. (I) Autovector/Interrupt Acknowledge 5 System Control R/W Function AVEC/IACK5 Autovector request during an interrupt acknowledge cycle (open-drain I/O) or interrupt level 5 acknowledge line. (O) Soft Reset RESETS Soft system reset. (open-drain I/O) Hard Reset RESETH Hard system reset. (open-drain I/O) Halt HALT Suspends external bus activity. (open-drain I/O) Bus Error BERR Indicates an erroneous bus operation is being attempted. (open-drain I/O) System Clock Out 1 CLKO1 Internal system clock output 1. (O) System Clock Out 2 CLKO2 Internal system clock output 2 - normally 2x CLKO1. (O) Crystal Oscillator External Filter Capacitor Clock Mode Select 1-0 EXTAL, XTAL Connections for an external crystal to the internal oscillator circuit. EXTAL (I), XTAL (O). XFC Connection pin for an external capacitor to filter the circuit of the PLL. (I) MODCK1-MODCK0 Selects the source of the internal system clock. (I) THESE PINS SHOULD NOT BE SET TO 00 Instruction Fetch/ Development Serial Input IFETCH/DSI Indicates when the CPU32+ is performing an instruction word prefetch (O) or input to the CPU32+ background debug mode. (I) Instruction Pipe 0/ Development Serial Output IPIPE0/DSO Used to track movement of words through the instruction pipeline (O) or output from the CPU32+ background debug mode. (O) IPIPE1/RAS1DD Used to track movement of words through the instruction pipeline (O), or a row address select 1 “double-drive” output (O). BKPT/DSCLK Signals a hardware breakpoint to the QUICC (open-drain I/O), or clock signal for CPU32+ background debug mode (I). FREEZE/CONFIG2 Indicates that the CPU32+ has acknowledged a breakpoint (O), or initial QUICC configuration select (I). Instruction Pipe 1/Row Address Select 1 Double-Drive Breakpoint/Development Serial Clock Freeze/Initial Configuration 2 7 2113A–HIREL–03/02 Table 1. System Bus Signal Index (Normal Operation) (Continued) Group Signal Name Clock and Test (Cont’d) Three-State TRIS Used to three-state all pins if QUICC is configured as a master. Always Sampled except during system reset. (I) Test Clock TCK Provides a clock for Scan test logic. (I) Test Mode Select TMS Controls test mode operations. (I) Test Data In TDI Serial test instructions and test data signal. (I) Test Data Out TDO Serial test instructions and test data signal. (O) Test Reset TRST Provides an asynchronous reset to the test controller. (I) Power -Note: 8 Mnemonic Function Clock Synthesizer Power VCCSYN Power supply to the PLL of the clock synthesizer. Clock Synthesizer Ground GNDSYN Ground supply to the PLL of the clock synthesizer. Clock Out Power VCCCLK Power supply to clock out pins. Clock Out Ground GNDCLK Ground supply to clock out pins. Special Ground 1 GNDS1 Special ground for fast AC timing on certain system bus signals. Special Ground 2 GNDS2 Special ground for fast AC timing on certain system bus signals. System Power Supply and Return VCC, GND Power supply and return to the QUICC. No Connect NC4-NC1 Four no-connect pins. 1. I denotes input, O denotes output and I/O is input/output. TS68EN360 2113A–HIREL–03/02 TS68EN360 Table 2. Peripherals Signal Index Group Signal Name Mnemonic SCC Receive Data RXD4-RXD1 Serial receive data input to the SCCs. (I) Transmit Data TXD4-TXD1 Serial transmit data output from the SCCs. (O) Request to Send RTS4-RTS1 Request to send outputs indicate that the SCC is ready to transmit data. (O) Clear to Send CTS4-CTS1 Clear to send inputs indicate to the SCC that data transmission may begin. (I) Carrier Detect CD4-CD1 Carrier detect inputs indicate that the SCC should begin reception of data. (I) Receive Start RSTRT1 This output from SCC1 identifies the start of a receive frame. Can be used by an Ethernet CAM to perform address matching. (O) Receive Reject RRJCT1 This input to SCC1 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match. (I) Clocks IDMA TIMER CLK8-CLK1 Input clocks to the SCCs, SCMs, SI, and the baud rate generators. (I) DMA Request DREQ2-DREQ1 A request (input) to an IDMA channel to start an IDMA transfer. (I) DMA Acknowledge DACK2-DACK1 An acknowledgement (output) by the IDMA that an IDMA transfer is in progress. (O) DMA Done DONE2-DONE1 A bidirectional signal that indicates the last IDMA transfer in a block of data. (I/O) Timer Gate TGATE2-TGATE1 Timer Input TIN4-TIN1 Time reference input to the timer that allows it to function as a counter. (I) TOUT4-TOUT1 Output waveform (pulse or toggle) from the timer as a result of a reference value being reached. (O) SPI Master In Slave Out SPIMISO Serial data input to the SPI master (I); serial data output from an SPI slave. (O) SPI Master Out Slave In SPIMOSI Serial data output from the SPI master (O); serial data input to an SPI slave. (I) SPI Clock SPICLK Output clock from the SPI master (O); input clock to the SPI slave. (I) SPI Select SPISEL SPI slave select input. (I) Timer Output SPI SMC Function An input to a timer that enables/disables the counting function. (I) SMC Receive Data SMRXD2-SMRXD1 Serial data input to the SMCs. (I) SMC Transmit Data SMTXD2-SMTXD1 Serial data output from the SMCs. (O) SMC Sync SMSYN2-SMSYN1 SMC synchronization signal. (I) 9 2113A–HIREL–03/02 Table 2. Peripherals Signal Index (Continued) Group Signal Name Mnemonic SI SI Receive Data L1RXDA, L1RXDB Serial input to the time division multiplexed (TDM) channel A or channel B. SI Transmit Data L1TXDA, L1TXDB Serial output from the TDM channel A or channel B. SI Receive Clock L1RCLKA, L1RCLKB Input receive clock to TDM channel A or channel B. SI Transmit Clock L1TCLKA, L1TCLKB Input transmit clock to TDM channel A or channel B. SI Transmit Sync Signals L1TSYNCA, L1TSYNCB Input transmit data sync signal to TDM channel A or channel B. SI Receive Sync Signals L1RSYNCA, L1RSYNCB Input receive data sync signal to TDM channel A or channel B. IDL Interface Request BRG L1RQA, L1RQB IDL interface request to transmit on the D channel. Output from the SI. SI Output Clock L1CLKOA, L1CLKOB Output serial data rate clock. Can output a data rate clock when the input clock is 2x the data rate. SI Data Strobes L1ST4-L1ST1 Serial data strobe outputs can be used to gate clocks to external devices that do not have a built-in time slot assigner (TSA). BRGO4-BRGO1 Baud rate generator output clock allows baud rate generator to be used externally. CLK2, CLK6 Baud rate generator input clock from which BRG will derive the baud rates. Baud Rate Generator Out 4-1 BRG Input Clock PIP SDMA Function Port B 15-0 PB15-BP0 Strobe Out STRBO This input causes the PIP output data to be placed on the PIP data pins. Strobe In STRBI This input causes data on the PIP data pins to be latched by the PIP as input data. SDACK2-SDACK1 SDMA output signals used in RISC receiver to mark fields in the Ethernet receive frame. SDMA Acknowledge 2-1 Scope PIP Data I/O Pins. This drawing describes the specific requirements for the microcontroller TS68EN360 25 MHz and 33 MHz in compliance with MIL-STD-883 class B or Atmel standard screening. Applicable Documents MIL-STD-883 1. MIL-STD-883: test methods and procedures for electronics. 2. MIL-PRF-38535: general specifications for microcircuits. 3. DESC 5962-SMD-97607 10 TS68EN360 2113A–HIREL–03/02 TS68EN360 Requirements General This microcircuits are in accordance with the applicable document and as specified herein. Design and Construction Terminal Connections Depending on the package, the terminal connections shall be as shown in Figure 2 and Figure 3. Lead Material and Finish Lead material and finish shall be as specified in MIL-STD-883 (see enclosed “Ordering Information” on page 79). Package The macrocircuits are packaged in hermetically sealed ceramic packages which are conform to case outlines of MIL-STD-1835 or as follow: • PGA but see “241-pin – PGA” on page 77 • CERQUAD The precise case outlines are described at the end of the specification (“Package Mechanical Data” on page 77) and into MIL-STD-1835. Electrical Characteristics Table 3. Absolute Maximum Ratings Rating Symbol Value Unit VCC -0.3 to +6.5 V Input Voltage VIN -0.3 to +6.5 V Storage Temperature Range TSTG -55 to +150 °C Supply Voltage (1)(2) (1)(2) Note: This device contains protective circuitry against damage due to high static voltages or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VDD). Notes: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3. The supply voltage VCC must start and restart from 0.0V; otherwise, the 360 will not come out of reset properly.Unless otherwise stated, all voltages are referenced to the reference terminal. 11 2113A–HIREL–03/02 Table 4. Recommended Conditions Of Use Unless otherwise stated, all voltages are referenced to the reference terminal. Symbol Parameter Min. VCC Supply Voltage Range VIL Typ. Max. Unit +4.75 +5.25 V Logic Low Level Input Voltage Range GND +0.8 V VIH Logic High Level Input Voltage Range +2.0 VCC V Tcase Operating Temperature -55 +125 °C VOH High Level Output Voltage +2.4 fsys System Frequency V (For 25 MHz version) 25 MHz (For 33 MHz version) 33 MHz Value Unit Table 5. Thermal Characteristics Symbol Parameter θJC Thermal Resistance - Junction to Case θJA Thermal Resistance - Junction to Ambient 240-pin Cerquad 2 241-pin PGA 7 240-pin Cerquad 27.4 241-pin PGA 22.8 °C/W °C/W TJ = TA + (PD · θJA) PD = (VDD · IDD) + PI/O Where PI/O is the power dissipation on pins. Power Considerations The average chip-junction temperature, TJ, in °C can be obtained from: TJ = TA ÷ (PD · ΘJA) (1) where: TA = Ambient Temperature, °C ΘJA = Package Thermal Resistance, Junction-to-Ambient, C/W PD = PINT + P I/O PINT = ICC · VCC, Watts-chip Internal Power PI/O = Power Dissipation on Input and Output Pins-User Determined For most applications, PI/O < 0.3 · PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273°C) (2) Solving Equations (1) and (2) for K gives: K = PD · (TA + 273°C) + ΘJA · PD2 (3) where K is a constant pertaining to the particular part. K can be determined from Equation (3) by measuring PD (at thermal equilibrium) for a know TA. Using this value of K, the values of PD and TJ can be obtained by solving Equations (1) and (2) iteratively for any value of TA. 12 TS68EN360 2113A–HIREL–03/02 TS68EN360 Mechanical and Environment The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-883 for class B devices or for Atmel standard screening. Marking The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and permanently marked with the following information as minimum: • Atmel logo • Manufacturer’s part number • Class B identification • Date-code of inspection lot • ESD identifier if available • Country of manufacturing Quality Conformance Inspection DESC/MIL-STD-883 Is in accordance with MIL-M-38535 and method 5005 of MIL-STD-883. Group A and B inspections are performed on each production lot. Group C and D inspections are performed on a periodical basis. Electrical Characteristics General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below: • Static electrical characteristics for the electrical variants • Dynamic electrical characteristics for TS68EN360 (25 MHz, 33 MHz) For static characteristics, test methods refer to IEC 748-2 method number, where existing. For dynamic characteristics, test methods refer to clause “Static Characteristics” on page 14 of this specification. 13 2113A–HIREL–03/02 Static Characteristics GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary. (See numbered notes). Characteristic Symbol Min. Max. Unit Input High Voltage (except EXTAL) VIH 2.0 VCC V Input Low Voltage (5V Part) VIL GND 0.8 V Input Low Voltage (Part Only; PA8-15, PB1, PC5, PC7, TCK) VIL GND 0.5 V Input Low Voltage (Part Only; All Other Pins) VIL GND 0.8 V VIHC 0.8*(VCC) VCC + 0.3 V - - -0.8 V Input Leakage Current (All Input Only Pins except for TMS, TDI and TRST) Vin = 0/5V Iin -2.5 2.5 µA Hi-Z (Off-State) Leakage Current (All Noncrystal Outputs and I/O Pins except TMS,TDI and TRST) Vin = 0/5V IOZ -2.5 -2.5 µA Signal Low Input Current VIL = 0.8V (TMS, TDI and TRST Pins Only) Signal High Input Current VIH = 2.0V (TMS, TDI and TRST Pins Only) IL IH -0.5 -0.5 0.5 0.5 mA mA VOH 2.4 - V EXTAL Input High Voltage Undershoot Output High Voltage IOH = -0.8 mA, VCC = 4.75V AII Noncrystal Outputs Except Open Drain Pins Output Low Voltage IOL = 2.0 mA, CLKO1-2, FREEZE, IPIPE0-1, IFETCH, BKPTO IOL = 3.2 mA, A31-A0, D31-D0, FC3-0, SIZ0-1, PA0, 2, 4, 6, 8-15, PB0-5, PB8-17, PC0-11, TDO, PERR, PRTY0-3, IOUT0-2, AVECO, AS, CAS3-0, BLCRO, RAS0-7 IOL = 5.3 mA, DSACK0-1, R/W, DS, OE, RMC, BG, BGACK, BERR IOL = 7 mA, TXD1-4 IOL = 8.9 mA, PB6, PB7, HALT, RESET, BR (Output) VOL Input Capacitance AII I/O Pins Cin - 20 pF Load Capacitance (except CLKO1-2) CL - 100 pF Load Capacitance (CLKO1-2) CLc 50 pF Power VCC 5.25 V Dynamic Characteristics 0.5 0.5 V 0.5 0.5 0.5 4.75 The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals. The measurement of the AC specifications is defined by the waveforms shown in Figure 5. To test the parameters guaranteed by Atmel inputs must be driven to the voltage levels specified in the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown. Inputs are specified with minimum setup and hold times and are measured as shown. Finally, the measurement for signal-to-signal specifications are shown. Note that the testing levels used to verify conformance to the AC specifications do not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics. 14 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 5. Drive Levels and Test Points For AC Specifications 2.0V 2.0V CLKOUT 0.8V 0.8V A B OUTPUTS(1) VALID OUTPUT n 2.0V 2.0V 0.8V 0.8V VALID OUTPUT A n+1 B VALID OUTPUT n OUTPUTS(2) C INPUTS(3) 2.0V 2.0V 0.8V 0.8V 2.0V 0.8V C 2.0V INPUTS(4) 0.8V ALL SIGNALS(5) VALID OUTPUT n+1 D VALID INPUT 0.8V 2.0V D VALID INPUT 2.0V 0.8V DRIVE TO 2.4V DRIVE TO 0.5V 2.0V 0.8V E F 2.0V 0.8V Notes: 1. 2. 3. 4. 5. This output timing is applicable to all parameters specified relative to the rising edge of the clock. This output timing is applicable to all parameters specified relative to the falling edge of the clock. This input timing is applicable to all parameters specified relative to the rising edge of the clock. This input timing is applicable to all parameters specified relative to the falling edge of the clock. This timing is applicable to all parameters specified relative to the assertion/negation of another signal. Legend: a) Maximum output delay specification. b) Minimum output hold time. c) Minimum input setup time specification. d) Minimum input hold time specification. e) Signal valid to signal valid specification (maximum or minimum). f) Signal valid to signal invalid specification (maximum or minimum). 15 2113A–HIREL–03/02 AC Power Dissipation Table 6. Typical Current Drain Mode of Operation System Clock Frequency BRGCLK Clock Frequency SyncCLK Clock Frequency Typ Unit (1) and Rev B ) IDD 25 MHz 25 MHz 25 MHz 250 mA (3) and Newer) IDD 25 MHz 25 MHz 25 MHz 237 mA IDD 33 MHz 33 MHz 33 MHz 327 mA Low Power Mode IDDSB Divide by 2 12.5 MHz Divide by 16 1.56 MHz Divide by 2 12.5 MHz 150 mA Low Power Mode IDDSB Divide by 4 6.25 MHz Divide by 16 1.56 MHz Divide by 4 6.25 MHz 85 mA Low Power Mode IDDSB Divide by 16 1.56 MHz Divide by 16 1.56 MHz Divide by 4 6.25 MHz 35 mA Low Power Mode IDDSB Divide by 256 97.6 kHz Divide by 16 1.56 MHz Divide by 4 6.25 MHz 20 mA Low Power Mode IDDSB Divide by 256 97.6 kHz Divide by 64 390 kHz Divide by 64 390 kHz 13 mA Low Power Stop VCO Off(4) IDDSP 0.5 mA PLL Supply Current PLL Disabled PLL Enabled IDDPD IDDPE TBD TBD Normal mode (Rev A Normal Mode (Rev C (2) Symbol Normal Mode Notes: 1. 2. 3. 4. Rev A mask is C63T Rev B masks are C69T and F35G Current Rev C masks are E63C, E68C and F15W EXTAL frequency is 32 kHz All measurements were taken with only CLKO1 enabled, VCC = 5.0V, VIL = 0V and VIH = VCC Table 7. Maximum Power Dissipation Notes: 16 System Frequency VCC Max PD Unit Mask 25 MHz 5.25V 1.80 W REV A(1) and REV B(2) 25 MHz 5.25V 1.45 W REV C(3) and Newer 25 MHz 3.6V 0.65 W REV C(3) and Newer 33 MHz 5.25V 2.00 W REV C(3) and Newer 1. Rev A mask is C63T 2. Rev B masks are C69T and F35G 3. Current Rev C masks are E63C, E68C and F15W TS68EN360 2113A–HIREL–03/02 TS68EN360 AC Electrical Specifications Control Timing GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 6). 25 MHz Number Characteristic 33.34 MHz Symbol Min Max System Frequency fsys dc(1) 25.00 Crystal Frequency fXTAL 25 6000 On-Chip VCO System Frequency fsys 20 50 Start-up Time With external clock (oscillator disabled) or after changing the multiplication factor MF tpll Min Max Unit 33.34 MHz 25 6000 kHz 20 67 MHz 2500 clks % ∆CLK TBD TBD CLKO1 Period tcyc 40 - 30 - ns 1A EXTAL Duty Cycle, MF tdcyc 40 60 40 60 % 1C External Clock Input Period tEXTcyc 40 - 30 - ns 2, 3 CLKO1 Pulse Width (Measured at 1.5V) tCW1 19 - 14 - ns 2A, 3A CLKO2 Pulse Width (Measured at 1.5V) tCW2 9.5 - 7 - ns 4, 5 CLKO1 Rise and Fall Times (Full drive) tCrf1 - 2 - 2 ns 4A, 5A CLKO2 Rise and Fall Times (Full drive) tCrf2 - 2 - 1.6 ns CLKO1-2 stability 1 5B EXTAL to CLKO1 Skew-PLL enabled (MF< 5) tEXTP1 a a ns 5C EXTAL to CLKO2 Skew-PLL enabled (MF< 5) tEXTP2 a a ns 5D CLKO1 to CLKO2 Skew AtmelKW a a ns Note: 1. Note that the minimum VCO frequency and the PLL default values put some restrictions on the minimum system frequency. The following calculation should be used to determine the actual value for specifications 5B, 5C and 5D. 5B: 25 MHz ±(0.9 ns + 0.25 x (rise time)) (1.4 ns @ rise = 2 ns; 1.9 ns @ rise = 4 ns) 33 MHz ±(0.5 ns + 0.25 x (rise time)) (1 ns @ rise = 2 ns; 1.5 ns @ rise = 4 ns) 5C: 25/33 MHz ±(2 ns + 0.25 x (rise time)) (2.5 ns @ rise = 2 ns; 3 ns @ rise = 4 ns) 5D: 25 MHz ±(3 ns + 0.5 x (rise time)) (4 ns @ rise = 2 ns; 5 ns @ rise = 4 ns) 33 MHz ±(2.5 ns + 0.5 x (rise time)) (3.5 ns @ rise = 2 ns; 4.5 ns @ rise = 4 ns) 17 2113A–HIREL–03/02 Figure 6. Clock Timing 1A 1C EXTAL (INPUT) VOLTAGE MIDPOINT 1 5C 5B CLKO1 (OUTPUT) 2 4 5 3 5D CLKO2 (OUTPUT) 4A 5A 2A 3A External Capacitor For PLL GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary. Characteristic Symbol Min Max Unit (1) MF x 340 MF x 480 pF (1) MF x 380 MF x 970 pF PLL External Capacitor (XFC to VCCSYN) cXFC MF< 5 (Recommended value MF x 400 pF) MF> 4 (Recommended value MF x 540 pF) Note: 1. MF - multiplication factor. Examples: Notes: 18 1. MODCK1 pin = 0, MF = 1 ⇒ CXFC = 400 pF 2. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency = 13.14 MHz, later on MF is changed to 762 to support a frequency of 25 MHz. Minimum CXFC is: 762 x 380 = 289 nF, Maximum CXFC is: 401 x 970 = 390 nF. The recommended CXFC for 25 MHz is: 762 x 540 = 414 nF. 289 nF < CXFC < 390 nF and closer to 414 nF. The proper available value for CXFC is 390 nF. 3. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency = 13.14 MHz, later on MF is changed to 1017 to support a frequency of 33.34 MHz. Minimum CXFC is: 1017 x 380 = 386 nF, Maximum CXFC is: 401 x 970 = 390 nF ⇒ 386 nF < CXFC < 390 nF. The proper available value for CXFC is 390 nF. 4. In order to get higher range, higher crystal frequency can be used (i.e. 50 kHz), in this case: Minimum CXFC is: 667 x 380 = 253 nF, Maximum CXFC is: 401 x 970 = 390 nF ⇒ 386 nF < CXFC < 390 nF. TS68EN360 2113A–HIREL–03/02 TS68EN360 Bus Operation AC Timing Specifications GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 7 to Figure 23). 25 MHz Number Symbol Min Max Min Max Unit CLKO1 High to Address, FC, SIZ, RMC Valid tCHAV 0 15 0 12 ns CLKO1 High to Address Valid (GAMX = 1) tCHAV 0 20 0 15 ns 7 CLKO1 High to Address, Data, FC, SIZ, RMC High Impedance tCHAZx 0 40 0 30 ns 8 CLKO1 High to Address, Data, FC, SIZ, RMC Invalid tCHAZn -2 - -2 - ns 9 CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE, IACKx Asserted tCLSA 3 20 3 15 ns CLKO1 Low to CSx/RASx Asserted tCLSA 4 16 4 12 ns CLKO1 High to CSx/RASx Asserted tCHCA 4 16 4 12 ns 9A(2)(10) AS to DS or CSx/RASx or OE Asserted (Read) tSTSA -6 6 -5.625 5.625 ns 9C(2)(11) AS to CSx/RASx Asserted tSTCA 14 26 9 21 ns Address, FC, SIZ, RMC, valid to AS, CSx/RASx, OE, WE, (and DS Read) Asserted tAVSA 10 - 8 - ns Address, FC, SIZ, RMC, Valid to CSx/RASx Asserted tAVCA 30 - 22.5 - ns CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE, IACKx Negated tCLSN 3 20 3 15 ns CLKO1 Low to CSx/RASx Negated tCLSN 4 16 4 12 ns CLKO1 High to CSx/RASx Negated tCHCN 4 16 4 12 ns AtmelTW 15 - 12 - ns 6 6A 9(10) (11) 9B 11(10) 11A(11) 12 12(16) (13)(16) 12A Characteristic 33.34 MHz 12B CS negate to WE negate (CSNTQ = 1) 13(12) AS, DS, CSx, OE, WE, IACKx Negated to Address, FC, SIZ Invalid (Address Hold) tSNAI 10 - 7.5 - ns 13A(13) CSx Negated to Address, FC, SIZ, Invalid (Address Hold) tCNAI 30 - 22.5 - ns 14(10)(12) AS, CSx, OE, WE (and DS Read) Width Asserted tSWA 75 - 56.25 - ns CSx Width Asserted tCWA 35 - 26.25 - ns (11)(13) 14C 14A DS Width Asserted (Write) tSWAW 35 - 26.25 - ns 14B AS, CSx, OE, WE, IACKx, (and DS Read) Width Asserted (Fast Termination Cycle) tSWDW 35 - 26.25 - ns CSx Width Asserted (Fast Termination Cycle) tCWDW 15 - 10 - ns tSN 35 - 26.25 - ns CLKO1 High to AS, DS, R/W High Impedance tCHSZ - 40 - 30 ns AS, DS, CSx, WE Negated to R/W High tSNRN 10 - 7.5 - ns 17A(13) CSx Negated to R/W High tCNRN 30 - 22.5 - ns 18 CLKO1 High to R/W High tCHRH 0 20 0 15 ns 14D(13) (3)(10)(12) 15 16 17 (12) AS, DS, CSx, OE, WE Width Negated 19 2113A–HIREL–03/02 Bus Operation AC Timing Specifications (Continued) GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 7 to Figure 23). 25 MHz Number Symbol Min Max Min Max Unit CLKO1 High to R/W Low tCHRL 3 20 3 15 ns R/W High to AS, CSx, OE Asserted tRAAA 10 - 7.5 - ns R/W High to CSx Asserted tRACA 30 - - ns 22 R/W Low to DS Asserted (Write) tRASA 47 - 36 - ns 23 CLKO1 High to Data-Out tCHDO - 23 - 18 ns 23A CLKO1 High to Parity Valid tCHPV - 25 - 20 ns 23B Parity Valid to CAS Low tPVCL 3 - 3 - ns 24(12) Data-Out, Parity-Out Valid to Negating Edge of AS, CSx, WE, (Fast Termination Write) tDVASN 10 - 7.5 - ns 25(12) DS, CSX, WE Negated to Data-Out, Parity-Out Invalid (Data-Out, Parity-Out Hold) tSNDOI 10 - 7.5 - ns CSx Negated to Data-Out, Parity-Out Invalid (DataOut, Parity-Out Hold) tCNDOI 35 - 25 - ns Data-Out, Parity-Out Valid to DS Asserted (Write) tDVSA 10 - 7.5 - ns Data-In, Parity-In to CLKO1 Low (Data-Setup) tDICL 1 - 1 - ns Data-In, Parity-In Valid to CLKO1 Low (Data-Setup) tDICL 20 - 15 - ns 27A Late BERR, HALT, BKPT Asserted to CLKO1 Low (Setup Time) tBELCL 10 - 7.5 - ns 28(18) AS, DS Negated to DSACKx, BERR, HALT Negated tSNDN 0 50 0 37.5 ns 29(4) DS, CSx, OE, Negated to Data-In Parity-In Invalid (Data-In, Parity-In Hold) tSNDI 0 - 0 - ns 29A(4) DS, CSx, OE Negated to Data-In High Impedance tSHDI - 40 - 30 ns CLKO1 Low to Data-In, Parity-In Invalid (Fast Termination Hold) tCLDI 10 - 7.5 - ns 30A(4) CLKO1 Low to Data-In High Impedance tCLDH - 60 - 45 ns 31(5)(15) DSACKx Asserted to Data-in, Parity-In Valid tDADI - 32 - 24 ns 31A DSACKx Asserted to DSACKx Valid (Skew) tDADV - 10 - 7.5 ns DSACKx Asserted to Data-in, Parity-In Valid tDADI - 35 - 26 ns 32 HALT an RESET Input Transition Time tHRrf - 140 - 33 CLKO1 High to BG Asserted tCLBA - 20 - 15 ns 34 CLKO1 High to BG Negated tCLBN - 20 22.5 15 ns BR Asserted to BG Asserted (RMC Not Asserted) tBRAGA 1 - 1 - CLKO1 37 BGACK Asserted to BG Negated tGAGN 1 2.5 1 2.5 CLKO1 39 BG Width Negated tGH 2 - 2 - CLKO1 39A BG Width Asserted tGA 1 - 1 - CLKO1 20 21(10) (11) 21A 25A(13) 26 27(15) (14) 27B 30(4) (5)(14) 31B 35 20 (6) Characteristic 33.34 MHz ns TS68EN360 2113A–HIREL–03/02 TS68EN360 Bus Operation AC Timing Specifications (Continued) GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 7 to Figure 23). 25 MHz Number Symbol Min Max Min Max Unit R/W Width Asserted (Write or Read) tRWA 100 - 75 - ns 46A R/W Width Asserted (Fast Termination Write or Read) tRWAS 75 - 56 - ns 47A Asynchronous Input Setup Time tAIST 5 - 4 - ns 47B Asynchronous Input Hold Time tAIHT 10 - 7.5 - ns DSACKx Asserted to BERR, HALT Asserted tDABA - 30 - 22.5 ns 53 Data-Out, Parity-Out Hold from CLKO1 High tDOCH 0 - 0 - ns 54 CLKO1 High to Dat-Out, Parity-Out High Impedance tCHDH - 20 - 15 ns 55 R/W Asserted to Data Bus Impedance Change tRADC 25 - 19 - ns 56 RESET Pulse Width (Reset Instruction) tHRPW 512 - 512 - CLKO1 RESET Pulse Width (Input from External Device) tRPWI 20 - 20 - CLKO1 57 BERR Negated to HALT Negated (Return) tBNHN 0 - 0 - ns 58 CLKO1 High to BERR, RESETS, RESETH Driven Low tCHBRL - 30 26 ns 58A CLKO1 Low RESETS Driven Low (upon Reset Instruction execution only) tCLRL - 30 26 ns 58B CLKO1 High to BERR, RESETS, RESETH tri-stated tCLRL - 20 - 15 ns 46 48 (5)(7) 56A Characteristic 33.34 MHz 60 CLKO1 High to BCLRO Asserted tCHBCA - 20 - 15 ns 61 CLKO1 High to BCLRO Negated tCHBCN - 20 - 15 ns BR Synchronous Setup Time tBRSU 5 - 3.75 - ns 63(9) BR Synchronous Hold Time tBRH 10 - 7.5 - ns 64(9) BGACK Synchronous Setup Time tBGSU 5 - 3.75 - ns BGACK Synchronous Hold Time tBGH 10 - 7.5 - ns 66 BR Low to CLKO1 Rising Edge (040 comp. mode) tBRCH 5 - 5 - ns 70 CLKO1 Low to Data Bus Driven (Show Cycle) tSCLDD 0 30 0 22.5 ns 71 Data Setup Time to CLKO1 Low (Show Cycle) tSCLDS 10 - 7.5 - ns 72 Data Hold from CLKO1 Low (Show Cycle) tSCLDH 6 - 3.75 - ns 73 BKPT Input Setup Time tBKST 10 - 7.5 - ns 74 BKPT Input Hold Time tBKHT 6 - 3.75 - ns 75 RESETH Low to Config2-0, MOD1-0, B16M Valid tMST - 500 - 500 CLKO1 76 Config2-0 tMSH 0 - 0 - ns 77 MOD1-0 Hold Time, B16M Hold Time tMSH 10 - 10 - CLKO1 80 DSI Input Setup Time tDSISU 10 - 7.5 - ns 62 65 (9) (9) 21 2113A–HIREL–03/02 Bus Operation AC Timing Specifications (Continued) GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 7 to Figure 23). 25 MHz Number Symbol Min Max Min Max Unit 81 DSI Input Hold Time tDSIH 6 - 3.75 - ns 82 DSCLC Setup Time tDSCSU 10 - 7.5 - ns 83 DSCLC Hold Time tDSCH 6 - 3.75 - ns 84 DSO Delay Time tDSOD - tcyc+2 0 - tcyc+2 0 ns 85 DSCLK Cycle tDSCCYC 2 - 2 - CLKO1 86 CLKO1 High to Freeze Asserted tFRZA 0 35 0 26.25 ns 87 CLKO1 High to Freeze Negated tFRZN 0 35 0 26.25 ns 88 CLKO1 High to IFETCH High Impedance tIFZ 0 35 0 26.25 ns 89 CLKO1 High to IFETCH Valid tIF 0 35 0 26.25 ns 90 CLKO1 High to PERR Asserted tCHPA 0 20 0 15 ns 91 CLKO1 High to PERR Negated tCHPN 0 20 0 15 ns 92 VCC Ramp-Up Time At Power-On Reset tRMIN 5 - 5 - ns Notes: 22 Characteristic 33.34 MHz 1. All AC timing is shown with respect to 0.8V and 2.0V levels unless otherwise noted. 2. This number can be reduced to 5 ns if strobes have equal loads. 3. If multiple chip selects are used, the CSx width negated (#15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. 4. Hold times are specified with respect to DS or CSx on asynchronous reads and with respect to CLKO1 on fast termination reads. The user is free to use either hold time for fast termination reads. 5. If the asynchronous setup (#17) requirements are satisfied, the DSACKx low to data setup time (#31) and DSACKx low to BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKO1 low setup time (#27) for the following clock cycle: BERR must only satisfy the late BERR low to CLKO1 low setup time (#27A) for the following clock cycle. 6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of the current operand transfer are complete and RMC is negated. 7. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous setup time (#47). 8. During interrupt acknowledge cycles, the processor may insert up to two wait states between states S0 and S1. 9. Specs are for Synchronous Arbitration only. ASTM = 1. 10. CSx specs are for TRLX = 0. 11. CSx specs are for TRLX = 1. 12. CSx specs are for CSNTQ = 0. 13. CSx specs are for CSNTQ = 1; or RASx specs for DRAM accesses. 14. Specs are read cycles with parity check and PBEE = 1. 15. Specs are read cycles with parity check and PBEE = 0, PAREN = 1. 16. RASx specs are for page miss case. 17. Specifications only apply to CSx/RASx pins. 18. Specification applies to non fast termination cycles. In fast termination cycles, the BERR signal must be negated by 20 ns after negation of AS, DS. TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 7. Read Cycle S0 S1 S2 S3 S4 S5 CLKO1 (OUTPUT) 6 8 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT) 11 16 14 AS (OUTPUT) 12 9 13 DS (OUTPUT) 15 9A CSx (OUTPUT) OE (OUTPUT) 18 20 21 R/W (OUTPUT) 46 DSACK0 (I/O) 28 47A DSACK1 (I/O) 31A 29 31 D31-D0 (INPUT) 27 48 BERR, HALT (INPUT) IFETCH IPIPE1,0 (OUTPUT) 27A 9 47A 29A 12 12 47B ASYNCHRONOUS INPUTS 73 74 BKPT (INPUT) Note: All timing is shown with respect to 0.8V and 2.0V levels. 23 2113A–HIREL–03/02 Figure 8. Fast Termination Read Cycle (Parity Check PAREN = 1, PBEE = 0) CPU CLEARS PERn BIT S1 S0 S4 S5 S0 S0 CLKO1 (OUTPUT) 8 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 9 14B AS (OUTPUT) 12 DS (OUTPUT) CSx (OUTPUT) OE (OUTPUT) R/W (OUTPUT) 18 46A 27 30 D31-D0 (INPUT) 30A 73 74 BKPT (INPUT) 90 91 PERR (OUTPUT) 24 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 9. Read Cycle (With Parity Check, PBEE = 1) S0 S1 S2 S3 S4 S5 CLKO1 (OUTPUT) 6 8 A31-A0, FC3-FC0, SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT) 11 16 14 AS (OUTPUT) 12 9 13 DS (OUTPUT) 15 9A CSx (OUTPUIT) OE (OUTPUT) 18 21 20 R/W (OUTPUT) 46 31A DSACK0 (I/O) 47A 28 DSACK1 (I/O) PRTY0-PRTY3 (INPUT) 29 31B D31-D0 (INPUT) 29A 27B BERR (INPUT) 48 27A HALT (INPUT) 9 12 12 IFETCH (OUTPUT) 47A 47B IPIPE1,0 (OUTPUT) ASYNCHRONOUS INPUTS 73 74 BKPT (INPUT) Note: All timing is shown with respect to 0.8V and 2.0V levels. 25 2113A–HIREL–03/02 Figure 10. SRAM: Read Cycle (TRLX = 1) S0 S2 S1 S3 S4 S5 CLKO1 (OUTPUT) 6 8 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT) 16 9C AS (OUTPUT) 13 11A 12 DS (OUTPUT) 15 9B CSx (OUTPUT) 20 21A OE (OUTPUT) 18 R/W (OUTPUT) 46 28 DSACK0 (I/O) 47A DSACK1 (I/O) 31A 29 31 D31-D0 (INPUT) 29A 27 26 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 11. CPU32+ IACK Cycle 0-2 CLOCKS * A1 S0 A2 A3 A4 S1 S2 S3 S4 S5 CLKO1 (OUTPUT) 8 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 11 16 14 AS (OUTPUT) 13 9 12 DS (OUTPUT) 15 9A IACKx (OUTPUT) OE (OUTPUT) 18 20 21 R/W (OUTPUT) 46 31A 28 DSACK0 (I/O) 47A DSACK1 (I/O) 31 29 D31-D0 (INPUT) 29A 27 Note: Up to two wait states may be inserted by the processor between states S0 and S1. 27 2113A–HIREL–03/02 Figure 12. Write Cycle S1 S0 S3 S2 S4 S5 CLKO1 (OUTPUT) 6 8 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 11 15 14 AS (OUTPUT) 9 12 9 13 DS (OUTPUT) 14A CSn (OUTPUT) 22 WEn (OUTPUT) 17 18 20 R/W (OUTPUT) 46 DSACK0 (I/O) 31A 28 47A DSACK1 (I/O) 25 55 53 D31-D0 (OUTPUT) 23 54 26 PRTY3-PRTY0 (OUTPUT) BERR (INPUT) 48 HALT (INPUT) 73 74 BKPT (INPUT) Note: 28 All timing is shown with respect to 0.8V and 2.0V levels. TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 13. Fast Termination Write Cycle S1 S0 CLKO1 (OUTPUT) S4 S0 S5 8 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 12 AS (OUTPUT) 9 14B CSx (OUTPUT) DS (OUTPUT) WEx (OUTPUT) 20 46A R/W (OUTPUT) 23 18 24 D31-D0 (OUTPUT) 25 PRTY3-PRTY0 (OUTPUT) 73 74 BKPT (INPUT) Figure 14. SRAM: Fast Termination Write Cycle (CSNTQ = 1) S4 S1 S0 S5 S0 CLKO1 (OUTPUT) 8 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 12A AS (OUTPUT) 9 14D CSx (OUTPUT) DS (OUTPUT) WEx (OUTPUT) 20 46A R/W (OUTPUT) 18 23 D31-D0 (OUTPUT) 25A PRTY3-PRTY0 (OUTPUT) 29 2113A–HIREL–03/02 Figure 15. SRAM: Write Cycle (TRLX = 1, CSNTQ = 1, TCYC = 0) S1 S0 S3 S2 S4 S5 CLKO1 (OUTPUT) A31-A0 (OUTPUT) AS (OUTPUT) 9C DS (OUTPUT) 11A 9B 12A CSx (OUTPUT) 14C WEx (OUTPUT) 13A 20 17A 22 R/W (OUTPUT) 46 47A DSACK0 (I/O) 31A DSACK1 (I/O) 55 25A 26 D31-D0 (OUTPUT) 23 PRTY0-PRTY3 (OUTPUT) Note: All timing is shown with respect to 0.8V and 2.0V levels. Figure 16. ASYNC Bus Arbitration – IDLE Bus Case CLKO1 (OUTPUT) A31-A0 (OUTPUT) D31-D0 (OUTPUT) AS (OUTPUT) 47A 47A BR (INPUT) 35 37 BG (OUTPUT) 33 34 47A BGACK (INPUT) 47A BCLRO (OUTPUT) 60 30 61 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 17. ASYNC Bus Arbitration – Active Bus Case S0 S1 S2 S3 S4 S5 CLKO1 (OUTPUT) A31-A0 (OUTPUT) 7 D31-D0 (OUTPUT) AS (OUTPUT) 16 DS (OUTPUT) R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) 47A 47A BR (INPUT) 39A 35 BG (OUTPUT) 33 34 BGACK (INPUT) 47A 37 BCLRO (OUTPUT) 60 Figure 18. SYNC Bus Arbitration – IDLE Bus Case CLKO1 (OUTPUT) A31-A0 (OUTPUT) D31-D0 (OUTPUT) AS (OUTPUT) 63 62 BR (INPUT) 37 35 BG (OUTPUT) 33 34 65 BGACK (INPUT) 64 BCLRO (OUTPUT) 60 61 31 2113A–HIREL–03/02 Figure 19. SYNC Bus Arbitration – Active Bus Case S0 S1 S2 S3 S4 S5 S98 CLKO1 (OUTPUT) A31-A0 (OUTPUT) 7 D31-D0 (OUTPUT) AS (OUTPUT) 16 DS (OUTPUT) R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) 62 BR (INPUT) 35 39A BG (OUTPUT) 33 34 BGACK (INPUT) 64 37 BCLRO (OUTPUT) 60 Figure 20. Configuration and Clock Mode Select Timing RESETH CONFIG2-CONFIG0, 76 MODCK1-MODCK0, 16BM 75 32 77 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 21. Show Cycle S0 S41 S42 S0 S43 S2 S1 CLKO1 (OUTPUT) 8 6 A31-A0 (OUTPUT) 18 R/W (OUTPUT) 20 AS (OUTPUT) 12 15 9 DS (OUTPUT) 72 71 70 D31-D0 27A BKPT (INPUT) SHOW CYCLE START OF EXTERNAL CYCLE Figure 22. Background Debug Mode FREEZE Timing CLKO1 86 FREEZE 87 IFETCH/DSI 89 88 Figure 23. Background Debug Mode Serial Port Timing CLKO1 FREEZE 83 82 BKPT/DSCLK 80 81 IFETCH 84 IPIPE0/DSO 85 DSI 80 33 2113A–HIREL–03/02 Bus Operation - DRAM Accesses AC Timing Specification GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 24 to Figure 28). 25.0 MHz Number Min 100 RASx Asserted to Row Address Invalid 15 11.25 ns 101 RASx Asserted to column Address Valid 20 15 ns 102 RASx Width Asserted 75 56.25 ns 103A RASx width Negated (Back to back Cycle) Non page mode @ WBTQ = 0 75 56.25 ns 103B RASx width Negated (Back to back Cycle) Page mode @ WBTQ = 0 55 41.25 ns 103C RASx width Negated (Back to back Cycle) Non page mode @ WBTQ = 1 115 86.25 ns 103D RASx width Negated (Back to back Cycle) Page mode @ WBTQ = 1 95 69.23 ns 104 RASx Asserted to CASx Asserted 35 26.25 ns 105 CLKO1 Low to CASx Asserted 3 13 2 10 ns CLKO1 High to CASx Asserted (Refresh Cycle) 3 13 2 10 ns 106 CLKO1 High to CASx Negated 3 13 2 10 ns 107 Column Address Valid to CASx Asserted 15 11.25 ns 108 CASx Asserted to Column Address Negated 40 30 ns 109 CASx Asserted to RASx Negated 35 27 ns 110 CASx Width Asserted 50 37.5 ns CASx Width Negated (Back to Back Cycles) 95 71.25 ns CASx Width Negated (Page Mode) 20 15 ns 113 WE Low to CASx Asserted 35 27 ns 114 CASx Asserted to WE Negated 35 27 ns 115 R/W Low to CASx Asserted (Write) 52.5 40 ns 116 CASx Asserted to R/W High (Write) 55 41.25 ns 117 Data-Out, Parity-Out Valid to CASx Asserted 10 7.5 ns 119 CLKO1 High to AMUX Negated 3 16 2 12 ns 120 CLKO1 High to AMUX Asserted 3 16 2 12 ns 121 AMUX High to RASx Asserted 15 11.25 ns 122 RASx Asserted to AMUX Low 15 11.25 ns 123 AMUX Low to CASx Asserted 15 11.25 ns 124 CASx Asserted to AMUX High 55 41.25 ns 125 RAS/CASx Negated to R/W change 0 0 ns 111 1 111A 34 Min Unit Characteristic 105A Max 33.34 MHz Max TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 24. DRAM: Normal Read Cycle (Internal Mux, TRLX = 0) S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 SW SW CLKO1 (OUTPUT) 6A 6 8 A31-A0 (OUTPUT) 108 11 107 AS (OUTPUT) 9 12 100 9 101 RASx (OUTPUT) 103 102 106 109 104 CAS3-CAS0 (OUTPUT) 110 111 105 OE (OUTPUT) 21 18 R/W (OUTPUT) DSACK1,0 (I/O) 27 D31ÐD0 (INPUT) PBEE = 0 29 27B PARITY3-PARITY0 (INPUT) PBEE = 1 D31-D0 (INPUT) Note: All timing is shown with respect to 0.8V and 2.0V levels. 35 2113A–HIREL–03/02 Figure 25. DRAM: Normal Write Cycle S1 S0 S3 S2 S5 S4 S0 CLKO1 (OUTPUT) 6A 6 8 A31-A0 (OUTPUT) 108 11 107 AS (OUTPUT) 9 12 100 RASx (OUTPUT) 101 102 106 CAS3-CAS0 (OUTPUT) 105 113 WEx (OUTPUT) 110 114 20 116 115 R/W (OUTPUT) 17 DSACK1,0 (I/O) 117 D31-D0 (OUTPUT) 23 53 PARITY0-PARITY3 (OUTPUT) Note: 36 All timing is shown with respect to 0.8V and 2.0V levels. TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 26. DRAM: Refresh Cycle S4 S5 S0 S1 CLKO1 (OUTPUT) A31-A0 (OUTPUT) 106 CAS3-CAS0 (OUTPUT) 105A 12 12 9 RASx (OUTPUT) 12A RASx (OUTPUT) PAGE MODE NOT IN PAGE MODE Note: All timing is shown with respect to 0.8V and 2.0V levels. Figure 27. DRAM: Page Mode – Page-Hit S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 CLKO1 (OUTPUT) 6A 8 6A A31-A0 (OUTPUT) 108 11 INTERNAL INTERNALMUX MUX 107 107 AS (OUTPUT) 9 100 RASx (OUTPUT) 105 101 106 CAS3-CAS0 (OUTPUT) 121 122 105 111A 123 AMUX (OUTPUT) 119 120 124 EXTERNAL MUX Note: All timing is shown with respect to 0.8V and 2.0V levels. 37 2113A–HIREL–03/02 Figure 28. DRAM: Page Mode – Page-Miss S0 S1 S2 S3 S4 S5 S1 S0 S2 S3 SW SW CLKO1 (OUTPUT) 6A 6A 8 A31-A0 (OUTPUT) INTERNAL MUX 11 AS (OUTPUT) 9 12A RASn (OUTPUT) 106 CAS3-CAS0 (OUTPUT) 105 122 123 AMUX (OUTPUT) 120 119 120 EXTERNAL MUX Note: 38 All timing is shown with respect to 0.8V and 2.0V levels. TS68EN360 2113A–HIREL–03/02 TS68EN360 040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 29). 25.0 MHz Number Min Max Min Max Unit Address, Transfer Attributes High Impedance to Clock High 7 - 6 - ns Clock High to BG Low - 20 - 15 ns 233 Clock High to BG High 4 20 4 15 ns 234 BB High to Clock High (040 output) 7 - 6 - ns 235 BB High Impedance to Clock High (040 output) 0 - 0 - ns 236 Clock High to BB Low (360 Output) - 20 - 15 ns 237 Clock High to BB High (360 Output) - 20 - 15 ns 238 Clock Low to BB High Impedance (360 output) - 20 - 15 ns 231 232 Note: (1) Characteristic 33.34 MHz 1. BG remains low until either the SDMA or the IDMA requests the external bus. Figure 29. TS68040 Companion Mode Arbitration 040 BUS MASTER 360 BUS MASTER C2 C1 S0 S1 S2 S3 S4 S5 CLKO1 (OUTPUT) A31-A0 (I/O) 231 TRANSFER ATTRIBUTES (INPUT) 232 233 BG (OUTPUT) 234 BB (I/O) 237 235 238 236 60 61 BCLRO (OUTPUT) 140 141 BCLRI (INPUT) Notes: 1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK. 2. BG always remains asserted until either the SDMA or the IDMA requests the external bus. 39 2113A–HIREL–03/02 040 Bus Type Slave Mode Internal Read/Write/Lack Cycles AC Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 30 to Figure 33) 25.0 MHz Number Min Max Min Max Unit Address, Transfer Attributes Valid to Clock Low 15 - 11.25 - ns 252 TS Low to Clock High 7 - 6 - ns 253 Clock High to TS High 5 - 3 - ns 254 Clock high to Address, Transfer Attributes Invalid 0 - 0 - ns 255 Data-In, MBARE Valid to Clock High (040 Write) 0 - 0 - ns 256 Clock High to Data-In, MBARE Hold Time 0 - 0 - ns 257 Clock High to TA, TBI Low (External to External) 4 20 4 15 ns 257 Clock High to TA, TBI Low (External to Internal) 4 23 4 18 ns Clock High to TA, TBI High 4 20 4 15 ns 259 TA, TBI High to TA, TBI High Impedance - 15 - 11.25 ns 260 Clock Low to Data-Out Valid (040 Read) - 20 - 15 ns 262 Clock Low to Data-Out Invalid - 20 - 15 ns 263 Clock Low to Data-Out High Impedance - 15 - 264 Clock High to AVECO Low - 20 - 15 ns 265 Clock Low to AVECO High Impedance - 30 - 23 ns 266 Clock Low to IACK Low - 30 - 23 ns 267 Clock High to IACK High - 30 - 23 ns Clock Low to AVEC Low - 30 - 23 ns 251(1) 258(2)(3) 268 Notes: 40 Characteristic 33.34 MHz ns 1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK. 2. When TS68040 is accessing the internal registers, specification 258 is from clock low not clock high. 3. The clock reference is EXTAL, not CLK01.TS68040 Internal Registers Read Cycles TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 30. TS68040 Internal Registers Read Cycles C1 C2 CW CW CW CW C1 CLKO1 (OUTPUT) 251 A31-A0 (INPUT) 254 TRANSFER ATTRIBUTES (INPUT) 253 252 TS (INPUT) 260 263 D31-D0 (040 WRITE) (INPUT) TA (OUTPUT) 258 257 259 TBI (OUTPUT) 3Ð4 CLOCKS Notes: 1. Three wait states are inserted when reading the SIM, dual-port RAM, and CPM. Four wait states are inserted when reading the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10 and one of the internal masters is accessing an internal peripheral. 2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK. Figure 31. TS68040 Internal Registers Write Cycles C1 C2 CW CW CW C1 CLKO1 (OUTPUT) 251 A31-A0 (INPUT) 254 TRANSFER ATTRIBUTES (INPUT) 252 TS (INPUT) D31-D0 (040 WRITE) (INPUT) 253 256 255 256 255 MBARE (INPUT) 258 TA (OUTPUT) 257 TBI (OUTPUT) Notes: 259 2Ñ4 CLOCKS 1. Two wait states are inserted when writing. Three wait states are inserted when writing to the dual-port RAM and CPM. Four wait states are inserted when writing to the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10 and one of the internal masters is accessing an internal peripheral. 2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK. 41 2113A–HIREL–03/02 Figure 32. TS68040 IACK Cycles (Vector Driven) C1 C2 CW CW CW CW CW CLKO1 (OUTPUT) 251 254 A31-A0 (INPUT) TRANSFER ATTRIBUTES (INPUT) 253 252 TS (INPUT) 263 262 D31-D0 (OUTPUT) 260 258 TA (OUTPUT) 257 259 TBI (OUTPUT) IACK7-1 (OUTPUT) 266 267 0Ð2 CLOCKS Notes: 1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK. 2. Up to two wait states may be inserted for internal peripheral. Figure 33. TS68040 IACK Cycles (No Vector Driven) C1 C2 CW CW CLKO1 (OUTPUT) 251 254 A31-A0 (INPUT) TRANSFER ATTRIBUTES (INPUT) 253 252 TS (INPUT) 290 TA (INPUT) 289 TBI (OUTPUT) 257 250 264 265 AVECO (OUTPUT) IACK7-1 (OUTPUT) 266 Note: 42 267 TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK. TS68EN360 2113A–HIREL–03/02 TS68EN360 040 Bus Type SRAM/DRAM Cycles AC Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 34 to Figure 38). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit 280 Address Valid to BADD2-3 Valid - 20 - 15 ns 280A BADD2-3 Valid to CAS Assertion 15 - 10 - ns 281 Address Invalid to BADD2-3 Invalid 0 - 0 - ns 282 Clock High to CSx/RASx Low (TSS40 = 0) 4 16 4 12 ns 283 Clock High to CSx/RASx High (CSNT40 = 0) 4 16 4 12 ns 284 Clock High to BRK Low - 20 - 15 ns 284A Clock Low to BRK Low - 20 - 15 ns 285 Clock high to BRK High - 20 - 15 ns 286 Clock Low to CSx/RASx Low (TSS40 = 1) 4 16 4 12 ns 287 Clock Low to CSx/RASx High (CSNT40 = 1) 4 16 4 12 ns 288 (1) Address Transfer Attributes Valid to Clock High (TSS40 = 0) 10 - 10 - ns 289 (2) TA Low to Clock High (External Termination) 11 - 9 - ns Clock High to TA High (External Termination) - 20 - 15 ns 291 Clock High to OE Low (Read Cycles) - 20 - 15 ns 292 Clock High to OE High (Read Cycles) - 20 - 15 ns 293 Clock High to WE Low (Write Cycles) - 20 - 15 ns 294 Clock High to WE High (Write Cycles) - 20 - 15 ns 295 Clock High to CASx Low 4 13 4 10 ns Clock Low to CASx Low (040 Burst Read only) 4 13 4 10 ns Clock High to CASx High 4 13 4 10 ns 297 Clock Low to AMUX Low 3 16 3 12 ns 298 Clock High to AMUX High 3 16 3 12 ns 299 Clock High to BADD2-3 Valid (040 Burst Cycles) 4 20 4 15 ns TEA Low to Clock High 11 - - ns Clock High to TEA High 2 20 2 15 ns 302 Data, Parity Valid to Clock High (Data, Parity Setup) 7 - 6 - ns 303 Clock High to Data, Parity Invalid (Data, Parity Hold) 7 - 5 - ns 305 CLKO1 High (After TS Low) to Parity Valid - 20 - 15 ns CLKO1 High (After TA Low) to Parity Hi-Z 4 20 15 ns 290(2) 295A 296 300 (3) (2) 301(2) 306 Notes: 1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK. 2. TEA/TA should not be asserted on a DRAM burst access, or on the same clock or before RASx/CSx is asserted. 3. The clock reference is EXTAL, not CLK01. 43 2113A–HIREL–03/02 Figure 34. TS68040 SRAM Read/Write Cycles (TSS40 = 0, CSNT40 = 0) C1 C2 CLKO1 (OUTPUT) 288 TRANSFER ATTRIBUTES (INPUT) 254 A31-A0 (INPUT) 280 281 BADD3BADD2 (OUTPUT) TS (INPUT) 252 282 253 283 CSx (OUTPUT) 258 TA (OUTPUT) 259 257 TBI (OUTPUT) 284 BKPTO (OUTPUT) 285 OE (OUTPUT) (READ CYCLES) 291 292 WE (OUTPUT) (WRITE CYCLES) 293 294 300 301 TEA (INPUT) Note: 44 TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK. TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 35. TS68040 SRAM Read/Write Cycles (TSS40 = 1, CSNT40 = 1) C1 C2 C3 CLKO1 (OUTPUT) 251 TRANSFER ATTRIBUTES (INPUT) 254 A31-A0 (INPUT) 281 280 BADD3BADD2 (OUTPUT) 253 TS (INPUT) 252 287 CSn (OUTPUT) 286 258 TA (OUTPUT) 259 257 TBI (OUTPUT) 284A 285 BKPTO (OUTPUT) 300 301 289 290 TEA (INPUT) TA (INPUT) 45 2113A–HIREL–03/02 Figure 36. External TS68040 DRAM Cycles Timing Diagram C1 Cw C2 C1 CLKO1 (OUTPUT) 288 TRANSFER ATTRIBUTES (INPUT) 254 A31-A0 (INPUT) 281 280 BADD3BADD2 (OUTPUT) 253 252 TS (INPUT) 282 283 RASx (OUTPUT) 296 295 CAS3CAS0 (OUTPUT) 122 121 123 298 298 AMUX (OUTPUT) 297 WE (WRITE CYCLE OUTPUT) 294 293 258 TA (OUTPUT) 257 259 TBI (OUTPUT) TEA (INPUT) 46 300 301 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 37. External TS68040 DRAM Burst Cycles Timing Diagram C1 Cw C1 C2 C2 CLKO1 (OUTPUT) 288 TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) 299 280 299 BADD3BADD2 (OUTPUT) TS (INPUT) 252 253 282 RASx (OUTPUT) 295A 296 296 CAS3CAS0 (OUTPUT) 295 295 AMUX (OUTPUT) 297 WE (WRITE CYCLE OUTPUT) 293 258 TA (OUTPUT) 257 258 257 TBI (OUTPUT) 47 2113A–HIREL–03/02 Figure 38. External TS68040 Parity Bit Checking Timing Diagram D31-D0 (INPUT) PRTY3PRTY0 (OUTPUT) 212 213 (a) Generation Timing Diagram CPU Clears PERn Bit C1 C2 C1 CLKO1 (OUTPUT) TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) BADD3BADD2 (OUTPUT) TS (INPUT) TA (OUTPUT) 302 303 D31-D0, (INPUT) 305 PRTY3PRTY0 (INPUT) 306 90 91 PERR (OUTPUT) (b) Checking Timing Diagram 48 TS68EN360 2113A–HIREL–03/02 TS68EN360 IDMA AC Electrical Specifications GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary (See Figure 39 and Figure 40). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit 1 CLKO1 Low to DACK, DONE Asserted 3 24 3 18 ns 2 CLKO1 Low to DACK, DONE Negated 3 24 3 18 ns 3 (1) DREQx Asserted to AS Asserted (for DMA Bus Cycle) 4 (1) Asynchronous Input Setup Time to CLKO1 Low 12 - 9 - ns Asynchronous Input Hold Time from CLKO1 Low 0 - 0 - ns 6 AS to DACK Assertion Skew 0 20 0 15 ns 7 DACK to DONE Assertion Skew -8 8 -6 6 ns 8 AS, DACK, DONE Width Asserted 70 - 52.5 - ns 5(1) 8A 3tcyc + tAIST + tCLSA AS, DACK, DONE Width Asserted (Fast Termination Cycle) 28 - 20.5 - ns (1) Asynchronous Input Setup Time to CLKO1 Low 5 - 4 - ns (1) Asynchronous Input Hold Time from CLKO1 Low 10 - 7.5 - ns (2) 12 DREQ Input Setup Time to CLKO1 Low 20 - 15 - ns 13(2) 10 11 DREQ Input Hold Time from CLKO1 Low 5 - 3.75 - ns (2) DONE Input Setup Time to CLKO1 Low 20 - 15 - ns (2) DONE Input Hold Time From CLKO1 Low 5 - 3.75 - ns (2) DREQ Asserted to AS Asserted 2 - 2 - clk 14 15 16 Notes: 1. These specifications are for asynchronous mode. 2. These specifications are for synchronous mode. 49 2113A–HIREL–03/02 Figure 39. IDMA Signal Asynchronous Timing Diagram CPU_CYCLE (IDMA REQUEST) S0 S1 S2 IDMA_CYCLE S3 S5 S4 S0 S1 S3 S2 S5 S4 CLKO1 (OUTPUT) 4 1 5 DREQ (INPUT) 6 8 3 AS (OUTPUT) 1 2 DACK (OUTPUT) 7 DONE (OUTPUT) 1 DONE (INPUT) 11 10 Figure 40. IDMA Signal Synchronous Timing Diagram CPU_CYCLE (IDMA REQUEST) S0 S1 S2 IDMA_CYCLE S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKO1 (OUTPUT) 12 DREQ (INPUT) 1 13 6 8 16 AS (OUTPUT) 1 2 DACK (OUTPUT) 7 DONE (OUTPUT) 1 DONE (INPUT) 15 14 50 TS68EN360 2113A–HIREL–03/02 TS68EN360 PIP/PIO Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C.The electrical specifications in this document are preliminary (See Figure 41 to Figure 45). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit 21 Data-In Setup Time to STBI Low 0 - 0 - ns 22 Data-In Hold Time to STBI High 2.5 - t3 - 2.5 - t3 - clk 23 STBI Pulse Width 1.5 - 1.5 - clk 24 STBO Pulse Width 1 CLKO1 5 ns - 1 CLKO1 5 ns - - 25 Data-Out Setup Time to STBO Low 2 - 2 - clk 26 Data-Out Hold Time from STBO High 5 - 5 - clk 27 STBI Low to STBO Low (Rx Interlock) - 2 - 2 clk 28 STBI Low to STBO High (Tx Interlock) 2 - 2 - clk 29 Data-In Setup Time to Clock Low 20 - 15 - ns 30 Data-In Hold Time from Clock Low 10 - 7.5 - ns - 25 - 25 ns Clock High to Data-Out Valid (CPU Writes Data, Control, or Direction) Note: 1. t3 = spec. 3 on “AC Electrical Specifications Control Timing” on page 17. Figure 41. PIP Rx (Interlock Mode) 26 25 DATA OUT STRBO (OUTPUT) 28 23 STRBI (INPUT) 51 2113A–HIREL–03/02 Figure 42. PIP Tx (Interlock Mode) 22 21 DATA IN 23 STRBI (INPUT) 24 STRBO (OUTPUT) Figure 43. PIP Tx (Pulse Mode) 22 21 DATA IN 23 STBI (INPUT) 24 STBO (OUTPUT) 52 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 44. PIP Tx (Pulse Mode) 26 25 DATA OUT 24 STBO (OUTPUT) 23 STBI (INPUT) Figure 45. Parallel I/O Data-in/Data-out Timing Diagram CLKO1 (OUTPUT) DATA IN 29 30 DATA OUT 31 CPU WRITE S4 Interrupt Controller AC Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C.The electrical specifications in this document are preliminary. (See Figure 46 and Figure 47). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit 35 Port C Interrupt Pulse Width Low (Edge Triggered Mode) 70 - 55 - ns 36 Minimum Time Between Active Edges Port C 70 - 55 - clk 37 Clock High to IOUT Valid (Slave Mode) - 20 - 17 ns 38 Clock High to RQOUT Valid (Slave Mode) - 20 - 17 ns 53 2113A–HIREL–03/02 Figure 46. Interrupts Timing Diagram Port C (INPUT) 35 36 Figure 47. Slave Mode: Interrupts Timing Diagram CLKO1 (OUTPUT) IOUT2IOUT0 (OUTPUT) 37 RQOUT (OUTPUT) 38 BAUD Rate Generator AC Electrical Specifications GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary (See Figure 48). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit - 10 - 7.5 ns 60 40 60 % 50 BRGO Rise and Fall Time 51 BRGO Duty Cycle 40 52 BRGO Cycle 40 30 ns Figure 48. Baud Rate Generator Output Signals 50 50 BRGOx 51 51 52 54 TS68EN360 2113A–HIREL–03/02 TS68EN360 Timer Electrical Specifications GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 49). 25.0 MHz Number Characteristic 33.34 MHz Symbol Min Max Min Max Unit 61 TIN/TGATE Rise and Fall Time trf 10 - 10 - ns 62 TIN/TGATE Low Time - 1 - 1 - clk 63 TIN/TGATE High Time - 2 - 2 - clk 64 TIN/TGATE Cycle Time - 3 - 3 - clk 65 CLKO1 High to TOUT Valid tTO 3 25 3 22 ns Figure 49. CPM General-purpose Timers 60 CLKO1 (OUTPUT) 61 62 63 TIN/TGATE (INPUT) 64 61 65 TOUT (OUTPUT) 55 2113A–HIREL–03/02 SI Electrical Specifications GND = 0 VDC, TC = -55 to +125°C.The electrical specifications in this document are preliminary (See Figure 50 to Figure 54). 25.0 MHz Number (1)(3) (1) 70 71 71A(2) Characteristic 33.34 MHz Min Max Min Max Unit L1RCLK, L1TCLK Frequency (DCS = 0) - 10 - 10 MHz L1RCLK, L1TCLK Width Low (DCS = 0) P+10 - P+10 - ns L1RCLK, L1TCLK Width High (DCS = 0) P+10 - P+10 - ns - 15 - 15 ns 72 L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time 73 L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time) 20 - 20 - ns 74 L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time) 35 - 35 - ns 75 L1RSYNC, L1TSYNC Rise/Fall Time - 15 - 15 ns 76 L1RXD Valid to L1CLK Edge (L1RXD Setup Time) 42 - 42 - ns 77 L1CLK Edge to L1RXD Invalid (L1RXD Hold Time) 35 - 35 - ns 78 L1CLK Edge to L1ST(1-4) Valid 10 45 10 45 ns 78A(4) L1SYNC Valid to L1ST(1-4) Valid 10 45 10 45 ns 79 L1CLK Edge to L1ST(1-4) Invalid 10 45 10 45 ns 80 L1CLK Edge to L1TXD Valid 10 65 10 65 ns L1TSYNC Valid to L1TXD Valid 10 65 10 65 ns 81 L1CLK Edge to L1TXD High Impedance 0 42 0 42 ns 82 L1RCLK, L1TCLK Frequency (DSC = 1) - 12.5 - 16 MHz 83 L1RCLK, L1TCLK Width Low (DSC = 1) P+10 - P+10 - ns 83A L1RCLK, L1TCLK Width High (DSC = 1) P+10 - P+10 - ns 84 L1CLK Edge to L1CLKO Valid (DSC = 1) - 30 - 30 ns (4) 80A (2) 85(3) L1RQ Valid Before Falling Edge of L1TSYNC 1 - 1 - L1TCLK (3) L1GR Setup Time 42 - 42 - ns (3) L1RG Hold Time 42 - 42 - ns - 0 - 0 ns 86 87 L1CLK Edge to L1SYNC Valid (FSD = 00, CNT = 0000, BYT = 0, DSC = 0) 88 Notes: 56 1. 2. 3. 4. The ratio SyncCLK/L1RC LK must be greater than 2.5/1. Where P = 1/CLKO1. Thus for a 25 MHz CLKO1 rate, P = 40 ns. These specs are valid for IDL mode only. The strobes and Txd on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later. TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 50. SI Receive Timing with Normal Clocking (DSC = 0) L1RCLK (FE = 0,CE = 0) (INPUT) 72 70 L1RCLK (FE =1,CE = 1) (INPUT) 71 75 RFCD = 1 L1RSYNC (INPUT) 73 74 77 76 L1RXD (INPUT) BIT0 78 79 L1ST (4-1) (OUTPUT) 57 2113A–HIREL–03/02 Figure 51. SI Receive Timing with Double Speed Clocking (DSC = 1) 72 L1RCLK (FE = 0, CE = 0) (INPUT) 83A 82 L1RCLK (FE = 1, CE = 1) (INPUT) 75 RFCD = 1 L1RSYNC (INPUT) 73 74 77 76 L1RXD (INPUT) BIT0 78 79 L1ST (4-1) (OUTPUT) L1CLKO (OUTPUT) 84 58 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 52. SI Transmit Timing with Normal Clocking (DSC = 0) L1TCLK (FE = 0, CE = 0) (INPUT) 72 70 L1TCLK (FE = 1, CE = 1) (INPUT) 71 75 L1TSYNC (OUTPUT) 73 74 81 80A L1TXD (INPUT) TFCD = 0 BIT0 80 78A 79 L1ST (4-1) (OUTPUT) 78 59 2113A–HIREL–03/02 Figure 53. SI Transmit Timing with Double Speed Clocking (DSC = 1) 72 83A L1RCLK (FE = 0, CE = 0) (INPUT) 82 L1RCLK (FE = 1, CE = 1) (INPUT) 75 L1TSYNC (INPUT) 73 74 TFCD = 0 81 80A L1TXD (OUTPUT) BIT0 80 78A 79 L1ST (1-4) (OUTPUT) 78 L1CLKO (OUTPUT) 84 60 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 54. IDL Timing SI Transmit Timing with Double Speed Clocking (DSC = 1) SCC in NMSI Mode-external Clock Electrical Specifications GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 55 to Figure 57). 25.0 MHz Number Min Max Min Max RCLK1 and TCLK1 Width High CLKO1 - CLKO1 - 101 RCLK1 and TCLK1 Width Low CLKO1 + 5 ns - CLKO1 + 5 ns - 102 RCLK1 and TCLK1 Rise/Fall Time - 15 - 15 ns 103 TXD1 Active Delay (From TCLK1 Falling Edge) 0 50 0 50 ns 104 RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) 0 50 0 50 ns 105 CTS1 Setup Time to TCLK1 Rising Edge 40 - 40 - ns 106 RXD1 Setup Time to RCLK1 Rising Edge 40 - 40 - ns RXD1 Hold Time from RCLK1 Rising Edge 0 - 0 - ns CD1 Setup Time to RCLK1 Rising Edge 40 - 40 - ns 100 (1) 107(2) 108 Notes: Characteristic 33.34 MHz Unit 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1. 2. Also applies to CD and CTS hold time when they are used as external sync signals. 61 2113A–HIREL–03/02 SCC in NMSI Mode-internal Clock Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 55 to Figure 57). 25.0 MHz Number Min Max Min Max Unit RCLK1 and TCLK1 Frequency 0 8.3 0 11 MHz 102 RCLK1 and TCLK1 Rise/Fall Time - - - - ns 103 TXD1 Active Delay (From TCLK1 Falling Edge) 0 30 0 30 ns 104 RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) 0 30 40 - ns 105 CTS1 Setup Time to TCLK1 Rising Edge 40 - 40 - ns 106 RXD1 Setup Time to RCLK1 Rising Edge 40 - 0 - ns RXD1 Hold Time from RCLK1 Rising Edge 0 - 40 - ns CD1 Setup Time to RCLK1 Rising Edge 40 - 0 30 ns 100 (1) 107(2) 108 Notes: Characteristic 33.34 MHz 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1. 2. Also applies to CD and CTS hold time when they are used as external sync signals. Figure 55. SCC NMSI Receive 102 102 101 RCLK1 100 106 RXD1 (INPUT) 107 CD1 (INPUT) 108 107 CD1 (SYNCINPUT) 62 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 56. SCC NMSI Transmit 102 102 101 TCLK1 100 103 TXD1 (OUTPUT) RTS1 (OUTPUT) 104 104 105 CTS1 (INPUT) 107 CTS1 (SYNCINPUT) Figure 57. HDLC BUS Timing 102 102 101 TCLK1 100 103 TXD1 (OUTPUT) RTS1 (OUTPUT) 104 104 107 105 CTS1 (ECHO INPUT) 63 2113A–HIREL–03/02 Ethernet Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 58 to Figure 63). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit 40 - 40 - ns - 15 - 15 ns 120 CLSN Width High 121 RCLK1 Rise/Fall Time 122 RCLK1 Width Low CLKO1 + 5 ns - CLKO1 + 5 ns - 123(1) RCLK1 Width High CLKO1 - CLKO1 - 124 RXD1 Setup Time 20 - 20 - ns 125 RXD1 Hold Time 5 - 5 - ns 126 RENA Active Delay (from RCLK1 rising edge of the last data bit) 10 - 10 - ns 127 RENA Width Low 100 - 100 - ns 128 TCLK1 Rise/Fall Time - 15 - 15 ns 129 TCLK1 Width Low CLKO1 + 5 ns - CLKO1 + 5 ns - 130(1) TCLK1 Width High CLKO1 - CLKO1 - 131 TXD1 Active Delay (from TCLK1 rising edge) 10 50 10 50 ns 132 TXD1 Inactive Delay (from TCLK1 rising edge) 10 50 10 50 ns 133 TENA Active Delay (from TCLK1 rising edge) 10 50 10 50 ns 134 TENA Inactive Delay (from TCLK1 rising edge) 10 50 10 50 ns 135 RSTRT Active Delay (from TCLK1 falling edge) 10 50 10 50 ns 136 RSTRT Inactive Delay (from TCLK1 falling edge) 10 50 10 50 ns 137 RRJCT Width Low 1 - 1 - CLKO1 138 (2) CLKO1 Low to SDACK Asserted - 20 - 20 ns 139 (2) CLKO1 Low to SDACK Negated - 20 - 20 ns Notes: 1. SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1 2. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. Figure 58. Ethernet Collision Timing CLSN (CTS1) (INPUT) 120 64 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 59. Ethernet Receive Timing 121 121 122 RCLK1 123 124 RXD1 (INPUT) LAST BIT 125 127 RENA (CD1) (INPUT) 126 Figure 60. Ethernet Transmit Timing 128 128 129 TCLK1 (NOTE 1) 130 131 132 TXD1 (OUTPUT) 133 TENA (RTS1) (OUTPUT) 134 RENA (CD1) (INPUT) (NOTE 2) Notes: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is deasserted before TENA, or RENA is not asserted at all during transit, then CSL bit is set in the buffer descriptor at the end of frame transmission. 65 2113A–HIREL–03/02 Figure 61. CAM Interface Receive Start Timing RCLK1 RXD1 (INPUT) 1 0 1 Bit # 1 Bit # 2 START FRAME DELIMITER 135 136 RSTRT (OUTPUT) Note: Valid for the ethernet protocol only. Figure 62. CAM Interface Reject Timing 137 RRJCT (INPUT) Note: Valid for the ethernet protocol only. Figure 63. SDACK Timing Diagram SDMA CYCLE S0 S1 S2 S3 S4 S5 CLKO1 (OUTPUT) AS (OUTPUT) SDACKx (OUTPUT) Note: 138 139 SDACKx is asserted when the SDMA writes the received Ethernet frame into memory. SMC Transparent Mode Electrical Specifications GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 64). 25.0 MHz Number Characteristic Min Max Min Max Unit SMCLK Clock Period 100 - 100 - ns 151 SMCLK Width Low 50 - 50 - ns 151A SMCLK Width High 50 - 50 - ns 150(1) 66 33.34 MHz TS68EN360 2113A–HIREL–03/02 TS68EN360 SMC Transparent Mode Electrical Specifications GND = 0 VDC, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 64). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit - 15 - 15 ns 152 SMCLK Rise/Fall Time 153 SMTXD Active Delay (from SMCLK falling edge) 10 50 10 50 ns 154 SMRXD/SYNC1 Setup Time 20 - 20 - ns 155 SMRXD/SYNC1 Hold Time 5 - 5 - ns Note: 1. The ratio SyncCLK/SMCLK must be greater or equal to 2/1. SMC Transparent. Figure 64. SMC Transparent 152 152 151A 151 SMCLK 150 TXD1 (OUTPUT) Note 1 153 154 155 SYNC1 154 RXD1 (INPUT) 155 Note: This delay is equal to an integer number of “Character length” clocks. 67 2113A–HIREL–03/02 SPI Master Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 65 and Figure 66). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit 160 Master Cycle Time 4 1024 4 1024 tcyc 161 Master Clock (SPICLK) High or Low Time 2 512 2 512 tcyc 162 Master Data Setup Time (Inputs) 50 - 50 - ns 163 Master Data Hold Time (Inputs) 0 - 0 - ns 164 Master Data Valid (after SPICLK Edge) - 20 - 20 ns 165 Master Data Hold Time (Outputs) 0 - 0 - ns 166 Rise Time: Output 15 15 ns 167 Fall Time: Output 15 15 ns Figure 65. SPI Master (CP = 0) 167 166 SPICLK CI=0 OUTPUT 167 161 160 SPICLK CI=1 OUTPUT 161 162 166 163 SPIMISO INPUT MSB IN DATA 165 SPIMOSI OUTPUT "1" MSB OUT 167 68 MSB IN LSB IN 164 DATA LSB OUT "1" MSB OUT 166 TS68EN360 2113A–HIREL–03/02 TS68EN360 Figure 66. SPI Master (CP = 1) 167 160 166 SPICLK CI=0 OUTPUT 161 160 SPICLK CI=1 OUTPUT 163 166 161 162 SPIMISO INPUT MSB IN DATA 165 SPIMOSI OUTPUT "1" MSB OUT DATA MSB LSB IN 164 LSB OUT "1" MSB 166 167 SPI Slave Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 67 and Figure 68). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit - 2 - tcyc 170 Slave Cycle Time 2 171 Slave Enable Lead Time 15 15 ns 172 Slave Enable Lag Time 15 15 ns 173 Slave Clock (SPICLK) High or Low Time 1 174 Slave Sequential Transfer Delay (Does Not Require Deselect) 1 175 Slave Data Setup Time (Inputs) 20 - 20 - ns 176 Slave Data Hold Time (Inputs) 20 - 20 - ns 177 Slave Access Time 50 50 ns 178 Slave SPIMISO Disable Time 50 50 ns 179 Slave Data Valid (after SPICLK Edge) - 50 - 50 ns 180 Slave Data Hold Time (Outputs) 0 - 0 - ns 181 Rise Time: Input 15 15 ns 182 Fall Time: Input 15 15 ns - 1 - 1 tcyc tcyc 69 2113A–HIREL–03/02 Figure 67. SPI Slave (CP = 0) 171 172 SPISEL INPUT 174 182 181 SPICLK CI=0 INPUT 173 170 SPICLK CI=1 INPUT 181 173 SPIMISO OUTPUT 182 MSB OUT 180 179 180 177 DATA LSB OUT UNDEF. 181 176 178 MSB OUT 182 175 SPIMOSI INPUT MSB IN DATA LSB IN MSB IN Figure 68. SPI Slave (CP = 1) SPISEL INPUT 174 182 170 181 173 SPICLK CI=0 INPUT 172 173 171 SPICLK CI=1 INPUT 181 179 179 180 177 SPIMISO OUTPUT UNDEF. 182 MSB OUT DATA SLAVE LSB OUT 178 UNDEF. 181 176 175 SPIMOSI INPUT 70 MSB IN DATA LSB IN TS68EN360 2113A–HIREL–03/02 TS68EN360 JTAG Electrical Specifications GND = 0 Vdc, TC = -55 to +125°C. The electrical specifications in this document are preliminary (See Figure 69 and Figure 72). 25.0 MHz Number Characteristic 33.34 MHz Min Max Min Max Unit TCK Frequency of Operation 0 25 0 25 MHz 1 TCK Cycle Time in Crystal Mode 40 - 40 - ns 2 TCK Clock Pulse Width Measured at 1.5V 18 - 18 - ns 3 TCK rise and Fall Times 0 3 0 3 ns 6 Boundary Scan Input Data Setup Time 10 - 10 - ns 7 Boundary Scan Input Data Hold Time 18 - 18 - ns 8 TCK Low to Output Data Valid 0 30 0 30 ns 9 TCK Low to Output High Impedance 0 40 0 40 ns 10 TMS, TDI Data Setup Time 10 - 10 - ns 11 TMS, TDI Data Hold Time 10 - 10 - ns 12 TCK Low to TDO Data Valid 0 20 0 20 ns 13 TCK Low to TDO High Impedance 0 20 0 20 ns 14 TRST Assert Time 100 - 100 - ns 15 TRST Setup Time to TCK Low 40 - 40 - ns Figure 69. Test Clock Input Timing Diagram 1 2 2 VIH TCK (INPUT) VM VM VIL 3 3 Figure 70. TRST Timing Diagram TCK (INPUT) 15 TRST (INPUT) 14 71 2113A–HIREL–03/02 Figure 71. Boundary Scan (JTAG) Timing Diagram TCK (INPUT) VIH VIL 6 DATA INPUTS 7 INPUT DATA VALID 8 DATA OUTPUTS OUTPUT DATA VALID 9 DATA OUTPUTS 8 DATA OUTPUTS OUTPUT DATA VALID Figure 72. Test Access Port Timing Diagram TCK (INPUT) VIH VIL 10 TDI TMS (INPUT) 11 INPUT DATA VALID 12 TDO (OUTPUT) OUTPUT DATA VALID 13 TDO (OUTPUT) 12 TDO (OUTPUT) 72 OUTPUT DATA VALID TS68EN360 2113A–HIREL–03/02 TS68EN360 Functional Description CPU32+ Core The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB and apply the larger bus width. Although the original CPU32 core had a 32-bit internal data path and 32-bit arithmetic hardware, its interface to the IMB was 16 bits. The CPU32+ core can operate on 32-bit external operands with one bus cycle. This allows the CPU32+ core to fetch a long-word instruction in one bus cycle an to fetch two wordlength instructions in one bus cycle, filling the internal instruction queue more quickly. The CPU32+ core can also read and write 32-bits of data in one bus cycle. Although the CPU32+ instruction timings are improved, its instruction set is identical to that of the CPU32. It will also execute the entire 68000 instruction set. It contains the same background debug mode (BDM) features as the CPU32. No new compilers, assemblers or other software support tools need be implemented for the CPU32+; standard CPU32 tools can be used. The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted) assumption that a 10-MHz 68000 delivers 1 VAX MIPS. If an application requires more performance, the CPU32+ can be disabled, allowing the rest of the QUICC to operate as an intelligent peripheral to a faster processor. The QUICC provides a special mode called TS68040 companion mode to allow it to conveniently interface to members of the TS68040 family. This two-chip solution provides a 22-MIPS performance at 25 MHz. The CPU32+ also offers automatic byte alignment features that are not offered on the CPU32. These features allow 16- or 32-bit data to be read or written at an odd address. The CPU32+ automatically performs the number of bus cycles required. System Integration Module (SIM60) The SIM60 integrates general-purpose features that would be useful in almost any 32bit processor system. The term “SIM60” is derived from the QUICC part number, TS68EN360. The SIM60 is an enhanced version of the SIM40 that exists on the TS68332 device. First, new features, such as a DRAM controller and breakpoint logic, have been added. Second, the SIM40 was modified to support a 32-bit IMB as well as a 32-bit external system bus. Third, new configurations, such as slave mode and internal accesses by an external master, are supported. Although the QUICC is always a 32-bit device internally, it may be configured to operate with a 16-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is supported. Bus sizing allows 8-16-, and 32-bit peripherals and memory to exist in the 32-bit system bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system bus mode. Communications The CPM contains features that allow the QUICC to excel in communications and conProcessor Module (CPM) trol applications. These features may be divided into three sub-groups: • Communications Processor (CP) • Two IDMA Controllers • Four General-purpose Timers 73 2113A–HIREL–03/02 The CP provides the communication features of the QUICC. Included are a RISC processor, four SCCs, two SMCs, one SPI, 2.5K bytes of dual-port RAM, an interrupt controller, a time slot assigner, three parallel ports, a parallel interface port, four independent baud rate generators, and fourteen serial DMA channels to support the SCCs, SMCs, and SPI. The IDMAs provide two channels of general-purpose DMA capability. They offer highspeed transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge logic. The RISC controller may access the IDMA registers directly in the buffer chaining modes. The QUICC IDMAs are similar to, yet enhancements of, the one IDMA channel found on the TS68302. The four general-purpose timers on the QUICC are functionally similar to the two general-purpose timers found on the TS68302. However, they offer some minor enhancements, such as the internal cascading of two timers to form a 32-bit timer. The QUICC also contains a periodic interval timer in the SIM60, bringing the total to five on-chip timers. Ethernet on QUICC The Ethernet protocol is available only on the Ethernet version of the QUICC called the TS68EN360. The non-Ethernet version of the QUICC is the MC68360. The term “QUICC” is the overall device name that denotes all versions of the device. The TS68EN360 is a superset of the MC68360, having the additional option allowing Ethernet operation on any of the four SCCs. Due to performance reason not ass SCCs can be configured as Ethernet controller at the same time. The TS68EN360 is not restricted only to Ethernet operation. HDLC, UART, and other protocols may be used to allow dynamic switching between protocols. See Appendix A Serial Performance for available SCC performance. When the MODE bits of the SCC GSMR select the Ethernet protocol, then that SCC performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions (see Figure 73). Figure 73. Ethernet Block Diagram IMB SLOT TIME AND DEFER COUNTER RANDOM NO. CONTROL REGISTERS PERIPHERAL BUS CLOCK GENERATOR RX CLOCK TX CLOCK INTERNAL CLOCKS RTS = TENA RRJCT RECEIVER CONTROL UNIT RSTRT CD = RENA CTS = CLSN RXD 74 RECEIVE DATA FIFO TRANSMIT DATA FIFO SHIFTER SHIFTER TRANSMITTER CONTROL UNIT CD = RENA CTS = CLSN TXD TS68EN360 2113A–HIREL–03/02 TS68EN360 Upgrading Designs from the TS68302 Since the QUICC is a next-generation TS68302, many designers currently using the TS68302 may wish to use the QUICC in a follow-on design. The following paragraphs briefly discuss this endeavor in terms of architectural approach, hardware issues, and software issues. Architectural Approach The QUICC is the logical extension of the TS86302, but the overall architecture and philosophy of the TS86302 design remains intact in the QUICC. The QUICC keeps the best features of the TS86302, while making the changes required to provide for the increased flexibility, integration, and performance requested by customers. Because the CPM is probably the most difficult module to learn, anyone who has used the TS86302 can easily become familiar with the QUICC since the CPM architectural approach remains intact. The most significant architectural change made on the QUICC was the translation of the design into the standard 68300 family IMB architecture, resulting in a faster CPU and different system integration features. Although the features of the SIM60 do not exactly correspond to those of the TS86302 SIM, they are very similar. Because of the similarity of the QUICC SIM60 and CPU to other members of the 68300 family, such as the TS68332, previous users of these devices will be comfortable with these same features on the QUICC. Hardware Compatibility Issues The following list summarizes the hardware differences between the TS86302 and the QUICC: • Pinout – The pinout is not the same. The QUICC has 240 pins; the TS86302 has 132 pins. • Package – Both devices offer PGA and PQFP packages. However, the QUICC QFP package has a 20-mil pitch; whereas, the TS86302 QFP package has a 25-mil pitch. • System Bus – The system bus signals now look like those of the TS68020 as opposed to those of the 68000. It is still possible to interface 68000 peripherals to the QUICC, utilizing the same techniques used to interface them to a TS68020. • System Bus in Slave Mode – A number of QUICC pins take on new functionality in slave mode to support an external TS68EC040. On the TS68302, the pin names generally remained the same in slave mode. • Peripheral Timing – The external timings of the peripherals (SCCs, timers, etc.) are very similar (if not identical) to corresponding peripherals on the TS68302. • Pin Assignments – The assignment of peripheral functions to I/O pins is different in several ways. First, the QUICC contains more general-purpose parallel I/O pins than the TS68302. However, the QUICC offers many more functions than even a 240-pin package would normally allow, resulting in more multifunctional pins than the TS68302. 75 2113A–HIREL–03/02 Software Compatibility Issues The following list summarizes the major software differences between the TS68302 and the QUICC: • Since the CPU32+ is a superset of the 68000 instruction set, all previously written code will run. However, if such code is accessing the TS68302 peripherals, it will require some modification. • The QUICC contains an 8-Kbyte block of memory as opposed to a 4-Kbyte block on the TS68302. The register addresses within that memory map are different. • The code used to initialize the system integration features of the TS68302 has to be modified to write the corresponding features on the QUICC SIM60. • As much as possible, QUICC CPM features were made identical to those of the TS68302 CP. The most important benefit is that the code flow (if not the code itself) will port easily from the TS68302 to the QUICC. The nuances learned from the TS68302 will still be useful in the QUICC. • Although the registers used to initialize the QUICC CPM are new (for example, the SCM on the TS68302 is replaced with the GSMR and PSMR on the QUICC), most registers retain their original purpose such as the SCC event, SCC mask, SCC status, and command registers. The parameter RAM of the SCCs is very similar, and most parameter RAM register names and usage are retained. More importantly, the basic structure of a buffer descriptor (BD) on the QUICC is identical to that of the TS68302, except for a few new bit functions that were added. (In a few cases, a bit in a BD status word had to be shifted.) • When porting code from the TS68302 CP to the QUICC CPM, the software writer may find that the QUICC has new options to simplify what used to be a more codeintensive process. For specific examples, see the INIT TX AND RX PARAMETERS, GRACEFUL STOP TRANSMIT, and CLOSE BD commands. Preparation for Delivery Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535 or Atmel standards. Certificate of Compliance Atmel offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 or Atmel standard and guarantying the parameters not tested at temperature extremes for the entire temperature range. Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: a) Devices should be handled on benches with conductive and grounded surfaces. b) Ground test equipment, tools and operator. c) Do not handle devices by the leads. d) Store devices in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50% if practical. 76 TS68EN360 2113A–HIREL–03/02 TS68EN360 Package Mechanical Data 241-pin – PGA Inches A (top view) Millimeters Dim Min Max Min Max A 1.840 1.880 46.74 47.75 C 0.110 0.140 2.79 3.56 D 0.016 0.020 0.41 0.51 E 0.045 0.055 1.143 1.4 F 0.045 0.055 1.143 1.4 G K 0.100 BASIC 0.150 0.170 2.54 BASIC 3.81 4.32 C G E A1 D G T (BOTTOM VIEW) 1 18 F A A K 77 2113A–HIREL–03/02 240-pin – CERQUAD S VIEW AC VIEW AC 4 PLACES U AD 121 AD 120 Y P 181 G 180 –X– X = L, M or N SECTION AD F –N– –L– 240 D 0.08(0.003) M T L–N 61 1 60 MILLIMETERS –M– A 4 x 60 TIPS 0.20 (0.008) M H L–N S M S W E C 0.25(0.010) T L–N M –H– DATUM PLANE 0.10(0.004) AB –T– SEATING PLANE VIEW AE VIEW AE θ2 –H– DATUM PLANE K AA Notes: 1. Dimensioning and tolerancing per ASME Y 14.5, 1994. 2. Controlling dimension: millimeter. 3. Datum plane -H- is located at bottom of lead and is coincident with the lead where the lead exits the ceramic body at the bottom of the parting line. 4. Datums -L-, -M- and -N- to be determined at datum plane -H-. 5. Dimensions S and V to be determined at seating plane -T-. 6. Dimensions A and B define maximum ceramic body dimensions including glass protrusion and top and bottom mismatch. S M S INCHES DIM MIN MAX MIN MAX A 30.86 31.75 1.215 1.250 B 30.86 31.75 1.215 1.250 C 3.67 4.15 0.144 0.163 D 0.18 0.30 0.007 0.012 E 3.10 3.90 0.122 0.154 F 0.17 0.23 0.007 0.009 G 0.50 BSC 0.019 BSC J 0.13 0.175 0.005 0.007 K 0.45 0.55 0.018 0.021 P 0.25 BSC 0.010 BSC R 0.15 BSC 0.006 BSC S U 34.41 34.75 17.30 BSC 1.355 1.37 0.681 BSC V 34.41 34.75 1.355 1.37 W 0.25 0.75 0.01 0.03 Y Z 17.30 BSC 0.12 0.13 0.681 BSC 0.005 0.005 AA 1.80 REF 0.071 REF AB 0.95 REF 0.037 REF θ2 78 J Z B V 240 PLACES 1° 7° 1° 7° TS68EN360 2113A–HIREL–03/02 TS68EN360 Ordering Information Hi-REL Product Commercial Atmel Part-Number Norms Package Temperature Range Tc (°C) Frequency (MHz) TS68EN360MRB/C25L MIL-STD-883 PGA 241 Gold -55/+125 25 - TS68EN360MRB/C33L MIL-STD-883 PGA 241 Gold -55/+125 33 - TS68EN360MR1B/C25L MIL-STD-883 PGA 241 Tinned -55/+125 25 - TS68EN360MR1B/C33L MIL-STD-883 PGA 241 Tinned -55/+125 33 - TS68EN360MAB/C25L MIL-STD-883 CERQUAD 240 -55/+125 25 - TS68EN360MAB/C33L MIL-STD-883 CERQUAD 240 -55/+125 33 - TS68EN360DES01MXCL DSCC PGA 241 Gold -55/+125 25 5962-9760701MXC TS68EN360DES02MXCL DSCC PGA 241 Gold -55/+125 33 5962-9760702MXC TS68EN360DES01MXAL DSCC PGA 241 Tinned -55/+125 25 5962-9760701MXA TS68EN360DES02MXAL DSCC PGA 241 Tinned -55/+125 33 5962-9760702MXA TS68EN360DES01MYAL DSCC CERQUAD 240 -55/+125 25 5962-9760701MYA TS68EN360DES02MYAL DSCC CERQUAD 240 -55/+125 33 5962-9760702MYA Commercial Atmel Part-Number Norms Package Temperature Range Tc (°C) Frequency (MHz) TS68EN360VR25L Atmel Standard PGA 241 -40/+85 25 Internal TS68EN360MR25L Atmel Standard PGA 241 -55/+125 25 Internal TS68EN360VA25L Atmel Standard CERQUAD 240 -40/+85 25 Internal TS68EN360MA25L Atmel Standard CERQUAD 240 -55/+125 25 Internal TS68EN360VR33L Atmel Standard PGA 241 -40/+85 33 Internal TS68EN360MR33L Atmel Standard PGA 241 -55/+125 33 Internal TS68EN360VA33L Atmel Standard CERQUAD 240 -40/+85 33 Internal TS68EN360MA33L Atmel Standard CERQUAD 240 -55/+125 33 Internal Drawing Number Standard Product Drawing Number 79 2113A–HIREL–03/02 (TSX) TS68EN360 M R 1 B/C 25 X Prototype version Generic Revision level L: Temperature range : (TC ) M : -55°C, +125°C V : -40°C, +110°C C : 0°C, +70°C Operating frequency : Package : R = Pin grid array 241 (gold) 25 : 25 MHz 33 : 33 MHz A = CERQUAD 240 (tin) Screening : Hirel lead finish : ___ = Standard 80 _= Gold (for PGA) B/C = MIL STD 883 Class B _= Hot solder dip (for CERQUAD) B/T = According to MIL-STD883 1= Hot solder dip (for PGA - On request) D/T = Standard + Burn in TS68EN360 2113A–HIREL–03/02 TS68EN360 81 2113A–HIREL–03/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Asia Atmel Asia, Ltd. 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Atmel’s products are not authorized for use as critical components in life support devices or systems. ATMEL ® is the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. 2113A–HIREL–03/02 0M