FREESCALE MCF51JU64VLF

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MCF51JU128
Rev. 0, 05/2011
MCF51JU128
MCF51JU128 Advance
Information
Supports the MCF51JU128VLH,
MCF51JU128VHX, MCF51JU128VHS,
MCF51JU64VLF, MCF51JU64VHS,
MCF51JU32VHS, MCF51JU32VFM
Features
• Operating characteristics
– Voltage range: 1.71 V to 3.6 V
– Flash write voltage range: 1.71 V to 3.6 V
– Temperature range (ambient): -40°C to 105°C
• Core
– Up to 50 MHz V1 ColdFire CPU
– Dhrystone 2.1 performance: 1.10 DMIPS per MHz
when executing from internal RAM, 0.99 DMIPS
per MHz when executing from flash memory
• System
– DMA controller with four programmable channels
– Integrated ColdFire DEBUG_Rev_B+ interface with
single-wire BDM connection
• Power management
– 10 low power modes to provide power optimization
based on application requirements
– Low-leakage wakeup unit (LLWU)
– Voltage regulator (VREG)
• Clocks
– Crystal oscillators (two, each with range options): 1
kHz to 32 kHz (low), 1 MHz to 8 MHz (medium), 8
MHz to 32 MHz (high)
– Multipurpose clock generator (MCG)
• Memories and memory interfaces
– Flash memory, FlexNVM, FlexRAM, and RAM
– Serial programming interface (EzPort)
– Mini-FlexBus external bus interface
• Analog
– 12-bit SAR ADC
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
– Voltage reference (VREF)
• Timers
– Programmable delay block (PDB)
– Motor control/general purpose/PWM timers (FTM)
– 16-bit low-power timers (LPTMRs)
– 16-bit modulo timer (MTIM)
– Carrier modulator transmitter (CMT)
• Communication interfaces
– UARTs with Smart Card support and FIFO
– SPI modules, one with FIFO
– Inter-Integrated Circuit (I2C) modules
– USB full/low speed On-the-Go controller with onchip transceiver
– Integrated Interchip Sound (I2S) / Serial Audio
Interface (SAI) to support full-duplex serial
interfaces with frame sync such as AC97 and
CODEC
• Human-machine interface
– Up to 48 EGPIO pins
– Up to 16 rapid general purpose I/O (RGPIO) pins
– Low-power hardware touch sensor interface (TSI)
– Interrupt request pin (IRQ)
• Security and integrity
– Hardware CRC module to support fast cyclic
redundancy checks
– 128-bit unique identification (ID) number per chip
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
© 2011 Freescale Semiconductor, Inc.
Preliminary
Table of Contents
1 Ordering parts...........................................................................3
5.4.1
Thermal operating requirements...........................19
1.1 Determining valid orderable parts......................................3
5.4.2
Thermal attributes.................................................19
2 Part identification......................................................................3
6 Peripheral operating requirements and behaviors....................20
2.1 Description.........................................................................3
6.1 Core modules....................................................................20
2.2 Format...............................................................................3
6.1.1
Debug specifications.............................................20
2.3 Fields.................................................................................3
6.2 System modules................................................................20
2.4 Example............................................................................4
6.3 Clock modules...................................................................21
3 Terminology and guidelines......................................................4
6.3.1
MCG specifications...............................................21
3.1 Definition: Operating requirement......................................4
6.3.2
Oscillator electrical specifications.........................23
3.2 Definition: Operating behavior...........................................5
6.4 Memories and memory interfaces.....................................26
3.3 Definition: Attribute............................................................5
6.4.1
Flash (FTFL) electrical specifications....................26
3.4 Definition: Rating...............................................................5
6.4.2
EzPort Switching Specifications............................30
3.5 Result of exceeding a rating..............................................6
6.4.3
Mini-Flexbus Switching Specifications..................31
3.6 Relationship between ratings and operating
6.5 Security and integrity modules..........................................33
requirements......................................................................6
6.6 Analog...............................................................................34
3.7 Guidelines for ratings and operating requirements............6
6.6.1
ADC electrical specifications.................................34
3.8 Definition: Typical value.....................................................7
6.6.2
CMP and 6-bit DAC electrical specifications.........37
4 Ratings......................................................................................8
6.6.3
12-bit DAC electrical characteristics.....................39
4.1 Thermal handling ratings...................................................8
6.6.4
Voltage reference electrical specifications............42
4.2 Moisture handling ratings..................................................8
6.7 Timers................................................................................43
4.3 ESD handling ratings.........................................................9
6.8 Communication interfaces.................................................44
4.4 Voltage and current operating ratings...............................9
6.8.1
USB electrical specifications.................................44
5 General.....................................................................................9
6.8.2
USB DCD electrical specifications........................44
5.1 Typical Value Conditions...................................................9
6.8.3
USB VREG electrical specifications......................44
5.2 Nonswitching electrical specifications...............................10
6.8.4
SPI switching specifications..................................45
6.8.5
I2S/SAI Switching Specifications..........................49
5.2.1
Voltage and Current Operating Requirements......10
5.2.2
LVD and POR operating requirements.................11
5.2.3
Voltage and current operating behaviors..............12
5.2.4
Power mode transition operating behaviors..........12
7 Dimensions...............................................................................52
5.2.5
Power consumption operating behaviors..............13
7.1 Obtaining package dimensions.........................................52
5.2.6
EMC radiated emissions operating behaviors.......16
8 Pinout........................................................................................53
5.2.7
Designing with radiated emissions in mind...........16
8.1 Signal Multiplexing and Pin Assignments..........................53
5.2.8
Capacitance attributes..........................................16
8.2 Pinout diagrams.................................................................55
5.3 Switching electrical specifications.....................................17
8.3 Module-by-module signals.................................................59
5.3.1
General Switching Specifications..........................17
6.9 Human-machine interfaces (HMI)......................................51
6.9.1
TSI electrical specifications...................................51
9 Revision History........................................................................70
5.4 Thermal specifications.......................................................19
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
2
Preliminary
Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device:
1. Go to http://www.freescale.com.
2. Perform a part number search for the following partial device numbers: PCF51JU
and MCF51JU.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q CCCC DD MMM T PP
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general
market flow
• P = Prequalification
CCCC
Core code
CF51 = ColdFire V1
DD
Device number
JF, JU, QF, QH, QM, QU
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
3
Terminology and guidelines
Field
Description
Values
MMM
Memory size (program flash
T
Temperature range, ambient (°C)
PP
Package identifier
memory)1
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
V = –40 to 105
• FM = 32 QFN (5 mm x 5 mm)
• HS = 44 Laminate QFN (5 mm x 5
mm)
• LF = 48 LQFP (7 mm x 7 mm)
• HX = 64 Laminate QFN (9 mm x 9
mm)
• LH = 64 LQFP (10 mm x 10 mm)
1. All parts also have FlexNVM, FlexRAM, and RAM.
2.4 Example
This is an example part number:
MCF51JU128VLH
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
Unit
1.1
V
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
4
Preliminary
Freescale Semiconductor, Inc.
Terminology and guidelines
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
5
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
Min.
1.0 V core supply
voltage
Max.
–0.3
Unit
1.2
V
3.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
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- Possible decreased life
- Possible incorrect operation
- Probable permanent failure
Handling range
- No permanent failure
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–∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
6
Preliminary
Freescale Semiconductor, Inc.
Terminology and guidelines
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
7
Ratings
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.95
0.90
1.05
1.00
1.10
VDD (V)
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
Solder temperature, leaded
—
245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
8
Preliminary
Freescale Semiconductor, Inc.
General
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
VDD + 0.3
V
VAIO
Analog, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to all
port pins)
–25
25
mA
ID
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
IDDA
Analog supply current
—
TBD
mA
VUSB_DP
USB_DP input voltage
–0.3
3.63
V
VUSB_DM
USB_DM input voltage
–0.3
3.63
V
VREGIN
USB Regulator input
–0.3
6.0
V
5 General
5.1 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
9
Nonswitching electrical specifications
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
5.2 Nonswitching electrical specifications
5.2.1 Voltage and Current Operating Requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
VIH
VIL
IIC
Input high voltage
1
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
Input low voltage
2
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
DC injection current — single pin
3
• VIN > VDD
0
2
mA
• VIN < VSS
0
–0.2
mA
DC injection current — total MCU limit, includes sum
of all stressed pins
• VIN > VDD
• VIN < VSS
VRAM
Notes
VDD voltage required to retain RAM
3
0
25
mA
0
–5
mA
1.2
—
V
1. The device always interprets an input as a 1 when the input is greater than or equal to VIH (min.) and less than or equal to
VIH (max.), regardless of whether input hysteresis is turned on.
2. The device always interprets an input as a 0 when the input is less than or equal to VIL (max.) and greater than or equal to
VIL (min.), regardless of whether input hysteresis is turned on.
3. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified.
To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp
voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during
instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the
injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external
VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
10
Preliminary
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall
power consumption).
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
TBD
1.1
TBD
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
TBD
2.56
TBD
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
TBD
2.70
TBD
V
VLVW2H
• Level 2 falling (LVWV=01)
TBD
2.80
TBD
V
VLVW3H
• Level 3 falling (LVWV=10)
TBD
2.90
TBD
V
VLVW4H
• Level 4 falling (LVWV=11)
TBD
3.00
TBD
V
60
TBD
mV
1.60
TBD
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
TBD
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
TBD
1.80
TBD
V
VLVW2L
• Level 2 falling (LVWV=01)
TBD
1.90
TBD
V
VLVW3L
• Level 3 falling (LVWV=10)
TBD
2.00
TBD
V
VLVW4L
• Level 4 falling (LVWV=11)
TBD
2.10
TBD
V
40
TBD
mV
VHYSL
Notes
Low-voltage inhibit reset/recover hysteresis —
low range
VBG
Bandgap voltage reference
TBD
1.00
TBD
V
tLPO
Internal low power oscillator period
TBD
1000
TBD
μs
factory trimmed
1. Rising thresholds are falling threshold + hysteresis voltage
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
11
Nonswitching electrical specifications
5.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
VOH
Description
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3 mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6 mA
VDD – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3 mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6 mA
—
0.5
V
—
100
mA
• @ full temperature range
—
TBD
μA
• @ 25 °C
—
TBD
μA
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
IOZ
Hi-Z (off-state) leakage current (per pin)
—
TBD
μA
RPU
Internal pullup resistors
20
50
kΩ
1
RPD
Internal pulldown resistors
20
50
kΩ
2
1. Measured at Vinput = VSS
2. Measured at Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx-RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 50 MHz
• Bus clock (and flash and Mini-FlexBus clocks) = 25 MHz
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
12
Preliminary
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Table 4. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.8 V to execution of the first instruction
across the operating temperature range of the chip.
Min.
Max.
Unit
Notes
—
300
μs
1
RUN → VLLS1 → RUN
1
• RUN → VLLS1
—
4.4
μs
• VLLS1 → RUN
—
TBD
μs
RUN → VLLS2 → RUN
1
• RUN → VLLS2
—
4.6
μs
• VLLS2 → RUN
—
TBD
μs
RUN → VLLS3 → RUN
1
• RUN → VLLS3
—
4.4
μs
• VLLS3 → RUN
—
TBD
μs
• RUN → LLS
—
4.4
μs
• LLS → RUN
—
6.5
μs
• RUN → VLPS
—
4.4
μs
• VLPS → RUN
—
4.6
μs
• RUN → STOP
—
4.4
μs
• STOP → RUN
—
4.6
μs
RUN → LLS → RUN
RUN → VLPS → RUN
RUN → STOP → RUN
1. Normal boot (FTFL_FOPT[LPBOOT] is 1)
5.2.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
TBD
mA
1
Run mode current — all peripheral clocks
disabled, code executing from RAM
• @ 1.8 V
• @ 3.0 V
2
—
13.5
TBD
mA
—
14
TBD
mA
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
13
Nonswitching electrical specifications
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_RUN
Run mode current — all peripheral clocks
disabled, code executing from flash memory with
page buffering disabled
• @ 1.8 V
• @ 3.0 V
IDD_RUN
Max.
Unit
• @ 3.0 V
Run mode current — all peripheral clocks
enabled and peripherals active, code executing
from flash memory
• @ 1.8 V
• @ 3.0 V
Notes
2
—
16.6
TBD
mA
—
17
TBD
mA
Run mode current — all peripheral clocks
enabled, code executing from RAM, exercising
flash memory
• @ 1.8 V
IDD_RUN_MAX
Typ.
3
—
20
TBD
mA
—
20
TBD
mA
4
—
TBD
TBD
mA
—
TBD
TBD
mA
IDD_WAIT
Wait mode current at 3.0 V — all peripheral
clocks disabled
—
6.6
TBD
mA
5
IDD_WAIT
Wait mode current at 3.0 V — all peripheral
clocks disabled
—
TBD
TBD
mA
6
IDD_STOP
Stop mode current at 3.0 V
—
0.34
TBD
mA
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
0.63
TBD
mA
7
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
0.78
TBD
mA
8
IDD_VLPW
Very-low-power wait mode current at 3.0 V
—
0.15
TBD
mA
9
IDD_VLPS
Very-low-power stop mode current at 3.0 V
—
12
TBD
μA
10
IDD_LLS
Low leakage stop mode current at 3.0 V
IDD_VLLS3
IDD_VLLS2
10,11,12
• @ –40 to 25 °C
—
3.0
TBD
μA
• @ 70 °C
—
TBD
TBD
μA
• @ 105 °C
—
TBD
TBD
μA
Very low-leakage stop mode 3 current at 3.0 V
10,11,12
• @ –40 to 25 °C
—
2.0
TBD
μA
• @ 70 °C
—
TBD
TBD
μA
• @ 105 °C
—
TBD
TBD
μA
Very low-leakage stop mode 2 current at 3.0 V
10,11
• @ –40 to 25 °C
—
1.5
TBD
μA
• @ 70 °C
—
TBD
TBD
μA
• @ 105 °C
—
TBD
TBD
μA
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
14
Preliminary
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Table 5. Power consumption operating behaviors (continued)
Symbol
IDD_VLLS1
IDD_OSC
Description
Min.
Typ.
Max.
Unit
Very low-leakage stop mode 1 current at 3.0 V
10,11
• @ –40 to 25 °C
—
1.3
TBD
μA
• @ 70 °C
—
TBD
TBD
μA
• @ 105 °C
—
TBD
TBD
μA
—
0.7
—
μA
—
TBD
—
μA
—
TBD
—
μA
Average current for OSC enabled with 32 kHz
crystal at 3.0 V
• @ –40 to 25 °C
• @ 70 °C
Notes
• @ 105 °C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks disabled.
3. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, but
peripherals are not in active operation.
4. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode. All peripheral clocks enabled, and
peripherals are in active operation.
5. 25 MHz core and system clocks, and 12.5 MHz bus clock. MCG configured for FEI mode.
6. 50 MHz core and system clocks, and 25 MHz bus clock. MCG configured for FEI mode.
7. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for BLPE mode. All peripheral clocks disabled.
Code executing from flash memory.
8. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks enabled,
but peripherals are not in active operation. Code executing from flash memory.
9. 2 MHz core and system clocks, and 1 MHz bus clock. MCG configured for fast IRCLK mode. All peripheral clocks disabled.
10. OSC clocks disabled.
11. All pads disabled.
12. Data reflects devices with 32 KB of RAM. For devices with 16 KB of RAM, power consumption is reduced by 500 nA. For
devices with 8 KB of RAM, power consumption is reduced by 750 nA.
5.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
•
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks disabled except FTFL
LVD disabled, USB voltage regulator disabled
No GPIOs toggled
Code execution from flash memory
DIAGRAM TBD
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks enabled, but peripherals are not in active operation
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
15
Nonswitching electrical specifications
• LVD disabled, USB voltage regulator disabled
• No GPIOs toggled
• Code execution from flash memory
DIAGRAM TBD
Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled
5.2.6 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
dBμV
1, 2
—
2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
TBD
VRE2
Radiated emissions voltage, band 2
50–150
TBD
VRE3
Radiated emissions voltage, band 3
150–500
TBD
VRE4
Radiated emissions voltage, band 4
500–1000
TBD
0.15–1000
TBD
VRE_IEC_SAE IEC and SAE level
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/
Wideband TEM (GTEM) Cell Method.
2. VDD = 3 V, TA = 25 °C, fOSC = 16 MHz (crystal), fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 7. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
16
Preliminary
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
5.3 Switching electrical specifications
Table 8. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
50
MHz
System and core clock when USB in operation
20
—
MHz
Bus clock
—
25
MHz
Mini-FlexBus clock
—
25
MHz
LPTMR clock
—
25
MHz
Notes
Normal run mode
fSYS
fSYS_USB
fBUS
FB_CLK
fLPTMR
VLPR mode
fSYS
System and core clock
—
2
MHz
fBUS
Bus clock
—
1
MHz
Mini-FlexBus clock
—
1
MHz
LPTMR clock
—
25
MHz
FB_CLK
fLPTMR
5.3.1 General Switching Specifications
These general purpose specifications apply to all signals configured for EGPIO, MTIM,
CMT, PDB, IRQ, and I2C signals. The conditions are 50 pf load, VDD = 1.71 V to 3.6 V,
and full temperature range. The GPIO are set for high drive, no slew rate control, and no
input filter, digital or analog, unless otherwise specified.
Table 9. EGPIO General Control Timing
Symbol
Description
Min.
Max.
Unit
G1
Bus clock from CLK_OUT pin high to GPIO output valid
—
32
ns
G2
Bus clock from CLK_OUT pin high to GPIO output invalid
(output hold)
1
—
ns
G3
GPIO input valid to bus clock high
28
—
ns
G4
Bus clock from CLK_OUT pin high to GPIO input invalid
—
4
ns
GPIO pin interrupt pulse width (digital glitch filter disabled)
1.5
—
Bus
clock
cycles
100
—
ns
Synchronous path1
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter enabled)
Asynchronous path2
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
17
Nonswitching electrical specifications
Table 9. EGPIO General Control Timing (continued)
Symbol
Description
Min.
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter disabled)
Max.
Unit
50
—
ns
External reset pulse width (digital glitch filter disabled)
100
—
ns
Mode select (MS) hold time after reset deassertion
2
—
Bus
clock
cycles
Asynchronous path2
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
Bus clock
G1
G2
Data outputs
G3
G4
Data inputs
Figure 3. EGPIO timing diagram
The following general purpose specifications apply to all signals configured for RGPIO,
FTM, and UART. The conditions are 25 pf load, VDD = 3.6 V to 1.71 V, and full
temperature range. The GPIO are set for high drive, no slew rate control, and no input
filter, digital or analog, unless otherwise specified.
Table 10. RGPIO General Control Timing
Symbol
Description
Min.
Max.
Unit
R1
CPUCLK from CLK_OUT pin high to GPIO output valid
—
16
ns
R2
CPUCLK from CLK_OUT pin high to GPIO output invalid
(output hold)
1
—
ns
R3
GPIO input valid to bus clock high
17
—
ns
R4
CPUCLK from CLK_OUT pin high to GPIO input invalid
—
2
ns
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
18
Preliminary
Freescale Semiconductor, Inc.
Thermal specifications
Bus clock
R1
R2
Data outputs
R3
R4
Data inputs
Figure 4. RGPIO timing diagram
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
5.4.2 Thermal attributes
Board type
Symbol
Description
64 LQFP
64
Laminate
QFN
48 LQFP
44
Laminate
QFN
32 QFN
Unit
Notes
Single-layer RθJA
(1s)
Thermal resistance,
junction to ambient
(natural convection)
73
108
79
108
98
°C/W
1
Four-layer
(2s2p)
Thermal resistance,
junction to ambient
(natural convection)
54
69
55
69
33
°C/W
1
Single-layer RθJMA
(1s)
Thermal resistance,
junction to ambient
(200 ft./min. air speed)
61
91
66
91
81
°C/W
1
Four-layer
(2s2p)
Thermal resistance,
junction to ambient
(200 ft./min. air speed)
48
63
48
63
28
°C/W
1
RθJA
RθJMA
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
19
Peripheral operating requirements and behaviors
Board type
Symbol
Description
64 LQFP
64
Laminate
QFN
48 LQFP
44
Laminate
QFN
32 QFN
Unit
Notes
—
RθJB
Thermal resistance,
junction to board
37
44
34
44
13
°C/W
2
—
RθJC
Thermal resistance,
junction to case
20
31
20
31
2.2
°C/W
3
—
ΨJT
Thermal
characterization
parameter, junction to
package top outside
center (natural
convection)
5.0
6.0
4.0
6.0
6.0
°C/W
4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug specifications
Table 12. Background debug mode (BDM) timing
Number
Symbol
Description
Min.
Max.
Unit
1
tMSSU
BKGD/MS setup time after issuing background
debug force reset to enter user mode or BDM
500
—
ns
2
tMSH
BKGD/MS hold time after issuing background
debug force reset to enter user mode or BDM1
100
—
µs
1. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after
VDD rises above VLVD.
6.2 System modules
There are no specifications necessary for the device's system modules.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
20
Preliminary
Freescale Semiconductor, Inc.
Clock modules
6.3 Clock modules
6.3.1 MCG specifications
Table 13. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
31.25
—
39.0625
kHz
Internal reference (slow clock) current
—
TBD
—
µA
Internal reference (slow clock) startup time
—
TBD
4
µs
Δfdco_res_t
Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
and SCFTRIM
—
± 0.1
± 0.3
%fdco
1
Δfdco_res_t
Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
only
—
± 0.2
± 0.5
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
+ 0.5
± 3.5
%fdco
1
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 0.5
± TBD
%fdco
1
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
3.4
—
4
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed
3
—
5
MHz
Internal reference (fast clock) current
—
TBD
—
µA
Internal reference startup time (fast clock)
—
TBD
TBD
µs
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25°C
fints_t
Internal reference frequency (slow clock) — user
trimmed
Iints
tirefsts
Δfdco_t
Iintf
tirefstf
Notes
- 1.0
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
FLL
ffll_ref
FLL reference frequency range
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
21
Clock modules
Table 13. MCG specifications (continued)
Symbol
fdco
Description
DCO output
frequency range
Low range (DRS=00)
Min.
Typ.
Max.
Unit
Notes
20
20.97
25
MHz
2, 3
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
4, 5
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
—
TBD
TBD
ps
6
Jacc_fll
FLL accumulated jitter of DCO output over a 1µs
time window
—
TBD
TBD
ps
6
FLL target frequency acquisition time
—
—
1
ms
7
48.0
—
100
MHz
—
1060
—
µA
—
600
—
µA
2.0
—
4.0
MHz
tfll_acquire
PLL
fvco
VCO operating frequency
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
Jcyc_pll
PLL period jitter
Jacc_pll
8
8
9, 10
• fvco = 48 MHz
—
120
—
ps
• fvco = 100 MHz
—
50
—
ps
PLL accumulated jitter over 1µs window
9, 10
• fvco = 48 MHz
—
1350
—
ps
• fvco = 100 MHz
—
600
—
ps
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
22
Preliminary
Freescale Semiconductor, Inc.
Clock modules
Table 13. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
—
0.15 +
1075(1/
fpll_ref)
ms
Notes
11
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification was obtained at TBD frequency.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. PLL period jitter is measured in RMS.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1
Symbol
VDD
IDDOSC
Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 1 MHz
—
100
—
μA
• 4 MHz
—
200
—
μA
• 8 MHz (only RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
23
Clock modules
Table 14. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
IDDOSC
Supply current — high gain mode (HGO=1)
Typ.
Max.
Unit
Notes
1
• 32 kHz
—
25
—
μA
• 1 MHz
—
200
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (only RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
6.6
—
kΩ
—
3.3
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
• 1 MHz resonator
• 2 MHz resonator
• 4 MHz resonator
• 8 MHz resonator
• 16 MHz resonator
• 20 MHz resonator
• 32 MHz resonator
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
24
Preliminary
Freescale Semiconductor, Inc.
Clock modules
Table 14. Oscillator DC electrical specifications (continued)
Symbol
Vpp5
1.
2.
3.
4.
5.
Description
Min.
Typ.
Max.
Unit
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx,Cy can be provided by using either the integrated capacitors or by using external components.
When low power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2
Symbol
Oscillator frequency specifications
Table 15. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
1
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
750
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
250
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1
2, 3
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL
2. Proper PC board layout procedures must be followed to achieve specifications.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
25
Memories and memory interfaces
3. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFL) electrical specifications
This section describes the electrical characteristics of the FTFL module.
6.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 16. NVM program/erase timing specifications
Symbol
Description
thvpgm4
thversscr
thversblk32k
Min.
Typ.
Max.
Unit
Longword Program high-voltage time
—
20
TBD
μs
Sector Erase high-voltage time
—
20
100
ms
1
Erase Block high-voltage time for 32 KB
—
20
100
ms
1
—
80
400
ms
1
Notes
thversblk128k Erase Block high-voltage time for 128 KB
Notes
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2
Symbol
Flash timing specifications — commands
Table 17. Flash command timing specifications
Description
Min.
Typ.
Max.
Unit
Read 1s Block execution time
trd1blk32k
• 32 KB data flash
—
—
0.4
ms
trd1blk128k
• 128 KB data flash
—
—
1.4
ms
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
40
μs
1
tpgmchk
Program Check execution time
—
—
35
μs
1
trdrsrc
Read Resource execution time
—
—
35
μs
1
tpgm4
Program Longword execution time
—
50
TBD
μs
Erase Flash Block execution time
2
tersblk32k
• 32 KB data flash
—
20
100
ms
tersblk128k
• 128 KB data flash
—
80
400
ms
—
20
100
ms
tersscr
Erase Flash Sector execution time
2
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
26
Preliminary
Freescale Semiconductor, Inc.
Memories and memory interfaces
Table 17. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Program Section execution time
tpgmsec512
• 512 B flash
—
TBD
TBD
ms
tpgmsec1k
• 1 KB flash
—
TBD
TBD
ms
trd1all
Read 1s All Blocks execution time
—
—
1.8
ms
trdonce
Read Once execution time
—
—
35
μs
Program Once execution time
—
50
TBD
μs
tersall
Erase All Blocks execution time
—
100
500
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
35
μs
1
—
25
TBD
ms
tpgmonce
1
Program Partition for EEPROM execution time
tpgmpart32k
• 32 KB FlexNVM
Set FlexRAM Function execution time:
tsetram8k
• 8 KB EEPROM backup
—
TBD
TBD
ms
tsetram32k
• 32 KB EEPROM backup
—
TBD
TBD
ms
Byte-write to FlexRAM for EEPROM operation
teewr8bers
Byte-write to erased FlexRAM location execution
time
—
100
TBD
μs
3
Byte-write to FlexRAM execution time:
teewr8b8k
• 8 KB EEPROM backup
—
TBD
TBD
ms
teewr8b16k
• 16 KB EEPROM backup
—
TBD
TBD
ms
teewr8b32k
• 32 KB EEPROM backup
—
TBD
1.5
ms
Word-write to FlexRAM for EEPROM operation
teewr16bers
Word-write to erased FlexRAM location
execution time
—
100
TBD
μs
Word-write to FlexRAM execution time:
teewr16b8k
• 8 KB EEPROM backup
—
TBD
TBD
ms
teewr16b16k
• 16 KB EEPROM backup
—
TBD
TBD
ms
teewr16b32k
• 32 KB EEPROM backup
—
TBD
1.5
ms
Longword-write to FlexRAM for EEPROM operation
teewr32bers
Longword-write to erased FlexRAM location
execution time
—
200
TBD
μs
Longword-write to FlexRAM execution time:
teewr32b8k
• 8 KB EEPROM backup
—
TBD
TBD
ms
teewr32b16k
• 16 KB EEPROM backup
—
TBD
TBD
ms
teewr32b32k
• 32 KB EEPROM backup
—
TBD
2.7
ms
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
27
Memories and memory interfaces
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3
Flash (FTFL) current and power specfications
Table 18. Flash (FTFL) current and power specfications
Symbol
Description
IDD_PGM
Worst case programming current in program flash
6.4.1.4
Symbol
Typ.
Unit
10
mA
Reliability specifications
Table 19. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k
Data retention after up to 10 K cycles
5
TBD
—
years
2
tnvmretp1k
Data retention after up to 1 K cycles
10
TBD
—
years
2
tnvmretp100
Data retention after up to 100 cycles
15
TBD
—
years
2
10 K
TBD
—
cycles
3
nnvmcycp
Cycling endurance
Data Flash
tnvmretd10k
Data retention after up to 10 K cycles
5
TBD
—
years
2
tnvmretd1k
Data retention after up to 1 K cycles
10
TBD
—
years
2
tnvmretd100
Data retention after up to 100 cycles
15
TBD
—
years
2
10 K
TBD
—
cycles
3
nnvmcycd
Cycling endurance
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
TBD
—
years
2
tnvmretee10
Data retention up to 10% of write endurance
10
TBD
—
years
2
tnvmretee1
Data retention up to 1% of write endurance
15
TBD
—
years
2
Write endurance
4
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
35 K
TBD
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
315 K
TBD
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
1.27 M
TBD
—
writes
nnvmwree4k
• EEPROM backup to FlexRAM ratio = 4096
10 M
TBD
—
writes
• EEPROM backup to FlexRAM ratio = 8192
20 M
TBD
—
writes
nnvmwree8k
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
4. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup. Minimum value assumes all
byte-writes to FlexRAM.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
28
Preliminary
Freescale Semiconductor, Inc.
Memories and memory interfaces
6.4.1.5
Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set size
can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFL to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that can
be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout the
entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
Writes_FlexRAM =
EEPROM – 2 × EEESIZE
EEESIZE
× Write_efficiency × nnvmcycd
where
• Writes_FlexRAM — minimum number of writes to each FlexRAM location
• EEPROM — allocated FlexNVM based on DEPART; entered with Program
Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition
command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• nnvmcycd — data flash cycling endurance
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
29
Memories and memory interfaces
Figure 5. EEPROM backup writes to FlexRAM
6.4.2 EzPort Switching Specifications
Table 20. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
15
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
0.0
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
15
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
0.0
—
ns
EP7
EZP_CK low to EZP_Q output valid (setup)
—
25
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0.0
—
ns
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
30
Preliminary
Freescale Semiconductor, Inc.
Memories and memory interfaces
Table 20. EzPort switching specifications (continued)
Num
Description
EP9
EZP_CS negation to EZP_Q tri-state
Min.
Max.
Unit
—
12
ns
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 6. EzPort Timing Diagram
6.4.3 Mini-Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships
can be derived from these values.
Table 21. Flexbus switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
FB1
Clock period
20
—
ns
FB2
Address, data, and control output valid
TBD
20
ns
1
FB3
Address, data, and control output hold
1
—
ns
1
FB4
Data and FB_TA input setup
20
—
ns
2
FB5
Data and FB_TA input hold
10
—
ns
2
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
31
Memories and memory interfaces
1. Specification is valid for all FB_AD[31:0], FB_CSn, FB_OE, FB_R/W, and FB_TS.
2. Specification is valid for all FB_AD[31:0].
Note
The following diagrams refer to signal names that may not be
included on your particular device. Ignore these extraneous
signals.
Also, ignore the AA=0 portions of the diagrams because this
setting is not supported in the Mini-FlexBus.
FB1
FB_CLK
FB3
FB5
FB_A[Y]
FB2
FB_D[X]
Address
FB4
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 7. Mini-FlexBus read timing diagram
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
32
Preliminary
Freescale Semiconductor, Inc.
Memories and memory interfaces
FB1
FB_CLK
FB2
FB_A[Y]
FB3
Address
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 8. Mini-FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
33
Analog
6.6 Analog
6.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
6.6.1.1
12-bit ADC operating conditions
Table 22. 12-bit ADC operating conditions
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDDVDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSSVSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
Reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
CADIN
Input
capacitance
—
4
5
pF
2
5
kΩ
Symbol
RADIN
RAS
fADCK
Crate
• 8/10/12 bit
modes
Input resistance
—
—
Analog source
resistance
12 bit modes
ADC conversion
clock frequency
≤ 12 bit modes
ADC conversion
rate
≤ 12 bit modes
fADCK < 4MHz
3
—
—
5
kΩ
4
1.0
No ADC hardware
averaging
Notes
—
18.0
MHz
5
20.000
—
818.330
Ksps
Continuous
conversions enabled,
subsequent conversion
time
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS/
CAS time constant should be kept to <1ns.
4. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
34
Preliminary
Freescale Semiconductor, Inc.
Analog
5. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
ADC SAR
ENGINE
R ADIN
V ADIN
C AS
V AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 9. ADC input impedance equivalency diagram
6.6.1.2
12-bit ADC electrical characteristics
Table 23. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC=1, ADHSC=0
1.2
2.4
3.9
MHz
• ADLPC=1, ADHSC=1
3.0
4.0
7.3
MHz
tADACK = 1/
fADACK
• ADLPC=0, ADHSC=0
2.4
5.2
6.1
MHz
• ADLPC=0, ADHSC=1
4.4
6.2
9.5
MHz
See Reference Manual chapter for sample times
Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC
configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/
converters/ADC_CALCULATOR_CNV.zip?fpsp=1
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
35
Analog
Table 23. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
TUE
DNL
INL
EFS
Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
LSB4
ADC
conversion
clock
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
LSB4
ADC
conversion
clock
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
LSB4
Max
averaging
LSB4
VADIN =
VDDA
Total unadjusted
error
• 12 bit modes
±0.8
±TBD
• <12 bit modes
±0.5
±1
Differential nonlinearity
• 12 bit modes
±0.7
±TBD
• <12 bit modes
±0.2
±0.5
Integral nonlinearity
• 12 bit modes
±0.5
±TBD
Full-scale error
• 12 bit modes
• <12 bit modes
±0.4
• <12 bit modes
EQ
Quantization
error
EIL
Input leakage
error
• 12 bit modes
—
—
±0.5
IIn × RAS
LSB4
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
VTEMP25
Temp sensor
voltage
• –40°C to 25°C
—
TBD
—
mV/°C
• 25°C to 105°C
—
TBD
—
mV/°C
—
TBD
—
mV
25°C
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
36
Preliminary
Freescale Semiconductor, Inc.
Analog
Figure TBD
Figure 10. Typical TUE vs. ADC conversion rate 12-bit single-ended mode
6.6.2 CMP and 6-bit DAC electrical specifications
Table 24. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
120
250
600
ns
Analog comparator initialization delay2
—
—
40
μs
6-bit DAC current adder (enabled)
—
7
—
μA
IDAC6b
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
37
Analog
0.08
0.07
0.06
HYSTCTR
Setting
CM P Hystereris (V)
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 11. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
38
Preliminary
Freescale Semiconductor, Inc.
12-bit DAC electrical characteristics
0.18
0.16
0.14
CMP
P Hystereris (V)
0.12
HYSTCTR
Setting
0.1
00
01
0
08
0.08
10
11
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
Vin level (V)
1.9
2.2
2.5
2.8
3.1
Figure 12. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1
Symbol
12-bit DAC operating requirements
Table 25. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
TA
Temperature
−40
105
°C
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1
2
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
39
12-bit DAC electrical characteristics
6.6.3.2
Symbol
12-bit DAC operating behaviors
Table 26. 12-bit DAC operating behaviors
Description
Min.
Typ.
Max.
Unit
IDDA_DACLP Supply current — low-power mode
—
—
150
μA
IDDA_DACH Supply current — high-speed mode
—
—
700
μA
Notes
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) — lowpower mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) — highpower mode
—
15
30
μs
1
tCCDACLP
Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode and high-speed mode
—
0.7
1
μs
1
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2 V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREFO (1.15 V)
—
—
±1
LSB
4
VOFFSET
Offset error
±0.4
—
±0.8
%FSR
5
EG
Gain error
±0.1
—
±0.6
%FSR
5
90
dB
PSRR
1.
2.
3.
4.
5.
Power supply rejection ratio, VDDA > = 2.4 V
60
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
TBD
—
ppm of
FSR/C
AC
Offset aging coefficient
—
—
TBD
μV/yr
Rop
Output resistance load = 3 kΩ
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
CT
Channel to channel cross talk
BW
3dB bandwidth
6
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0+100mV to VDACR−100 mV
The DNL is measured for 0+100 mV to VDACR−100 mV
The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
Calculated by a best fit curve from VSS+100 mV to VREF−100 mV
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
40
Preliminary
Freescale Semiconductor, Inc.
12-bit DAC electrical characteristics
6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set
to 0x800, Temp range from -40C to 105C
Figure 13. Typical INL error vs. digital code
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
41
12-bit DAC electrical characteristics
Figure 14. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 27. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Supply voltage
1.71
3.6
V
TA
Temperature
−40
105
°C
CL
Output load capacitance
—
100
nF
VDDA
Notes
Table 28. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
TBD
1.2
TBD
V
Vout
Voltage reference output with— factory trim
TBD
—
TBD
V
Notes
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
42
Preliminary
Freescale Semiconductor, Inc.
12-bit DAC electrical characteristics
Table 28. VREF full-range operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
1.198
—
1.202
V
Vout
Voltage reference output — user trim
Vstep
Voltage reference trim step
—
0.5
—
mV
Vdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
40
mV
Ac
Aging coefficient
—
—
TBD
ppm/year
Ibg
Bandgap only (MODE_LV = 00) current
—
—
TBD
µA
Itr
Tight-regulation buffer (MODE_LV =10) current
—
—
1.1
mA
ΔVLOAD
Load regulation (MODE_LV = 10)
Notes
See
Figure 15
mV
• current = + 1.0 mA
—
—
TBD
• current = - 1.0 mA
—
—
TBD
Tstup
Buffer startup time
—
—
100
µs
DC
Line regulation (power supply rejection)
—
—
TBD
mV
–60
—
TBD
dB
1
1. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 29. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
50
°C
Notes
Table 30. VREF limited-range operating behaviors
Symbol
Vout
Description
Min.
Max.
Unit
Voltage reference output with factory trim
TBD
TBD
V
Notes
TBD
Figure 15. Typical output vs.temperature
TBD
Figure 16. Typical output vs. VDD
6.7 Timers
See General Switching Specifications.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
43
Communication interfaces
6.8 Communication interfaces
6.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
6.8.2 USB DCD electrical specifications
Table 31. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
TBD
TBD
TBD
V
0.8
—
2.0
V
VLGC
Threshold voltage for logic high
IDP_SRC
USB_DP source current
7
10
13
μA
IDM_SINK
USB_DM sink current
50
100
150
μA
RDM_DWN
D- pulldown resistance for data pin contact detect
14.25
—
24.8
kΩ
VDAT_REF
Data detect voltage
0.25
TBD
0.4
V
6.8.3 USB VREG electrical specifications
Table 32. USB VREG electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VREGIN
Input supply voltage
2.7
—
5.5
V
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
—
120
TBD
μA
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
1.1
TBD
μA
IDDoff
Quiescent current — Shutdown mode
—
500
—
nA
—
—
TBD
μA
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
ILOADrun
Maximum load current — Run mode
—
—
120
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
Notes
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
44
Preliminary
Freescale Semiconductor, Inc.
Communication interfaces
Table 32. USB VREG electrical specifications
(continued)
Symbol
Description
Min.
Typ.
Max.
Unit
VReg33out
Regulator output voltage — Input supply
(VREGIN) > 3.6 V
3
3.3
3.6
V
TBD
2.8
3.6
V
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
TBD
—
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
TBD
290
TBD
mA
• Run mode
• Standby mode
VReg33out
Notes
1
1. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
6.8.4 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of
the chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes
slew rate control is disabled and high drive strength is enabled for SPI output pins.
Table 33. SPI master mode timing
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
tHI
Description
Min.
Max.
Unit
Comment
fBUS/2048
fBUS/2
Hz
fBUS is the
bus clock
as defined
in Table 8.
2 x tBUS
2048 x
tBUS
ns
tBUS = 1/
fBUS
Enable lead time
1/2
—
tSPSCK
—
Enable lag time
1/2
—
tSPSCK
—
tBUS - 30
1024 x
tBUS
ns
—
Data setup time (inputs)
21
—
ns
—
Data hold time (inputs)
0
—
ns
—
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
45
Communication interfaces
Table 33. SPI master mode timing (continued)
Num.
Symbol
8
tv
9
10
11
Description
Min.
Max.
Unit
Comment
Data valid (after SPSCK edge)
—
25
ns
—
tHO
Data hold time (outputs)
0
—
ns
—
tRI
Rise time input
—
tBUS - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
SS1
(OUTPUT)
3
SPSCK
(CPOL = 0)
(OUTPUT)
2
11
10
11
6
7
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
4
5
SPSCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
10
5
MSB OUT2
9
BIT 6 . . . 1
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI master mode timing (CPHA=0)
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
46
Preliminary
Freescale Semiconductor, Inc.
Communication interfaces
SS1
(OUTPUT)
2
3
SPSCK
(CPOL = 0)
(OUTPUT)
5
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
10
11
4
10
11
7
MSB IN2
BIT 6 . . . 1
8
MOSI
2
(OUTPUT)PORT DATA MASTER MSB OUT
LSB IN
9
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI master mode timing (CPHA=1)
Table 34. SPI slave mode timing
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
Description
Min.
Max.
Unit
Comment
0
fBUS/4
Hz
fBUS is the
bus clock
as defined
in Table 8.
4 x tBUS
—
ns
tBUS = 1/
fBUS
Enable lead time
1
—
tBUS
—
Enable lag time
1
—
tBUS
—
tBUS - 30
—
ns
—
Data setup time (inputs)
19.5
—
ns
—
tHI
Data hold time (inputs)
0
—
ns
—
8
ta
Slave access time
—
tBUS
ns
Time to
data active
from highimpedanc
e state
9
tdis
Slave MISO disable time
—
tBUS
ns
Hold time
to highimpedanc
e state
10
tv
Data valid (after SPSCK edge)
—
27
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
Table continues on the next page...
38
<<CLASSIFICATION>>
<<NDA MESSAGE>>
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
47
Communication interfaces
Table 34. SPI slave mode timing (continued)
Num.
Symbol
12
tRI
Rise time input
tFI
Fall time input
tRO
Rise time output
tFO
Fall time output
13
Description
Min.
Max.
Unit
Comment
—
tBUS - 25
ns
—
—
25
ns
—
SS
(INPUT)
2
SPSCK
(CPOL = 0)
(INPUT)
5
3
SPSCK
(CPOL = 1)
(INPUT)
5
13 4
12
13
9
8
MISO
(OUTPUT)
12
10
see
note
SLAVE MSB
6
11
11
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
7
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined!
Figure 19. SPI slave mode timing (CPHA=0)
SS
(INPUT)
4
2
3
SPSCK
(CPOL = 0)
(INPUT)
5
SPSCK
(CPOL = 1)
(INPUT)
5
see
note
8
MOSI
(INPUT)
SLAVE
13
12
13
9
11
10
MISO
(OUTPUT)
12
MSB OUT
6
BIT 6 . . . 1
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined!
Figure 20. SPI slave mode timing (CPHA=1)
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
48
Preliminary
Freescale Semiconductor, Inc.
Communication interfaces
6.8.5 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
Table 35. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
3.6
Unit
Operating voltage
1.71
V
S1
I2S_MCLK cycle time1
40
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK cycle time (output)1
80
—
ns
I2S_RX_BCLK cycle time (output)1
160
—
S4
I2S_TX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S11
I2S_TX_FS input assertion to I2S_TXD output valid2
—
21
ns
ns
1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
49
Communication interfaces
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 21. I2S/SAI timing — master modes
Table 36. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
I2S_RX_BCLK cycle time (input)
80
—
ns
I2S_TX_BCLK cycle time (input)
160
—
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
29
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
10
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1
—
21
ns
S11
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
50
Preliminary
Freescale Semiconductor, Inc.
Human-machine interfaces (HMI)
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 22. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 37. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDDTSI
Operating voltage
1.71
—
3.6
V
Target electrode capacitance range
1
20
500
pF
1
fREFmax
Reference oscillator frequency
—
5.5
TBD
MHz
2
fELEmax
Electrode oscillator frequency
—
0.5
TBD
MHz
3
Internal reference capacitor
TBD
1
TBD
pF
Oscillator delta voltage
TBD
600
TBD
mV
4
CELE
CREF
VDELTA
Notes
IREF
Reference oscillator current source base current
—
1.133
TBD
μA
3, 5
IELE
Electrode oscillator current source base current
—
1.133
TBD
μA
3, 5
Pres5
Electrode capacitance measurement precision
—
TBD
TBD
%
6
Pres20
Electrode capacitance measurement precision
—
TBD
TBD
%
7
Pres100
Electrode capacitance measurement precision
—
TBD
TBD
%
8
MaxSens2 Maximum sensitivity @ 20 pF electrode
0
0.003
0.25
—
fF/count
9
MaxSens
0.003
—
—
fF/count
10
Resolution
—
—
16
bits
Response time @ 20 pF
8
15
25
μs
Res
TCon20
Maximum sensitivity
11
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
51
Dimensions
Table 37. TSI electrical specifications (continued)
Symbol
Description
ITSI_RUN
ITSI_LP
Min.
Typ.
Max.
Unit
Current added in run mode
—
55
—
μA
Low power mode current adder
—
1.3
TBD
μA
Notes
12
1.
2.
3.
4.
5.
6.
7.
8.
9.
The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
CAPTRM=7, DELVOL=7, and fixed external capacitance of 20 pF.
CAPTRM=0, DELVOL=2, and fixed external capacitance of 20 pF.
CAPTRM=0, EXTCHRG=9, and fixed external capacitance of 20 pF.
The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
Measured with a 20 pF electrode, reference oscillator frequency of ~5 MHz (IREF = 5 μA, REFCHRG = 4), PS = 128,
NSCN = 2; Iext = 16 (EXTCHRG = 15).
10. Typical value depends on the configuration used.
11. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
12. CAPTRM=7, DELVOL=2, REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and
fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
Then use this document number
32-pin QFN
98ARE10566D
44-pin Laminate QFN
98ASA00239D
48-pin LQFP
98ASH00962A
64-pin Laminate QFN
98ASA00279D
64-pin LQFP
98ASS23234W
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
52
Preliminary
Freescale Semiconductor, Inc.
Pinout
8 Pinout
8.1 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Mux Control module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
• On PTB0, EZP_MS_b is active only during reset. Refer to
the detailed boot description.
• PTC1 is open drain.
64pin
48pin
44pin
32pin
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
1
—
—
—
VDD
VDD
2
—
—
—
VSS
VSS
3
—
—
—
Disabled
Disabled
PTC6
UART0_TX
I2C0_SCL
RGPIO6
SPI1_MOSI FBa_AD11
4
—
—
—
Disabled
Disabled
PTC7
UART0_RX
I2C0_SDA
RGPIO7
SPI1_MISO FBa_AD12
5
1
—
—
Disabled
Disabled
PTD0
UART0_CT
S_b
I2C1_SDA
RGPIO8
SPI1_SCLK FBa_AD13
I2S0_MCLK
/
I2S0_CLKIN
6
2
—
—
Disabled
Disabled
PTD1
UART0_RT
S_b
I2C1_SCL
RGPIO9
SPI1_SS
FBa_AD14
I2S0_RX_B
CLK
7
3
1
1
Disabled
Disabled
PTA0
I2C2_SCL
FTM1_CH0
SPI0_SS
FBa_AD15
I2S0_RX_F
S
8
4
2
2
Disabled
Disabled
PTA1
I2C2_SDA
FTM1_CH1
FBa_AD16
I2S0_RXD
EzPort
9
5
3
3
Disabled
Disabled
PTA2
UART1_TX
FTM1_CH2
SPI1_SS
10
6
4
4
Disabled
Disabled
PTA3
UART1_RX
FTM1_CH3
SPI1_SCLK
I2S0_TX_B
CLK
EZP_CLK
11
7
5
5
ADC0_SE2
ADC0_SE2
PTA4
UART1_CT
S_b
I2C2_SCL
FTM1_CH4
SPI1_MISO
I2S0_TX_F
S
EZP_DI
12
8
6
6
ADC0_SE3
ADC0_SE3
PTA5
UART1_RT
S_b
I2C2_SDA
FTM1_CH5
SPI1_MOSI CLKOUT
I2S0_TXD
EZP_DO
13
9
7
7
VDDA
VDDA
14
10
8
—
VREFH
VREFH
15
11
9
—
VREF_OUT VREF_OUT
16
12
10
—
VREFL
VREFL
17
13
11
8
VSSA
VSSA
18
14
12
9
DAC0_OUT DAC0_OUT
19
15
13
10
VREGIN
VREGIN
20
16
14
11
VOUT33
VOUT33
21
17
15
12
USB0_DM
USB0_DM
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
53
Pinout
64pin
48pin
44pin
32pin
Default
ALT0
ALT1
ALT2
ALT3
ALT4
LPTMR_AL
T1
FTM_FLT1
FTM0_QD_
PHA
RGPIO10
FTM0_CH0
FTM0_QD_
PHB
RGPIO11
FTM0_CH1
ALT5
ALT6
22
18
16
13
USB0_DP
USB0_DP
23
19
17
14
VSS
VSS
24
20
18
—
VDD
VDD
25
21
19
15
ADC0_SE8/ ADC0_SE8/ PTA6
TSI0_CH0 TSI0_CH0
26
—
—
—
ADC0_SE9/ ADC0_SE9/ PTD2
TSI0_CH1 TSI0_CH1
27
22
20
—
ADC0_SE1 ADC0_SE1 PTD3
0/TSI0_CH2 0/TSI0_CH2
28
—
—
—
ADC0_SE1 ADC0_SE1 PTD4
1/TSI0_CH3 1/TSI0_CH3
RGPIO12
FBa_D7
29
—
—
—
ADC0_SE1 ADC0_SE1 PTD5
2/TSI0_CH4 2/TSI0_CH4
RGPIO13
FBa_D6
30
23
21
16
ADC0_SE1 ADC0_SE1 PTA7
3/TSI0_CH5 3/TSI0_CH5
UART0_TX
31
24
22
—
ADC0_SE1 ADC0_SE1 PTD6
4/TSI0_CH6 4/TSI0_CH6
UART0_RX
RGPIO14
32
—
—
—
ADC0_SE1 ADC0_SE1 PTD7
5/TSI0_CH7 5/TSI0_CH7
UART0_CT
S_b
I2C3_SCL
33
—
—
—
TSI0_CH8
TSI0_CH8
PTE0
UART0_RT
S_b
I2C3_SDA
34
—
—
—
TSI0_CH9
TSI0_CH9
PTE1
SPI0_SS
35
25
23
17
IRQ/
EZP_MS_b
Disabled
PTB0
I2C0_SCL
36
26
24
18
TSI0_CH10
TSI0_CH10
PTB1
SPI0_SCLK I2C0_SDA
FBa_D7
FBa_AD17
FBa_D6
FBa_AD0
FTM0_QD_
PHA
ALT7
EzPort
FBa_D5
FBa_D4
RGPIO15
FBa_D3
FBa_D2
FTM_FLT0
FBa_D1
IRQ/
EZP_MS_b
FTM_FLT2
LPTMR_AL
T2
EZP_CS_b
FTM0_QD_
PHB
37
—
—
—
TSI0_CH11
TSI0_CH11
PTE2
I2C3_SCL
38
—
—
—
ADC0_SE1
6/
TSI0_CH12
ADC0_SE1
6/
TSI0_CH12
PTE3
SPI0_MOSI I2C3_SDA
FBa_OE_b
39
27
25
19
ADC0_SE1
7/
TSI0_CH13
ADC0_SE1
7/
TSI0_CH13
PTB2
SPI0_MISO
FBa_CS0_b
40
28
26
20
ADC0_SE1
8/
TSI0_CH14
ADC0_SE1
8/
TSI0_CH14
PTB3
SPI0_MOSI
41
29
—
—
ADC0_SE1
9/
TSI0_CH15
ADC0_SE1
9/
TSI0_CH15
PTE4
UART0_RT
S_b
LPTMR_AL
T3
SPI1_SS
FBa_AD1
42
30
—
—
ADC0_SE2
0
ADC0_SE2
0
PTE5
UART0_CT
S_b
I2C1_SCL
SPI1_SCLK
FBa_AD2
43
—
—
—
ADC0_SE2
1
ADC0_SE2
1
PTE6
UART0_RX
I2C1_SDA
SPI1_MISO
FBa_AD3
44
31
27
—
ADC0_SE2
2
ADC0_SE2
2
PTE7
UART0_TX
PDB0_EXT
RG
SPI1_MOSI FBa_RW_b
FBa_AD4
45
32
28
21
BKGD/MS
Disabled
PTB4
BKGD/MS
46
33
29
22
XTAL2
XTAL2
PTB5
FB_CLKOU
T
FBa_D0
FBa_CS1_b FBa_ALE
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
54
Preliminary
Freescale Semiconductor, Inc.
Pinout
64pin
48pin
44pin
32pin
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
47
34
30
23
EXTAL2
EXTAL2
48
35
31
24
VDD
VDD
49
36
32
25
VSS
VSS
50
37
33
26
EXTAL1
EXTAL1
PTB7
I2C1_SDA
TMR_CLKI
N1
51
38
34
27
XTAL1
XTAL1
PTC0
I2C1_SCL
TMR_CLKI
N0
52
39
35
28
RESET_b
Disabled
PTC1
RESET_b
53
—
—
—
CMP0_IN0
CMP0_IN0
PTF0
SPI0_SS
54
—
—
—
Disabled
Disabled
PTF1
SPI0_SCLK
CMP0_OUT FBa_AD6
55
—
—
—
CMP0_IN1
CMP0_IN1
PTF2
SPI0_MISO
FBa_AD7
ALT7
EzPort
PTB6
RGPIO0
FBa_AD5
56
40
36
—
CMP0_IN2
CMP0_IN2
PTF3
SPI0_MOSI
RGPIO1
FBa_AD8
I2S0_TXD
57
41
37
29
CMP0_IN3
CMP0_IN3
PTC2
UART1_RT
S_b
SPI1_SS
RGPIO2
FBa_AD18
I2S0_TX_F
S
58
42
38
—
Disabled
Disabled
PTF4
UART1_CT
S_b
SPI1_SCLK
FBa_D3
FBa_AD19
I2S0_TX_B
CLK
59
43
39
—
Disabled
Disabled
PTF5
UART1_RX
SPI1_MISO
FBa_D2
FBa_RW_b
I2S0_RXD
60
44
40
—
Disabled
Disabled
PTF6
UART1_TX
SPI1_MOSI
FBa_D1
FBa_AD9
I2S0_RX_F
S
61
45
41
—
Disabled
Disabled
PTF7
UART0_RT
S_b
FBa_D0
FBa_AD10
I2S0_RX_B
CLK
62
46
42
30
Disabled
Disabled
PTC3
UART0_CT
S_b
RGPIO3
SPI0_SCLK CLKOUT
USB_CLKIN I2S0_MCLK
/
I2S0_CLKIN
63
47
43
31
Disabled
Disabled
PTC4
UART0_RX
RGPIO4
SPI0_MISO PDB0_EXT
RG
USB_SOF_
PULSE
64
48
44
32
Disabled
Disabled
PTC5
UART0_TX
RGPIO5
SPI0_MOSI CMT_IRO
SPI0_SS
8.2 Pinout diagrams
The following diagrams show pinouts for the 64-pin, 48-pin, 44-pin, and 32-pin
packages.
For each pin, the diagrams show the default function or (when disabled is the default) the
ALT1 signal for a GPIO function. However, many signals may be multiplexed onto a
single pin.
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
55
PTC5
PTC4
PTC3
PTF7
PTF6
PTF5
PTF4
CMP0_IN3
CMP0_IN2
CMP0_IN1
PTF1
CMP0_IN0
RESET_b
XTAL1
EXTAL1
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Pinout
PTA2
9
40
ADC0_SE18/TSI0_CH14
PTA3
10
39
ADC0_SE17/TSI0_CH13
ADC0_SE2
11
38
ADC0_SE16/TSI0_CH12
ADC0_SE3
12
37
TSI0_CH11
VDDA
13
36
TSI0_CH10
VREFH
14
35
IRQ/EZP_MS_b
VREF_OUT
15
34
TSI0_CH9
VREFL
16
33
TSI0_CH8
32
ADC0_SE19/TSI0_CH15
ADC0_SE15/TSI0_CH7
41
31
8
ADC0_SE14/TSI0_CH6
PTA1
30
ADC0_SE20
ADC0_SE13/TSI0_CH5
42
29
7
ADC0_SE12/TSI0_CH4
PTA0
28
ADC0_SE21
ADC0_SE11/TSI0_CH3
43
27
6
ADC0_SE10/TSI0_CH2
PTD1
26
ADC0_SE22
ADC0_SE9/TSI0_CH1
44
25
5
ADC0_SE8/TSI0_CH0
PTD0
24
BKGD/MS
VDD
45
23
4
VSS
PTC7
22
XTAL2
USB0_DP
46
21
3
USB0_DM
PTC6
20
EXTAL2
VOUT33
47
19
2
VREGIN
VSS
18
VDD
DAC0_OUT
48
17
1
VSSA
VDD
Figure 23. 64-pin Laminate QFN (pinout identical for 64-pin LQFP)
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
56
Preliminary
Freescale Semiconductor, Inc.
PTC5
PTC4
PTC3
PTF7
PTF6
PTF5
PTF4
CMP0_IN3
CMP0_IN2
RESET_b
XTAL1
EXTAL1
48
47
46
45
44
43
42
41
40
39
38
37
Pinout
ADC0_SE2
7
30
ADC0_SE20
ADC0_SE3
8
29
ADC0_SE19/TSI0_CH15
VDDA
9
28
ADC0_SE18/TSI0_CH14
VREFH
10
27
ADC0_SE17/TSI0_CH13
VREF_OUT
11
26
TSI0_CH10
VREFL
12
25
IRQ/EZP_MS_b
24
ADC0_SE22
ADC0_SE14/TSI0_CH6
31
23
6
ADC0_SE13/TSI0_CH5
PTA3
22
BKGD/MS
ADC0_SE10/TSI0_CH2
32
21
5
ADC0_SE8/TSI0_CH0
PTA2
20
XTAL2
VDD
33
19
4
VSS
PTA1
18
EXTAL2
USB0_DP
34
17
3
USB0_DM
PTA0
16
VDD
VOUT33
35
15
2
VREGIN
PTD1
14
VSS
DAC0_OUT
36
13
1
VSSA
PTD0
Figure 24. 48-pin LQFP
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
57
PTC5
PTC4
PTC3
PTF7
PTF6
PTF5
PTF4
CMP0_IN3
CMP0_IN2
RESET_b
XTAL1
44
43
42
41
40
39
38
37
36
35
34
Pinout
28
BKGD/MS
VDDA
7
27
ADC0_SE22
VREFH
8
26
ADC0_SE18/TSI0_CH14
VREF_OUT
9
25
ADC0_SE17/TSI0_CH13
VREFL
10
24
TSI0_CH10
VSSA
11
23
IRQ/EZP_MS_b
22
6
ADC0_SE14/TSI0_CH6
ADC0_SE3
21
XTAL2
ADC0_SE13/TSI0_CH5
29
20
5
ADC0_SE10/TSI0_CH2
ADC0_SE2
19
EXTAL2
ADC0_SE8/TSI0_CH0
30
18
4
VDD
PTA3
17
VDD
VSS
31
16
3
USB0_DP
PTA2
15
VSS
USB0_DM
32
14
2
VOUT33
PTA1
13
EXTAL1
VREGIN
33
12
1
DAC0_OUT
PTA0
Figure 25. 44-pin Laminate QFN
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
58
Preliminary
Freescale Semiconductor, Inc.
PTC5
PTC4
PTC3
CMP0_IN3
RESET_b
XTAL1
EXTAL1
VSS
32
31
30
29
28
27
26
25
Pinout
21
BKGD/MS
ADC0_SE2
5
20
ADC0_SE18/TSI0_CH14
ADC0_SE3
6
19
ADC0_SE17/TSI0_CH13
VDDA
7
18
TSI0_CH10
VSSA
8
17
IRQ/EZP_MS_b
VREGIN
DAC0_OUT
16
4
ADC0_SE13/TSI0_CH5
PTA3
15
XTAL2
ADC0_SE8/TSI0_CH0
22
14
3
VSS
PTA2
13
EXTAL2
USB0_DP
23
12
2
USB0_DM
PTA1
11
VDD
VOUT33
24
10
1
9
PTA0
Figure 26. 32-pin QFN
8.3 Module-by-module signals
NOTE
• On PTB0, EZP_MS_b is active only during reset. Refer to
the detailed boot description.
• PTC1 is open drain.
Table 38. Module signals by GPIO port and pin
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
Power and ground
1
24
VDD
20
18
VDD
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
59
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
48
35
31
24
Port
Module signal(s)
VDD
2
VSS
23
19
17
14
VSS
49
36
32
25
VSS
System
45
32
28
21
PTB4
BKGD/MS
12
8
6
6
PTA5
CLKOUT
62
46
42
30
PTC3
CLKOUT
10
6
4
4
PTA3
EZP_CLK
11
7
5
5
PTA4
EZP_DI
12
8
6
6
PTA5
EZP_DO
35
25
23
17
PTB0
IRQ/EZP_MS_b,
EZP_CS_b
52
39
35
28
PTC1
RESET_b
OSC
50
37
33
26
PTB7
EXTAL1
47
34
30
23
PTB6
EXTAL2
51
38
34
27
PTC0
XTAL1
46
33
29
22
PTB5
XTAL2
PTC7
LLWU_P0
PTD1
LLWU_P1
LLWU
4
6
2
12
8
6
6
PTA5
LLWU_P2
30
23
21
16
PTA7
LLWU_P3
PTD7
LLWU_P4
32
35
25
23
17
PTB0
LLWU_P5
36
26
24
18
PTB1
LLWU_P6
39
27
25
19
PTB2
LLWU_P7
44
31
27
PTE7
LLWU_P8
45
32
28
PTB4
LLWU_P9
PTF2
LLWU_P10
PTF3
LLWU_P11
PTC2
LLWU_P12
PTF5
LLWU_P13
PTC3
LLWU_P14
21
55
56
40
36
57
41
37
59
43
39
62
46
42
29
30
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
60
Preliminary
Freescale Semiconductor, Inc.
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
63
47
43
31
PTC4
LLWU_P15
27
PTC0
RGPIO0
PTF3
RGPIO1
RGPIO
51
38
34
56
40
36
57
41
37
29
PTC2
RGPIO2
62
46
42
30
PTC3
RGPIO3
63
47
43
31
PTC4
RGPIO4
64
48
44
32
PTC5
RGPIO5
3
PTC6
RGPIO6
4
PTC7
RGPIO7
5
1
PTD0
RGPIO8
6
2
PTD1
RGPIO9
PTD2
RGPIO10
PTD3
RGPIO11
28
PTD4
RGPIO12
29
PTD5
RGPIO13
PTD6
RGPIO14
PTD7
RGPIO15
26
27
31
22
24
20
22
32
LPTMR
25
21
19
15
PTA6
LPTMR_ALT1
36
26
24
18
PTB1
LPTMR_ALT2
41
29
PTE4
LPTMR_ALT3
LPTMR-TOD
50
37
33
26
PTB7
EXTAL1
47
34
30
23
PTB6
EXTAL2
25
21
19
15
PTA6
LPTMR_ALT1
36
26
24
18
PTB1
LPTMR_ALT2
41
29
PTE4
LPTMR_ALT3
51
38
34
27
PTC0
XTAL1
46
33
29
22
PTB5
XTAL2
PTA
7
3
1
1
PTA0
PTA0
8
4
2
2
PTA1
PTA1
9
5
3
3
PTA2
PTA2
10
6
4
4
PTA3
PTA3
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
61
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
11
7
5
5
PTA4
PTA4
12
8
6
6
PTA5
PTA5
25
21
19
15
PTA6
PTA6
30
23
21
16
PTA7
PTA7
PTB
35
25
23
17
PTB0
PTB0
36
26
24
18
PTB1
PTB1
39
27
25
19
PTB2
PTB2
40
28
26
20
PTB3
PTB3
45
32
28
21
PTB4
PTB4
46
33
29
22
PTB5
PTB5
47
34
30
23
PTB6
PTB6
50
37
33
26
PTB7
PTB7
PTC
51
38
34
27
PTC0
PTC0
52
39
35
28
PTC1
PTC1
57
41
37
29
PTC2
PTC2
62
46
42
30
PTC3
PTC3
63
47
43
31
PTC4
PTC4
64
48
44
32
PTC5
PTC5
3
PTC6
PTC6
4
PTC7
PTC7
PTD
5
1
PTD0
PTD0
6
2
PTD1
PTD1
PTD2
PTD2
PTD3
PTD3
28
PTD4
PTD4
29
PTD5
PTD5
PTD6
PTD6
PTD7
PTD7
33
PTE0
PTE0
34
PTE1
PTE1
38
PTE3
PTE2
26
27
31
22
24
20
22
32
PTE
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
62
Preliminary
Freescale Semiconductor, Inc.
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
39
27
25
19
PTB2
PTE3
41
29
PTE4
PTE4
42
30
PTE5
PTE5
PTE6
PTE6
PTE7
PTE7
53
PTF0
PTF0
54
PTF1
PTF1
55
PTF2
PTF2
43
44
31
27
PTF
56
40
36
PTF3
PTF3
58
42
38
PTF4
PTF4
59
43
39
PTF5
PTF5
60
44
40
PTF6
PTF6
61
45
41
PTF7
PTF7
5 V VREG
20
16
14
11
VOUT33
19
15
13
10
VREGIN
USB0
63
47
43
31
PTC4
USB_SOF_PULSE
62
46
42
30
PTC3
USB_CLKIN
21
17
15
12
USB0_DM
22
18
16
13
USB0_DP
20
16
14
11
VOUT33
19
15
13
10
VREGIN
ADC0
11
7
5
5
PTA4
ADC0_SE2
12
8
6
6
PTA5
ADC0_SE3
25
21
19
15
PTA6
ADC0_SE8
PTD2
ADC0_SE9
PTD3
ADC0_SE10
28
PTD4
ADC0_SE11
29
PTD5
ADC0_SE12
PTA7
ADC0_SE13
PTD6
ADC0_SE14
PTD7
ADC0_SE15
26
27
22
20
30
23
21
31
24
22
16
32
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
63
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
38
Port
Module signal(s)
PTE3
ADC0_SE16
39
27
25
19
PTB2
ADC0_SE17
40
28
26
20
PTB3
ADC0_SE18
41
29
PTE4
ADC0_SE19
42
30
PTE5
ADC0_SE20
PTE6
ADC0_SE21
PTE7
ADC0_SE22
43
44
31
27
13
9
7
14
10
8
VREFH
16
12
10
VREFL
17
13
11
7
VDDA
8
VSSA
9
DAC0_OUT
DAC0
18
14
12
VREF
15
11
9
VREF_OUT
CMP0
53
PTF0
CMP0_IN0
55
PTF2
CMP0_IN1
PTF3
CMP0_IN2
PTC2
CMP0_IN3
PTF1
CMP0_OUT
PTC5
CMT_IRO
PTD0
I2S0_MCLK/
I2S0_CLKIN
PTC3
I2S0_MCLK/
I2S0_CLKIN
PTD1
I2S0_RX_BCLK
PTF7
I2S0_RX_BCLK
PTA0
I2S0_RX_FS
PTF6
I2S0_RX_FS
PTA1
I2S0_RXD
PTF5
I2S0_RXD
PTA3
I2S0_TX_BCLK
PTF4
I2S0_TX_BCLK
56
40
36
57
41
37
29
54
CMT
64
48
44
32
I2S0
5
1
62
46
6
2
61
45
41
7
3
1
60
44
40
8
4
2
59
43
39
10
6
4
58
42
38
42
30
1
2
4
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
64
Preliminary
Freescale Semiconductor, Inc.
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
11
7
5
5
PTA4
I2S0_TX_FS
57
41
37
29
PTC2
I2S0_TX_FS
12
8
6
6
PTA5
I2S0_TXD
56
40
36
PTF3
I2S0_TXD
PTA6
TSI0_CH0
PTD2
TSI0_CH1
PTD3
TSI0_CH2
28
PTD4
TSI0_CH3
29
PTD5
TSI0_CH4
PTA7
TSI0_CH5
PTD6
TSI0_CH6
32
PTD7
TSI0_CH7
33
PTE0
TSI0_CH8
34
PTE1
TSI0_CH9
PTB1
TSI0_CH10
37
PTE2
TSI0_CH11
38
PTE3
TSI0_CH12
TSI0
25
21
19
15
26
27
22
20
30
23
21
31
24
22
36
26
16
24
18
39
27
25
19
PTB2
TSI0_CH13
40
28
26
20
PTB3
TSI0_CH14
41
29
PTE4
TSI0_CH15
PTE7
PDB0_EXTRG
PTC4
PDB0_EXTRG
PTE1
FTM_FLT0
PDB0
44
31
27
63
47
43
31
FTM0
34
25
21
19
15
PTA6
FTM_FLT1
36
26
24
18
PTB1
FTM_FLT2 /
FTM0_QD_PHB
PTD2
FTM0_CH0/
FTM0_QD_PHA
PTD3
FTM0_CH1 /
FTM0_QD_PHB
26
27
22
20
30
23
21
16
PTA7
FTM0_QD_PHA
51
38
34
27
PTC0
TMR_CLKIN0
50
37
33
26
PTB7
TMR_CLKIN1
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
65
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
PTE1
FTM_FLT0
FTM1
34
25
21
19
15
PTA6
FTM_FLT1
36
26
24
18
PTB1
FTM_FLT2
7
3
1
1
PTA0
FTM1_CH0
8
4
2
2
PTA1
FTM1_CH1
9
5
3
3
PTA2
FTM1_CH2
10
6
4
4
PTA3
FTM1_CH3
11
7
5
5
PTA4
FTM1_CH4
12
8
6
6
PTA5
FTM1_CH5
51
38
34
27
PTC0
TMR_CLKIN0
50
37
33
26
PTB7
TMR_CLKIN1
MTIM
51
38
34
27
PTC0
TMR_CLKIN0
50
37
33
26
PTB7
TMR_CLKIN1
18
PTB1
FB_CLKOUT
PTD3
FBa_AD0
Mini-FlexBus
36
26
24
27
22
20
41
29
PTE4
FBa_AD1
42
30
PTE5
FBa_AD2
PTE6
FBa_AD3
PTE7
FBa_AD4
53
PTF0
FBa_AD5
54
PTF1
FBa_AD6
55
PTF2
FBa_AD7
43
44
31
27
56
40
36
PTF3
FBa_AD8
60
44
40
PTF6
FBa_AD9
61
45
41
PTF7
FBa_AD10
3
PTC6
FBa_AD11
4
PTC7
FBa_AD12
5
1
PTD0
FBa_AD13
6
2
PTD1
FBa_AD14
7
3
1
1
PTA0
FBa_AD15
8
4
2
2
PTA1
FBa_AD16
25
21
19
15
PTA6
FBa_AD17
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
66
Preliminary
Freescale Semiconductor, Inc.
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
57
41
37
29
PTC2
FBa_AD18
58
42
38
PTF4
FBa_AD19
40
28
26
20
PTB3
FBa_ALE
39
27
25
19
PTB2
FBa_CS0_b
37
PTE2
FBa_D0
34
PTE1
FBa_D1
33
PTE0
FBa_D2
32
PTD7
FBa_D3
PTD6
FBa_D4
PTA7
FBa_D5
29
PTD5
FBa_D6
28
PTD4
FBa_D7
38
PTE3
FBa_OE_b
PTF5
FBa_RW_b
31
24
22
30
23
21
59
43
16
39
DATA_BUS
8
4
2
2
PTA1
FBa_AD16
39
27
25
19
PTB2
FBa_CS0_b
61
45
41
PTF7
FBa_D0
60
44
40
PTF6
FBa_D1
59
43
39
PTF5
FBa_D2
58
42
38
PTF4
FBa_D3
31
24
22
PTD6
FBa_D4
30
23
21
PTA7
FBa_D5
27
22
20
PTD3
FBa_D6
25
21
19
PTA6
FBa_D7
44
31
27
PTE7
FBa_RW_b
PTC6
I2C0_SCL
PTB0
I2C0_SCL
PTC7
I2C0_SDA
PTB1
I2C0_SDA
16
15
I2C0 and I2C1
3
35
25
23
17
4
36
26
24
18
6
2
PTD1
I2C1_SCL
42
30
PTE5
I2C1_SCL
51
38
PTC0
I2C1_SCL
5
1
PTD0
I2C1_SDA
34
27
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
67
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
44-pin
32-pin
Port
Module signal(s)
PTE6
I2C1_SDA
26
PTB7
I2C1_SDA
43
50
37
33
I2C2 and I2C3
7
3
1
1
PTA0
I2C2_SCL
11
7
5
5
PTA4
I2C2_SCL
8
4
2
2
PTA1
I2C2_SDA
12
8
6
6
PTA5
I2C2_SDA
32
PTD7
I2C3_SCL
37
PTE2
I2C3_SCL
33
PTE0
I2C3_SDA
38
PTE3
I2C3_SDA
PTB2
SPI0_MISO
PTF2
SPI0_MISO
PTC4
SPI0_MISO
PTE3
SPI0_MOSI
PTB3
SPI0_MOSI
PTF3
SPI0_MOSI
SPI0
39
27
25
19
55
63
47
43
31
38
40
28
26
20
56
40
36
64
48
44
32
PTC5
SPI0_MOSI
36
26
24
18
PTB1
SPI0_SCLK
PTF1
SPI0_SCLK
54
62
46
42
30
PTC3
SPI0_SCLK
7
3
1
1
PTA0
SPI0_SS
34
PTE1
SPI0_SS
53
PTF0
SPI0_SS
PTF7
SPI0_SS
PTC7
SPI1_MISO
PTA4
SPI1_MISO
PTE6
SPI1_MISO
PTF5
SPI1_MISO
PTC6
SPI1_MOSI
PTA5
SPI1_MOSI
61
45
41
SPI1
4
11
7
5
5
43
59
43
39
3
12
8
6
6
44
31
27
PTE7
SPI1_MOSI
60
44
40
PTF6
SPI1_MOSI
Table continues on the next page...
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
68
Preliminary
Freescale Semiconductor, Inc.
Pinout
Table 38. Module signals by GPIO port and pin (continued)
64-pin
48-pin
5
1
10
6
42
30
58
42
6
2
9
5
41
29
57
41
44-pin
32-pin
4
Port
Module signal(s)
PTD0
SPI1_SCLK
PTA3
SPI1_SCLK
PTE5
SPI1_SCLK
PTF4
SPI1_SCLK
PTD1
SPI1_SS
PTA2
SPI1_SS
PTE4
SPI1_SS
PTC2
SPI1_SS
PTD0
UART0_CTS_b
PTD7
UART0_CTS_b
PTE5
UART0_CTS_b
PTC3
UART0_CTS_b
PTD1
UART0_RTS_b
PTE0
UART0_RTS_b
PTE4
UART0_RTS_b
PTF7
UART0_RTS_b
PTC7
UART0_RX
PTD6
UART0_RX
PTE6
UART0_RX
PTC4
UART0_RX
PTC6
UART0_TX
PTA7
UART0_TX
PTE7
UART0_TX
32
PTC5
UART0_TX
5
PTA4
UART1_CTS_b
PTF4
UART1_CTS_b
4
38
3
3
37
29
UART0
5
1
32
42
30
62
46
6
2
42
30
33
41
29
61
45
41
4
31
24
22
43
63
47
43
31
3
30
23
21
44
31
27
64
48
44
16
UART1
11
7
5
58
42
38
12
8
6
6
PTA5
UART1_RTS_b
57
41
37
29
PTC2
UART1_RTS_b
10
6
4
4
PTA3
UART1_RX
59
43
39
PTF5
UART1_RX
9
5
3
PTA2
UART1_TX
60
44
40
PTF6
UART1_TX
3
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
Freescale Semiconductor, Inc.
Preliminary
69
Revision History
9 Revision History
The following table provides a revision history for this document.
Table 39. Revision History
Rev. No.
Date
Substantial Changes
0
05/2011
Initial released version
MCF51JU128 Advance Information Data Sheet, Rev. 0, 05/2011.
70
Preliminary
Freescale Semiconductor, Inc.
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Preliminary
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