ispLSI 5256V ® In-System Programmable 3.3V SuperWIDE™ High Density PLD — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Features • SuperWIDE HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 12000 PLD Gates / 256 Macrocells — Up to 192 I/O Pins — 256 Registers — High-Speed Global Interconnect — SuperWIDE 32 Generic Logic Block (GLB) Size for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. — PCB Efficient Ball Grid Array (BGA) Package Options Generic Logic Block Generic Logic Block Boundary Scan Interface Input Bus Input Bus Generic Logic Block Input Bus Generic Logic Block • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels — Electrically Erasable and Reprogrammable — Non-Volatile — Programmable Speed/Power Logic Path Optimization Input Bus Generic Logic Block Input Bus Functional Block Diagram • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE Generic Logic Block Input Bus Global Routing Pool (GRP) Generic Logic Block Generic Logic Block Input Bus Input Bus ispLSI 5000V Description The ispLSI 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. • ARCHITECTURE FEATURES — Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWide GLBs — Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell — Macrocells Support Concurrent Combinatorial and Registered Functions — Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable — Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks — Slew and Skew Programmable I/O (SASPI/O™) Supports Programmable Bus Hold, Pull-up, Open Drain and Slew and Skew Rate Options — Six Global Output Enable Terms, Two Global OE Pins and One Product Term OE per Macrocell Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device. Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and 5 extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 5256v_03 1 May 1999 Specifications ispLSI 5256V Functional Block Diagram Input Bus Generic Logic Block Input Bus Generic Logic Block TMS Input Bus I/O 20 I/O 21 I/O 22 I/O 23 Boundary Scan Interface Generic Logic Block 1I/O 0 / TOE I/O 1 I/O 2 I/O 3 TCK Input Bus Generic Logic Block VCCIO I/O 147 I/O 146 I/O 145 I/O 144 I/O 167 I/O 166 I/O 165 I/O 164 I/O 171 I/O 170 I/O 169 I/O 168 I/O 191 I/O 190 I/O 189 I/O 188 GOE1 GOE0 Figure 1. ispLSI 5256V Functional Block Diagram (272 BGA Option) Generic Logic Block Generic Logic Block Input Bus Input Bus Input Bus Input Bus Generic Logic Block I/O 44 I/O 45 I/O 46 I/O 47 Generic Logic Block Global Routing Pool (GRP) I/O 24 I/O 25 I/O 26 I/O 27 TDI TDO I/O 143 I/O 142 I/O 141 I/O 140 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 I/O 118 I/O 117 I/O 116 I/O 99 I/O 98 I/O 97 I/O 96 1. 1CLK 2 1CLK 3 CLK 0 CLK 1 I/O 92 I/O 93 I/O 94 I/O 95 I/O 72 I/O 73 I/O 74 I/O 75 I/O 68 I/O 69 I/O 70 I/O 71 I/O 48 I/O 49 I/O 50 I/O 51 GSET/GRST CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is determined by the package type used – see table below. Package Type 208 PQFP 208 BGA 272 BGA Multplexed Signals I/O 89 / CLK2 I/O 98 / CLK3 I/O 89 / CLK2 I/O 98 / CLK3 I/O 119 / CLK2 I/O 131 / CLK3 2 I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE Specifications ispLSI 5256V drivers to drive either 3.3V or 2.5V output levels while the device logic and the output current drive is always powered from 3.3V. The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs and a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device. ispLSI 5000V Description (Continued) sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The five extra product terms are used for shared GLB controls, set, reset, clock, clock enable and output enable. The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch/toggle flip-flop and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, which can be fed back through the Global Routing Pool. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to construct high-speed input registers. The ispLSI 5000V Family features 3.3V, non-volatile insystem programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface. Boundary Scan test is also supported through the same interface. An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction. Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also provided, eliminating the need to gate the clock to the macrocell registers. Reset and preset for the macrocell register is provided from both global and product term signals. The macrocell register can be programmed to operate as a Dtype register, a D-type latch or a T-type flip flop. ispLSI 5000V Family Members The ispLSI 5000V family ranges from 256 macrocells to 512 macrocells and operates from a 3.3V power supply. All family members will be available with multiple package options. The ispLSI 5000V family device matrix showing the various bondout options is shown in the table below. The 32 outputs from the GLB can drive both the Global Routing Pool and the device I/O cells. The Global Routing Pool contains one line from each macrocell output and one line from each I/O pin. The interconnect structure (GRP) is very similar to Lattice's existing 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. The ispLSI 5000V family does not, however, use registered I/O cells or an Output Routing Pool. The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source 4mA and sink 8mA. The output drivers have a separate VCCIO reference input which is independent of the main VCC supply for the device. This feature allows the output Table 1. ispLSI 5000V Family Package Type Device GLBs Macrocells 208 BGA* 208 PQFP 272 BGA 388 BGA ispLSI 5256V 8 256 144 I/O 144 I/O 192 I/O — ispLSI 5384V 12 384 144 I/O 144 I/O 192 I/O 288 I/O ispLSI 5512V 16 512 — — — 288 I/O *1.0mm ball pitch Fine Pitch BGA 3 Specifications ispLSI 5256V Figure 2. ispLSI 5256V Block Diagram (192 I/O Version) 24 I/O 24 24 32 32 32 32 24 32 Q D D 160 PT 160 PT 5 PT 5 24 24 32 32 32 Q D 160 160 32 Q 24 24 32 32 160 Q 24 24 32 32 5 5 24 I/O TOE 32 D D 160 5 PT 24 5 PT 160 32 32 32 68 68 24 Q 160 160 PT 160 PT 24 I/O 24 I/O D 448 160 5 5 32 D 5 PT 24 5 PT 160 32 24 32 68 68 CLK3 Q 160 160 PT 160 PT 24 I/O Buffers/Pins 24 I/O D 5 PT 5 5 32 32 24 Generic Logic Block (GLB) 24 68 68 CLK2 32 5 PT 160 160 24 I/O Q 160 160 Global Routing Pool (GRP) 24 I/O Q 32 24 160 160 PT 160 PT 160 160 68 68 4 5 PT 5 5512_384 CLK0 CLK1 GOE0 GOE1 SET/RESET Specifications ispLSI 5256V Figure 3. ispLSI 5000V Generic Logic Block (GLB) From Global Routing Pool 0 1 2 66 67 Global PTOE Bus PTSA Macrocell 0 PT 0 PT 1 From PTSA PTSA bypass PT 2 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 3 PT 4 Shared PT Clock 0 Shared PT (P)reset 0 Shared PT Clock 1 Shared PT (P)reset 1 6 To GRP Global PTOE 0 ... 5 Macrocell 1 PT 9 PT 8 From PTSA PTSA bypass PT 7 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 6 PT 5 Shared PT Clock 0 Shared PT (P)reset 0 Shared PT Clock 1 Shared PT (P)reset 1 6 To GRP Global PTOE 0 ... 5 Macrocell 15 PT 79 PT 78 From PTSA PTSA bypass PT 77 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 76 PT 75 Shared PT Clock 0 Shared PT (P)reset 0 Shared PT Clock 1 Shared PT (P)reset 1 6 To GRP Global PTOE 0 ... 5 Macrocell 31 PT 159 PT 158 From PTSA PTSA bypass PT 157 To I/O Pad PTOE PT Clock PT Reset PT Preset PT 156 PT 155 PT 160 PT 161 Shared PT Clock 0 Shared PT (P)reset 0 PT 162 PT 163 Shared PT Clock 1 Shared PT (P)reset 1 6 PT 164 To GRP Global PTOE 0 ... 5 GLB_5K Programmable AND Array 5 Specifications ispLSI 5256V Figure 4. ispLSI 5000V Macrocell VCCIO Global PTOE 0 Global PTOE 1 Global PTOE 2 Global PTOE 3 Global PTOE 4 Global PTOE 5 PTOE VCC VCCIO GOE0 GOE1 TOE PTSA bypass I/O Pad Delay D PTSA PT Clock Q D/T Shared PT Clock 0 Shared PT Clock 1 Slew Open rate drain 2.5V/3.3V Output Clk En To GRP R/L CLK0 CLK1 CLK2 CLK3 Clk R P PT Reset D D Q Q SET/RESET PT Preset D/T Clk En Clk Shared PT (P)reset 0 Shared PT (P)reset 1 Programmable Speed/Power Option Register/ Latch R P 6 Specifications ispLSI 5256V speed. The clock inversion is available on the remaining CLK1 - CLK3 signals. By sharing the pins with the I/O pins, CLK2 and CLK3 can not only be inverted but also is available for logic implementation through GRP signal routing. Figure 5 shows these different clock distribution options. Global Clock Distribution The ispLSI 5000V family has four dedicated clock input pins - CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest internal clock Figure 5. ispLSI 5000V Global Clock Structure CLK 0 CLK0 CLK 1 CLK1 IO/CLK 2 To GRP CLK2 CLK3 IO/CLK 3 To GRP GSET/GRST SET/RESET 7 Specifications ispLSI 5256V Figure 6. Boundary Scan Register Circuit for I/O Pins HIGHZ EXTEST SCANIN (from previous cell) BSCAN Registers D Q TOE BSCAN Latches D Normal Function OE Q 0 1 EXTEST PROG_MODE Normal Function Shift DR D Q D Q Clock DR D 0 I/O Pin 1 Q SCANOUT (to next cell) Update DR Reset Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN (from previous cell) D Shift DR Clock DR 8 Q SCANOUT (to next cell) Specifications ispLSI 5256V Figure 8. Boundary Scan Waveforms and Timing Specifications TMS TDI Tbtsu Tbtch Tbth Tbtcl Tbtcp TCK Tbtvo Tbtco TDO Valid Data Tbtcpsu Data to be captured Valid Data Tbtcph Data Captured Tbtuov Tbtuco Data to be driven out SYMBOL Tbtoz Valid Data Tbtuoz Valid Data PARAMETER MIN MAX UNITS tbtcp TCK [BSCAN test] clock pulse width 125 – ns tbtch tbtcl TCK [BSCAN test] pulse width high 62.5 – ns TCK [BSCAN test] pulse width low 62.5 – ns tbtsu TCK [BSCAN test] setup time 20 – ns tbth TCK [BSCAN test] hold time 25 – ns trf TCK [BSCAN test] rise and fall time 50 – mV/ns 25 ns tbtco TAP controller falling edge of clock to valid output – tbtoz TAP controller falling edge of clock to data output disable – 25 ns tbtvo TAP controller falling edge of clock to data output enable – 25 ns tbtcpsu BSCAN test Capture register setup time 20 – ns tbtcph BSCAN test Capture register hold time 25 – ns tbtuco BSCAN test Update reg, falling edge of clock to valid output – 50 ns tbtuoz BSCAN test Update reg, falling edge of clock to output disable – 50 ns tbtuov BSCAN test Update reg, falling edge of clock to output enable – 50 ns 9 Specifications ispLSI 5256V Absolute Maximum Ratings 1, 2 Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Condition SYMBOL MIN. MAX. UNITS Commercial TA = 0°C to +70°C 3.00 3.60 V Industrial TA = -40°C to +85°C 3.00 3.60 V 2.3 3.60 PARAMETER VCC Supply Voltage VCCIO I/O Reference Voltage V Table 2 - 0005/5256 Capacitance (TA=25°C,f=1.0 MHz) SYMBOL C1 C2 C3 PARAMETER I/O Capacitance TYPICAL UNITS 10 pf TEST CONDITIONS VCC = 3.3V, VI/O = 2.0V Clock Capacitance 10 pf VCC = 3.3V, VCK = 2.0V Global Input Capacitance 10 pf VCC = 3.3V, VG = 2.0V Table 2 - 0006/5384 Erase Reprogram Specification PARAMETER MINIMUM MAXIMUM 20 – Years 10000 – Cycles Data Retention ispLSI Erase/Reprogram Cycles UNITS Table 2-0008/3320 10 Specifications ispLSI 5256V Switching Test Conditions Figure 9. Test Load Input Pulse Levels GND to VCCIOmin ≤ 1.5ns 10% to 90% Input Rise and Fall Time Input Timing Reference Levels 1.5V Ouput Timing Reference Levels 1.5V Output Load VCCIO R1 See figure Device Output Table 2 - 0003/5384 3-state levels are measured 0.5V from steady-state active level. Test Point CL* R2 Output Load Conditions (See figure 8) 3.3V R1 R2 R1 316Ω 348Ω 511Ω 475Ω 35pF Active High ∞ 348Ω ∞ 475Ω 35pF Active Low 316Ω ∞ 511Ω ∞ 35pF Active High to Z at VOH -0.5V ∞ 348Ω ∞ 475Ω 5pF Active Low to Z at VOL+0.5V 316Ω ∞ 511Ω ∞ 5pF ∞ ∞ ∞ ∞ 35pF TEST CONDITION A B C D *CL includes Test Fixture and Probe Capacitance. 2.5V Slow Slew R2 0213D CL Table 2 - 0004A/5384 DC Electrical Characteristics for 3.3V Range Over Recommended Operating Conditions SYMBOL VCCIO VIL VIH VOL VOH PARAMETER 1 CONDITION MIN. 3.0 – 3.6 V Input Low Voltage VOH ≤ VOUT or VOUT ≤ VOL (max) -0.3 – 0.8 V Input High Voltage VOH ≤ VOUT or VOUT ≤ VOL(max) 2.0 – 5.25 V Output Low Voltage IOL = 8 mA – – 0.4 V Output High Voltage IOH = -4 mA 2.4 – – V I/O Reference Voltage TYP. MAX. UNITS Table 2 - 0007/5256 1. Typical values are at VCC = 3.3V and TA = 25°C. 11 Specifications ispLSI 5256V DC Electrical Characteristics for 2.5V Range Over Recommended Operating Conditions SYMBOL CONDITION PARAMETER MIN. TYP. MAX. UNITS VCCIO VIL VIH 2.3 – 2.7 V Input Low Voltage VOH(min) ≤ VOUT or VOUT ≤ VOL(max) -0.3 – 0.7 V Input High Voltage VOH(min) ≤ VOUT or VOUT ≤ VOL(max) 1.7 – 5.25 V VOL Output Low Voltage VCCIO=min, VIN=VIH or VIL, IOL= 100µA – – 0.2 V VOH I/O Reference Voltage VCCIO=min, VIN=VIH or VIL, IOL= 2mA Output High Voltage – – 0.7 V VCCIO=min, VIN=VIH or VIL, IOH= -100µA 2.1 – – V VCCIO=min, VIN=VIH or VIL, IOH= -2mA 1.7 – – V 2.5V/5000 DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL IIL IIH 2 IPU IBHL IBHH IBHLO IBHLH IBHT IVCCIO CONDITION PARAMETER 1 MIN. TYP. MAX. UNITS Input or I/O Low Leakage Current 0V ≤ VIN≤ VIL(Max.) – – -10 µA Input or I/O High Leakage Current (VCCIO-0.2)V ≤ VIN ≤ VCCIO – – 10 µA VCCIO ≤ VIN ≤ 5.25V – – 50 µA I/O Active Pullup Current 0V ≤ VIN ≤ VIL – – -150 µA Bus Hold Low Sustaining Current VIN ≥ VIL(max) 40 – – µA Bus Hold High Sustaining Current -40 – – µA Bus Hold Low Overdrive Current VIN ≤ VIH(min) 0V ≤ VIN ≤ VCCIO – – 550 µA Bus Hold High Overdrive Current 0V ≤ VIN ≤ VCCIO – – -550 µA VIL – VIH V – – 30 Bus Hold Trip Points Current Needed for VCCIO Pin All I/Os Pulled-up, (Total I/Os * IPUmax) 1. Typical values are at VCC = 3.3V and TA = 25°C. 2. Pullup is capable of pulling to a minimum voltage of VOH under no-load conditions. 12 mA DC Char_5256V Specifications ispLSI 5256V External Switching Characteristics Over Recommended Operating Conditions PARAM. tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 th2 TEST3 # COND. DESCRIPTION -125 4,5 -100 -70 MIN. MAX. MIN. MAX. MIN. MAX. UNITS A 1 Data Prop. Delay, 5PT Bypass — 7.5 — 10 — 15 ns A 2 Data Propagation Delay — 9.5 — 13 — 19 ns 1 A 3 Clock Frequency with Internal Feedback 125 — 100 — 70 — MHz — 4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) 87 — 64.5 — 43.5 — MHz 2 — 5 Clock Frequency, Max Toggle 167 — 125 — 83 — MHz — 6 GLB Reg. Setup Time before Clk, 5PT bypass 6 — 8 — 12 — ns A 7 GLB Reg. Clock to Output Delay — 4 — 5.5 — 8 ns — 8 GLB Reg. Hold Time after Clock, 5PT bypass 0 — 0 — 0 — ns 7.5 — 10 — 15 — ns 0 — 0 — 0 — ns 6 — 8 — 12 — ns — 9 GLB Reg. Setup Time before Clock — 10 GLB Reg. Hold Time after Clock tsu3 — 11 th3 tr1 trw1 tptoe/dis tgptoe/dis tgoe/dis twh twl — 12 GLB Reg. Hold Time after Clock, Input Reg. Path 0 — 0 — 0 — ns A 13 Ext. Reset Pin to Output Delay — 15 — 20 — 30 ns — 14 Ext. Reset Pulse Duration 7 — 9 — 14 — ns 1. 2. 3. 4. 5. GLB Reg. Setup Time before Clock, Input Reg. Path B/C 15 Local Product Term Output Enable/Disable — 9 — 12 — 18 ns B/C 16 Global Product Term Output Enable/Disable — 18 — 24 — 30 ns B/C 17 Global OE Input to Output Enable/Disable — 6 — 8 — 12 ns — 18 Ext. Sync. Clock Pulse Duration, High 3 — 4 — 6 — ns — 19 Ext. Sync. Clock Pulse Duration, Low 3 — 4 — 6 — ns Standard 32-bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, and CLK0. Timing parameters measured using normal active output driver. Timing Ext.5256.eps 13 Specifications ispLSI 5256V Internal Timing Parameters1 Over Recommended Operating Conditions PARAM -125 -100 -70 MIN MAX MIN MAX MIN MAX # DESCRIPTION 22 Input Pad and Buffer, Combinatorial Input – 0.7 – 0.9 – 1.4 ns 23 Input Pad and Buffer, Registered Input – 4.7 – 6.6 – 9.7 ns 24 Output Pad and Buffer, Combinatorial Output – 1.3 – 2 – 2.6 ns UNIT I/O Buffer tidcom tidreg todcom todreg todz tslf tsls tslfd tslsd 25 Output Pad and Buffer, Registered Output – 1.8 – 2.8 – 4.6 ns 26 Output Buffer Enable/Disable – 1.3 – 1.7 – 2.6 ns 27 Slew Rate Adder, Fast Slew – 0 – 0 – 0 ns 28 Slew Rate Adder, Slow Slew – 7.5 – 10 – 15 ns 29 Programmable Delay Adder, Fast Slew – 0.5 – 0.7 – 1 ns 30 Programmable Delay Adder, Slow Slew – 8 – 10.7 – 16 ns Macrocell Register/Latch Bypass – 0 – 0 – 0 ns 32 Macrocell Latch Delay – 1 – 1.4 – 2 ns 33 Macrocell Register/Latch Clock to Output – 1 – 1 – 1 ns 34 Macrocell Register/Latch Setup Time 1 – 1.1 – 1.7 – ns 35 Macrocell Register/Latch Hold Time 2.5 – 3.9 – 5.3 – ns 36 Macrocell Register/Latch CLKEN Setup Time 1 – 1.4 – 2 – ns 37 Macrocell Register/Latch CLKEN Hold Time 1 – 1.4 – 2 – ns 38 Macrocell Register/Latch Set/Reset Time – 1 – 1.4 – 2 ns 39 Toggle Flip-Flop Feedback – 1 – 1.3 – 2 ns 40 AND Array, High Speed Mode – 3 – 4 – 6 ns 41 AND Array, Low Power Mode – 5 – 6.0 – 10 ns 42 5 Product Term Bypass, Combinatorial – 1 – 1.4 – 2 ns 43 5 Product Term Bypass, Registered – 1 – 1.7 – 2.3 ns 44 5 Product Term XOR, Combinatorial – 2.5 – 3.6 – 5 ns 45 5 Product Term XOR, Registered – 1.5 – 2.2 – 3.3 ns 46 Product Term Sharing Array, Combinatorial – 3 – 4.1 – 6 ns 47 Product Term Sharing Array, Registered – 2.0 – 2.7 – 4.3 ns 48 Product Term Clock Delay – 0.5 – 0.7 – 1 ns GLB/Macrocell Delay Register tmbp tmlat tmco tmsu tmh tmsuce tmhce tmrst tftog 31 AND Array tandhs tandlp PTSA t5ptcom t5ptreg t5ptxcom t5pxtreg tptsacom tptsareg PTSA Controls tpck tpcken tscken tsck tptsacken tsrst tprst tpoe tgpoe 49 Product Term CLKEN Delay – 1 – 1.4 – 2 ns 50 Shared Product Term CLKEN Delay – 1 – 1.4 – 2 ns 51 Shared Product Term Clock Delay – 0.5 – 0.7 – 1 ns 52 Product Term Sharing Array CLKEN Delay – 2.0 – 2.4 – 4 ns 53 Shared Product Term Set/Reset Delay – 2.5 – 3.4 – 5 ns 54 Product Term Set/Reset Delay – 1.5 – 2 – 3 ns 55 Product Term Output Enable/Disable – 2.5 – 3.4 – 5 ns 56 Global PT Output Enable/Disable – 11.5 – 15.4 – 17 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 14 Specifications ispLSI 5256V Internal Timing Parameters1 Over Recommended Operating Conditions PARAM -125 -100 -70 MIN MAX MIN MAX MIN MAX # DESCRIPTION 57 GRP Delay from I/O Pad – 1.5 – 2 – 3 ns 58 GRP Delay from Macrocell – 1.0 – 1.2 – 1.2 ns UNIT GRP tgrpi tgrpm Global Control Delays tgclk01 tgclk23 tgclken0 tgclken1 tgrst tgoe ttoe 59 Global Clock 0 or 1 Delay – 1.2 – 1.7 – 2.4 ns 60 Global Clock 2 or 3 Delay – 2.2 – 2.7 – 4.4 ns 61 Global CLKEN 0 Delay – 1.7 – 2.4 – 3.4 ns 62 Global CLKEN 1 Delay – 2.7 – 3.4 – 5.4 ns 63 Global Set/Reset Delay – 12.2 – 15.8 – 23.4 ns 64 Global OE Delay – 4.7 – 6.3 – 9.4 ns 65 Test OE Delay – 4.7 – 6.2 – 9.4 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. ispLSI 5256V Timing Model Input Buffer I/O Pad INPUT #20 tidcom tidreg #56 tgrpm PTSA #21 #40 t5ptcom #44 tptsacom #42 t5ptxcom #41 t5ptxreg #45 tptsareg #43 t5ptreg AND Array #29 #30 #32 tmbp tmlat tmsu #31 tmco #35 tmhce #34 tmsuce tandhs tandlp #39 Register #33 tmh #38 Input Pad Buffer Delays #37 tftog #55 tgrpi Dedicated Input Buffers #57 tgclk0 #58 tgclk123 #59 tgclken0 #60 tgclken1 #61 tgrst #62 tgoe #63 ttoe Output Buffer GLB/Macrocell GRP #36 tmrst PT Controls #49 tsck #46 tpck #50 tptsacken #47 tpcken #48 tscken #51 tsrst #52 tprst #53 tpoe #54 tgpoe 15 #22 todcom #23 todreg #24 todz Slew tslsd tslfd #28 #27 #25 #26 tslf tsls I/O Pad OUTPUT Specifications ispLSI 5256V Power Consumption Power Consumption in the ispLSI 5256V device depends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/power tradeoff setting. Each group of four product terms has a single speed/power tradeoff control fuse that acts on the complete group of four. The fast "high-speed" setting operates product terms at their normal full power consumption. For portions of the logic that can tolerate longer propagation delays, selecting the slower "lowpower" setting will significantly reduce the power dissipation for these product terms.Figure 10 shows the relationship between power and operating speed. Figure 10. Typical Device Power Consumption vs fmax 400 ispLSI 5256V High Speed Mode 350 ICC (mA) 300 250 200 ispLSI 5256V Low Power Mode 150 100 0 20 40 60 80 100 120 140 fmax (MHz) Notes: Configuration of 16 16-bit Counters Typical Current at 3.3V, 25° C ICC can be estimated for the ispLSI 5256V using the following equation: High Speed Mode: ICC = 30 + (# of PTs * 0.456) + (# of nets * Max. freq * 0.0039) Low Power Mode: ICC = 30 + (# of PTs * 0.22) + (# of nets * Max. freq * 0.0039) # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/5256 16 Specifications ispLSI 5256V Signal Descriptions Signal Name TMS Description Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. TCK Input - This pin is the Test Clock input pin used to clock through the JTAG state machine. TDI Input - This pin is the JTAG Test Data In pin used to load Data. TDO Output - This pin is the JTAG Test Data Out pin used to shift data out. TOE / I/O0 Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon customer's design. TOE tristates all I/O pins when a logic low is driven. GOE0, GOE1 Input - These two pins are the Global Output Enable input pins. GSET/GRST Dedicated Set/Reset Input - This pin is available to all registers in the device and can independently be configured as preset, reset or no effect on each register. The global polarity (active high or low input) for this pin is also selectable. I/O Input/Output – These are the general purpose I/O used by the logic array. GND Ground NC1 No connect. VCC Vcc CLK0, CLK1 Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock input to all registers in the device. CLK2 / I/O, CLK3 / I/O Input/Output - These pins function as either dedicated clock inputs for all registers or an I/O pin based upon customer's design. Both clocks are muxed before being used as the clock input to all registers in the device. VCCIO Input - This pin is used if an optional 2.5V output is to be used. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply. 1. NC pins are not to be connected to any active signals, VCC or GND. 17 Specifications ispLSI 5256V Signal Locations (208-Pin PQFP) Signal GOE0, GOE1 Pin 78, 79 TOE / I/O0 32 GSET/GRST 138 TCK 29 TDI 30 TDO 136 TMS 28 CLK0, CLK1 184,185 CLK2 / I/O89 162 CLK3 / I/O98 173 VCCIO 137 GND 3, 12, 19, 27, 39, 48, 58, 69, 77, 88, 99, 113, 121, 128, 135, 150, 164, 170, 179, 191, 199 VCC 7, 14, 22, 31, 41, 61, 80, 90, 110, 123, 139, 152, 156, 177, 186, 201 NC 49, 50, 51, 52, 101, 102, 103, 104, 105, 106, 107, 108, 109, 157, 158, 207, 208 1. NCs are not to be connected to any active signals, VCC or GND. 18 Specifications ispLSI 5256V I/O Locations (208-Pin PQFP) I/O # Pin I/O # Pin I/O # Pin I/O # Pin I/O # Pin I/O # Pin 0* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 32 33 34 35 36 37 38 40 42 43 44 45 46 47 53 54 55 56 57 59 60 62 63 64 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 65 66 67 68 70 71 72 73 74 75 76 81 82 83 84 85 86 87 89 91 92 93 94 95 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 96 97 98 100 111 112 114 115 116 117 118 119 120 122 124 125 126 127 129 130 131 132 133 134 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89* 90 91 92 93 94 95 140 141 142 143 144 145 146 147 148 149 151 153 154 155 159 160 161 162 163 165 166 167 168 169 96 97 98* 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 171 172 173 174 175 176 178 180 181 182 183 187 188 189 190 192 193 194 195 196 197 198 200 202 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 203 204 205 206 1 2 4 5 6 8 9 10 11 13 15 16 17 18 20 21 23 24 25 26 * I/O 89 is multiplexed with CLK2, I/O 98 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 19 Specifications ispLSI 5256V Signal Locations (208-Ball BGA) Signal GOE0, GOE1 Ball P9, P10 TOE / I/O0 K1 GSET/GRST H14 TCK K2 TDI K3 TDO G14 TMS J1 CLK0, CLK1 A7, B8 CLK2 / I/O89 B13 CLK3 / I/O98 A11 VCCIO H15 GND D10, D12, D13, D5, D7, D8, E4, F13, G4, G8, G9, H10, H13, H7, J10, J13, J4, J7, K8, K9, L13, L4, M13, N10, N12, N4, N5, N7, N8 VCC D11, D4, D6, D9, E13, F4, G10, G13, G7, H4, H8, H9, J8, J9, K10, K13, K4, K7, M4, N11, N13, N6, N9 NC1 E15, C14 1. NCs are not to be connected to any active signals, VCC or GND. 20 Specifications ispLSI 5256V I/O Locations (208-Ball BGA) I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball I/O # Ball 0* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 K1 L2 L1 L3 M1 M2 M3 N1 N3 N2 P2 P1 R1 R2 R3 P3 T1 P4 R4 R5 P5 T2 R6 T3 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 T4 T5 R7 P6 T6 T7 R8 P8 P7 T8 T9 R9 R10 T10 T11 T12 T13 T14 P11 P12 R11 T15 T16 R14 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 R12 P14 P13 R13 R15 P15 R16 P16 N15 N14 M14 N16 M15 M16 L14 L15 L16 K14 K15 K16 J14 J15 J16 H16 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89* 90 91 92 93 94 95 G16 F14 G15 F16 E14 F15 E16 D16 C16 B16 D15 D14 A16 C15 B15 A15 B14 B13 C13 A14 C12 B12 A13 A12 96 97 98* 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 C11 B11 A11 B10 A10 C10 B9 C9 A9 A8 C8 C7 B7 A6 A5 C6 B6 A4 A3 A2 C5 B5 B4 C4 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 C3 C2 B3 B2 A1 D2 B1 D3 E2 C1 E3 D1 F2 E1 F1 G2 F3 H2 H3 G3 G1 H1 J2 J3 * I/O 89 is multiplexed with CLK2, I/O 98 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 21 Specifications ispLSI 5256V Signal Locations (272-Ball Grid Array) Signal GOE0, GOE1 Ball V11, U11 TOE / I/O 0 M2 SET/RST J18 TCK L4 TDI M1 TDO J20 TMS L3 CLK0, CLK1 C10, D10 CLK2 / I/O 119 A18 CLK3 / I/O 131 B13 VCCIO J19 GND A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12, N4, N17, U4, U8, U13, U17 VCC D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 NC1 U1, W1, E2, U2, W2, Y2, B3, C3, D3, U3, C5, W4, T4, Y12, A17, T17, W17, B18, C18, B19, C19, D19, W19, B20, T20, W20, Y20, P19, R3 1. NCs are not to be connected to any active signals, VCC or GND. 22 Specifications ispLSI 5256V I/O Locations (272-Ball Grid Array) I/O # Ball I/O # Ball I/O # Ball 0* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 M2 M3 M4 N1 N2 N3 P1 P2 R1 P3 R2 T1 P4 T2 T3 V1 V2 V3 Y1 W3 V4 U5 Y3 Y4 V5 W5 Y5 V6 U7 W6 Y6 V7 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 W7 Y7 V8 W8 Y8 U9 V9 W9 Y9 W10 V10 Y10 Y11 W11 W12 V12 U12 Y13 W13 V13 Y14 W14 Y15 V14 W15 Y16 U14 V15 W16 Y17 V16 Y18 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 U16 V17 W18 Y19 V18 V19 U19 U18 V20 U20 T18 T19 R18 P17 R19 R20 P18 P20 N18 N19 N20 M17 M18 M19 M20 L19 L18 L20 K20 K19 K18 K17 I/O # 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119* 120 121 122 123 124 125 126 127 Ball I/O # Ball I/O # J17 H20 H19 H18 G20 G19 F20 G18 F19 E20 G17 F18 E19 D20 E18 C20 E17 D18 A20 A19 B17 C17 D16 A18 C16 B16 A16 C15 D14 B15 A15 C14 128 129 130 131* 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 B14 A14 C13 B13 A13 D12 C12 B12 A12 B11 C11 A11 A10 B10 A9 B9 C9 D9 A8 B8 C8 A7 B7 A6 C7 B6 A5 D7 C6 B5 A4 B4 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 * I/O 119 is multiplexed with CLK2, I/O 131 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE. 23 Ball A3 D5 C4 B2 A2 B1 C2 D2 E4 C1 D1 E3 E1 F3 G4 F2 F1 G3 G2 G1 H3 H2 H1 J4 J3 J2 J1 K2 K3 K1 L1 L2 Specifications ispLSI 5256V Pin Configuration 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 NC1 NC1 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 VCC I/O 118 GND I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 I/O 111 GND I/O 110 I/O 109 I/O 108 I/O 107 VCC CLK1 CLK0 I/O 106 I/O 105 I/O 104 I/O 103 GND I/O 102 VCC I/O 101 I/O 100 I/O 99 I/O 98 / CLK32 I/O 97 I/O 96 GND I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 GND I/O 90 I/O 89 / CLK22 I/O 88 I/O 87 I/O 86 NC1 NC1 ispLSI 5256V 208-pin PQFP ispLSI 5256V Top View 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VCC I/O 85 I/O 84 I/O 83 VCC I/O 82 GND I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 VCC GSET/GRST VCCIO TDO GND I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 GND I/O 65 I/O 64 I/O 63 I/O 62 VCC I/O 61 GND I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 GND I/O 53 I/O 52 VCC NC1 NC1 NC1 NC1 NC1 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 GND I/O 19 I/O 20 VCC I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 GND I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 GND GOE0 GOE1 VCC I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 GND I/O 42 VCC I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 GND I/O 51 1NC 1NC 1NC 1NC I/O 124 I/O 125 GND I/O 126 I/O 127 I/O 128 VCC I/O 129 I/O 130 I/O 131 I/O 132 GND I/O 133 VCC I/O 134 I/O 135 I/O 136 I/O 137 GND I/O 138 I/O 139 VCC I/O 140 I/O 141 I/O 142 I/O 143 GND TMS TCK TDI VCC 2I/O 0 / TOE I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 GND I/O 7 VCC I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 GND 1NC 1NC 1NC 1NC 208-PQFP/5256V 1. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability. 24 Specifications ispLSI 5256V Part Number Description ispLSI 5256V – XXX X XXXX X Device Family Grade Blank = Commercial Device Number Package B272 = 272-BGA Q208 = 208-PQFP B208 = 208-BGA Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 70 = 70 MHz fmax Power L = Low 0212/5256 Ordering Information COMMERCIAL Family fmax tpd Ordering Number Package ispLSI 125 7.5 ispLSI 5256V-125LB272 272-Ball BGA ispLSI 5256V-125LQ208* 208-Pin PQFP ispLSI 5256V-125LB208* 208-Ball BGA ispLSI 5256V-100LB272 272-Ball BGA ispLSI 5256V-100LQ208* 208-Pin PQFP ispLSI 5256V-100LB208* 208-Ball BGA ispLSI 5256V-70LB272 272-Ball BGA ispLSI 5256V-70LQ208* 208-Pin PQFP ispLSI 5256V-70LB208* 208-Ball BGA ispLSI ispLSI 100 70 10 15 *Contact Factory for Availability 25