LT1469-2 Dual 200MHz, 30V/µs 16-Bit Accurate AV ≥ 2 Op Amp FEATURES DESCRIPTION n The LT®1469-2 is a dual, precision high speed operational amplifier with 16-bit accuracy, decompensated to be stable in a gain of 2 or greater. The combination of precision and AC performance makes the LT1469-2 the optimum choice for high accuracy applications such as DAC current-to-voltage conversion and ADC buffers. The initial accuracy and drift characteristics of the input offset voltage and inverting input bias current are tailored for inverting applications. n n n n n n n n n n n n n n Stable in Gain AV ≥ 2 (AV = –1) 200MHz Gain Bandwidth Product 30V/μs Slew Rate Settling Time: 800ns (150μV, 10V Step) Specified at ±5V and ±15V Supplies Maximum Input Offset Voltage: 125μV Low Distortion: –96.5dB for 100kHz, 10VP-P Maximum Input Offset Voltage Drift: 3μV/°C Maximum Inverting Input Bias Current: 10nA Minimum DC Gain: 300V/mV Minimum Output Swing into 2k: ±12.8V Input Noise Voltage: 5nV/√Hz Input Noise Current: 0.6pA/√Hz Total Input Noise Optimized for 1kΩ < RS < 20kΩ Available in 8-Lead Plastic SO and 12-Lead (4mm × 4mm) DFN Packages The 200MHz gain bandwidth ensures high open-loop gain at frequency for reducing distortion. In noninverting applications such as an ADC buffer, the low distortion and DC accuracy allow full 16-bit AC and DC performance. The high slew rate of the LT1469-2 improves large-signal performance in applications such as active filters and instrumentation amplifiers compared to other precision op amps. APPLICATIONS n n n n n n The LT1469-2 is specified on power supply voltages of ±5V and ±15V and from –40°C to 85°C. It is available in an 8-lead SOIC package and a space saving 4mm × 4mm leadless package. For a unity-gain stable op amp with same DC performance, see the LT1469 datasheet. Precision Instrumentation High Accuracy Data Acquisition Systems 16-Bit DAC Current-to-Voltage Converter ADC Buffer Low Distortion Active Filters Photodiode Amplifiers L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 16-Bit DAC I-to-V Converter Large-Signal Transient, AV = –1 DAC INPUTS 16 6k LTC®1597 – 1/2 LT1469-2 + VS = ±15V AV = –1 RF = RG = 2k CF = 22pF 10V 20pF 2k VOUT 2V/DIV 50pF 0V OPTIONAL NOISE FILTER OFFSET: VOS + IB (6kΩ) < 1LSB SETTLING TIME TO 150μV = 1.6μs SETTLING LIMITED BY 6k AND 20pF TO COMPENSATE DAC OUTPUT CAPACITANCE 14692 TA01a 200ns/DIV 14692 TA02 14692f 1 LT1469-2 ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (V + to V–).................................36V Input Current (Note 2)..........................................±10mA Output Short-Circuit Duration (Note 3) ............ Indefinite Operating Temperature Range (Note 4).... –40°C to 85°C Specified Temperature Range (Note 5) .... –40°C to 85°C Maximum Junction Temperature........................... 150°C Storage Temperature Range................... –65°C to 150°C PIN CONFIGURATION TOP VIEW OUT A 1 –IN A 2 +IN A 3 V– 4 N/C 5 N/C TOP VIEW 12 V+ A 13 B 6 11 OUT B OUT A 1 10 –IN B –IN A 2 8 V+ 7 OUT B 6 –IN B 5 +IN B A 9 +IN B +IN A 3 8 N/C V– 4 7 N/C B S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 190°C/W DF PACKAGE 12-LEAD (4mm × 4mm) PLASTIC DFN TJMAX = 150°C, θJA = 37°C/W EXPOSED PAD (PIN 13) IS GND, MUST BE CONNECTED TO V– ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT1469CS8-2#PBF LT1469CS8-2#TRPBF 14692 8-Lead Plastic Small Outline 0°C to 70°C LT1469IS8-2#PBF LT1469IS8-2#TRPBF 14692 8-Lead Plastic Small Outline –40°C to 85°C LT1469ACDF-2#PBF LT1469ACDF-2#TRPBF 14692 12-Lead (4mm × 4mm) Plastic DFN 0°C to 70°C LT1469AIDF-2#PBF LT1469AIDF-2#TRPBF 14692 12-Lead (4mm × 4mm) Plastic DFN –40°C to 85°C LT1469CDF-2#PBF LT1469CDF-2#TRPBF 14692 12-Lead (4mm × 4mm) Plastic DFN 0°C to 70°C LT1469IDF-2#PBF LT1469IDF-2#TRPBF 14692 12-Lead (4mm × 4mm) Plastic DFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS TYP MAX UNITS VOS Input Offset Voltage S8 Package ±15V ±5V 50 50 125 200 μV μV LT1469A, DF Package ±15V ±5V 50 50 125 200 μV μV LT1469, DF Package ±15V ±5V 100 150 225 300 μV μV ±5V to ±15V 13 ±50 nA IOS Input Offset Current VSUPPLY MIN 14692f 2 LT1469-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCM = 0V unless otherwise noted. SYMBOL PARAMETER IB – Inverting Input Bias Current IB + Noninverting Input Bias Current CONDITIONS VSUPPLY MIN TYP MAX UNITS ±5V to ±15V 3 ±10 nA ±40 ±5V to ±15V –10 Input Noise Voltage 0.1Hz to 10Hz ±5V to ±15V 0.3 en Input Noise Voltage Density f = 10kHz ±5V to ±15V 5 nV/√Hz in Input Noise Current Density f = 10kHz ±5V to ±15V RIN Input Resistance Common Mode, VCM = ±12.5V Differential CIN Input Capacitance VCM Input Voltage Range (Positive) Guaranteed by CMRR ±15V ±5V Input Voltage Range (Negative) Guaranteed by CMRR ±15V ±5V Common Mode Rejection Ratio VCM = ±12.5V VCM = ±2.5V ±15V ±5V Minimum Supply Voltage Guaranteed by PSRR CMRR ±15V ±15V 100 50 ±15V 12.5 2.5 0.6 pA/√Hz 240 150 MΩ kΩ 4 pF 13.5 3.6 V V –14.3 –4.4 96 96 nA μVP-P –12.5 –2.5 110 112 ±2.5 V V dB dB ±4.5 V PSRR Power Supply Rejection Ratio VS = ±4.5V to ±15V 100 112 dB AVOL Large-Signal Voltage Gain VOUT = ±12.5V, RL = 10k VOUT = ±12.5V, RL = 2k VOUT = ±2.5V, RL = 10k VOUT = ±2.5V, RL = 2k ±15V ±15V ±5V ±5V 300 300 200 200 2000 2000 8000 8000 V/mV V/mV V/mV V/mV VOUT Maximum Output Swing RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive ±15V ±15V ±5V ±5V ±13.0 ±12.8 ±3.0 ±2.8 ±13.6 ±13.5 ±3.7 ±3.6 V V V V IOUT Maximum Output Current VOUT = ±12.5V, 1mV Overdrive VOUT = ±2.5V, 1mV Overdrive ±15V ±5V ±15 ±15 ±22 ±22 mA mA ISC Output Short-Circuit Current VOUT = 0V, 0.2V Overdrive (Note 3) ±15V ±25 ±40 mA SR Slew Rate RL = 2k (Note 6) ±15V ±5V 20 15 30 22 V/μs V/μs FPBW Full-Power Bandwidth 10V Peak, (Note 7) 3V Peak, (Note 7) ±15V ±5V 475 1160 kHz kHz GBW Gain Bandwidth Product f = 100kHz, RL = 2k ±15V ±5V 200 190 MHz MHz tS Settling Time 10V Step, 0.01%, AV = –1 10V Step, 150μV, AV = –1 ±15V ±15V 650 800 ns ns ROUT Output Resistance AV = –1, f = 100kHz ±15V Channel Separation VOUT = ±12.5V, RL = 2k VOUT = ±2.5V, RL = 2k ±15V ±5V IS Supply Current Per Amplifier ±15V ±5V 4.1 3.8 5.2 5 mA mA ΔVOS Input Offset Voltage Match ±15V ±5V 30 50 225 350 μV μV ΔIB– Inverting Input Bias Current Match ±5V to ±15V 2 18 nA ΔIB+ Noninverting Input Bias Current Match ±5V to ±15V 5 78 nA ΔCMRR Common Mode Rejection Match VCM = ±12.5V (Note 9) VCM = ±2.5V (Note 9) ΔPSRR Power Supply Rejection Match VS = ±4.5V to ±15V (Note 9) ±15V ±5V 140 130 100 100 0.02 Ω 130 130 dB dB 93 93 113 115 dB dB 97 115 dB 14692f 3 LT1469-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, 0°C ≤ TA ≤ 70°C. VCM = 0V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MAX UNITS VOS Input Offset Voltage S8 Package ±15V ±5V ● ● 350 350 μV μV LT1469A, DF Package ±15V ±5V ● ● 225 275 μV μV LT1469, DF Package ±15V ±5V ● ● 450 450 μV μV (Note 8) ±15V ±5V ● ● ±5V to ±15V ● ±5V to ±15V ● ±5V to ±15V ● ΔVOS/ΔT Input Offset Voltage Drift IOS Input Offset Current ΔIOS/ΔT Input Offset Current Drift IB – Inverting Input Bias Current MIN TYP 1 1 5 3 ±80 60 μV/°C μV/°C nA pA/°C ±20 nA ±5V to ±15V ● ±5V to ±15V ● Guaranteed by CMRR ±15V ±5V ● ● Input Voltage Range (Negative) Guaranteed by CMRR ±15V ±5V ● ● Common Mode Rejection Ratio VCM = ±12.5V ±15V ● 94 dB VCM = ±2.5V ±5V ● 94 dB ΔIB–/ΔT Inverting Input Bias Current Drift IB + Noninverting Input Bias Current VCM Input Voltage Range (Positive) CMRR (Note 8) VSUPPLY (Note 8) 40 pA/°C ±60 12.5 2.5 nA V V –12.5 –2.5 V V Minimum Supply Voltage Guaranteed by PSRR ● PSRR Power Supply Rejection Ratio VS = ±4.5V to ±15V ● 95 dB AVOL Large-Signal Voltage Gain VOUT = ±12.5V, RL = 10k VOUT = ±12.5V, RL = 2k VOUT = ±2.5V, RL = 10k VOUT = ±2.5V, RL = 2k ±15V ±15V ±5V ±5V ● ● ● ● 100 100 100 100 V/mV V/mV V/mV V/mV VOUT Maximum Output Swing RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive ±15V ±15V ±5V ±5V ● ● ● ● ±12.9 ±12.7 ±2.9 ±2.7 V V V V IOUT Maximum Output Current VOUT = ±12.5V, 1mV Overdrive VOUT = ±2.5V, 1mV Overdrive ±15V ±5V ● ● ±12.5 ±12.5 mA mA ISC Output Short-Circuit Current VOUT = 0V, 0.2V Overdrive (Note 3) ±15V ● ±17 mA SR Slew Rate RL = 2k (Note 6) ±15V ±5V ● ● 18 13 V/μs V/μs GBW Gain Bandwidth Product f = 100kHz, RL = 2k ±15V ±5V ● ● 130 120 Channel Separation VOUT = ±12.5V, RL = 2k VOUT = ±2.5V, RL = 2k ±15V ±5V ● ● 98 98 IS Supply Current Per Amplifier ±15V ±5V ● ΔVOS Input Offset Voltage Match ±15V ±5V ● ● ± 4.5 ● 200 190 V MHz MHz dB dB 6.5 6.3 mA mA 600 600 μV μV ΔIB – Inverting Input Bias Current Match ±5V to ±15V ● 38 nA ΔIB + Noninverting Input Bias Current Match ±5V to ±15V ● 118 nA ΔCMRR Common Mode Rejection Match VCM = ±12.5V (Note 9) VCM = ±2.5V (Note 9) ±15V ±5V ● ● 91 91 dB dB ΔPSRR Power Supply Rejection Match VS = ±4.5V to ±15V (Note 9) ● 92 dB 14692f 4 LT1469-2 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, –40°C ≤ TA ≤ 85°C, VCM = 0V unless otherwise noted. (Note 5) SYMBOL PARAMETER CONDITIONS MAX UNITS VOS Input Offset Voltage S8 Package ±15V ±5V ● ● 500 500 μV μV LT1469A, DF Package ±15V ±5V ● ● 300 350 μV μV LT1469, DF Package ±15V ±5V ● ● 600 600 μV μV (Note 8) ±15V ±5V ● ● ±5V to ±15V ● ±5V to ±15V ● ±5V to ±15V ● ΔVOS/ΔT Input Offset Voltage Drift IOS Input Offset Current ΔIOS/ΔT Input Offset Current Drift IB – Inverting Input Bias Current ΔIB–/ΔT Inverting Input Bias Current Drift IB + Noninverting Input Bias Current VCM Input Voltage Range (Positive) CMRR (Note 8) VSUPPLY MIN ±5V to ±15V ● ±5V to ±15V ● Guaranteed by CMRR ±15V ±5V ● ● Input Voltage Range (Negative) Guaranteed by CMRR ±15V ±5V ● ● Common Mode Rejection Ratio VCM = ±12.5V VCM = ±2.5V ±15V ±5V ● ● (Note 8) TYP 1 1 6 5 ±120 120 μV/°C μV/°C nA pA/°C ±40 80 nA pA/°C ±80 12.5 2.5 nA V V 92 92 –12.5 –2.5 V V ±4.5 dB dB Minimum Supply Voltage Guaranteed by PSRR ● PSRR Power Supply Rejection Ratio VS = ±4.5V to ±15V ● 93 dB AVOL Large-Signal Voltage Gain VOUT = ±12,5V, RL = 10k VOUT = ±12.5V, RL = 2k VOUT = ±2.5V, RL = 10k VOUT = ±2.5V, RL = 2k ±15V ±15V ±5V ±5V ● ● ● ● 75 75 75 75 V/mV V/mV V/mV V/mV VOUT Maximum Output Swing RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive RL = 10k, 1mV Overdrive RL = 2k, 1mV Overdrive ±15V ±15V ±5V ±5V ● ● ● ● ±12.8 ±12.6 ±2.8 ±2.6 IOUT Maximum Output Current VOUT = ±12.5V, 1mV Overdrive VOUT = ±2.5V, 1mV Overdrive ±15V ±5V ● ● ±7 ±7 mA mA ISC Output Short-Circuit Current VOUT = 0V, 0.2V Overdrive (Note 3) ±15V ● ±12 mA SR Slew Rate RL = 2k (Note 6) ±15V ±5V ● ● 15 11 V/μs V/μs GBW Gain Bandwidth Product f = 100kHz, RL = 2k ±15V ±5V ● ● 110 100 Channel Separation VOUT = ±12.5V, RL = 2k VOUT = ±2.5V, RL = 2k ±15V ±5V ● ● 96 96 IS Supply Current Per Amplifier ±15V ±5V ● ● 7 6.8 mA mA ΔVOS Input Offset Voltage Match ±15V ±5V ● ● 800 800 μV μV V V V V V 200 190 MHz MHz dB dB ΔIB – Inverting Input Bias Current Match ±5V to ±15V ● 78 nA ΔIB + Noninverting Input Bias Current Match ±5V to ±15V ● 158 nA ΔCMRR Common Mode Rejection Match VCM = ±12.5V (Note 9) VCM = ±2.5V (Note 9) ±15V ±5V ● ● 89 89 dB dB ΔPSRR Power Supply Rejection Match VS = ±4.5V to ±15V (Note 9) ● 90 dB 14692f 5 LT1469-2 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The inputs are protected by back-to-back diodes and two 100Ω series resistors. If the differential input voltage exceeds 0.7V, the input current should be limited to less than 10mA. Input voltages outside the supplies will be clamped by ESD protection devices and input currents should also be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefinitely. Note 4: The LT1469C-2 and LT1469I-2 are guaranteed functional over the operating temperature range of – 40°C to 85°C. Note 5: The LT1469C-2 is guaranteed to meet specified performance from 0°C to 70°C and is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1469I-2 is guaranteed to meet specified performance from –40°C to 85°C. Note 6: Slew rate is measured between ±8V on the output with ±12V swing for ±15V supplies and ±2V on the output with ±3V swing for ±5V supplies. Tested in AV = –10 Note 7: Full-power bandwidth is calculated from the slew rate. FPBW = SR/2πVP. Note 8: This parameter is not 100% tested. Note 9: ΔCMRR and ΔPSRR are defined as follows: 1) CMRR and PSRR are measured in μV/V on each amplifier; 2) the difference between the two sides is calculated in μV/V; 3) the result is converted to dB. TYPICAL PERFORMANCE CHARACTERISTICS Distribution of Input Offset Voltage Distribution of Inverting Input Bias Current 50 40 6 VS = ±15V TA = 25°C 30 20 10 0 75 125 –175 –125 –75 –25 25 INPUT OFFSET VOLTAGE (μV) 85°C 5 30 SUPPLY CURRENT (mA) 40 PERCENTAGE OF UNITS (%) PERCENTAGE OF UNITS (%) VS = ±15V TA = 25°C 20 10 0 –10 –7.5 –5 –2.5 0 2.5 5 7.5 INVERTING INPUT BIAS CURRENT (nA) 175 10 0.1 100 1k FREQUENCY (Hz) 10k 0.01 100k 100 VS = ±15V TA = 25°C f = 10kHz TOTAL NOISE 10 RESISTOR NOISE ONLY 1 RS + – 0.1 TIME (1s/DIV) 10 14692 G05 14692 G04 20 14692 G03 TOTAL NOISE VOLTAGE (nV/√Hz) en 10 5 10 15 SUPPLY VOLTAGE (±V) 0 Total Noise vs Unmatched Source Resistance VOLTAGE NOISE (100nV/DIV) 1 10 1 1 10 VS = ±15V TA = 25°C INPUT CURRENT NOISE (pA/√Hz) VS = ±15V TA = 25°C AV = 101 RS = 100k FOR in 1 –40°C 0.1Hz to 10Hz Voltage Noise 1000 in 3 14692 G02 Input Noise Spectral Density 100 25°C 4 2 14692 G01 INPUT VOLTAGE NOISE (nV/√Hz) Supply Current vs Supply Voltage and Temperature 1k 10k 100 SOURCE RESISTANCE, RS (Ω) 100k 14692 G06 14692f 6 LT1469-2 TYPICAL PERFORMANCE CHARACTERISTICS Input Bias Current vs Temperature Input Bias Current vs Input Common Mode Voltage 30 INPUT BIAS CURRENT (nA) 10 IB– 0 –10 IB+ –20 –30 VS = ±15V TA = 25°C 40 20 IB– 0 IB+ –20 –40 –60 50 25 75 0 TEMPERATURE (°C) 100 –80 –15 125 –1.0 OUTPUT VOLTAGE SWING (V) –5 5 10 0 INPUT COMMON MODE VOLTAGE (V) –2 –3 –4 4 3 2 RL = 2k 1 RL = 10k 10 15 5 SUPPLY VOLTAGE (±V) 0 –40°C –2.0 –2.5 2.5 –40°C 2.0 1.5 25°C 85°C 1.0 20 V– 0.5 –20 –15 –10 –5 0 10 5 OUTPUT CURRENT (mA) TA = 25°C 15 135 50 OPEN-LOOP GAIN (dB) 120 115 100 1k LOAD RESISTANCE (Ω) 10k 14692 G13 SINK 40 35 30 25 20 15 –25 50 25 0 75 TEMPERATURE (°C) 100 14692 G12 RL = 2k 0 140 130 120 VS = ±15V 110 90 –50 –25 125 Warm-Up Drift vs Time 100 110 SOURCE 45 10 VS = ±5V VS = ±15V 18 VS = ±15V VIN = ±0.2V 55 10 –50 20 150 125 15 14692 G11 160 130 9 12 6 SUPPLY VOLTAGE (±V) 14692 G09 Open-Loop Gain vs Temperature VS = ±5V 3 0 Output Short-Circuit Current vs Temperature 85°C 25°C –1.5 Open-Loop Gain vs Resistive Load OPEN-LOOP GAIN (dB) 1.0 60 VS = ±15V 14692 G10 10 1.5 15 OFFSET VOLTAGE DRIFT (μV) OUTPUT VOLTAGE SWING (V) V+ –0.5 RL = 2k TA = 25°C 2.0 Output Voltage Swing vs Load Current RL = 10k V– –2.0 14692 G08 Output Voltage Swing vs Supply Voltage –1 –1.5 V– –10 14692 G07 V+ –1.0 0.5 OUTPUT SHORT-CIRCUIT CURRENT (mA) –40 –50 –25 TA = 25°C ΔVOS < 100μV –0.5 COMMON MODE RANGE (V) 60 20 INPUT BIAS CURRENT (nA) V+ 80 VS = ±15V 140 Input Common Mode Range vs Supply Voltage S0-8 ±5V –10 –20 –30 –40 –50 –60 S0-8 ±15V –70 50 25 75 0 TEMPERATURE (°C) 100 125 14692 G14 –80 0 20 40 60 80 100 120 TIME AFTER POWER UP (s) 140 14692 G15 14692f 7 LT1469-2 TYPICAL PERFORMANCE CHARACTERISTICS Open-Loop Gain and Phase vs Frequency Gain vs Frequency, AV = –1 100 60 80 PHASE 60 GAIN (dB) 40 GAIN 30 20 20 0 TA = 25°C 10 AV = –1 RF = RG = 5.1k 0 CF = 5pF RL = 2k –10 100k 10k 1M 10M FREQUENCY (Hz) PHASE (DEG) 40 GAIN (dB) 50 TA = 25°C 5 AV = –1 4 RF = RG = 2k CF = 6.8pF 3 RL = 500Ω 2 CL = 47pF CL = 22pF 1 0 NO CL –1 –2 –20 –5 100k 0.1 AV = –1 1M 10M FREQUENCY (Hz) 100M 0.001 10k 15 10 1000 1M 10M FREQUENCY (Hz) 10 10 9 8 8 6 7 4 6 AV = –1 5 4 3 V = ±5V 2 S TA = 25°C 1 RL = 2k THD<1% 0 1 10 100 FREQUENCY (kHz) 14692 G19 2 VS = ±15V TA = 25°C RF = RG = 2.5k RL = 2.5k INTO DIODES CF = 8pF 150μV 0.01% 0.1% 0 –2 –4 –6 –8 –10 1000 2000 0.1% 150μV 0.01% 0 100 200 300 400 500 600 700 800 900 1000 SETTLING TIME (ns) 14692 G21 14692 G20 Settling Time vs Output Step, AV = 2 Large-Signal Transient, AV = –1 Small-Signal Transient, AV = –1 10 VS = ±15V 8 VS = ±15V AV = –1 RF = RG = 2k CL = 22pF 10V 0.01% 6 100M Settling Time vs Output Step, AV = –1 OUTPUT STEP (V) OUTPUT VOLTAGE SWING (VP-P) AV = –1 20 100k 14692 G18 Undistorted Output Swing vs Frequency, VS = ±5V 25 OUTPUT VOLTAGE SWING (VP-P) AV = 10 14692 G17 30 OUTPUT STEP (V) AV = 100 1 –4 –60 100M Undistorted Output Swing vs Frequency, VS = ±15V 10 100 FREQUENCY (kHz) 10 0.01 –3 –40 VS = ±15V TA = 25°C CL = 100pF 14692 G16 VS = ±15V 5 TA = 25°C RL = 2k THD<1% 0 1 Output Impedance vs Frequency 100 6 OUTPUT IMPEDANCE (Ω) 70 4 2 2V/DIV 20mV/DIV 0 –2 –4 –6 –8 –10 0.01% VS = ±15V TA = 25°C RF = RG = 1k RL = 2.5k INTO DIODES CF = 22pF RS = 511Ω//30pF 0V 200ns/DIV 50ns/DIV 14692 G23 14692 G24 0 100 200 300 400 500 600 700 800 900 1000 SETTLING TIME (ns) 14692 G22 14692f 8 LT1469-2 APPLICATIONS INFORMATION Gain of 2 Stable The LT1469-2 is a decompensated version of the LT1469. The DC precision performance is identical, but the internal compensation capacitors have been reduced to a point where the op amp needs a gain of 2 or greater in order to be stable. In general, for applications where the gain around the op amp is ≥ 2, the decompensated version should be used, because it will give the best AC performance. In applications where the gain is <2, the unity-gain stable version should be used. The appropriate way to define the ‘gain’ is as the inverse of the feedback ratio from output to differential input, including all relevant parasitics. Moreover, as with all feedback loops, the stability of the loop depends on the value of that feedback ratio at frequencies where the total loop-gain would cross unity. Therefore, it is possible to have circuits in which the gain at DC is lower than the gain at high frequency, and these circuits can be stable even with a non unity-gain stable op amp. An example is many current-output DAC buffer applications. Layout and Passive Components The LT1469 requires attention to detail in board layout in order to maximize DC and AC performance. For best AC results (for example, fast settling time) use a ground plane, short lead lengths and RF quality bypass capacitors (0.01μF to 0.1μF) in parallel with low ESR bypass capacitors (1μF to 10μF tantalum). For best DC performance, use “star” grounding techniques, equalize input trace lengths and minimize leakage (e.g., 1.5GΩ of leakage between an input and a 15V supply will generate 10nA—equal to the maximum IB – specification). Board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs: for inverting configurations tie the ring to ground, in noninverting connections tie the ring to the inverting input (note the input capacitance will increase which may require a compensating capacitor as discussed below). Microvolt level error voltages can also be generated in the external circuitry. Thermocouple effects caused by temperature gradients across dissimilar metals at the contacts to the inputs can exceed the inherent drift of the amplifier. Air currents over device leads should be minimized, package leads should be short and the two input leads should be as close together as possible and maintained at the same temperature. The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole which can cause peaking or even oscillations. A feedback capacitor of value CF = RG • CIN/RF may be used to cancel the input pole and optimize dynamic performance. For applications where the DC noise gain is one, and a large feedback resistor is used, CF should be less than or equal to one half of CIN. An example would be a DAC I-to-V converter as shown on the front page of the data sheet where the DAC can have many tens of picofarads of output capacitance. V+ CF +IN R1 100Ω Q1 R1 Q2 100Ω –IN RF RG – CIN 1/2 LT1469-2 VIN VOUT + 14692 F01 Figure 1. Nulling Input Capacitance V– 14692 F02 Figure 2. Input Stage Protection 14692f 9 LT1469-2 APPLICATIONS INFORMATION Input Considerations Each input of the LT1469 is protected with a 100Ω series resistor and back-to-back diodes across the bases of the input devices. If large differential input voltages are anticipated, limit the input current to less than 10mA with an external series resistor. Each input also has two ESD clamp diodes—one to each supply. If an input is driven beyond the supply, limit the current with an external resistor to less than 10mA. The LT1469 employs bias current cancellation at the inputs. The inverting input current is trimmed at zero common mode voltage to minimize errors in inverting applications such as I-to-V converters. The noninverting input current is not trimmed and has a wider variation and therefore a larger maximum value. As the input offset current can be greater than either input current, the use of balanced source resistance is NOT recommended as it actually degrades DC accuracy and also increases noise. The input bias currents vary with common mode voltage. The cancellation circuitry was not designed to track this common mode voltage because the settling time would have been adversely affected. The LT1469 inputs can be driven to the negative supply and to within 0.5V of the positive supply without phase reversal. As the input moves closer than 0.5V to the positive supply, the output reverses phase. Total Input Noise The total input noise of the LT1469 is optimized for a source resistance between 1k and 20k. Within this range, the total input noise is dominated by the noise of the source resistance itself. When the source resistance is below 1k, voltage noise of the amplifier dominates. When the source resistance is above 20k, the input noise current is the dominant contributor. SIMPLIFIED SCHEMATIC V+ I1 I5 I2 Q10 Q8 +IN Q1 Q2 –IN Q5 Q6 Q7 Q3 I3 I4 OUT Q9 Q4 BIAS Q11 C I6 V– 14692 SS 14692f 10 LT1469-2 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN 7 6 5 .160 ±.005 .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) .030 ±.005 TYP 1 RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) 2 3 4 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) 0°– 8° TYP .016 – .050 (0.406 – 1.270) .050 (1.270) BSC .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) NOTE: 1. DIMENSIONS IN SO8 0303 DF Package 12-Lead Plastic DFN (4mm × 4mm) (Reference LTC DWG # 05-08-1773 Rev Ø) 4.00 ± 0.10 (4 SIDES) 2.50 REF 2.50 REF 7 12 0.70 ±0.05 0.40 ± 0.10 3.38 ±0.10 3.38 ±0.05 4.50 ± 0.05 3.10 ± 0.05 2.65 ± 0.10 2.65 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 0.200 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (NOTE 6) 6 R = 0.115 TYP 0.75 ± 0.05 1 (DF12) DFN 0806 REV Ø 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 0.00 – 0.05 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 14692f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LT1469-2 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1167 Precision Instrumentation Amplifier Single Resistor Gain Set, 0.04% Max Gain Error, 10ppm Max Gain Nonlinearity LT1468 Single 90MHz, 22V/μs, 16-Bit Accurate Op Amp 75μV Max VOS, Single Version of LT1469 LTC1595/LTC1596 16-Bit Serial Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade LTC1597 16-Bit Parallel Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors LTC1604 16-Bit, 333ksps Sampling ADC ± 2.5V Input, SINAD = 90dB, THD = –100dB LTC1605 Single 5V, 16-Bit, 100ksps Sampling ADC Low Power, ±10V Inputs, Parallel/Byte Interface 14692f 12 Linear Technology Corporation LT 0808 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008