RMLA3565C Wideband Low Noise MMIC Amplifier General Description Features The Fairchild Semiconductor’s RMLA3565C is a single bias wideband low noise MMIC amplifier designed for the 3.5– 6.5 GHz frequency range. The MMIC requires no external matching circuits or external gate bias supply. This device uses our advanced 0.25µm PHEMT process to provide low noise, high linearity, and low current. • 20dB Gain typical • 1.2dB Noise Figure Typical 5.0–6.5GHz • 4.0V Single Positive Bias • Small Outline Metal Base Quad Plastic Package • Internal 50Ω Matching Device Absolute Ratings Symbol Vdd PIN (CW) Idd Tcase Tstorage Tsolder Rjc Parameter Positive Drain DC Voltage RF Input Power (from 50Ω source) Drain Current Case Operating Temperature Storage Temperature Range Soldering Temperature Thermal Resistance (Channel to Case) Ratings 6.5 0 130 -30 to 85 -40 to 110 220 8 Units V dBm mA °C °C °C °C/W Electrical Characteristics (50Ω System, Vdd = 4V, T = +25°C) Parameter Frequency Range Gain (Small Signal)1, 2 Gain Variation vs Temp Noise Figure2 3.5–5 GHz 5–6.5 GHz Power Out, P-1dB OIP3 @ 5.5 GHz, 0 dBm per tone Pout Idd Vdd Input/Output Return Loss Min 3.5 17.0 8.0 3.0 Typ Max 6.5 Units GHz dB dB/C° 2.2 1.6 dB dB dBm dBm mA V dB 20 0.013 1.5 1.2 13 25.5 80 4.0 10.0 90 6.0 Notes: 1. Pin = -20, Vd = 4.0V, Frequency 3.5–6.5Ghz 2. Data de-embedded from fixture loss. ©2004 Fairchild Semiconductor Corporation RMLA3565C Rev. C RMLA3565C May 2004 CAUTION: THIS IS AN ESD SENSITIVE DEVICE The following briefly describes a procedure for evaluating the high efficiency PHEMT amplifier packaged in a surface mount package. It may be noted that the chip is a fully monolithic single ended two stage amplifier for 3.5 to 6.5 GHz applications. Figure 1 shows the functional block diagram of the packaged product. Test Fixture Figure 2 shows the outline and pin-out descriptions for the packaged device. A typical test fixture schematic showing external bias components is shown in Figure 3. Figure 4 shows typical layout of an evaluation board corresponding to the schematic diagram. Typical performance of the test fixture is shown in the performance data section. The following should be noted: (1) Package pin designations are shown in Figure 2. (2) Vd is the drain voltage (positive) applied at the pins of the package. (3) Vdd is the positive supply voltage at the evaluation board terminal. GROUND Pin# 5 GROUND Pin# 1, 3, 4, 6, 9, 10, 11, 13 MMIC CHIP GROUND Pin# 7 RF IN Pin# 8 RF OUT Pin# 2 Vd Pin# 12 Figure 1. Functional Block Diagram Top View Bottom View 0.200 SQ. 6 5 4 7 0.030 4 6 0.015 3 8 2 9 5 3 7 2 8 1 9 0.020 1 0.011 10 11 12 12 11 10 Plastic Lid 0.010 0.075 MAX 0.230 0.246 0.282 Side Section Dimensions in inches 0.041 Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 GND RF Out GND GND GND GND GND RF In GND GND GND Vd GND (Package Base) Figure 2. Package Outline Dimensions ©2004 Fairchild Semiconductor Corporation RMLA3565C Rev. C RMLA3565C Application Information RF Out J2 RMLA3565C-58 GND P2 C1 (OPT) RMLA3565C RF In J1 C2 (OPT) Vdd P1 C3 Figure 3. Schematic for a Typical Test Evaluation Board (RMLA3565C-TB) Pin 5 must be grounded U1 RF In J1 RF Out J2 Fairchild C1 & C2 (OPT) C3 GROUND (GND) P2 Vdd P1 Figure 4. Layout and Assembly of Test Evaluation Board (RMLA3565C-TB) Test Procedure for the evaluation board (RMLA3565C-TB) The following sequence of procedure must be followed to properly test the power amplifier: Step 4: After the bias condition is established, RF input signal may now be applied. Step 1: Turn off RF input power. Step 5: Follow turn-off sequence of: Step 2: Use GND terminal of the evaluation board to connect DC supply grounds and Pin 5. (i) Turn off RF input power. (ii) Turn down and off Vdd. Step 3: Apply drain supply voltage of +4.0V to evaluation board terminal Vdd. ©2004 Fairchild Semiconductor Corporation RMLA3565C Rev. C RMLA3565C Parts List For Test Evaluation Board (RMLA3565C-TB) Part Value 330 pF 1000 pF 4.75 µF RMLA3565C Terminals SMA Connectors RO4003 (Rogers) C1 C2 C3 U1 P1, P2 J1, J2 Board Size (EIA) .04” x .02” .04” x .02” .14” x .11” .28” x .28” x .07” Vendor(s) AVX, Murata, Novacap AVX, Murata, Novacap Sprague, ATC, AVX, Murata Fairchild Samtec E.F. Johnson Fairchild 1.99 x 1.50 x .032 Typical Characteristics RMLA3565CS-Parameters vs. Frequency 4V 80mA RMLA3565C Pout vs Pin 4V 80mA 20 20 15 S11 (dB) S21 (dB) S22 (dB) 0 Pout (dBm) Sij (dB) 10 -10 -20 -30 2 10 3.5 GHz 4.5 GHz 5.5 GHz 6.5 GHz 5 0 -5 0 1 2 3 4 5 6 7 Frequency (GHz) 8 9 -10 -30 10 RMLA3565C Noise Figure vs. Frequency 4V 80mA -25 -20 -15 Pin (dBm) -10 -5 0 RMLA3565C OIP3 vs Single Tone Pout Tone Sep = 1MHz F = 5.5GHz 4V 80mA 27 26 1.8 25 24 OIP3 (dBm) NF (dB) 1.6 1.4 1.2 23 22 21 20 19 1 18 0.8 3.5 4 4.5 5 Frequency (GHz) 5.5 6 17 -4 -2 0 2 4 6 1TPout (dBm) 8 10 12 RMLA3565C Idd vs. Pin Vdd = 4V 86 85 84 Idd (mA) 83 82 81 80 79 78 77 -25 ©2004 Fairchild Semiconductor Corporation -20 -15 Pin (dBm) -10 -5 RMLA3565C Rev. C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I11