SY89295U 2.5V/3.3V 1.5GHz Precision LVPECL Programmable Delay General Description The SY89295U is a programmable delay line that delays the input signal using a digital control signal. The delay can vary from 3.2ns to 14.8ns in 10ps increments. In addition, the input signal is LVPECL, uses either a 2.5V ±5% or 3.3V ±10% power supply, and is guaranteed over the full industrial temperature range (–40°C to +85°C). The delay varies in discrete steps based on a control word. The control word is 10-bits long and controls the delay in 10ps increments. The eleventh bit is D[10] and is used to simultaneously cascade the SY89295U which allows for a larger delay range. In addition, the input pins IN and /IN default to an equivalent low state when left floating. Further, for maximum flexibility, the control register interface accepts CMOS or TTL level signals. For applications that require an analog delay input, see the SY89296L which is a programmable delay chip with fine tune control. The SY89295U and SY89296U are part of ® Micrel’s high-speed, Precision Edge product line. Data sheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Precision Edge® Features • Precision LVPECL programmable delay line • Guaranteed AC performance over temperature and voltage: − >1.5GHz fMAX − <160ps rise/fall times • Low-jitter design: − <10psPP total jitter − <2psRMS cycle-to-cycle jitter − <1psRMS random jitter • Programmable delay range: 3.2ns to 14.8ns in 10ps increments • Increased monotonicity over the MIC100EP195 • ±10ps INL • VBB output reference voltage • • • • Parallel inputs accepts LVPECL or CMOS/LVTTL Low voltage operation: 2.5V ±5% and 3.3V ±10% Industrial –40°C to +85°C temperature range Available in 32-pin (5mm × 5mm) MLF® and 32-pin TQFP packages Applications • Clock de-skewing • Timing adjustments • Aperture centering Precision Edge is a registered trademark of Micrel, Inc MicroLeadFrame and MLF are registered trademarks of Amkor, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com March 2011 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Ordering Information(1) Part Number Package Type Operating Range Package Marking Lead Finish SY89295UMI MLF-32 Industrial SY89295U Sn-Pb MLF-32 Industrial SY89295U Sn-Pb (2) SY89295UMI TR SY89295UTI T32-1 Industrial SY89295U Sn-Pb SY89295UTITR(2) T32-1 Industrial SY89295U Sn-Pb SY89295UMG(3) MLF-32 Industrial SY89295U with Pb-Free bar-line indicator Pb-Free NiPd Au SY89295UMGTR(2, 3) MLF-32 Industrial SY89295U with Pb-Free bar-line indicator Pb-Free NiPd Au SY89295UTG(3) T32-1 Industrial SY89295U with Pb-Free bar-line indicator Pb-Free NiPd Au SY89295UTGTR(2, 3) T32-1 Industrial SY89295U with Pb-Free bar-line indicator Pb-Free NiPd Au Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. Pin Configuration 32-Pin MLF® (MLF-32) March 2011 32-Pin TQFP (T32-1) 2 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Truth Tables Input/Output Inputs IN 0 1 Digital Control Latch LEN 0 1 Input Enable /EN 0 1 March 2011 Outputs /IN 1 0 OUT 0 1 /OUT 1 0 Latch Action Pass Through D[10:0] Latched Q, /Q IN, /IN Delayed Latched D[10:0] 3 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Functional Block Diagram SY89295U Block Diagram March 2011 4 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Pin Description Pin Number Pin Name Pin Function CMOS, ECL, or TTL Control Bits: These control signals adjust the delay from IN to Q. See “AC Electrical Characteristics” for delay values. In addition, see “Interface Applications” section which illustrates the proper interfacing techniques for different logic standards. D[9:0] contains pull-downs and defaults LOW when left floating. D0 (LSB), and D9 (MSB). See “Typical Operating Characteristics” for delay information. 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 D[9:0] 3 D10 CMOS, ECL, or TTL Control Bit: This bit is used to cascade devices for an extended delay range. In addition, it drives CASCADE, and /CASCADE. Further, D[10] contains a pull-down and defaults LOW when left floating. 4, 5 IN, /IN LVPECL/ECL Signal Input: Input signal to be delayed. IN contains a 75ký pull-down and will default to a logic LOW if left floating. 6 (1) VBB Reference Voltage Output: When using a single-ended input signal source to IN or /IN, connect the unused input of the differential pair to this pin. This pin can also be used to re-bias AC-coupled inputs to IN and /IN. When used, de-couple to VCC using a 0.01µF capacitor, otherwise leave floating if not used. Maximum sink/source is ±0.5mA. Reference Voltage Output: Connect this pin to VCF when D[9:0], and D[10] is ECL.. 7 VEF Logic Standard VCF Connects to: LVPECL VEF,(1) CMOS No Connect TTL 1.5V Source 8 VCF Reference Voltage Input: The voltage driven on VCF sets the logic transition threshold for D[9:0], and D[10]. 9, 24, 28 GND, Exposed Pad(2) ® Negative Supply: For MLF package, exposed pad must be connected to a ground plane that is the same potential as the ground pin. 10 LEN ECL Control Input: When HIGH latches the D[9:0] and D[10] bits. When LOW, the D[9:0] and D[10] latches are transparent. 11 SETMIN ECL Control Input: When HIGH, D[9:0] registers are reset. When LOW, the delay is set by SETMAX or D[9:0] and D[10]. SETMIN contains a pull-down and defaults LOW when left floating. 12 SETMAX ECL Control Input: When SETMAX is set HIGH and SETMIN is set LOW, D[9:0] = 1111111111. When SETMAX is LOW, the delay is set by SETMIN or D[9:0] and D[10]. SETMAX contains a pull-down and defaults LOW when left floating. 13, 18, 19, 22 VCC 14, 15 /Cascade, Cascade 16 /EN 20, 21 /Q, Q 17 NC Positive Power Supply: Bypass with 0.1µF and 0.01µF low ESR capacitors. LVPECL Differential Output: The outputs are used when cascading two or more SY89295U to extend the delay range. LVPECL Single-Ended Control Input: When LOW, Q is delayed from IN. When HIGH, Q is a differential LOW. /EN contains a pull-down and defaults LOW when left floating. LVPECL Differential Output: Q is a delayed version of IN. Always terminate the output with 50Ω to VCC – 2V. See “Output Interface Applications” section. No Connect. Notes: 1. Single-ended operation is only functional at 3.3V. ® 2. MLF package only. March 2011 5 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) ................................... –0.5V to +4.0V Input Voltage (VIN) .......................................... –0.5V to VCC LVPECL Output Current (IOUT) Continuous............................................................50mA Surge ..................................................................100mA Lead Temperature (soldering, 20 sec.).................... +260°C Storage Temperature Range (TS).............–65°C to +150°C DC Electrical Characteristics(4) Supply Voltage (VCC) ............................... +2.375V to +3.6V Ambient Temperature (TA).......................... –40°C to +85°C Package Thermal Resistance(3) MLF® (θJA) Still-Air ...............................................................................35°C/W MLF® (ψJB) Junction-to-Board ..........................................................28°C/W TQFP (θJA) Still-Air ...............................................................................28°C/W TQFP (ψJB) Junction-to-Board ..........................................................20°C/W TA = –40°C to +85°C, unless noted. Symbol Parameter Condition Min. Typ. Max. VCC Power Supply VCC = 2.5V 2.375 2.5 2.625 VCC = 3.3V 3 3.3 3.6 IEE Power Supply Current No load, max. VCC VIN Input Voltage Swing (IN, /IN) See Figure 1a. VDIFF_IN Differential Input Voltage Swing (IN, /IN) See Figure 1b. VIHCMR Input High Common Mode Range IN, /IN Units V 220 mA 150 1200 mV 300 2400 mV VEE + 1.2 VCC V Max. Units VCC = 3.3V, TA = –40°C to 85°C, unless otherwise stated. Symbol Parameter Condition Min. Typ. VIH Input High Voltage (IN, /IN) 2.075 2.420 V VIL Input Low High Voltage (IN, /IN) 1.355 1.675 V VBB Output Voltage Reference 1.775 1.875 1.975 V VEF Mode Connection 1.9 2.0 2.1 V VCF Input Select Voltage 1.55 1.65 1.75 V Notes: 1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Rating” conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. ® 3. Thermal performance on MLF packages assumes exposed pad is soldered (or equivalent) to the device most negative potential (GND). 4. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. Input and output parameters vary 1:1 with VCC, with the exception of VCF. March 2011 6 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U DC Electrical Characteristics(4) (Continued) VCC = 2.5V, TA = –40°C to 85°C, unless otherwise stated. Symbol Parameter VIH Input High Voltage (IN, /IN) VIL Condition Min. Typ. Max. Units 1.275 1.62 V Input Low High Voltage (IN, /IN) 0.555 0.875 V VBB Output Voltage Reference 1.175 1.075 0.975 V VEF Mode Connection 1.10 1.20 1.30 V VCF Input Select Voltage 1.15 1.25 1.35 V LVPECL Outputs DC Electrical Characteristics(4) VCC = 3.3V; RLOAD = 50Ω to VCC−2V; TA = –40°C to +85°C, unless noted. Symbol Parameter VOH Condition Min. Typ. Max. Units Output HIGH Voltage (Q, /Q) 2.155 2.280 2.405 V VOL Output LOW Voltage (Q, /Q) 1.355 1.480 1.605 V VOUT Output Voltage Swing (Q, /Q) See Figure 1a. 550 800 mV VDIFF_OUT Differential Output Voltage Swing (Q, /Q) See Figure 1b. 1.1 1.6 V Min. Typ. Max. Units LVPECL Outputs DC Electrical Characteristics(5) VCC = 2.5V; RLOAD = 50Ω to VCC−2V; TA = –40°C to +85°C, unless noted. Symbol Parameter Condition VCC Output HIGH Voltage (Q, /Q) 1.355 1.480 1.605 V IEE Output LOW Voltage (Q, /Q) 0.555 0.68 0.805 V VIN Output Voltage Swing (Q, /Q) See Figure 1a. 550 800 mV VDIFF_OUT Differential Output Voltage Swing (Q, /Q) See Figure 1b. 1.1 1.6 V Min Typ LVTTL/CMOS DC Electrical Characteristics(6) VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to +85°C, unless noted. Symbol Parameter Condition Max Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V IIH Input HIGH Current 40 µA IIL Input LOW Current 2.0 V −300 µA Notes: 5. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. VOH and VOL parameters vary 1:1 with VCC. 6. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established. March 2011 7 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U AC Electrical Characteristics(7) TA = –40°C to +85°C, unless noted. Symbol Parameter Condition fMAX Maximum Operating Frequency Clock Min. VOUT ≥ 400mV Typ. Max. 1.5 Units GHz Propagation Delay IN to Q; D[0–10]=0 IN to Q; D[0–10]=1023 /EN to Q: D[0–10]=0 D10 to CASCADE 3200 11500 3400 350 tRANGE Programmable Range tpd (max.) – tpd (min) 8300 tSKEW Duty Cycle Skew tpd tPHL – tPLH 4200 14800 4400 670 ps ps Note 8 25 ps Step Delay D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High D0-D9 High Δt INL Note 9 Integral Non-Linearity 10 15 35 70 145 290 575 1150 2300 4610 9220 ps ±10 ps Setup Time tS D to LEN D to IN /EN to IN Note 10 Note 11 200 350 300 ps LEN to D IN to /EN Note 12 200 400 ps Hold Time tH Notes: 7. High-frequency AC electricals are guaranteed by design and characterization. 8. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output. 9. INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay – measured minimum delay) ÷ 1024. INL = measured delay – measured minimum delay + (step number ∞ TIL). 10. This setup time defines the amount of time prior to the input signal. The delay tap of the device must be set. 11. This setup time defines the amount of the time that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than ±75mV to the IN, /IN transition. 12. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater than ±75mV to the IN, /IN transition. March 2011 8 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U AC Electrical Characteristics (7) TA = –40°C to +85°C, unless noted. Symbol Parameter Condition Min. Typ. Max. Units Release Time /EN to IN SETMAX to LEN SETMIN to LEN tR 500 500 450 tJITTER Cycle-to-Cycle Jitter Total Jitter Random Jitter Note 13 Note 14 Note 15 tr, tf Output Rise/Fall Time 20% to 80% (Q) 20% to 80% (Cascade) Duty Cycle 50 90 ps 85 45 2 10 1 psRMS psPP psRMS 160 300 ps 55 % Notes: 13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles over a random sample of adjacent cycle pairs. Tjitter_cc = Tn – Tn+1, where T is the time between rising edges of the output signal. 14. Total jitter definition: With an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-topeak jitter value. 15. Random jitter definition: Jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean. Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps. March 2011 9 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Typical Operating Characteristics VCC = 3.3V, GND = 0, DIN = 100mV, TA = 25ºC, unless otherwise stated. March 2011 10 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Timing Diagrams Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing Input and Output Stages Figure 2a. Differential Input Stage March 2011 Figure 2b. Single-Ended Input Stage 11 Figure 3. LVPECL Output Stage M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Output Interface Applications Figure 5. Y-Termination Figure 4. Parallel Termination Figure 6. Terminating Unused I/O March 2011 12 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Applications Information For best performance, use good high-frequency layout techniques, filter VCC supplies, and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the SY89295U data inputs and outputs. Setting D Input Logic Thresholds In all designs where the SY89295U GND supply is at zero volts, the D inputs can accommodate CMOS and TTL level signals, as well as PECL or LVPECL. Figures 11, 12 and 14 show how to connect VCF and VEF for all possible cases. VBB Reference The VBB pin is an internally generated reference and is available for use only by the SY89295U. When unused, this pin should be left unconnected. Two common uses for VBB are to handle a single-ended PECL input, and to re-bias inputs for AC-coupling applications. If IN and /IN are driven by a single-ended output, VBB is used to bias the unused input. Please refer to Figure 10. The PECL signal driving the SY89295U may optionally be inverted in this case. When the signal is AC-coupled, VBB is used, as shown in Figure 13, to re-bias IN and /IN. This ensures that SY89295U inputs are within acceptable common mode range. In all cases, VBB current sinking or sourcing must be limited to 0.5mA or less. March 2011 Cascading Two or more SY89295U may be cascaded in order to extend the range of delays permitted. Each additional SY89295U adds about 3.2ns to the minimum delay and adds another 10240ps to the delay range. Internal cascade circuitry has been included in the SY89295U. Using this internal circuitry, the SY89295U may be cascaded without any external gating. Examples of cascading 2, 3, or 4 SY89295U appear in Figures 7, 8, and 9. 13 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Figure 7. Cascading Two SY89295U Figure 8. Cascading Three SY89295U Figure 8. Cascading Four SY89295U March 2011 14 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Interface Applications Figure 10. Interfacing to a Single-Ended LVPECL Signal Figure 11. VCF/VEF Biasing for LVPECL Control (D) Input Figure 13. Re-Biasing an AC-Coupled Signal Figure 12. VCF/VEF Biasing for CMOS (D) Input Figure 14. VCF/VEF Biasing for LVTTL Control (D) Input Related Product and Support Documentation Part Number Function Datasheet Link SY89295U 2.5/3.3V 1.5GHz Precision LVPECL Programmable Delay www.micrel.com/product-info/products/sy89295u.shtml SY89296U 2.5/3.3V 1.5GHz Precision LVPECL Programmable Delay with Fine Tune Control www.micrel.com/product-info/products/sy89296u.shtml 16-MLF Manufacturing Guidelines Exposed Pad Application Note www.amkor.com/products/notes_papers/MLF_appnote_0902.pdf HBW Solutions http://www.micrel.com/product-info/as/solutions.shtml March 2011 15 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Package Information PCB Thermal Consideration for 32-Pin MLF® Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 qualifications 2. All parts are dry-packed before shipment. 3. Exposed pads must be soldered to a ground for proper thermal management. ® 32-Pin MLF (MLF-32) March 2011 16 M9999-032511 [email protected] or (408) 955-1690 Micrel, Inc. SY89295U Package Information (Continued) 32-Pin TQFP (T32-1) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. March 2011 17 M9999-032511 [email protected] or (408) 955-1690