MICREL SY58604U_11

SY58604U
3.2Gbps Precision, LVPECL Buffer with
Internal Termination and Fail Safe Input
General Description
The SY58604U is a 2.5/3.3V, high-speed, fully
differential LVPECL buffer optimized to provide only
108fsRMS phase jitter. The SY58604U can process clock
signals as fast as 2.5GHz or data patterns up to
3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mVpp) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (VREF-AC) is provided to bias the VT pin.
The output is 800mV LVPECL, with extremely fast
rise/fall times guaranteed to be less than 110ps.
The SY58604U operates from a 2.5V ±5% supply or
3.3V ±10% supply and is guaranteed over the full
industrial temperature range (–40°C to +85°C). For
applications that require CML or LVDS outputs, consider
the SY58603U and the SY58605U, buffers with 400mV
and 325mV output swings respectively. The SY58604U
is part of Micrel’s high-speed, Precision Edge® product
line.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
• Precision 800mV LVPECL buffer
• Ultra-low jitter design
– 108fsRMS phase jitter
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps throughput
– <350ps typical propagation delay (IN-to-Q)
– <110ps rise/fall times
• Fail Safe Input
– Prevents output from oscillating when input is
invalid
• High-speed LVPECL output
• 2.5V ±5% or 3.3V ±10% power supply operation
• Industrial temperature range: –40°C to +85°C
• Available in 8-pin (2mm x 2mm) DFN package
Applications
•
•
•
•
All SONET clock and data distribution
Fibre Channel clock and data distribution
Gigabit Ethernet clock and data distribution
Backplane distribution
Markets
•
•
•
•
•
•
•
Storage
ATE
Test and measurement
Enterprise networking equipment
High-end servers
Access
Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
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SY58604U
Ordering Information(1)
Part Number
Package Type
Operating Range
Package Marking
SY58604UMG
DFN-8
Industrial
604 with Pb-Free
bar-line indicator
SY58604UMGTR(2)
DFN-8
Industrial
604 with Pb-Free
bar-line indicator
Notes:
1.
Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2.
Tape and Reel.
Pin Configuration
8-Pin DFN
Pin Description
Pin Number
Pin Name
1, 4
IN, /IN
Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of
this pair internally terminates with 50Ω to the VT pin. If the input swing falls below a
certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a
stable output by latching the output to its last valid state. See “Input Interface
Applications” subsection for more details.
2
VT
Input Termination Center-Tap: Each input terminates to this pin. The VT pin
provides a center-tap for each input (IN, /IN) to a termination network for maximum
interface flexibility. See “Input Interface Applications” subsection.
3
VREF-AC
5
GND,
Exposed pad
6, 7
/Q, Q
LVPECL Differential Output Pair: Differential buffered output copy of the input
signal. The output swing is typically 800mV. See “LVPECL Output Termination”
subsection.
8
VCC
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to
the VCC pin as possible.
September 2011
Pin Function
Reference Voltage: This output biases to VCC–1.2V. It is used for AC-coupling inputs
IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR
capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface
Applications” subsection for more details.
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
2
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SY58604U
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ............................... –0.5V to +4.0V
Input Voltage (VIN) ............................. –0.5V to VCC+0.5V
LVPECL Output Current (IOUT)
Continuous.......................................................50mA
Surge .............................................................100mA
Current (VT)
Source or sink on VT pin .............................±100mA
Input Current
Source or sink Current on (IN, /IN) ................±50mA
Current (VREF)
Source or sink current on VREF-AC(4) ............±1.5mA
Maximum Operating Junction Temperature.......... 125°C
Lead Temperature (soldering, 20sec.) .................. 260°C
Storage Temperature (Ts) ....................–65°C to +150°C
Supply Voltage (VIN)........................ +2.375V to +3.60V
Ambient Temperature (TA) ................... –40°C to +85°C
Package Thermal Resistance(3)
DFN
Still-air (θJA) ............................................ 93°C/W
Junction-to-board (ΨJB).......................... 56°C/W
DC Electrical Characteristics(5)
TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
VCC
Power Supply Voltage Range
Condition
ICC
Power Supply Current
RDIFF_IN
Differential Input Resistance
(IN-to-/IN)
VIH
Input HIGH Voltage
(IN, /IN)
IN, /IN, Note 7
VIL
Input LOW Voltage
(IN, /IN)
IN, /IN
VIN
Input Voltage Swing
(IN, /IN)
see Figure 3a, Note 6
VDIFF_IN
Differential Input Voltage Swing
(|IN - /IN|)
see Figure 3b
VIN_FSI
Input Voltage Threshold that
Triggers FSI
VREF-AC
Output Reference Voltage
VT_IN
Voltage from Input to VT
Min
Typ
Max
Units
2.375
2.5
2.625
V
3.0
3.3
3.6
30
45
mA
100
110
Ω
VCC–1.6
VCC
V
0
VIH–0.1
V
0.1
1.7
V
No load, max. VCC
90
0.2
VCC–1.3
V
30
100
mV
VCC–1.2
VCC–1.1
V
1.28
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions
for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ΨJB and θJA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
4. Due to the limited drive capability, use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. VIN (max) is specified when VT is floating.
7. VIH (min) not lower than 1.2V.
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SY58604U
LVPECL Outputs DC Electrical Characteristics(5)
VCC = +2.5V ±5% or +3.3V ±10%, RL = 50Ω to VCC-2V; TA = –40°C to +85°C, unless otherwise stated.
Symbol
Parameter
Max
Units
VOH
Output HIGH Voltage
VCC-1.145
VCC -0.895
V
VOL
Output LOW Voltage
VCC-1.945
VCC-1.695
V
VOUT
Output Voltage Swing
See Figure 3a
550
800
950
mV
VDIFF_OUT
Differential Output Voltage Swing
See Figure 3b
1100
1600
September 2011
Condition
Min
4
Typ
mV
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SY58604U
AC Electrical Characteristics
VCC = +2.5V ±5% or +3.3V ±10%, RL = 50Ω to VCC-2V, Input tr/tf: <300ps; TA = –40°C to +85°C, unless otherwise
stated.
Symbol
Parameter
Condition
Min
Typ
fMAX
Maximum Frequency
NRZ Data
3.2
4.25
Gbps
2.5
3
GHz
VIN: 100mV-200mV
180
320
450
ps
VIN: 200mV-800mV
150
230
350
ps
135
ps
VOUT > 400mV
tPD
Propagation Delay
tSkew
Part-to-Part Skew
tJitter
RMS Phase Jitter
IN-to-Q
Clock
Note 7
Units
Output = 622MHz
108
Integration Range: 12kHz – 20MHz
tr, tf
Max
Output Rise/Fall Times
(20% to 80%)
At full output swing.
Duty Cycle
Differential I/O
40
47
75
fsRMS
110
ps
53
%
Notes:
7.
Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
Phase Noise Plot
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SY58604U
Functional Description
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, then the FSI function will eliminate a
metastable condition and guarantee a stable output.
No ringing and no undetermined state will occur at the
output under these conditions.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal. Due to the FSI function, the
propagation delay will depend on rise and fall time of
the input signal and on its amplitude. Refer to “Typical
Characteristics” for detailed information.
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or
when the amplitude of the input signal drops
sufficiently below 100mVPK (200mVPP), typically
30mVPK. Maximum frequency of SY58604U is limited
by the FSI function.
Timing Diagrams
Figure 1a. Propagation Delay
Figure 1b. Fail Safe Feature
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SY58604U
Typical Characteristics
VCC = 3.3V, GND = 0V, VIN = 100mV, RL = 50Ω to VCC-2V, TA = 25°C, unless otherwise stated.
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SY58604U
Functional Characteristics
VCC = 3.3V, GND = 0V, VIN = 400mV, Data Pattern: 223-1, RL = 50Ω to VCC-2V, TA = 25°C, unless otherwise stated.
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SY58604U
Functional Characteristics (continued)
VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 50Ω to VCC-2V, TA = 25°C, unless otherwise stated.
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SY58604U
Input and Output Stage
Figure 2b. Simplified LVPECL Output Buffer
Figure 2a. Simplified Differential Input Buffer
Single-Ended and Differential Swings
Figure 3b. Differential Voltage Swing
Figure 3a. Single-Ended Voltage Swing
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SY58604U
Input Interface Applications
Figure 4a. CML Interface
(DC-Coupled)
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Option: May connect VT to VCC
Figure 4d. LVPECL Interface
(AC-Coupled)
September 2011
Figure 4e. LVDS Interface
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SY58604U
LVPECL Output Termination
LVPECL outputs have very low output impedance
(open emitter), and small signal swing which results in
low EMI. LVPECL is ideal for driving 50Ω-and-100Ωcontrolled impedance transmission lines. There are
several techniques in terminating the LVPECL output,
as shown in Figure 5a and 5b.
Figure 5b. Three-Resistor “Y-Termination”
Figure 5a. Parallel Termination-Thevenin Equivalent
Related Product and Support Documents
Part Number
Function
Data Sheet Link
SY58603U
4.25Gbps Precision CML Buffer with
Internal Termination and Fail Safe Input
http://www.micrel.com/page.do?page=/productinfo/products/sy58603u.shtml
SY58605U
3.2Gbps Precision LVDS Buffer with
Internal Termination and Fail Safe Input
http://www.micrel.com/page.do?page=/productinfo/products/sy58605u.shtml
HBW Solutions
New Products and Termination Application
Notes
http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml
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SY58604U
Package Information
8-Pin (2mm x 2mm) DFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
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warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
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© 2005 Micrel, Incorporated.
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