Revised June 2005
74VCX16245
Low Voltage 16-Bit Bidirectional Transceiver
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each
byte has separate 3-STATE control inputs which can be
shorted together for full 16-bit operation. The T/R inputs
determine the direction of data flow through the device.
The OE inputs disable both the A and B ports by placing
them in a high impedance state.
The 74VCX16245 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX16245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
■ 1.2V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ tPD
2.5 ns max for 3.0V to 3.6V VCC
■ Power-off high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ Static Drive (IOH/IOL)
r24 mA @ 3.0V VCC
■ Uses patented noise/EMI reduction circuitry
■ Latchup performance exceeds 300 mA
■ ESD performance:
Human body model ! 2000V
Machine model !200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
Package Number
74VCX16245G
(Note 2)(Note 3)
74VCX16245MTD
(Note 3)
BGA54A
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS012169
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74VCX16245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs
October 1996
74VCX16245
Connection Diagrams
Pin Descriptions
Pin Assignment of TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
T/Rn
Transmit/Receive Input
A0–A15
Side A Inputs or 3-STATE Outputs
B0–B15
Side B Inputs or 3-STATE Outputs
NC
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B0
NC
T/R1
OE1
NC
A0
B
B2
B1
NC
NC
A1
A2
C
B4
B3
VCC
VCC
A3
A4
D
B6
B5
GND
GND
A5
A6
E
B8
B7
GND
GND
A7
A8
F
B10
B9
GND
GND
A9
A10
A12
G
B12
B11
VCC
VCC
A11
H
B14
B13
NC
NC
A13
A14
J
B15
NC
T/R2
OE2
NC
A15
Truth Tables
Pin Assignment for FBGA
Inputs
OE1
T/R1
Outputs
L
L
L
H
Bus B0–B7 Data to Bus A0–A7
Bus A0–A7 Data to Bus B0–B7
H
X
HIGH Z State on A0–A7, B0–B7
Inputs
OE2
Outputs
L
L
Bus B8–B15 Data to Bus A8–A15
L
H
Bus A8–A15 Data to Bus B8–B15
H
X
HIGH Z State on A8–A15, B8–B15
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial (HIGH or LOW, inputs and I/O’s may not float)
Z High Impedance
(Top Thru View)
Logic Diagram
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T/R2
2
Recommended Operating
Conditions (Note 6)
0.5V to 4.6V
0.5V to 4.6V
Supply Voltage (VCC)
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Outputs 3-STATE
Outputs Active (Note 5)
DC Input Diode Current (IIK) VI 0V
0.5V to 4.6V
0.5 to VCC 0.5V
50 mA
Output in Active States
0V to VCC
Output in 3-STATE
VO 0V
50 mA
50 mA
VO ! VCC
r50 mA
(IOH/IOL)
0.0V to 3.6V
Output Current in IOH/IOL
DC Output Source/Sink Current
DC VCC or Ground Current per
Storage Temperature Range (TSTG)
1.2V to 3.6V
0.3V to 3.6V
Output Voltage (VO)
DC Output Diode Current (IOK)
Supply Pin (ICC or Ground)
Operating
Input Voltage
r100 mA
65qC to 150qC
VCC
3.0V to 3.6V
VCC
2.3V to 2.7V
VCC
1.65V to 2.3V
VCC
1.4V to 1.6V
VCC
1.2V
Free Air Operating Temperature (TA)
r24 mA
r18 mA
r6 mA
r2 mA
r100 PA
40qC to 85qC
Minimum Input Edge Rate ('t/'V)
VIN
0.8V to 2.0V, VCC
3.0V
10 ns/V
Note 4: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the “Electrical
Characteristics” table are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation.
Note 5: IO Absolute Maximum Rating must be observed.
Note 6: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
Parameter
Conditions
VCC
Min
Max
Units
(V)
VIH
VIL
HIGH Level Input Voltage
2.7 - 3.6
LOW Level Input Voltage
2.0
2.3 - 2.7
1.6
1.65 - 2.3
0.65 x VCC
1.4 - 1.6
0.65 x VCC
1.2
0.65 x VCC
2.7 - 3.6
0.8
2.3 - 2.7
0.7
1.65 - 2.3
0.35 x VCC
1.4 - 1.6
0.35 x VCC
1.2
VOH
HIGH Level Output Voltage
V
0.05 x VCC
IOH
100 PA
2.7 - 3.6
VCC - 0.2
IOH
12 mA
2.7
2.2
IOH
18 mA
3.0
2.4
IOH
24 mA
3.0
2.2
IOH
100 PA
2.3 - 2.7
VCC - 0.2
IOH
6 mA
2.3
2.0
IOH
12 mA
2.3
1.8
IOH
18 mA
2.3
1.7
1.65 - 2.3
VCC - 0.2
IOH
100 PA
IOH
6 mA
IOH
100 PA
IOH
2 mA
1.4
1.05
IOH
100 PA
1.2
VCC - 0.2
3
V
1.65
1.25
1.4 - 1.6
VCC - 0.2
V
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74VCX16245
Absolute Maximum Ratings(Note 4)
74VCX16245
DC Electrical Characteristics
Symbol
(Continued)
Parameter
VCC
Conditions
Min
Max
Units
(V)
VOL
LOW Level Output Voltage
IOL
100 PA
2.7 - 3.6
0.2
IOL
12 mA
2.7
0.4
IOL
18 mA
3.0
0.4
IOL
24 mA
3.0
0.55
IOL
100 PA
2.3 - 2.7
0.2
IOL
12 mA
2.3
0.4
IOL
18 mA
2.3
0.6
IOL
100 PA
1.65 - 2.3
0.2
IOL
6 mA
1.65
0.3
IOL
100 PA
IOL
2 mA
IOL
100 PA
II
Input Leakage Current
0V d VI d 3.6V
IOZ
3-STATE Output Leakage
0V d VO d 3.6V
VIH or VIL
VI
IOFF
Power Off Leakage Current
0V d (VI, VO) d 3.6V
ICC
Quiescent Supply Current
VI
'ICC
Increase in ICC per Input
VIH
VCC or GND
VCC d (VI, VO) d 3.6V (Note 7)
VCC 0.6V
1.4 - 1.6
0.2
1.4
0.35
V
1.2
VCC - 0.1
1.2 - 3.6
r5.0
PA
1.2 - 3.6
r10
PA
PA
0
10
1.2 - 3.6
20
1.2 - 3.6
r20
2.7 - 3.6
750
PA
PA
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Symbol
tPHL
Parameter
Propagation Delay
(Note 8)
Conditions
CL
30 pF, RL
500:
tPLH
CL
tPZL
Output Enable Time
CL
15 pF, RL
30 pF, RL
2k:
500:
tPZH
CL
tPLZ
Output Disable Time
CL
15 pF, RL
30 pF, RL
2k:
500:
tPHZ
CL
tOSHL
Output to Output
tOSLH
Skew (Note 9)
CL
CL
Note 8: For CL
15 pF, RL
30 pF, RL
15 pF, RL
2k:
500:
2k:
VCC
(V)
TA
40qC to 85qC
Min
Max
3.3 r 0.3
0.8
2.5
2.5 r 0.2
1.0
3.0
1.8 r 0.15
1.0
6.0
1.5 r 0.1
1.0
12.0
1.2
1.5
30
3.3 r 0.3
0.8
3.8
2.5 r 0.2
1.0
4.9
1.8 r 0.15
1.5
9.3
1.5 r 0.1
1.0
18.6
1.2
1.5
46.5
3.3 r 0.3
0.8
3.7
2.5 r 0.2
1.0
4.2
1.8 r 0.15
1.5
7.6
1.5 r 0.1
1.0
15.2
1.2
1.5
38
3.3 r 0.3
Units
Figure
Number
Figures
1, 2
ns
Figures
5, 6
Figures
1, 3, 4
ns
Figures
5, 7, 8
Figures
1, 3, 4
ns
Figures
5, 7, 8
0.5
2.5 r 0.2
0.5
1.8 r 0.15
0.75
1.5 r 0.1
1.5
1.2
1.5
ns
50pF, add approximately 300ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
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4
Symbol
VOLP
VOLV
VOHV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
VCC
Conditions
CL
CL
CL
30 pF, VIH
30 pF, VIH
30 pF, VIH
VCC, VIL
VCC, VIL
VCC, VIL
0V
0V
0V
25qC
TA
(V)
Typical
1.8
0.25
2.5
0.6
3.3
0.8
1.8
0.25
2.5
0.6
3.3
0.8
1.8
1.5
2.5
1.9
3.3
2.2
Units
V
V
V
Capacitance
Symbol
Parameter
TA
Conditions
CIN
Input Capacitance
VCC
CI/O
Output Capacitance
VI
0V, or VCC, VCC
1.8V, 2.5V, or 3.3V, VI
CPD
Power Dissipation Capacitance
VI
0V or VCC, F
5
25qC
Typical
Units
0V or VCC
6
pF
1.8V, 2.5V or 3.3V
7
pF
20
pF
10 MHz, VCC
1.8V, 2.5V or 3.3V
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74VCX16245
Dynamic Switching Characteristics
74VCX16245
AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V)
FIGURE 1. AC Test Circuit
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC
VCC x 2 at VCC
tPZH, tPHZ
3.3 r 0.3V;
2.5 r 0.2V; 1.8V r 0.15V
GND
FIGURE 2. Waveform for Inverting and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
Symbol
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VCC
3.3V r 0.3V
2.5V r 0.2V
1.8V r 0.15V
Vmi
1.5V
VCC/2
VCC/2
Vmo
1.5V
VCC/2
VCC/2
VX
VOL 0.3V
VOL 0.15V
VOL 0.15V
VY
VOH 0.3V
VOH 0.15V
VOH 0.15V
6
74VCX16245
AC Loading and Waveforms (VCC 1.5V r 0.1V to 1.2V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VCC x 2 at VCC
1.5 r 0.1V
FIGURE 5. AC Test Circuit
FIGURE 6. Waveform for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V r 0.1V
VCC/2
Vmi
Vmo
VCC/2
VX
VOL 0.1V
VY
VOH 0.1V
7
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74VCX16245
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
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8
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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74VCX16245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)