PEREGRINE PE42671

Preliminary Specification
PE42671 DIE
SP7T UltraCMOS™ 2.75 V Switch
100 – 3000 MHz, +68 dBm IIP3
Figure 1. Functional Diagram
Features
• 2 TX, 2 TRX, 3 RX ports
• Three pin CMOS logic control with
RX1
RX2
TRX1 (WCDMA, RX)
RX3
•
•
•
TX1 (GSM/PCS)
TRX2 (WCDMA, RX)
•
TX2 (GSM/PCS)
CMOS
Control/Driver
and ESD
V1
V2
•
•
•
integral decoder/driver
Exceptional harmonic performance:
2fo = -83 dBc and 3fo = -78 dBc
Low TX insertion loss: 0.65 dB at
900 MHz, 0.75 dB at 1900 MHz
TX – RX Isolation of 47 dB at 900 MHz,
40 dB at 1900 MHz
1500 V HBM ESD tolerance all ports
+68 dBm IIP3 @ 50 Ω
-111 dBm IMD3
No blocking capacitors required
V3
Product Description
Figure 2. Die Top View*
RX1
ANT
GND
RX2
GND
RX3
TRX1
GND
TRX2
1576 µm
GND
ANT
GND
GND
TX2
TX1
GND
GND
GND VDD
The PE42671 is a HaRP™-enhanced SP7T
RF Switch developed on the UltraCMOS™
process technology. It addresses the specific
design needs of the Quad-Band GSM Handset
Antenna Switch Module Market for use in
GSM/PCS/EDGE/WCDMA handsets. The
switch is comprised of two transmit ports that
can be used for GSM/PCS/EDGE, two
transmit/receive ports (TRX1 and TRX2) that
can be used for either WCDMA or as receive
ports, and three symmetric receive ports. Onchip CMOS decode logic facilitates three-pin
low voltage CMOS control, while high ESD
tolerance of 1500 V at all ports, no blocking
capacitor requirements, and on-chip SAW filter
over-voltage protection devices make this the
ultimate in integration and ruggedness.
V1 GND V2 V3 GND
1156 µm
* Dimensions shown are drawn die size.
Document No. 70-0196-03 │ www.psemi.com
Contact [email protected] for full version of datasheet
Peregrine’s HaRP™ technology
enhancements deliver high linearity and
exceptional harmonics performance. It is an
innovative feature of the UltraCMOS™
process, providing performance superior to
GaAs with the economy and integration of
conventional CMOS.
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 4
PE42671
Preliminary Specification
Table 1. Target Electrical Specifications @ 25 °C, VDD = 2.75 V
Parameter
Condition
Typ
Units
0.65
0.75
0.6
0.75
0.95
1.0
dB
dB
dB
dB
dB
dB
Insertion loss1
TX - ANT (850 / 900)
TX - ANT (1800 / 1900)
TRX - ANT ( 850 WCDMA )
TRX - ANT ( 2100 WCDMA )
RX - ANT (850 / 900)
RX - ANT (1800 / 1900)
Return Loss
Port under test in on state (850 / 900)
(1800 / 1900 / 2100)
20
15
dB
dB
Isolation
TX - RX (850 / 900)
TX - RX (1800 / 1900)
TX - TX (850 / 900)
TX - TX (1800 / 1900)
TX - TRX (850 / 900)
TX - TRX (1800 / 1900)
TRX - RX ( 850 WCDMA)
TRX - RX (2100 WCDMA)
47
40
33
27
36
29
40
31
dB
dB
dB
dB
dB
dB
dB
dB
2nd Harmonic
TX 850 / 900 MHz, +35 dBm output power, 50 Ω
TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω
-83
-82
dBc
dBc
3rd Harmonic
TX 850 / 900 MHz, +35 dBm output power, 50 Ω
TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω
-78
-78
dBc
dBc
WCDMA 2100 IMD3
TRX1 / TRX2: Measured at 2.14 GHz at ANT port, input +20 dBm CW
signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz
-111
dBm
WCDMA 2100 IIP3
TRX1 / TRX2: Measured at 2.14 GHz at ANT port, input +20 dBm CW
signal at 1.95 GHz and -15 dBm CW signal at 1.76 GHz
+68
dBm
Note: 1. Insertion loss specified with optimal impedance matching.
Table 2. Operating Ranges
Parameter
Temperature range
VDD Supply Voltage
IDD Power Supply Current
(VDD = 2.75 V)
Table 3. Absolute Maximum Ratings
Symbol Min Typ Max Units
TOP
VDD
-40
2.65
IDD
2.75
13
TX input power2 (VSWR ≤ 3:1)
824-915 MHz
TX input power2 (VSWR ≤ 3:1)
1710-1910 MHz
+85
2.85
50
°C
V
+33
TRX input power (VSWR ≤ 3:1)
824 - 2170 MHz
PIN
Control Voltage High
VIH
Control Voltage Low
VIL
+20
0.4
-0.3
4.0
V
-0.3
VDD+ 0.3
V
Storage temperature range
-65
+150
°C
TST
dBm
V
Note: 2. Assumes RF input period of 4620 µs and duty cycle of 50%.
Units
Voltage on any input
PIN (∞:1)
V
1.4
Max
Power supply voltage
PIN(50 Ω)
dBm
Min
VI
+31
RX input power2
(VSWR =1:1)
Parameter/Conditions
VDD
µA
+35
PIN
Symbol
VESD
TX input power (50 Ω) 3,4
824-915 MHz
+38
TX input power (50 Ω) 3,4
1710-1910 MHz
+36
TRX input power (50 Ω)
824 - 2170 MHz
+34
RX input power (50 Ω) 3,4
+23
dBm
TX input power (VSWR = (∞:1)3,4
824-915 MHz
+35
TX input power (VSWR = (∞:1)3,4
1710-1910 MHz
+33
TRX input power (VSWR = (∞:1)
824 - 2170 MHz
+31
ESD Voltage (HBM, MIL_STD 883
Method 3015.7)
1500
dBm
V
Note: 3. Assumes RF input period of 4620 µs and duty cycle of 50%.
4. V DD within operating range specified in Table 2.
Part performance is not guaranteed under these
conditions. Exposure to absolute maximum conditions
for extended periods of time may adversely affect
reliability. Stresses in excess of absolute maximum
ratings may cause permanent damage.
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 4
Document No. 70-0196-03 │ UltraCMOS™ RFIC Solutions
Contact [email protected] for full version of datasheet
PE42671
Preliminary Specification
GND5
6
TRX1
Ground
6
ANT
RF Common – Antenna
Redundant ANT pins for flexible bonding
7
GND5
Ground
RF I/O - TX1
TX1
5
4
RF I/O – TRX1
GND5
8
TRX1
Ground
9
GND
10
GND5
Ground
11
VDD
Supply
12
V1
GND
5
ANT
GND
6
TX1
8
GND
9
GND
10
13
GND
14
V2
15
V3
GND
17
GND5
6
18
TX2
19
GND5
RX2
23
22
GND
RX3
21
GND
20
TRX2
19
GND
18
TX2
17
GND
12
13
14 15
16
Table 5. Truth Table
V3
V2
V1
Ground
TX1 - ANT
Path
0
0
0
Ground
TX2 - ANT
0
0
1
RF I/O – TX2
TRX1 - ANT
0
1
0
Ground
TRX2 - ANT
1
1
0
0
1
1
Switch control input, CMOS logic level
16
11
24
Ground
Switch control input, CMOS logic level
5
PE42671
Die
7
Switch control input, CMOS logic level
5
1
Ground
5
6
GND
3
GND
3
RF I/O – RX1
2
V2
V3
RX16
RX1
GND
ANT
2
4
Description
RF Common – Antenna
Redundant ANT pins for flexible bonding
V1
1
Pin Name
VDD
Pin No.
Figure 3. Pad Configuration (Top View)
ANT
Table 4. Pin Descriptions
20
TRX2
RF I/O – TRX2
RX1 - ANT
21
GND5
Ground
RX2 - ANT
1
0
0
RF I/O – RX3
RX3 - ANT
1
0
1
6
6
22
RX3
23
GND5
Ground
Electrostatic Discharge (ESD) Precautions
24
RX26
RF I/O – RX2
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Notes: 5. Bond wires should be physically short and connected to
ground plane for best performance.
6. Blocking capacitors needed only when non-zero DC
voltage present.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 6. Ordering Information
Order Code
Description
Package
Shipping Method
42671-90
PE42671-DIE-D
Film Frame
Wafer (Gross Die / Wafer Quantity)
42671-99
PE42671-DIE-400G
Waffle Pack
400 Dice / Waffle Pack
42671-00
PE42671-DIE-1H
Evaluation Kit
1/ box
Document No. 70-0196-03 │ www.psemi.com
Contact [email protected] for full version of datasheet
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 4
PE42671
Preliminary Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corporation
Peregrine Semiconductor K.K.
9450 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor, Korea
Peregrine Semiconductor Europe
#B-2402, Kolon Tripolis, #210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-480 S. Korea
Tel: +82-31-728-4300
Fax: +82-31-728-4305
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
South Asia Pacific
Space and Defense Products
Peregrine Semiconductor, China
Americas:
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Tel: 858-731-9453
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence Cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
©2005-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 4
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
Document No. 70-0196-03 │ UltraCMOS™ RFIC Solutions
Contact [email protected] for full version of datasheet