Product Specification PE4257 50 ΩSPDT Absorptive UltraCMOS™ DC – 3.0 GHz RF Switch Product Description The PE4257 is a high-isolation UltraCMOS™ Switch designed for wireless applications, covering a broad frequency range from near DC up to 3000 MHz. This single-supply SPDT switch integrates a two-pin CMOS control interface. It also provides low insertion loss with extremely low bias requirements while operating on a single 3-volt supply. In a typical wireless application, the PE4257 provides unprecedented isolation and integration. Features • 50 Ω characteristic impedance • Integrated 50 Ω 0.25 watt terminations • High input IP3 > +55 dBm • High isolation 64 dB at 1000 MHz • Low insertion loss: typically 0.75 dB at 1000 MHz and 0.95 dB at 2000 MHz • LV CMOS two-pin control The PE4257 is manufactured in Peregrine’s patented Ultra Thin Silicon (UTSi®) CMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. • Single +3 volt supply operation • Low current consumption: 8 µA Figure 1. Functional Diagram Figure 2. Package Type RFC 4x4mm 20 Lead QFN RF1 RF2 CMOS Control Driver CTRL1 CTRL2 Table 1. Electrical Specifications @ +25 °C, VDD = 3.0 V (ZS = ZL = 50 Ω) Parameter Condition 1 Operating Frequency Minimum Typical DC 0.75 0.95 1.2 Maximum Units 3000 MHz 0.95 1.15 1.4 dB Insertion Loss 1000 MHz 2000 MHz 3000 MHz Isolation Input to Output 1000 MHz 2000 MHz 3000 MHz 61 46 40 64 50 44 dB Isolation Output to Output 1000 MHz 2000 MHz 3000 MHz 57 54 42 63 60 48 dB 80 dBm Input IP2 5 MHz - 1000 MHz Input IP3 5 MHz - 1000 MHz 50 55 dBm 1000 MHz 29 31 dBm Input 1dB Compression2 Switching Time Video Feedthrough3 50% CTRL to 10 / 90 RF 5 MHz - 1000 MHz 2 µs 15 mVpp Notes: 1. Device linearity will begin to degrade below 1 MHz. 2. Note Absolute Maximum ratings in Table 3. 3. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth Document No. 70-0166-02 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 7 PE4257 Product Specification GND CTRL1 CTRL2 Symbol 16 VI VDD 15 GND 1 GND GND 2 14 GND RF1 3 13 GND, RF1 Term. 4 12 GND, RF2 Term. GND 5 11 GND RF2 7 8 9 GND RFC GND GND 10 6 GND Table 2. Pin Descriptions Name GND RF Ground 2 GND RF Ground 3 RF1 RF I/O 4 GND RF Ground 5 GND RF Ground 6 GND RF Ground 7 GND RF Ground 81 RFC RF Common 9 GND RF Ground 10 GND RF Ground 11 GND RF Ground 12 GND RF Ground 13 RF2 RF I/O 14 GND RF Ground 15 GND RF Ground 162 CTRL2 Control 2 2 CTRL1 Control 1 1 TST TOP Min Max Unit Power supply voltage Parameter/Condition -0.3 V Voltage on CTRL input -0.3 4.0 VDD + 0.3 33/24 dBm -65 +150 °C -40 +85 °C RF power on RFC, RF1, RF2 On Port/ Terminated Port Storage temperature Operating temperature ESD voltage (Human Body Model) 1000 V V Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC Electrical Specifications table. Exposure to absolute maximum ratings for extended periods may affect device reliability. Description 1 1 PRF VESD 4x4mm 20-Lead QFN No. Table 3. Absolute Maximum Ratings 17 18 VSS/GND 19 GND 20 VDD Figure 3. Pin Configuration (Top View) Table 4. DC Electrical Specifications @ 25 °C Parameter VDD Power Supply Min Typ Max Unit 2.7 3.0 3.3 V 8 20 µA IDD Power Supply Current (VDD = 3V, VCNTL = 3V) Control Voltage High 0.70 VDD Control Voltage Low 0 V 0.30 VDD V Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Electrostatic Discharge (ESD) Precautions 18 VSS / GND Negative Supply Option 19 GND Digital Ground When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. 20 VDD Supply Switching Frequency Pad GND RF Ground Pad 17 3 Notes: 1. RF pins 3, 8, and 13 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is met. 2. Pins 16 and 17 are the CMOS controls that set the four operating states. 3. Connect pin 18 to GND to enable the negative voltage generator. Connect pin 18 to VSS (-3 V) to bypass and disable internal -3 V supply generator. See paragraph “Switching Frequency.” ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 7 The PE4257 has a maximum 25 kHz switching rate when the internal negative voltage generator is used (pin 18=GND). The rate at which the PE4257 can be switched is only limited to the switching time if an external -3 V supply is provided at (pin18=VSS ). Document No. 70-0166-02 │ UltraCMOS™ RFIC Solutions PE4257 Product Specification Table 5. Truth Table CTRL1 CTRL2 RFC – RF1 RFC – RF2 Low Low OFF OFF Low High OFF ON High Low ON OFF High Document No. 70-0166-02 │ www.psemi.com High N/A 1 N/A1 ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 7 PE4257 Product Specification Typical Performance Data @ 25°C (Unless Otherwise Noted) (50-ohm impedance) Figure 4. Insertion Loss – Input - Output Figure 5. RF1 to RF2 Isolation Figure 6. Isolation – RFC to RF1/RF2 Figure 7. Return Loss ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 7 Document No. 70-0166-02 │ UltraCMOS™ RFIC Solutions PE4257 Product Specification Evaluation Kit The SPDT Switch Evaluation Kit board was designed to ease customer evaluation of the PE4257 SPDT switch. The RF common port is connected through a 50 Ω transmission line to J2. Port 1 and Port 2 are connected through 50 Ω transmission lines to J1 and J3. A through transmission line connects SMA connectors J4 and J5. This transmission line can be used to estimate the loss of the PCB over the environmental conditions being evaluated. Figure 8. Evaluation Board Layouts Peregrine Specification 101/0151 The board is constructed of a four metal layer FR4 material with a total thickness of 0.031”. The transmission lines were designed using a coplanar waveguide with ground plane (28 mil core, 47.6 mil width, 30mil gap). Note the number of vias surrounding the device in the layout shown in Figure 8. These vias are critical for obtaining the specified isolation performance for the device shown in this datasheet. J6 provides a means for controlling DC and digital inputs to the device. The provided jumpers short the package pin to ground for logic low. When the jumper is removed, the pin is pulled up to VDD for logic high. When the jumper is in place, 3 µA of current will flow through the 1 MΩ pull up resistor. This extra current should not be attributed to the requirements of the device. Figure 9. Evaluation Board Schematic Peregrine Specification 102/0198 Document No. 70-0166-02 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 7 PE4257 Product Specification Figure 10. Package Drawing 20-Lead 4x4 QFN 4.00 INDEX AREA 2.00 X 2.00 2.00 4.00 2.00 -B- 0.25 C 0.80 -A- 0.10 C 0.08 C SEATING PLANE 2.00 TYP 0.55 1.00 6 0.18 10 5 11 2.00 4.00 DETAIL A 1.00 2.00 TYP 0.50 0.435 0.18 0.435 1 1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP. 2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. -C- 0.20 REF 0.020 EXPOSED PAD & TERMINAL PADS 15 20 EXPOSED PAD 16 DETAIL A 2 0.23 1 0.10 C A B Table 6. Ordering Information Order Code Part Marking Description Package 4257-01 4257 PE4257-20QFN 4x4mm-75A 20-lead 4x4mm QFN 75 units / Tube 4257-02 4257 PE4257-20QFN 4x4mm-3000C 20-lead 4x4mm QFN 3000 units / T&R 4257-00 PE4257-EK PE4257-20QFN 4x4mm-EK Evaluation Kit 1 / Box 4257-51 4257 PE4257G-20QFN 4x4mm-75A Green 20-lead 4x4mm QFN 75 units / Tube 4257-52 4257 PE4257G-20QFN 4x4mm-3000C Green 20-lead 4x4mm QFN 3000 units / T&R ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 7 Shipping Method Document No. 70-0166-02 │ UltraCMOS™ RFIC Solutions PE4257 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor Europe Commercial Products: Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 Space and Defense Products: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 South Asia Pacific Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0166-02 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 7