K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM Document Title 16M DDR SYNCHRONOUS SRAM Revision History Rev No. History Draft Data Remark Rev. 0.0 Initial document. Oct. 2003 Advance Rev. 0.1 Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS -to support 1.8~2.5V VDD, change some items. Nov. 2003 Preliminary Rev. 0.2 Change DC CHARACTERISTICS (Stop Clock Standby Current) -ISB1 : 100 -> 150 Feb. 2004 Preliminary Rev. 0.3 Change JTAG Instruction Cording - For Reserved Feb. 2004 Preliminary Rev. 1.0 Change DC CHARACTERISTICS (Increase Operating Current) - x36 : add 40mA, x18 : add 60mA Mar. 2004 Final Rev. 1.1 Add DC CHARACTERISTICS - VIN-CLK, VDIF-CLK, VCM-CLK Jan. 2004 Final Add AC INPUT CHARACTERISTICS Add INPUT DEFINITION The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters. -1- Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM FEATURES • Registered Addresses, Burst Control and Data Inputs. • Registered Outputs. • Double and Single Data Rate Burst Read and Write. • Burst Count Controllable With Max Burst Length of 4 • Interleved and Linear Burst mode support • Bypass Operation Support • Programmable Impedance Output Drivers. • JTAG Boundary Scan (subset of IEEE std. 1149.1) • 153(9x17) Pin Ball Grid Array Package(14mmx22mm) • • • • • 512Kx36 or 1Mx18 Organizations. 1.8~2.5V VDD/1.5V VDDQ.(1.9V max VDDQ) HSTL Input and Outputs. Single Differential HSTL Clock. Synchronous Pipeline Mode of Operation with Self-Timed Late Write. • Free Running Active High and Active Low Echo Clock Output Pin. • Asynchronous Output Enable. GENERAL DESCRIPTION The K7D163674B and K7D161874B are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as 524,288 words by 36 bits for K7D163674B and 1,048,576 words by 18 bits for K7D161874B, fabricated using Samsung's advanced CMOS technology. Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and falling edge of K clock for a double data rate (DDR) write operations. Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access time for all SDR and DDR operations. The chip is operated with a single +2.5V power supply and is compatible with Extended HSTL input and output. The package is 9x17(153) Ball Grid Array balls on a 1.27mm pitch. ORDERING INFORMATION Part Number Organization 375MHz K7D163674B-HC37 K7D163674B-HC33 Maximum Frequency 512Kx36 333MHz K7D163674B-HC30 300MHz K7D163674B-HC27 275MHz K7D161874B-HC37 375MHz K7D161874B-HC33 1Mx18 333MHz K7D161874B-HC30 300MHz K7D161874B-HC27 275MHz -2- Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM FUNCTIONAL BLOCK DIAGRAM SA[0:18]( or SA[0:19]) Address Register 17(or 18) (Burst Address) CE Clock Buffer K,K 19(or 20) Advance Control Co B3 SD/DD Data Out 36(or 18)x2 Synchronous Select & R/W control W/D Array (Burst Write Address) 19(or 20) 36(or 18)x2 17(or 18) 36(or18)x2 2 : 1 MUX CE Data In 36(or18)x2 S/A Array Write Address Register (2 stage) CE B2 Memory Array 512Kx36 or (1Mx18) Dec. Burst Counter Comparator B1 2:1 MUX Write Buffer Strobe_out Data Output Strobe LD Echo Clock Output Output Buffer R/W Data In Register (2 stage) Data Output Enable State Machine Internal Clock Generator 36(or 18) DQ G XDIN CQ,CQ PIN DESCRIPTION Pin Name Pin Description Pin Name Differential Clocks SA Synchronous Address Input TCK JTAG Test Clock Synchronous Burst Address Input (SA0 = LSB) TMS JTAG Test Mode Select Synchronous Data I/O TDI JTAG Test Data Input SA0, SA1 DQ ZQ Pin Description K, K Output Driver Impedance Control Input Differential Output Echo Clocks TDO JTAG Test Data Output B1 Load External Address VREF HSTL Input Reference Voltage B2 Burst R/W Enable VDD Power Supply B3 Single/Double Data Selection VDDQ Output Power Supply G Asynchronous Output Enable VSS GND Linear Burst Order NC No Connection CQ, CQ LBO -3- Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7D163674B(512Kx36) 1 2 3 4 5 6 7 8 9 A VSS VDDQ SA SA ZQ SA SA VDDQ VSS B DQ DQ SA VSS B1 VSS SA DQ DQ C VSS VDDQ SA SA G SA SA VDDQ VSS D DQ DQ SA VSS VDD VSS SA DQ DQ E VSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS F DQ CQ1 DQ VDD VDD VDD DQ CQ2 DQ G VSS VDDQ VSS VSS K VSS VSS VDDQ VSS H DQ DQ DQ VDD K VDD DQ DQ DQ J VSS VDDQ VSS VDD VDD VDD VSS VDDQ VSS K DQ DQ DQ VSS B2 VSS DQ DQ DQ L VSS VDDQ VSS LBO B3 MODE VSS VDDQ VSS M DQ CQ1 DQ VDD VDD VDD DQ CQ2 DQ N VSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS P DQ DQ NC VSS VDD VSS SA DQ DQ R VSS VDDQ VDD SA SA1 SA VDD VDDQ VSS T DQ DQ SA VSS SA0 VSS SA DQ DQ U VSS VDDQ TMS TDI TCK TDO NC VDDQ VSS * Mode Pin(6L) is a internally NC. K7D161874B(1Mx18) A 1 2 3 4 5 6 7 8 9 VSS VDDQ SA SA ZQ SA SA VDDQ VSS B NC DQ SA VSS B1 VSS SA NC DQ C VSS VDDQ SA SA G SA SA VDDQ VSS D DQ NC SA VSS VDD VSS SA DQ NC E VSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS F NC CQ1 NC VDD VDD VDD DQ NC DQ G VSS VDDQ VSS VSS K VSS VSS VDDQ VSS H DQ NC DQ VDD K VDD NC DQ NC J VSS VDDQ VSS VDD VDD VDD VSS VDDQ VSS K NC DQ NC VSS B2 VSS DQ NC DQ L VSS VDDQ VSS LBO B3 MODE VSS VDDQ VSS M DQ NC DQ VDD VDD VDD NC CQ1 NC N VSS VDDQ VSS VDD VREF VDD VSS VDDQ VSS P NC DQ SA VSS VDD VSS SA NC DQ R VSS VDDQ VDD SA SA1 SA VDD VDDQ VSS T DQ NC SA VSS SA0 VSS SA DQ NC U VSS VDDQ TMS TDI TCK TDO NC VDDQ VSS * Mode Pin(6L)is a internally NC. -4- Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM Read Operation(Single and Double) During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by burst order off the second rising and falling edge of K clock. Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4. To avoid data contention,at least one NOP operations are required between the last read and the first write operation. Write Operation(Late Write) During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM array. Echo clock operation Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation only when K clock is in the stop mode. Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture data outputs outputs. Bypass Read Operation Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. For this case, data outputs are from the data in registers instead of SRAM array. Programmable Impedance Output Driver The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and VSS, and are equal to RQ/5. For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 continuous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles. Power-Up/Power-Down Supply Voltage Sequencing The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-down. -5- Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM TRUTH TABLE K G B1 B2 B3 DQ Operation L X X X X Hi-Z Clock Stop ↑ X H L X Hi-Z No Operation, Pipeline High-Z ↑ L L H H DOUT Load Address, Single Read ↑ L L H L DOUT Load Address, Double Read ↑ X L L H DIN Load Address, Single Write ↑ X L L L DIN Load Address, Double Write ↑ X H H X B Increment Address, Continue NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care". - K & K are complementary. BURST SEQUENCE TABLE 4 Burst Operation for Interleaved Burst (LBO = VDDQ) Case 1 Interleaved Burst First Address Fourth Address Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V. 4 Burst Operation for Linear Burst (LBO = VSS) Linear Burst Mode First Address Fourth Address Case 1 Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 -6- Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM BUS CYCLE STATE DIAGRAM LOAD NEW ADDRESS 3 ,B 3 B1 B1 B1 B1 ,B B2 B2 ,B B2 B2 ,B 3 3 B1, B2 B1, B2 B1, B2 B1, B2 INCREMENT ADDRESS B1, B2 B1 , B2 B1, B2 B1 , B2 B1 , B2 B1, B2 POWER UP WRITE DDR INCREMENT ADDRESS B1 , B2 INCREMENT ADDRESS B1 , B2 INCREMENT ADDRESS READ DDR B1, B2 B1, B2 WRITE SDR B1, B2 B1, B2 READ SDR NO OP NOTE : 1. State transitions ; B1 =(Load Address), B1=(Increment Address, Continue) B2 =(Read), B2 =(Write) B3 =(Single Data Rate), B3 =(Double Data Rate) -7- Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Core Supply Voltage Relative to VSS Parameter VDD -0.5 to 3.13 V Output Supply Voltage Relative to VSS VDDQ -0.5 to 2.3 V VIN -0.5 to VDDQ+0.5 (2.3V MAX) V Voltage on any pin Relative to VSS Output Short-Circuit Current(per I/O) IOUT 25 mA Storage Temperature TSTR -55 to 125 °C NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data. Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS Symbol Min Typ Max Unit Core Power Supply Voltage Parameter VDD 1.7 2.5 2.63 V Output Power Supply Voltage VDDQ 1.4 1.5 1.9 V VIH VREF+0.1 - VDDQ+0.3 V 1, 2 1, 3 Input High Level Voltage Note Input Low Level Voltage VIL -0.3 - VREF-0.1 V Input Reference Voltage VREF 0.68 0.75 0.95 V Clock Input Signal Voltage VIN-CLK -0.3 - VDDQ+0.3 V 1, 4 Clock Input Differential Voltage VDIF-CLK 0.1 - VDDQ+0.6 V 1, 5 Clock Input Common Mode Voltage VCM-CLK 0.68 0.75 0.9 V 1, 6 NOTE :1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=2.6V (2.1V for DQs) (pulse width ≤ 20% of cycle time). 3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.0V (-0.5V for DQs) (pulse width ≤ 20% of cycle time). 4. VIN-CLK specifies the maximum allowable DC level for the differential clock. i.e VIL-CLK and VIH-CLK. 5. VDIF-CLK specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between VIL-CLK and VIH-CLK. 6. VCM-CLK specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock. DC CHARACTERISTICS Parameter Symbol Min Max Unit Note - 540 490 440 420 mA 1,2 mA 1,2 1 Average Power Supply Operating Current(x36) (Cycle time = tKHKH min) IDD37 IDD33 IDD30 IDD27 Average Power Supply Operating Current(x18) (Cycle time = tKHKH min) IDD37 IDD33 IDD30 IDD27 - 510 460 410 390 Stop Clock Standby Current (VIN=VDD-0.2V or 0.2V fixed, K=Low, K=High) ISB1 - 150 mA Input Leakage Current (VIN=VSS or VDDQ) ILI -1 1 µA Output Leakage Current (VOUT=VSS or VDDQ) ILO -1 1 µA Output High Voltage(Programmable Impedance Mode) VOH1 VDDQ/2 VDDQ V Output Low Voltage(Programmable Impedance Mode) VOL1 VSS VDDQ/2 V 4 Output High Voltage(IOH=-0.1mA) VOH2 VDDQ-0.2 VDDQ V 5 Output Low Voltage(IOL=0.1mA) VOL2 VSS 0.2 V 5 3 NOTE :1. Minimum cycle. IOUT=0mA. 2. 50% read cycles. 3. |IOH|=(VDDQ/2)/(RQ/5)±15% @VOH=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω. 4. |IOL|=(VDDQ/2)/(RQ/5)±15% @VOL=VDDQ/2 for 175Ω ≤ RQ ≤ 350Ω. 5. Minimum Impedance Mode when ZQ pin is connected to VSS. -8- Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM PIN CAPACITANCE Parameter Input Capacitance Data Output Capacitance Symbol Test Condition TYP Max Unit CIN VIN=0V - 4 pF COUT VOUT=0V - 5 pF Max Unit Note V - VREF - 0.4 V - V - V - Note NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=1MHz) AC INPUT CHARACTERISTICS Parameter Symbol Min AC Input Logic High VIH (AC) VREF + 0.4 AC Input Logic Low VIL (AC) Clock Input Differential Voltage VDIF (AC) VREF Peak-to-Peak AC Voltage VREF (AC) 0.8 5% VREF (DC) AC INPUT DEFINITION CK VDIF(AC) CK VIH(AC) VREF Setup Time VIL(AC) Hold Time AC TEST CONDITIONS(TA=0 to 70°C, VDD=1.7 -2.63V, VDDQ=1.5V) Symbol Value Unit Input High/Low Level Parameter VIH/VIL 1.25/0.25 V - Input Reference Level VREF 0.75 V - Input Rise/Fall Time TR/TF 0.5/0.5 ns - Output Timing Reference Level 0.75 V - Clock Input Timing Reference Level Cross Point V - Output Load See Below -9- - Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM AC TEST OUTPUT LOAD 50Ω 0.75V 50Ω 5pF 25Ω DQ 0.75V 50Ω 0.75V 50Ω 5pF AC TIMING CHARACTERISTICS PARAMETER SYMBOL -33 -37 -30 -27 Min Max Min Max Min Max Min Max UNITS NOTES Clock Clock Cycle Time tKHKH 2.66 - 3.0 - 3.3 - 3.63 - ns Clock High Pulse Width tKHKL 1.3 - 1.3 - 1.5 - 1.7 - ns Clock Low Pulse Width tKLKH 1.3 - 1.3 - 1.5 - 1.7 - ns Address Setup Time tAVKH 0.4 - 0.4 - 0.4 - 0.5 - ns Control(B1,B2,B3) Setup Time tBVKH 0.4 - 0.4 - 0.4 - 0.5 - ns Data Setup Time tDVKX 0.25 - 0.3 - 0.3 - 0.4 - ns 1 Setup Times 2 Hold Times Address Hold Time tKHAX 0.4 - 0.4 - 0.4 - 0.5 - ns Control(B1,B2,B3) Hold Time tKHBX 0.4 - 0.4 - 0.4 - 0.5 - ns Data Hold Time tKXDX 0.25 - 0.3 - 0.3 - 0.4 - ns 2 Output Times Echo Clock High Pulse Width tCHCL tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1 tKHKL-0.1 tKHKL+0.1 ns 2 Echo Clock Low Pulse Width tCLCH tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1 tKLKH-0.1 tKLKH+0.1 ns 2 Clock Crossing to Echo Clock tCXCH ns 3 3 0.5 2.3 0.5 2.3 0.5 2.3 0.5 2.3 Clock Crossing to Echo Clock tCXCL 0.5 2.3 0.5 2.3 0.5 2.3 0.5 2.3 ns Echo Clock High to Output Vaild tCHQV -0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns Echo Clock Low to Output Valid tCLQV -0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns Echo Clock High to Output Hold tCHQX -0.20 Echo Clock Low to Output Hold tCLQX -0.20 Echo Clock High to Output High-Z tCHQZ -0.20 -0.20 0.20 Echo Clock High to Output Low-Z tCHLZ -0.20 G Low to Output Valid tGLQV - G High to Output Low-Z tGHQX 0.5 G High to Output High-Z tGHQZ - -0.20 -0.20 0.20 -0.20 1.7 - - ns 0.20 ns 2.0 ns ns 4 2.0 ns 4 -0.20 1.9 0.5 1.7 ns -0.20 0.20 -0.20 1.7 0.5 1.7 -0.20 - ns 0.5 1.9 - 4 Notes: 1. The maximum cycle time must be limited to guarantee AC timing specification. 2. This parameter is guaranteed by design, and may not be tested at values shown in the table. 3. This parameter refers to CQ and CQ rising and falling edges. 4. This parameter is only for 16Mb density 5. K and K Clocks must be used differencitally to meet AC timing specifications. - 10 Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES (Burst Length=4, 2) NOP 1 READ READ READ CONTINUE READ CONTINUE READ NOP (burst of 4) (burst of 4) (burst of 2) 2 5 4 3 NOP 7 6 8 WRITE WRITE (burst of 4) 9 READ CONTINUE READ (burst of 4) 10 CONTINUE 12 11 K tKHKH tKHKL tKLKH K B1 B2 tBVKH tKHBX B3 SA A5 A0 tAVKH A2 A1 tKHAX G tGHQZ tGHQX DQ Q01 QX2 tKXCV tCHQV tCHQZ A3 Q02 Q03 Q04 tCHQX Q51 Q52 Q53 tCLQV Q54 Q11 Q12 tKHDX tGLQV tGLQX tDVKH D21 D22 D23 D24 Q31 tKXCL tCHCL tCLCH tCHLZ CQ CQ DON’T CARE UNDEFINED NOTE 1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc. 2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present. 3. Doing more than one Read Continue or Write Continue will cause the address to wrap around. - 11 Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES (Burst Length=4, 2, 1) NOP READ (burst of 4) 1 READ CONTINUE 2 3 READ READ CONTINUE CONTINUE 4 5 READ NOP (burst of 1) 6 NOP 7 8 WRITE WRITE (burst of 2) 9 READ CONTINUE READ CONTINUE (burst of 2) 10 11 12 K tKHKH tKHKL tKLKH K B1 B2 tBVKH tKHBX B3 tAVKH A2 A1 A0 SA A3 tDVKH tKHAX G tGHQZ tGHQX DQ Q01 QX1 Q02 Q03 Q04 Q11 tKHDX D21 tGLQV tGLQX D22 Q31 tKXCV tCHQV tCHQZ tCHQX tKXCL tCHCL tCLCH tCHLZ CQ CQ DON’T CARE UNDEFINED NOTE : 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc. 2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present. 3. This devices supports cycle lengths of 1, 2, 4. Continue(B1=HIGH, B2=HIGH, B3=X) up to three times following a B1 operation. Any further Continue assertions constitute invalid operations. 4. This device will have an address wraparound if further Continues are applied. - 12 Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Block Diagram JTAG Instruction Coding IR2 IR1 IR0 SRAM CORE SA SA TDI TDO Output Notes Boundary Scan Register 1 IDCODE Identification Register 3 SAMPLE-Z Boundary Scan Register 2 0 0 EXTEST 0 0 1 0 1 0 0 1 1 RESERVED Do Not Use 6 1 0 0 SAMPLE Boundary Scan Register 5 1 0 1 RESERVED Do Not Use 6 1 1 0 RESERVED Do Not Use 6 1 1 1 BYPASS Bypass Register 4 NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. TDO 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. BYPASS Reg. Identification Reg. Instruction Reg. Control Signals TMS TCK Instruction 0 TAP Controller 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 Select DR 1 Select IR 0 1 0 1 Capture DR 0 0 1 Pause DR 1 Exit2 DR 1 Update DR 0 - 13 Shift IR 1 Exit1 DR 0 1 Capture IR 0 Shift DR 1 1 0 1 Exit1 IR 0 0 0 Pause IR 1 Exit2 IR 1 Update IR 0 0 0 1 Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register Boundary Scan 512Kx36 3 bits 1 bits 32 bits 68 bits 1M x 18 3 bits 1 bits 32 bits 49 bits ID REGISTER DEFINITION Part Revision Number (31:28) Part Configuration (27:18) Vendor Definition (17:12) Samsung JEDEC Code (11: 1) Start Bit (0) 512Kx36 0000 00111 00100 XXXXXX 00001001110 1 1M x 18 0000 01000 00011 XXXXXX 00001001110 1 BOUNDARY SCAN EXIT ORDER(x36) BOUNDARY SCAN EXIT ORDER(x18) 36 4A SA SA 6A 35 26 4A SA SA 6A 25 37 4C SA SA 6C 34 27 4C SA SA 6C 24 38 3A SA SA 7A 33 28 3A SA SA 7A 23 39 3B SA SA 7B 32 29 3B SA SA 7B 22 40 3C SA SA 7C 31 30 3C SA SA 7C 21 41 3D SA SA 7D 30 31 3D SA SA 7D 20 32 2B DQ 42 2B DQ DQ 8B 29 43 1B DQ DQ 9B 28 DQ 9B 19 44 2D DQ DQ 8D 27 DQ 8D 18 45 3F DQ DQ 7F 26 DQ 7F 17 46 1D DQ DQ 9D 25 33 1D DQ 47 2F CQ CQ 8F 24 34 2F CQ 48 1F DQ DQ 9F 23 DQ 9F 16 49 3H DQ DQ 7H 22 50 2H DQ DQ 8H 21 DQ 8H 15 51 1H DQ DQ 9H 52 5A ZQ G 5C 14 35 3H DQ 20 36 1H DQ 19 37 5A ZQ G 5C 53 5B B1 K 5G 18 38 5B B1 K 5G 13 54 5K B2 K 5H 17 39 5K B2 K 5H 12 55 5L B3 MODE 6L 16 40 5L B3 MODE 6L 11 56 4L LBO DQ 9K 15 41 4L LBO DQ 9K 10 57 1K DQ DQ 8K 14 58 2K DQ DQ 7K 13 42 2K DQ DQ 7K 9 59 3K DQ DQ 9M 12 60 1M DQ CQ 8M 11 43 1M DQ CQ 8M 8 DQ 9P 7 61 2M CQ DQ 9P 10 62 1P DQ DQ 7M 9 63 3M DQ DQ 8P 8 44 3M DQ 64 2P DQ DQ 9T 7 45 2P DQ 46 1T DQ 65 1T DQ DQ 8T 6 66 2T DQ SA 7P 5 DQ 8T 6 SA 7P 5 67 3T SA SA 7T 4 47 3P SA SA 7T 4 68 4R SA SA 6R 3 48 3T SA SA 6R 3 SA 5T 2 49 4R SA SA 5T 2 SA 5R 1 SA 5R 1 * Reserved for Mode Pin * Reserved for Mode Pin - 14 Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM JTAG DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power Supply Voltage VDD 1.7 2.5 2.6 V Input High Level VIH 0.7*VDD - VDD+0.3 V Input Low Level VIL -0.3 - 0.3*VDD V Output High Voltage(IOH=-2mA) VOH 0.75*VDD - VDD V Output Low Voltage(IOL=2mA) VOL VSS - 0.25*VDD V Note NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Parameter Symbol Min Input High/Low Level VIH/VIL VDD/0.0 V Input Rise/Fall Time TR/TF 1.0/1.0 ns VDD/2 V Input and Output Timing Reference Level Unit Note 1 NOTE : 1. See SRAM AC test output load on page 5. JTAG AC Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tCHCH TMS tCHCL tMVCH tCHMX tDVCH tCHDX tCLCH TDI tCLQV TDO - 15 Rev 1.1 Jan. 2005 K7D163674B K7D161874B 512Kx36 & 1Mx18 SRAM 153 BGA PACKAGE DIMENSIONS 1.27 0.050 12.50 ±0.10 0.492 ±0.004 14.00 ±0.10 0.551 ±0.004 0.56 ±0.04 0.022 ±0.002 0.90 ±0.10 0.035 ±0.004 2.21 MAX 0.087 1.27 0.050 U T RPNML K J HGF EDCBA 9 8 7 6 5 4 3 2 1 22.00 ±0.10 0.866 ±0.004 20.50 ±0.10 0.807 ±0.004 0.60 ±0.10 0.024 ±0.004 153-∅ ∅ 0.3/0.012MAX 0.75 ±0.15 0.030 ±0.006 0.15 0.006 MAX BOTTOM VIEW TOP VIEW NOTE : 1. All Dimensions are in Millimeters. 2. Solder Ball to PCS Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX. 153 BGA PACKAGE THERMAL CHARACTERISTICS Symbol Thermal Resistance Unit Junction to Ambient(at still air) Parameter Theta_JA TBD °C/W Junction to Case Theta_JC TBD °C/W Junction to Board Theta_JB TBD °C/W Note NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA. - 16 Rev 1.1 Jan. 2005