K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM 18Mb DDRII SRAM Specification 165FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram Dec. 26, 2002 Preliminary 0.2 1. Add the speed bin (-25) Jan. 27, 2003 Preliminary 0.3 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) Mar. 20, 2003 Preliminary 0.4 1. Change the Maximum Clock cycle time. 2. Correct the 165FBGA package ball size. April. 4, 2003 Preliminary 0.5 1. Add the power up/down sequencing comment. 2. Update the DC current parameter (Icc and Isb). 3. Change the Max. speed bin from -33 to -30. June. 20, 2003 Preliminary 0.6 1. Change the ISB1. Oct. 20. 2003 Preliminary Rev. No. Speed Bin From To -30 200 230 -25 180 210 -20 160 190 -16 140 170 1.0 1. Final spec release Oct. 31, 2003 Final 2.0 1. Delete the x8 Org. 2. Delete the 300MHz speed bin Nov. 28, 2003 Final 3.0 1. Add the Industrial temp. & Lead Free Package Nov. 10. 2004 Final 4.0 1. Add the 300MHz speed bin Mar. 29. 2006 Final 5.0 1. Change Vss/SA to NC/SA in Pin Configuration Jul. 26 2006 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -2- Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM 512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM FEATURES • 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide output data valid window and future frequency scaling. • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/ -0.1V for 1.8V I/O. • Separate independent read and write data ports • HSTL I/O • Synchronous pipeline read with self timed late write. • Registered address, control and data input/output. • Full data coherency, providing most current data. • DDR (Double Data Rate) Interface on read and write ports. • Fixed 2-bit burst for both read and write operation. • Clock-stop supports to reduce current. • Two input clocks (K and K) for accurate DDR timing at clock rising edges only. • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches. • Two echo clocks (CQ and CQ) to enhance output data traceability. • Single address bus. • Byte write (x18, x36) function. • Simple depth expansion with no data contention. • Programmable output impedance. • JTAG 1149.1 compatible test access port. • 165FBGA(11x15 ball array) with body size of 13mmx15mm. & Lead Free • Operating in commercial and industrial temperature range. Part Number Organization X36 X18 Cycle Access Unit Time Time K7J163682B-E(F)C(I)25 4.0 0.45 ns K7J163682B-E(F)C(I)25 4.0 0.45 ns K7J163682B-E(F)C(I)20 5.0 0.45 ns K7J163682B-E(F)C(I)16 6.0 0.50 ns K7J161882B-E(F)C(I)25 4.0 0.45 ns K7J161882B-E(F)C(I)25 4.0 0.45 ns K7J161882B-E(F)C(I)20 5.0 0.45 ns K7J161882B-E(F)C(I)16 6.0 0.50 ns * -E(F)C(I) E(F) [Package type] : E-Pb Free, F-Pb C(I) [Operating Temperature] : C-Commercial, I-Industrial FUNCTIONAL BLOCK DIAGRAM K K C WRITE DRIVER 512kx36 (1Mx18) MEMORY ARRAY 36 (or 18) 72 (or 36) OUTPUT DRIVER CTRL LOGIC 18 (or 19) OUTPUT SELECT 4(or 2) ADD REG 36 (or 18) OUTPUT REG R/W LD BWX 18 (or 19) DATA REG SENSE AMPS ADDRESS 36 (or 18) WRITE/READ DECODE D(Data in) 36 (or 18) Q(Data Out) CQ, CQ (Echo Clock out) CLK GEN SELECT OUTPUT CONTROL C Notes: 1. Numbers in ( ) are for x18 device DDR II SRAM and Double Data Rate II comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology. -3- Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM PIN CONFIGURATIONS(TOP VIEW) K7J163682B(512Kx36) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/SA* NC/SA* R/W BW2 K BW1 LD NC/SA* NC/SA* CQ B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8 C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6 Q5 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1 P Q35 D35 Q26 SA SA C SA SA Q9 D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI Notes : 1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 3A for 72Mb, 9A for 36Mb, 10A for 144Mb and 2A for 288Mb. 2. BW0 controls write to D0:D8, BW1 controls write to D9:D17, BW2 controls write to D18:D26 and BW3 controls write to D27:D35. PIN NAME SYMBOL PIN NUMBERS DESCRIPTION K, K 6B, 6A Input Clock C, C 6P, 6R Input Clock for Output Data CQ, CQ 11A, 1A Output Echo Clock Doff 1H DLL Disable when low SA 4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs D0-35 10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L 9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N 1C,1D,2E,1G,1J,2K,1M,1N,2P Data Inputs Q0-35 11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L 9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N 3P,1B,2C,1E,1F,2J,1K,1L,2M,1P Data Outputs R/W 4A Read, Write Control Pin, Read active when high LD 8A Synchronous Load Pin, bus Cycle sequence is to be defined when low BW0, BW1,BW2, BW3 7B,7A,5A,5B Block Write Control Pin, active when low VREF 2H,10H Input Reference Voltage ZQ 11H Output Driver Impedance Control Input VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply (1.8 V) VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply (1.5V or 1.8V) VSS 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M, 8M,4N,8N Ground TMS 10R JTAG Test Mode Select TDI 11R JTAG Test Data Input TCK 2R JTAG Test Clock TDO 1R JTAG Test Data Output NC 2A,3A,10A,9A No Connect NOTE 1 2 3 Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally. -4- Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM PIN CONFIGURATIONS(TOP VIEW) K7J161882B(1Mx18) 1 2 3 4 5 6 7 8 9 10 11 A CQ VSS/SA* NC/SA* R/W BW1 K NC LD SA VSS/SA* CQ B NC Q9 D9 SA NC K BW0 SA NC NC Q8 D8 C NC NC D10 VSS SA SA SA VSS NC Q7 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS SA SA SA VSS NC NC D1 P NC NC Q17 SA SA C SA SA NC D0 Q0 R TDO TCK SA SA SA C SA SA SA TMS TDI Notes: 1. * Checked No Connect (NC) pins are reserved for higher density address, i.e. 3A for 36Mb, 10A for 72Mb and 2A for 144Mb. 2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17. PIN NAME SYMBOL PIN NUMBERS DESCRIPTION K, K 6B, 6A Input Clock C, C 6P, 6R Input Clock for Output Data CQ, CQ 11A, 1A Output Echo Clock Doff 1H DLL Disable when low SA 9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs D0-17 10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D, 3F,2G,3J,3L,3M,2N Data Inputs Q0-17 11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E, 2F,3G,3K,2L,3N,3P Data Outputs R/W 4A Read, Write Control Pin, Read active when high LD 8A Synchronous Load Pin, bus Cycle sequence is to be defined when low BW0, BW1 7B, 5A Block Write Control Pin,active when low VREF 2H,10H Input Reference Voltage ZQ 11H Output Driver Impedance Control Input VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply (1.8 V) VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply (1.5V or 1.8V) VSS 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground TMS 10R JTAG Test Mode Select JTAG Test Data Input TDI 11R TCK 2R JTAG Test Clock TDO 1R JTAG Test Data Output NC 2A,3A,7A,10A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9 F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M,2M, 9M,1N,9N,10N,1P,2P,9P No Connect NOTE 1 2 3 Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally. -5- Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM GENERAL DESCRIPTION The K7J163682B and K7J161882B are 18,874,368-bits DDR Separate I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7J163682B and 1,048,576 words by 18 bits for K7J161882B. The DDR SIO operation is possible by supporting DDR read and write operations through separate data output and input ports. Memory bandwidth is higher than DDR SRAM without separate input output as separate read and write ports eliminate bus turn around cycle. Address, data inputs, and all control signals are synchronized to the input clock (K or K). Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high, the data outputs are synchronized to the input clocks (K and K). Read data are referenced to echo clock (CQ or CQ) outputs. Read address and write address are registered on rising edges of the input K clocks. Common address bus is used to access address both for read and write operations. The internal burst counter is fixed to 2-bit sequential for both read and write operations. Synchronous pipeline read and late write enable high speed operations. Simple depth expansion is accomplished by using LD for port selection. Byte write operation is supported with BW0 and BW1 (BW2 and BW3) pins for x18 (x36) device. Nibble write operation is supported with NW0 and NW1 pins for x8 device. IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system. The K7J163682B and K7J161882B are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce. READ OPERATIONS Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K. Address is presented and stored in the read address register synchronized with K clock. For 2-bit burst DDR operation, it will access two 36-bit or 18-bit or 8-bit data words with each read command. The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge. Next burst data is triggered by the rising edge of following C clock rising edge. Continuous read operations are initiated with K clock rising edge. And pipelined data are transferred out of device on every rising edge of both C and C clocks. In case C and C tied to high, output data are triggered by K and K instead of C and C. When the LD is disabled after a read operation, the K7J163682B and K7J161882B will first complete burst read operation before entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state. ECHO CLOCK OPERATION To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are synchronized with internal data output. Echo clocks run free during normal operation. The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver. POWER-UP/POWER-DOWN SUPPLY VOLTAGE SEQUENCING The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-down. -6- Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM WRITE OPERATIONS Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K. Address is presented and stored in the write address register synchronized with next K clock. For 2-bit burst DDR operation, it will write two 36-bit or 18-bit or 8-bit data words with each write command. The first “late writed” data is transferred and registered in to the device synchronous with next K clock rising edge. Next burst data is transferred and registered synchronous with following K clock rising edge. Continuous write operations are initiated with K rising edge. And “late writed” data is presented to the device on every rising edge of both K and K clocks. When the LD is disabled, the K7J163682B and K7J161882B will enter into deselect mode. The device disregards input data presented on the same cycle W disabled. The K7J163682B and K7J161882B support byte write operations. With activating BW0 or BW1 (BW2 or BW3) in write cycle, only one byte of input data is presented. In K7J161882B, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17. And in K7J163682B BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35. PROGRAMMABLE IMPEDANCE OUTPUT BUFFER OPERATION The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor (RQ). The value of RQ (within 15%) is five times the output impedance desired. For example, 250Ω resistor will give an output impedance of 50Ω. Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates are transparent to the user and do not produce access time “push-outs” or other anomalous behavior in the SRAM. There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles. CLOCK CONSIDERATION K7J163682B and K7J161882B utilizes internal DLL (Delay-Locked Loops) for maximum output data valid window. It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles. Circuitry automatically resets the DLL when absence of input clock is detected. SINGLE CLOCK MODE K7J163682B and K7J161882B can be operated with the single clock pair K and K, instead of C or C for output clocks. To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high during operation. After power up, this device can′t change to or from single clock mode. System flight time and clock skew could not be compensated in this mode. DEPTH EXPANSION Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal for each bank. Before chip deselected, all read and write pending operations are completed. -7- Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM STATE DIAGRAM POWER-UP LOAD NOP LOAD LOAD NEW ADDRESS LOAD LOAD LOAD READ WRITE DDR READ LOAD DDR WRITE Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1. 2. “LOAD” refers to read new address active status with LD=Low, “LOAD” refers to read new address inactive status with LD=High. 3. “READ” refers to read active read status with R/W=High, “WRITE” refers to write active status with R/W=Low -8- Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE K LD R/W Stopped X ↑ D Q OPERATION D(A0) D(A1) Q(A0) Q(A1) X Previous state Previous state Previous state Previous state Clock Stop H X X X High-Z High-Z No Operation ↑ L H X X DOUT at C(t+1) DOUT at C(t+2) Read ↑ L L Din at K(t+1) Din at K(t+1) High-Z High-Z Write Notes: 1. X means “Don′t Care”. 2. The rising edge of clock is symbolized by ( ↑ ). 3. Before enter into clock stop status, all pending read and write operations will be completed. WRITE TRUTH TABLE(x18) K K ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ BW0 BW1 OPERATION L L WRITE ALL BYTEs ( K↑ ) L L WRITE ALL BYTEs ( K↑ ) L H WRITE BYTE 0 ( K↑ ) L H WRITE BYTE 0 ( K↑ ) H L WRITE BYTE 1 ( K↑ ) H L WRITE BYTE 1 ( K↑ ) H H WRITE NOTHING ( K↑ ) H H WRITE NOTHING ( K↑ ) Notes: 1. X means “Don′t Care”. 2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ). 3. Assumes a WRITE cycle was initiated. 4. This table illustrates operation for x18 devices. WRITE TRUTH TABLE(x36) K K ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ BW0 BW1 BW2 BW3 OPERATION L L L L WRITE ALL BYTEs ( K↑ ) L L L L WRITE ALL BYTEs ( K↑ ) L H H H WRITE BYTE 0 ( K↑ ) L H H H WRITE BYTE 0 ( K↑ ) H L H H WRITE BYTE 1 ( K↑ ) H L H H WRITE BYTE 1 ( K↑ ) H H L L WRITE BYTE 2 and BYTE 3 ( K↑ ) H H L L WRITE BYTE 2 and BYTE 3 ( K↑ ) H H H H WRITE NOTHING ( K↑ ) H H H H WRITE NOTHING ( K↑ ) Notes: 1. X means “Don′t Care”. 2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ). 3. Assumes a WRITE cycle was initiated. -9- Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM ABSOLUTE MAXIMUM RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VDD Supply Relative to VSS VDD -0.5 to 2.9 V Voltage on VDDQ Supply Relative to VSS VDDQ -0.5 to VDD V VIN -0.5 to VDD+0.3 V TSTG -65 to 150 °C Voltage on Input Pin Relative to VSS Storage Temperature Operating Temperature Commercial TOPR 0 to 70 °C Industrial TOPR -40 to 85 °C TBIAS -10 to 85 °C Storage Temperature Range Under Bias *Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation. DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C) PARAMETER SYMBOL TEST CONDITIONS Input Leakage Current IIL VDD=Max ; VIN=VSS to VDDQ Output Leakage Current IOL Output Disabled, Operating Current (x36) : DDR ICC MIN MAX -2 +2 µA µA -2 +2 -30 - 600 VDD=Max , IOUT=0mA -25 - 550 Cycle Time ≥ tKHKH Min -20 - 500 -16 Operating Current (x18) : DDR ICC - 500 VDD=Max , IOUT=0mA -25 - 450 Cycle Time ≥ tKHKH Min -20 - 400 -16 Standby Current (NOP): DDR ISB1 IOUT=0mA, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V Output High Voltage VOH1 Output Low Voltage VOL1 Output High Voltage VOH2 IOH=-1.0mA Output Low Voltage VOL2 IOL=1.0mA 1,5 mA 1,5 mA 1,6 350 -30 - 230 -25 - 210 -20 - 190 -16 mA 450 -30 Device deselected, UNIT NOTE - 170 VDDQ/2-0.12 VDDQ/2+0.12 V 2,7 VDDQ/2-0.12 VDDQ/2+0.12 V 3,7 VDDQ-0.2 VDDQ V 4 VSS 0.2 V 4 Input Low Voltage VIL -0.3 VREF-0.1 V 8,9 Input High Voltage VIH VREF+0.1 VDDQ+0.3 V 8,10 Notes: 1. Minimum cycle. IOUT=0mA. 2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω. 3. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω. 4. Minimum Impedance Mode when ZQ pin is connected to VDDQ. 5. Operating current is calculated with 50% read cycles and 50% write cycles. 6. Standby Current is only after all pending read and write burst operations are completed. 7. Programmable Impedance Mode. 8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 9. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns). 10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns). - 10 - Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C) PARAMETER MAX UNIT NOTES VREF + 0.2 - V 1,2 - VREF - 0.2 V 1,2 SYMBOL MIN Input High Voltage VIH (AC) Input Low Voltage VIL (AC) Notes: 1. This condition is for AC function test only, not for AC parameter test. 2. To maintain a valid level, the transition edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC) b) Reach at least the target AC level c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC) Overershoot Timing Undershoot Timing 20% tKHKH(MIN) VIH VDDQ+0.5V VDDQ+0.25V VSS VDDQ VSS-0.25V VSS-0.5V 20% tKHKH(MIN) VIL Note: For power-up, VIH ≤ VDDQ+0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C) PARAMETER SYMBOL MIN MAX UNIT VDD 1.7 1.9 V VDDQ 1.4 1.9 V Reference Voltage VREF 0.68 0.95 V Ground VSS 0 0 V Supply Voltage AC TEST CONDITIONS Symbol Value Unit Core Power Supply Voltage VDD 1.7~1.9 V Output Power Supply Voltage VDDQ 1.4~1.9 V Input High/Low Level VIH/VIL 1.25/0.25 V Input Reference Level VREF 0.75 V Input Rise/Fall Time TR/TF 0.3/0.3 ns VDDQ/2 V Parameter Output Timing Reference Level AC TEST OUTPUT LOAD VREF 0.75V 50Ω SRAM Zo=50Ω ZQ Note: Parameters are tested with RQ=250Ω - 11 - VDDQ/2 250Ω Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C) PARAMETER SYMBOL -30 -25 -20 -16 UNIT NOTE MIN MAX MIN MAX MIN MAX MIN MAX 3.30 8.40 4.00 8.40 5.00 8.40 6.00 8.40 ns 0.20 ns Clock Clock Cycle Time (K, K, C, C) tKHKH Clock Phase Jitter (K, K, C, C) tKC var Clock High Time (K, K, C, C) tKHKL 1.32 1.60 2.00 2.40 ns Clock Low Time (K, K, C, C) tKLKH 1.32 1.60 2.00 2.40 ns Clock to Clock (K↑ → K↑, C↑ → C↑) tKHKH 1.49 1.80 2.20 2.70 ns 0.20 0.00 1.80 0.20 tKHCH 0.00 DLL Lock Time (K, C) tKC lock 1024 1024 1024 1024 cycle K Static to DLL reset tKC reset 30 30 30 30 ns Clock to data clock (K↑ → C↑, K↑→ C↑) 1.45 0.20 0.00 2.30 0.00 2.80 5 ns 6 Output Times C, C High to Output Valid tCHQV C, C High to Output Hold tCHQX C, C High to Echo Clock Valid tCHCQV C, C High to Echo Clock Hold tCHCQX CQ, CQ High to Output Valid tCQHQV CQ, CQ High to Output Hold tCQHQX 0.45 -0.45 0.45 -0.45 0.45 -0.45 0.45 -0.45 0.27 -0.27 0.45 -0.45 0.45 -0.45 0.30 -0.30 0.45 0.50 -0.50 0.50 -0.50 0.35 -0.35 0.45 3 ns 3 ns ns 0.40 -0.40 0.45 ns 0.50 ns 7 ns 7 C, High to Output High-Z tCHQZ ns 3 C, High to Output Low-Z tCHQX1 -0.45 -0.45 -0.45 -0.50 ns 3 tAVKH 0.40 0.50 0.60 0.70 ns Control inputs valid to K rising edge tIVKH 0.40 0.50 0.60 0.70 ns Data-in valid to K, K rising edge tDVKH 0.30 0.35 0.40 0.50 ns tKHAX 0.40 0.50 0.60 0.70 ns K rising edge to control inputs hold tKHIX 0.40 0.50 0.60 0.70 ns K, K rising edge to data-in hold tKHDX 0.30 0.35 0.40 0.50 ns Setup Times Address valid to K rising edge 2 Hold Times K rising edge to address hold Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control signal are R and W. In case of BW0,BW1 (BW2, BW3, also for x36) signal follow the data setup/hold times. 3. If C,C are tied high, K,K become the references for C,C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. - 12 - Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM PIN CAPACITANCE PRMETER SYMBOL TESTCONDITION Typ MAX Unit CIN VIN=0V 4 5 pF Input and Output Capacitance COUT VOUT=0V 6 7 pF Clock Capacitance CCLK - 5 6 pF Address Control Input Capacitance NOTES Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V. 2. Periodically sampled and not 100% tested. THERMAL RESISTANCE PRMETER SYMBOL TYP Unit Junction to Ambient θJA 17.1 °C/W Junction to Case θJC 3.3 °C/W NOTES Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site thermal impedance. TJ=TA + PD x θJA APPLICATION INRORMATION SRAM#1 Vt D SA R R=250Ω ZQ R=250Ω CQ CQ Q R W BW0 BW1 C C K K Data In Data Out Address R W BW SRAM#4 CQ CQ Q RW BW0 BW1 C C K K D SA R ZQ ZQ Vt Vt MEMORY CONTROLLER Return CLK Source CLK Return CLK Source CLK Vt Vt R=50Ω Vt=VREF SRAM1 Input CQ SRAM1 Input CQ SRAM4 Input CQ SRAM4 Input CQ - 13 - Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM TIMING WAVE FORMS OF READ,WRITE AND NOP NOP 1 READ (burst of 2) READ (burst of 2) WRITE WRITE NOP (burst of 2) READ (burst of 2) NOP (burst of 2) 2 3 4 5 6 7 8 A4 A5 K tKHKL tKLKH tKHKH tKHKH K LD tIVKH tKHIX R/W A A1 tAVKH A2 A3 tKHAX tKHDX tKHDX tDVKH tDVKH D Q Qxx Q1-1 tKHCH Q1-2 tCHQV D3-1 D3-2 Q2-1 Q2-2 D4-1 D4-2 Q5-1 tCHQV Q5-2 tCQHQV tCHQX tKHCH tCHQX1 tCHQX tCHQZ C tKHKL tKLKH tKHKH tKHKH C tCHCQV tCHCQX CQ tCHCQV tCHCQX CQ Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0. 2. Outputs are disabled one cycle after a NOP. 3. D3-1 refers to input to address A3+0, D3-2 refers to input to address A3+1, i.e the next internal burst address following A3+0. 4. If address A4=A5, data Q5-1=D4-1, data Q5-2=D4-2. Write data is forwarded immediately as read results. - 14 - Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG BLOCK DIAGRAM JTAG INSTRUCTION CODING IR2 IR1 IR0 Instruction TDO Output Notes Boundary Scan Register 1 IDCODE Identification Register 3 SAMPLE-Z Boundary Scan Register 2 0 0 0 EXTEST 0 0 1 0 1 0 A,D 0 1 1 RESERVED Do Not Use 6 K,K 1 0 0 SAMPLE Boundary Scan Register 5 1 0 1 RESERVED Do Not Use 6 1 1 0 RESERVED Do Not Use 6 1 1 1 BYPASS Bypass Register 4 C,C SRAM CORE Q CQ CQ TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. Control Signals TMS TCK TAP Controller NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use. TAP CONTROLLER STATE DIAGRAM 1 Test Logic Reset 0 0 Run Test Idle 1 1 1 Select DR 0 1 Capture DR 0 Shift DR 1 Exit2 DR 1 Update DR 0 - 15 - Select IR 0 1 Capture IR 0 0 1 Exit1 DR 0 Pause DR 1 1 1 0 0 Shift IR 1 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register 512Kx36 3 bits 1 bit 32 bits Boundary Scan 107 bits 1Mx18 3 bits 1 bit 32 bits 107 bits ID REGISTER DEFINITION Part Revision Number (31:29) Part Configuration (28:12) Samsung JEDEC Code (11: 1) Start Bit(0) 512Kx36 000 00def0wx0t0q0b0s0 00001001110 1 1Mx18 000 00def0wx0t0q0b0s0 00001001110 1 Note : Part Configuration /def=001 for 18Mb, /wx=11 for x36, 10 for x18 /t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O BOUNDARY SCAN EXIT ORDER ORDER PIN ID ORDER PIN ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 PIN ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Note: 1. NC pins are read as “X” ( i.e. don′t care.) - 16 - Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM JTAG DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Power Supply Voltage VDD 1.7 1.8 1.9 V Input High Level VIH 1.3 - VDD+0.3 V Input Low Level VIL -0.3 - 0.5 V Output High Voltage(IOH=-2mA) VOH 1.4 - VDD V Output Low Voltage(IOL=2mA) VOL VSS - 0.4 V Note Note: 1. The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Parameter Symbol Min Unit Input High/Low Level VIH/VIL 1.8/0.0 V Input Rise/Fall Time TR/TF 1.0/1.0 ns 0.9 V Input and Output Timing Reference Level Note 1 Note: 1. See SRAM AC test output load on page 11. JTAG AC Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tCHCH tCHCL tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLCH TMS TDI PI (SRAM) tCLQV TDO - 17 - Rev. 5.0 July 2006 K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM 165 FBGA PACKAGE DIMENSIONS 13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array B Top View A C D Side View A G E B F Bottom View ∅H E Symbol Value Units A 13 ± 0.1 mm B 15 ± 0.1 mm C 1.3 ± 0.1 D 0.35 ± 0.05 Note Symbol Value Units E 1.0 mm F 14.0 mm mm G 10.0 mm mm H 0.5 ± 0.05 mm - 18 - Note Rev. 5.0 July 2006