SAMSUNG K7I161882B-FC20

K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
Document Title
512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
Revision History
Rev. No.
History
Draft Date
Remark
0.0
1. Initial document.
Oct. 23. 2002
Advance
0.1
1. Add the speed bin (-33, -30)
2. Delete the speed bin (-25, -13)
Oct. 24. 2002
Premilinary
0.2
1. Change the Boundary scan exit order.
2. Correct the Overshoot and Undershoot timing diagram.
Dec. 16, 2002
Premilinary
0.3
1. Add the speed bin (-25)
Jan. 27, 2003
Premilinary
0.4
1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
Mar. 20, 2003
Premilinary
0.5
1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
April. 4, 2003
Premilinary
0.6
1. Add the power up/down sequencing comment.
2. Update the DC current parameter (Icc and Isb).
3. Change the Max. speed bin from -33 to -30.
June. 20, 2003
Premilinary
0.7
1. Change the ISB1.
Oct. 20. 2003
Premilinary
Speed Bin
From
To
-30
200
230
-25
180
210
-20
160
190
-16
140
170
1.0
1. Final spec release
Oct. 31, 2003
Final
2.0
1. Delete the x8 Org.
2. Delete the 300MHz speed bin
Nov. 28, 2003
Final
3.0
1. Add the 300MHz speed bin
June. 18, 2004
Final
3.1
1. Change the stand-by current(ISB1)
before
after
Isb1
-30 :
230
260
-25 :
210
240
-20 :
190
220
-16 :
170
200
July. 28, 2004
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
• Pipelined, double-data rate operation.
• Common data input/output bus .
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write (x18, x36) function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball array FBGA) with body size of 13x15mm
Part
Number
Cycle
Time
K7I163682B-FC30
3.3
0.45
ns
K7I163682B-FC25
4.0
0.45
ns
K7I163682B-FC20
5.0
0.45
ns
K7I163682B-FC16
6.0
0.50
ns
K7I161882B-FC30
3.3
0.45
ns
K7I161882B-FC25
4.0
0.45
ns
K7I161882B-FC20
5.0
0.45
ns
K7I161882B-FC16
6.0
0.50
ns
Organization
X36
X18
Access
Unit
Time
FUNCTIONAL BLOCK DIAGRAM
36 (or 18)
DATA
REG
K
K
C
OUTPUT DRIVER
72
(or 36)
OUTPUT SELECT
36
(or 18)
OUTPUT REG
4(or 2)
CTRL
LOGIC
512Kx36
(1Mx18)
MEMORY
ARRAY
SENSE AMPS
LD
R/W
BWX
&
BURST
LOGIC
WRITE DRIVER
18
(or 19)
WRITE/READ DECODE
ADDRESS
A0
18 (or 19) ADD REG
36 (or 18)
36 (or 18)
DQ
CQ, CQ
(Echo Clock out)
CLK
GEN
SELECT OUTPUT CONTROL
C
Notes: 1. Numbers in ( ) are for x18 device.
DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
-2-
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I163682B(512Kx36)
1
2
3
4
A
CQ
B
NC
5
6
7
VSS/SA*
NC
DQ27
DQ18
R/W
BW2
K
BW1
SA
BW3
K
BW0
8
9
10
11
LD
SA
VSS/SA*
CQ
SA
NC
NC
DQ8
C
NC
NC
DQ28
VSS
SA
SA0
SA
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
SA
SA
SA
VSS
NC
NC
DQ10
P
NC
NC
DQ26
SA
SA
C
SA
SA
NC
DQ9
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb, 2A for 144Mb .
2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
PIN NAME
SYMBOL
PIN NUMBERS
DESCRIPTION
K, K
6B, 6A
Input Clock
NOTE
C, C
6P, 6R
Input Clock for Output Data
CQ, CQ
11A, 1A
Output Echo Clock
Doff
1H
DLL Disable when low
SA0
6C
Burst Count Address Inputs
SA
9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
DQ0-35
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
Data Inputs Outputs
R/W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1,BW2, BW3
7B,7A,5A,5B
Block Write Control Pin,active when low
VREF
2H,10H
Input Reference Voltage
ZQ
11H
Output Driver Impedance Control Input
VDD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
VSS
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
Ground
TMS
10R
JTAG Test Mode Select
TDI
11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
NC
3A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
No Connect
1
2
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-3-
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7I161882B(1Mx18)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/SA*
SA
R/W
BW1
K
NC
LD
SA
Vss
CQ
B
NC
DQ9
NC
SA
NC
K
BW0
SA
NC
NC
DQ8
C
NC
NC
NC
VSS
SA
SA0
SA
VSS
NC
DQ7
NC
D
NC
NC
DQ10
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
DQ2
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
N
NC
NC
DQ16
VSS
SA
SA
SA
VSS
NC
NC
NC
P
NC
NC
DQ17
SA
SA
C
SA
SA
NC
NC
DQ0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 72Mb.
2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17.
PIN NAME
SYMBOL
PIN NUMBERS
DESCRIPTION
K, K
6B, 6A
Input Clock
NOTE
C, C
6P, 6R
Input Clock for Output Data
CQ, CQ
11A, 1A
Output Echo Clock
Doff
1H
DLL Disable when low
SA0
6C
Burst Count Address Inputs
SA
3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
DQ0-17
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P
Data Inputs Outputs
R/W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1
7B, 5A
Block Write Control Pin,active when low
VREF
2H,10H
Input Reference Voltage
ZQ
11H
Output Driver Impedance Control Input
VDD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
VSS
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
TMS
10R
JTAG Test Mode Select
TDI
11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
NC
7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D
1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P
No Connect
1
2
3
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-4-
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
GENERAL DESCRIPTION
The K7I163682B and K7I1161882B are 18,874,368-bits DDR Common I/O
Synchronous Pipelined Burst SRAMs.
They are organized as 524,288 words by 36bits for K7I163682B and 1,048,576 words by 18 bits for K7I161882B for K7I160882B.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7I163682B and K7I161882B are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the LD is disabled after a read operation, the K7I163682B and K7I161882B will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
-5-
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
Write Operations
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with next K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.
The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initated with K rising edge.
And "late writed" data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7I163682B and K7I161882B will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7I163682B and K7I161882B support byte write operations.
With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented.
In K7I161882B, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7I163682B BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
Programmable Impedance Output Buffer Operation
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250Ω resistor will give an output impedance of 50Ω.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the
SRAM needs 1024 non-read cycles.
Clock Consideration
K7I163682B and K7I161882B utilize internal DLL(Delay-Locked Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Single Clock Mode
K7I163682B and K7I161882B can be operated with the single clock pair K and K,
insted of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can′t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Depth Expansion
Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal
for each bank.
Before chip deselected, all read and write pending operations are completed.
-6-
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
LINEAR BURST SEQUENCE TABLE
Case 1
SA0
0
1
BURST SEQUENCE
First Address
Second Address
Case 2
SA0
1
0
STATE DIAGRAM
POWER-UP
LOAD
NOP
LOAD
LOAD NEW ADDRESS
LOAD
LOAD
LOAD
READ
WRITE
DDR READ
LOAD
DDR WRITE
Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "LOAD" refers to read new address active status with LD=Low, "LOAD" refers to read new address inactive status with LD=High.
3. "READ" refers to read active read status with R/W=High, "WRITE" refers to write active status with R/W=Low
-7-
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Q
K
LD
R/W
Stopped
X
X
↑
H
X
↑
L
H
↑
L
L
Din at K(t+1)
OPERATION
Q(A0)
Q(A1)
Previous state
Previous state
Clock Stop
High-Z
High-Z
No Operation
QOUT at C(t+1)
QOUT at C(t+2)
Read
Din at K(t+1)
Write
Notes: 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
WRITE TRUTH TABLE(x18)
K
K
BW0
BW1
OPERATION
L
L
WRITE ALL BYTEs ( K↑ )
↑
L
L
WRITE ALL BYTEs ( K↑ )
L
H
WRITE BYTE 0 ( K↑ )
L
H
WRITE BYTE 0 ( K↑ )
H
L
WRITE BYTE 1 ( K↑ )
↑
↑
↑
↑
↑
↑
↑
H
L
WRITE BYTE 1 ( K↑ )
H
H
WRITE NOTHING ( K↑ )
H
H
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
WRITE TRUTH TABLE(x36)
K
K
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
BW0
BW1
BW2
BW3
OPERATION
L
L
L
L
WRITE ALL BYTEs ( K↑ )
L
L
L
L
WRITE ALL BYTEs ( K↑ )
L
H
H
H
WRITE BYTE 0 ( K↑ )
L
H
H
H
WRITE BYTE 0 ( K↑ )
H
L
H
H
WRITE BYTE 1 ( K↑ )
H
L
H
H
WRITE BYTE 1 ( K↑ )
H
H
L
L
WRITE BYTE 2 and BYTE 3 ( K↑ )
H
H
L
L
WRITE BYTE 2 and BYTE 3 ( K↑ )
H
H
H
H
WRITE NOTHING ( K↑ )
H
H
H
H
WRITE NOTHING ( K↑ )
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
-8-
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
ABSOLUTE MAXIMUM RATINGS*
SYMBOL
RATING
UNIT
Voltage on VDD Supply Relative to VSS
PARAMETER
VDD
-0.5 to 2.9
V
Voltage on VDDQ Supply Relative to VSS
VDDQ
-0.5 to VDD
V
VIN
-0.5 to VDD+0.3
V
TSTG
-65 to 150
°C
Voltage on Input Pin Relative to VSS
Storage Temperature
Operating Temperature
TOPR
0 to 70
°C
Storage Temperature Range Under Bias
TBIAS
-10 to 85
°C
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT NOTE
Input Leakage Current
IIL
VDD=Max ; VIN=VSS to VDDQ
-2
+2
µA
Output Leakage Current
IOL
Output Disabled,
-2
+2
µA
-30
-
600
VDD=Max , IOUT=0mA
-25
-
550
Cycle Time ≥ tKHKH Min
-20
-
500
Operating Current
(x36) : DDR
ICC
-16
Operating Current
(x18) : DDR
ICC
-
500
VDD=Max , IOUT=0mA
-25
-
450
Cycle Time ≥ tKHKH Min
-20
-
400
-16
Standby Current(NOP): DDR
ISB1
IOUT=0mA, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
1,5
mA
1,5
mA
1,6
450
-30
Device deselected,
mA
350
-30
-
260
-25
-
240
-20
-
220
-16
-
200
Output High Voltage
VOH1
VDDQ/2-0.12
VDDQ/2+0.12
V
2,7
Output Low Voltage
VOL1
VDDQ/2-0.12
VDDQ/2+0.12
V
3,7
Output High Voltage
VOH2
IOH=-1.0mA
VDDQ-0.2
VDDQ
V
4
Output Low Voltage
VOL2
IOL=1.0mA
VSS
0.2
V
4
Input Low Voltage
VIL
-0.3
VREF-0.1
V
8,9
Input High Voltage
VIH
VREF+0.1
VDDQ+0.3
V
8,10
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
3. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
4. Minimum Impedance Mode when ZQ pin is connected to VDDQ.
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring
timing parameters.
9. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
10. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
-9-
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTES
Input High Voltage
VIH (AC)
Input Low Voltage
VIL (AC)
VREF + 0.2
-
V
1,2
-
VREF - 0.2
V
1,2
Notes: 1. This condition is for AC function test only, not for AC parameter test.
2. To maintain a valid level, the transitioning edge of the input must :
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at least the target AC level
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overershoot Timing
Undershoot Timing
20% tKHKH(MIN)
VIH
VDDQ+0.5V
VDDQ+0.25V
VSS
VDDQ
VSS-0.25V
VSS-0.5V
20% tKHKH(MIN)
VIL
Note: For power-up, VIH ≤ VDDQ+0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms
OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)
PARAMETER
SYMBOL
MIN
MAX
UNIT
VDD
1.7
1.9
V
VDDQ
1.4
1.9
V
Reference Voltage
VREF
0.68
0.95
V
Ground
VSS
0
0
V
Supply Voltage
AC TEST CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Symbol
Value
Unit
VDD
1.7~1.9
V
VDDQ
1.4~1.9
V
Input High/Low Level
VIH/VIL
1.25/0.25
V
Input Reference Level
VREF
0.75
V
Input Rise/Fall Time
TR/TF
0.3/0.3
ns
VDDQ/2
V
Output Timing Reference Level
AC TEST OUTPUT LOAD
VREF 0.75V
50Ω
SRAM
Zo=50Ω
ZQ
Note: Parameters are tested with RQ=250Ω
- 10 -
VDDQ/2
250Ω
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
-30
-25
-20
-16
UNIT NOTE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.30
5.25
4.00
6.30
5.00
7.88
6.00
8.40
ns
0.20
ns
Clock
Clock Cycle Time (K, K, C, C)
tKHKH
Clock Phase Jitter (K, K, C, C)
tKC var
Clock High Time (K, K, C, C)
tKHKL
1.32
1.60
2.00
2.40
ns
Clock Low Time (K, K, C, C)
tKLKH
1.32
1.60
2.00
2.40
ns
Clock to Clock (K↑ → K↑, C↑ → C↑)
tKHKH
1.49
1.80
2.20
2.70
ns
0.20
1.45
0.20
0.00
1.80
0.20
Clock to data clock (K↑ → C↑, K↑→ C↑)
tKHCH
0.00
DLL Lock Time (K, C)
tKC lock
1024
1024
1024
0.00
2.30
1024
0.00
2.80
cycle
K Static to DLL reset
tKC reset
30
30
30
30
ns
5
ns
6
Output Times
C, C High to Output Valid
tCHQV
C, C High to Output Hold
tCHQX
C, C High to Echo Clock Valid
tCHCQV
C, C High to Echo Clock Hold
tCHCQX
CQ, CQ High to Output Valid
tCQHQV
CQ, CQ High to Output Hold
tCQHQX
0.45
-0.45
0.45
-0.45
0.45
-0.45
-0.45
0.45
-0.45
0.27
-0.27
0.45
-0.45
-0.30
0.45
3
ns
3
0.50
ns
0.40
ns
ns
7
0.50
ns
3
3
-0.50
0.35
-0.35
0.45
ns
-0.50
0.45
0.30
0.50
ns
-0.40
0.45
C, High to Output High-Z
tCHQZ
C, High to Output Low-Z
tCHQX1
-0.45
-0.45
-0.45
-0.50
ns
Address valid to K rising edge
tAVKH
0.40
0.50
0.60
0.70
ns
Control inputs valid to K rising edge
tIVKH
0.40
0.50
0.60
0.70
ns
Data-in valid to K, K rising edge
tDVKH
0.30
0.35
0.40
0.50
ns
K rising edge to address hold
tKHAX
0.40
0.50
0.60
0.70
ns
K rising edge to control inputs hold
tKHIX
0.40
0.50
0.60
0.70
ns
K, K rising edge to data-in hold
tKHDX
0.30
0.35
0.40
0.50
ns
7
Setup Times
2
Hold Times
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW0,BW1 and (NW0, NW1, for x8) and (BW2, BW3, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ± 0.1 ns variation from echo clock to data.
The data sheet parameters reflect tester guardbands and test setup variations.
- 11 -
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
PIN CAPACITANCE
PRMETER
SYMBOL
TESTCONDITION
TYP
MAX
UNIT
CIN
VIN=0V
4
5
pF
Input and Output Capacitance
COUT
VOUT=0V
6
7
pF
Clock Capacitance
CCLK
-
5
6
pF
Address Control Input Capacitance
NOTE
Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
THERMAL RESISTANCE
PRMETER
SYMBOL
TYP
UNIT
Junction to Ambient
θJA
17.1
°C/W
Junction to Case
θJC
3.3
°C/W
NOTE
Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site
thermal impedance. TJ=TA + PD x θJA
APPLICATION INRORMATION
SRAM#1
Vt
D
SA
R
R=250Ω
ZQ R=250Ω
CQ
CQ
Q
R W BW0 BW1 C C K K
Data In
Data Out
Address
R
W
BW
SRAM#4
CQ
CQ
Q
RW BW0 BW1 C C K K
D
SA
R
ZQ
ZQ
Vt
Vt
MEMORY
CONTROLLER
Return CLK
Source CLK
Return CLK
Source CLK
Vt
Vt
R=50Ω Vt=VREF
SRAM1 Input CQ
SRAM1 Input CQ
SRAM4 Input CQ
SRAM4 Input CQ
- 12 -
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
TIMING WAVE FORMS OF READ, WRITE AND NOP
NOP
READ
READ
READ
NOP
(burst of 2) (burst of 2) (burst of 2)
1
2
3
NOP
(Note3)
5
4
READ
WRITE WRITE
READ
(burst of 2) (burst of 2) (burst of 2) (burst of 2)
7
8
9
10
A3
A4
A5
A6
6
NOP
NOP
11
12
K
tKHKL
tKHKH
tKHKH
K
tIVKH
tKLKH
tKHIX
LD
R/W
SA
A0
A1
A2
tKHDX
tDVKH
DQ
Q01
tCHQV
tKHCH
tCHQX1
Q02
Q11
Q12
Q21
Q22
tCHQX
D31
D32
D41
D42
Q51
tCHQZ
tKHKH
tKHKL
Q52
Q61
Q62
tCHQV
tKLKH
C
C
tKHKH
tCHCQX
tCHCQX
tCHCQV
CQ
CQ
tCHCQV
DON′T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after a NOP .
3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent
bus contention.
- 13 -
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not
driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up,
therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without
interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an
undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be
tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0
SRAM
CORE
TDI
BYPASS Reg.
TDO
Identification Reg.
Instruction Reg.
Control Signals
TMS
TCK
TAP Controller
TDO Output
Notes
0
0
0
EXTEST
Instruction
Boundary Scan Register
1
0
0
1
IDCODE
Identification Register
3
0
1
0
SAMPLE-Z
Boundary Scan Register
2
0
1
1
RESERVED
Do Not Use
6
1
0
0
SAMPLE
Boundary Scan Register
5
1
0
1
RESERVED
Do Not Use
6
1
1
0
RESERVED
Do Not Use
6
1
1
1
BYPASS
Bypass Register
4
NOTE :
1. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs. This instruction is not IEEE 1149.1 compliant.
2. Places DQs in Hi-Z in order to sample all input data regardless of other
SRAM inputs.
3. TDI is sampled as an input to the first ID register to allow for the serial shift
of the external TDI data.
4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The
Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
5. SAMPLE instruction dose not places DQs in Hi-Z.
6. This instruction is reserved for future use.
TAP Controller State Diagram
1
Test Logic Reset
0
0
Run Test Idle
1
1
1
Select DR
0
1
Capture DR
0
Shift DR
1
Exit2 DR
1
Update DR
0
- 14 -
Select IR
0
1
Capture IR
0
0
1
Exit1 DR
0
Pause DR
1
1
1
0
0
Shift IR
1
0
Exit1 IR
0
Pause IR
1
Exit2 IR
1
Update IR
1
0
0
0
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
SCAN REGISTER DEFINITION
Part
Instruction Register
Bypass Register
ID Register
512Kx36
3 bits
1 bit
32 bits
Boundary Scan
107 bits
1Mx18
3 bits
1 bit
32 bits
107 bits
ID REGISTER DEFINITION
Part
Revision Number
(31:29)
Part Configuration
(28:12)
Samsung JEDEC Code
(11: 1)
Start Bit(0)
512Kx36
000
00def0wx0t0q0b0s0
00001001110
1
1Mx18
000
00def0wx0t0q0b0s0
00001001110
1
Note : Part Configuration
/def=001 for 18Mb, /wx=11 for x36, 10 for x18
/t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O
BOUNDARY SCAN EXIT ORDER
ORDER
PIN ID
ORDER
PIN ID
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
6R
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
9N
11L
11M
9L
10L
11K
10K
9J
9K
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
10D
9E
10C
11D
9C
9D
11B
11C
9B
10B
11A
Internal
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
1H
1A
2B
3B
1C
1B
3D
3C
1D
ORDER
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
PIN ID
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1J
2J
3K
3J
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
Note: 1. NC pins are read as "X" ( i.e. don′t care.)
- 15 -
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
VDD
1.7
Input High Level
VIH
1.3
1.8
1.9
V
-
VDD+0.3
V
Input Low Level
VIL
-0.3
Output High Voltage(IOH=-2mA)
VOH
1.4
-
0.5
V
-
VDD
V
Output Low Voltage(IOL=2mA)
VOL
VSS
-
0.4
V
Note
Note: 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Symbol
Min
Unit
Input High/Low Level
VIH/VIL
1.8/0.0
V
Input Rise/Fall Time
TR/TF
1.0/1.0
ns
0.9
V
Input and Output Timing Reference Level
Note
1
Note: 1. See SRAM AC test output load on page 11.
JTAG AC Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tCHCH
50
-
ns
TCK High Pulse Width
tCHCL
20
-
ns
TCK Low Pulse Width
tCLCH
20
-
ns
TMS Input Setup Time
tMVCH
5
-
ns
TMS Input Hold Time
tCHMX
5
-
ns
TDI Input Setup Time
tDVCH
5
-
ns
TDI Input Hold Time
tCHDX
5
-
ns
SRAM Input Setup Time
tSVCH
5
-
ns
SRAM Input Hold Time
tCHSX
5
-
ns
Clock Low to Output Valid
tCLQV
0
10
ns
Note
JTAG TIMING DIAGRAM
TCK
tCHCH
tCHCL
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLCH
TMS
TDI
PI
(SRAM)
tCLQV
TDO
- 16 -
July. 2004
Rev 3.1
K7I163682B
K7I161882B
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
165 FBGA PACKAGE DIMENSIONS
13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array
B
Top View
A
C
D
Side View
A
G
E
B
F
Bottom View
∅H
E
Symbol
Value
Units
Note
Symbol
Value
Units
A
13 ± 0.1
mm
E
1.0
mm
B
15 ± 0.1
mm
F
14.0
mm
C
1.3 ± 0.1
mm
G
10.0
mm
D
0.35 ± 0.05
mm
H
0.5 ± 0.05
mm
- 17 -
Note
July. 2004
Rev 3.1