K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM 36Mb DDRII+ SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit DDRTM II+ CIO b2 SRAM Revision History Rev. No. 1.0 History Draft Date 1. First Release Aug. 28, 2008 -2- Remark Final Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM 1Mx36-bit, 2Mx18-bit DDRII CIO b2 SRAM FEATURES • 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide output data valid window and future freguency scaling. • I/O Supply Voltage 1.5V+0.1V/-0.1V • Pipelined, double-data rate operation. • Common data input/output bus . • HSTL I/O • Full data coherency, providing most current data. • Synchronous pipeline read with self timed late write. • Read latency : 2.5 clock cycles • Registered address, control and data input/output. • DDR(Double Data Rate) Interface on read and write ports. • Fixed 2-bit burst for both read and write operation. • Clock-stop supports to reduce current. • Two input clocks(K and K) for accurate DDR timing at clock rising edges only. • Two echo clocks (CQ and CQ) to enhance output data traceability. • Data Valid pin(QVLD) supported • Single address bus. • Byte write (x18, x36) function. • Simple depth expansion with no data contention. • Programmable output impedance(ZQ). • JTAG 1149.1 compatible test access port. • 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm Organization X36 X18 Part Number Cycle Access Unit Time Time K7K3236U2C-F(E)C(I)45 2.22 0.45 ns K7K3236U2C-F(E)C(I)40 2.5 0.45 ns K7K3236U2C-F(E)C(I)33 3.0 0.45 ns K7K3218U2C-F(E)C(I)45 2.22 0.45 ns K7K3218U2C-F(E)C(I)40 2.5 0.45 ns K7K3218U2C-F(E)C(I)33 3.0 0.45 ns * -F(E)C(I) F(E) [Package type] : E-Pb Free, F-Pb C(I) [Operating Temperature] : C-Commercial, I-Industrial FUNCTIONAL BLOCK DIAGRAM 36 (or 18) DATA REG K K OUTPUT DRIVER 36 (or 18) OUTPUT SELECT 1Mx36 (2Mx18) MEMORY ARRAY OUTPUT REG 4(or 2) CTRL LOGIC 72 (or 36) SENSE AMPS LD R/W BWX ADD REG WRITE DRIVER 19 (or 20) WRITE/READ DECODE ADDRESS 19 (or 20) 36 (or 18) 36 (or 18) DQ QVLD CQ, CQ (Echo Clock out) CLK GEN Doff SELECT OUTPUT CONTROL Notes: 1. Numbers in ( ) are for x18 device DDR SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology. -3- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM PIN CONFIGURATIONS(TOP VIEW) K7K3236T2C(1Mx36) A 1 2 3 4 5 6 7 8 9 10 11 CQ NC/SA* SA R/W BW2 K BW1 LD SA NC/SA* CQ B NC DQ27 DQ18 SA BW3 K BW0 SA NC NC DQ8 C NC NC DQ28 VSS SA NC SA VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14 H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10 P NC NC DQ26 SA SA QVLD SA SA NC DQ9 DQ0 R TDO TCK SA SA SA NC SA SA SA TMS TDI Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb, 2A for 144Mb . 2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35. PIN NAME SYMBOL PIN NUMBERS DESCRIPTION K, K 6B, 6A Input Clock QVLD 6P Q Valid output CQ, CQ 11A, 1A Output Echo Clock Doff 1H DLL Disable SA 3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs DQ0-35 2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F 11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L 3M,10M,11M,2N,3N,11N,3P,10P,11P Data Inputs Outputs R/W 4A Read, Write Control Pin, Read active when high LD 8A Synchronous Load Pin, bus Cycle sequence is to be defined when low BW0, BW1,BW2, BW3 7B,7A,5A,5B Block Write Control Pin,active when low VREF 2H,10H Input Reference Voltage ZQ 11H Output Driver Impedance Control Input VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 1.8 V ) VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V ) VSS 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L, 4M-8M,4N,8N Ground TMS 10R JTAG Test Mode Select TDI 11R JTAG Test Data Input TCK 2R JTAG Test Clock TDO 1R JTAG Test Data Output NC 2A,10A,1B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E, 1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K 1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P,6R No Connect NOTE 1 2 Notes: 1. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 2. Not connected to chip pad internally. 3. K, K can not be set to VREF voltage. -4- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM PIN CONFIGURATIONS(TOP VIEW) K7K3218T2C(2Mx18) A 1 2 3 4 5 6 7 8 9 10 11 CQ NC/SA* SA R/W BW1 K NC LD SA SA CQ DQ8 B NC DQ9 NC SA NC K BW0 SA NC NC C NC NC NC VSS SA NC SA VSS NC DQ7 NC D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3 L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC N NC NC DQ16 VSS SA SA SA VSS NC NC NC P NC NC DQ17 SA SA QVLD SA SA NC NC DQ0 R TDO TCK SA SA SA NC SA SA SA TMS TDI Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 72Mb. 2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17. PIN NAME SYMBOL PIN NUMBERS DESCRIPTION K, K 6B, 6A Input Clock QVLD 6P Q Valid output CQ, CQ 11A, 1A Output Echo Clock Doff 1H DLL Disable SA 3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs DQ0-17 2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L 10M,3N,3P,11P Data Inputs Outputs R/W 4A Read, Write Control Pin, Read active when high LD 8A Synchronous Load Pin, bus Cycle sequence is to be defined when low BW0, BW1 7B, 5A Block Write Control Pin,active when low VREF 2H,10H Input Reference Voltage ZQ 11H Output Driver Impedance Control Input VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 1.8 V ) VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V ) VSS 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground TMS 10R JTAG Test Mode Select JTAG Test Data Input TDI 11R TCK 2R JTAG Test Clock TDO 1R JTAG Test Data Output NC 2A,7A,1B,3B,5B,9B,10B,1C,2C,3C,6C,9C,11C,1D,2D,9D,10D 11D,1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G 1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L 1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P,6R No Connect NOTE 1 2 Notes: 1. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 2. Not connected to chip pad internally. 3. K, K can not be set to VREF voltage. -5- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM GENERAL DESCRIPTION The K7K3236T2C and K7K3218T2C are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 1,048,576 words by 36bits for K7K3236T2C and 2,097,152 words by 18 bits for K7K3218T2C . Address, data inputs, and all control signals are synchronized to the input clock ( K or K ). Read data are referenced to echo clock ( CQ or CQ ) outputs. Read address and write address are registered on rising edges of the input K clocks. Common address bus is used to access address both for read and write operations. The internal burst counter is fixed to 2-bit sequential for both read and write operations. Synchronous pipeline read and late write enable high speed operations. Simple depth expansion is accomplished by using LD for port selection. Byte write operation is supported with BW0 and BW1 ( BW2 and BW3) pins for x18 ( x36 ) device. IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system. The K7K3236T2C and K7K3218T2C are implemented with SAMSUNG's high performance 6T CMOS technology and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce. Read Operations Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K. Address is presented and stored in the read address register synchronized with K clock. For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command. The first pipelined data is transfered out of the device triggered by K clock rising edge. Next burst data is triggered by the rising edge of following K clock rising edge. Continuous read operations are initated with K clock rising edge. And pipelined data are transferred out of device on every rising edge of both K and K clocks. Initial read data latency is 2.5 clock cycles when DLL is on. When the LD is disabled after a read operation, the K7K3236T2C and K7K3218T2C will first complete burst read operation before entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state. Write Operations Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K. Address is presented and stored in the write address register synchronized with next K clock. For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command. The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge. Next burst data is transfered and registered synchronous with following K clock rising edge. Continuous write operations are initated with K rising edge. And "late writed" data is presented to the device on every rising edge of both K and K clocks. When the LD is disabled, the K7K3236T2C and K7K3218T2C will enter into deselect mode. The device disregards input data presented on the same cycle R/W disabled. The K7K3236T2C and K7K3218T2C support byte write operations. With activating BW0 or BW1 ( BW2 or BW3 ) in write cycle, only one byte of input data is presented. In K7K3218T2C, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17. And in K7K3236T2C, BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35. -6- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM Depth Expansion Each port can be selected and deselected independently with R/W be shared among all SRAMs and provide a new LD signal for each bank. Before chip deselected, all read and write pending operations are completed. Programmable Impedance Output Buffer Operation The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ). The allowable range of RQ is between 175Ωand 350Ω. The value of RQ (within 15%) is five times the output impedance desired. For example, 250Ω resistor will give an output impedance of 50Ω. Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. To guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles. Output Valid Pin (QVLD) The Q Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for capturing the data. QVLD is edge aligned with CQ and CQ. Echo clock operation To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are synchronized with internal data output. Echo clocks run free during normal operation. The Echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver. Power-Up/Power-Down Supply Voltage Sequencing The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-down. -7- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM Detail Specification of Power-Up Sequence in DDRII+ SRAM DDRII+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. • Power-Up Sequence 1. Apply power and keep Doff at low state (All other inputs may be undefined) - Apply VDD before VDDQ - Apply VDDQ before VREF or the same time with VREF 2. Just after the stable power and clock(K,K), take Doff to be high. 3. The additional 2048 cycles of clock input is required to lock the DLL after enabling DLL * Notes: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds (Min. 30ns) to reset the DLL after it become a stable clock status. • DLL Constraints 1. DLL uses K clock as its synchronizing input, the input should have low phase jitter which is specified as TK var. 2. The lower end of the frequency at which the DLL can operate is 120MHz. 3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency and this may cause the failure in the initial stage. K,K Status Power-Up ~ ~ ~ ~ ~ ~ Power up & Initialization Sequence (Doff pin controlled) 2048 cycle Unstable CLKstage DLL Locking Range Any Command Inputs Clock must be stable VDD VDDQ VREF Doff Power-Up Unstable CLKstage Stop Clock 2048 cycle ~ ~ Status ~ Min 30ns ~ ~ K,K ~ ~ ~ Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled) DLL Locking Range Any Command Inputs Clock must be stable VDD VDDQ VREF * Notes: When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 2048 cycles of clock input is needed to lock the DLL. -8- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM TRUTH TABLES SYNCHRONOUS TRUTH TABLE K LD DQ R/W DQ(A1) DQ(A2) OPERATION Stopped X X Previous state Previous state Clock Stop ↑ H X High-Z High-Z No Operation ↑ L H QOUT at K(t+2) QOUT at K(t+2) Read ↑ L L Din at K(t+1) Din at K(t+1) Write Notes: 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ( ↑ ). 3. Before enter into clock stop status, all pending read and write operations will be completed. WRITE TRUTH TABLE(x18) K K ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ BW0 BW1 OPERATION L L WRITE ALL BYTEs ( K↑ ) L L WRITE ALL BYTEs ( K↑ ) L H WRITE BYTE 0 ( K↑ ) L H WRITE BYTE 0 ( K↑ ) H L WRITE BYTE 1 ( K↑ ) H L WRITE BYTE 1 ( K↑ ) H H WRITE NOTHING ( K↑ ) H H WRITE NOTHING ( K↑ ) Notes: 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ). 3. Assumes a WRITE cycle was initiated. 4. This table illustates operation for x18 devices. WRITE TRUTH TABLE(x36) K K BW0 L L L L WRITE ALL BYTEs ( K↑ ) ↑ L L L L WRITE ALL BYTEs ( K↑ ) L H H H WRITE BYTE 0 ( K↑ ) L H H H WRITE BYTE 0 ( K↑ ) H L H H WRITE BYTE 1 ( K↑ ) H L H H WRITE BYTE 1 ( K↑ ) H H L L WRITE BYTE 2 and BYTE 3 ( K↑ ) ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ BW1 BW2 BW3 OPERATION H H L L WRITE BYTE 2 and BYTE 3 ( K↑ ) H H H H WRITE NOTHING ( K↑ ) H H H H WRITE NOTHING ( K↑ ) Notes: 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ). 3. Assumes a WRITE cycle was initiated. -9- Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM ABSOLUTE MAXIMUM RATINGS SYMBOL RATING UNIT Voltage on VDD Supply Relative to VSS PARAMETER VDD -0.5 to 2.9 V Voltage on VDDQ Supply Relative to VSS VDDQ -0.5 to VDD V VIN -0.5 to VDD+0.3 V Voltage on Input Pin Relative to VSS Storage Temperature Operating Temperature Commercial / Industrial Storage Temperature Range Under Bias TSTG -65 to 150 °C TOPR 0 to 70 / -40 to 85 °C TBIAS -10 to 85 °C Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C) PARAMETER Supply Voltage SYMBOL MIN TYP MAX UNIT VDD 1.7 1.8 1.9 V VDDQ 1.4 1.5 1.6 V VREF 0.7 0.75 0.8 V 2,3) VIL(DC) -0.3 - VREF - 0.1 V Input High Voltage(DC) 2,4) V Reference Voltage Input Low Voltage(DC) VIH(DC) VREF + 0.1 - VDDQ + 0.3 Input Low Voltage(AC) 6,7) VIL(AC) - - VREF - 0.2 V Input High Voltage(AC) 6,7) VIH(AC) VREF + 0.2 - - V Note: 1. VDDQ must not exceed VDD during normal operation. 2. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns). 4. VIH (Max)DC=VDDQ+0.3V, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns). 5. Overshoot : VIH (AC) ≤ VDDQ+0.5V for t ≤ 50% tKHKH(MIN). Undershoot : VIL (AC) ≤ VSS-0.5V for t ≤ 50% tKHKH(MIN). 6. This condition is for AC function test only, not for AC parameter test. 7. To maintain a valid level, the transitioning edge of the input must : a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC) b) Reach at least the target AC level c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC) - 10 - Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM DC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C) PARAMETER SYMBOL TEST CONDITIONS Input Leakage Current IIL VDD=Max ; VIN=VSS to VDDQ Output Leakage Current IOL Output Disabled, Operating Current (x36): DDR Operating Current (x18): DDR Standby Current(NOP): DDR Output High Voltage ICC ICC ISB1 VDD=Max , IOUT=0mA Cycle Time ≥ tKHKH Min VDD=Max , IOUT=0mA Cycle Time ≥ tKHKH Min Device deselected, IOUT=0mA, f=Max, All Inputs≤0.2V or ≥ VDD-0.2V VOH1 MIN MAX -2 +2 µA µA -2 +2 -45 - 950 -40 - 900 -33 - 800 -45 - 850 -40 - 900 -33 - 700 -45 - 400 -40 - 350 -33 - 300 UNIT NOTES mA 1,4 mA 1,4 mA 1,5 VDDQ/2-0.12 VDDQ/2+0.12 V 2,6 VDDQ/2-0.12 VDDQ/2+0.12 Output Low Voltage VOL1 V 2,6 Output High Voltage VOH2 IOH=-1.0mA VDDQ-0.2 VDDQ V 3 Output Low Voltage VOL2 IOL=1.0mA VSS 0.2 V 3 Notes: 1. Minimum cycle. IOUT=0mA. 2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω. 3. Minimum Impedance Mode when ZQ pin is connected to VDD. 4. Operating current is calculated with 100% read cycles or 100% write cycles. 5. Standby Current is only after all pending read and write burst opeactions are completed. 6. Programmable Impedance Mode. - 11 - Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM AC TIMING CHARACTERISTICS (VDD=1.8V±0.1V, TA=0°C to +70°C) PARAMETER SYMBOL -45 -40 -33 MIN MAX MIN MAX MIN MAX 2.22 8.4 2.5 8.4 3.0 8.4 UNIT NOTE Clock Clock Cycle Time (K, K) tKHKH Clock Phase Jitter (K, K) tK var Clock High Time (K, K) tKHKL 0.20 0.4 0.20 0.4 0.20 ns ns 0.4 ns ns Clock Low Time (K, K) tKLKH 0.4 0.4 0.4 Clock to Clock (K↑ → K↑) tKHKH 0.95 1.06 1.3 ns DLL Lock Time (K) tK lock 2048 2048 2048 cycle K Static to DLL reset tK reset 30 30 30 ns 4 5 Output Times K, K High to Output Valid tKHQV K, K High to Output Hold tKHQX K, K High to Echo Clock Valid tKHCQV K, K High to Echo Clock Hold tKHCQX CQ, CQ High to Output Valid tCQHQV 0.45 -0.45 0.45 -0.45 0.45 -0.45 0.45 -0.45 0.45 -0.45 0.2 0.45 ns 0.2 ns -0.45 0.2 ns ns ns CQ, CQ High to Output Hold tCQHQX -0.2 -0.2 -0.2 ns CQ High to CQ High tCQHCQH 0.75 0.86 1.1 ns K, K High to Output High-Z K, K High to Output Low-Z CQ, CQ High to QVLD Valid tKHZ 0.45 tKLZ -0.45 tQVLD -0.2 0.45 -0.45 0.2 -0.2 0.45 ns 0.2 ns -0.45 0.2 -0.2 6 ns Setup Times Address valid to K rising edge tAVKH 0.40 0.40 0.40 ns Control inputs valid to K rising edge tIVKH 0.40 0.40 0.40 ns Data-in valid to K, K rising edge tDVKH 0.28 0.28 0.28 ns K rising edge to address hold tKHAX 0.40 0.40 0.40 ns K rising edge to control inputs hold tKHIX 0.40 0.40 0.40 ns K, K rising edge to data-in hold tKHDX 0.28 0.28 0.28 ns 2 Hold Times Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges. 2. Control signals are R/ W and LD. However BWx does not apply to this parameters. BWx signals obey the data setup and hold times. 3. To avoid bus contention, at a given voltage and temperature tKLZ is bigger than tKHZ. The specs as shown do not imply bus contention because tKLZ is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9V) than tKHZ, which is a MAX parameter(worst case at 70°C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature. 4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 5. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. 6. This parameter is extrapolated from the input timing parameters (tKHKH - 200ps where 200ps is the internal jitter.) This parameter is only guaranteed by design and not tested in production. - 12 - Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM THERMAL RESISTANCE SYMBOL TYP Unit Junction to Ambient PRMETER θJA 20.8 °C/W Junction to Case θJC 2.3 °C/W Junction to Pins θJB 4.3 °C/W NOTES Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site thermal impedance. TJ=TA + PD x θJA PIN CAPACITANCE PRMETER SYMBOL TESTCONDITION TYP MAX Unit CIN VIN=0V 3.5 4 pF Input and Output Capacitance COUT VOUT=0V 4 5 pF Clock Capacitance CCLK - 3 4 pF Address Control Input Capacitance NOTES Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V. 2. Periodically sampled and not AC TEST CONDITIONS AC TEST OUTPUT LOAD Symbol Value Unit Core Power Supply Voltage VDD 1.7~1.9 V Output Power Supply Voltage VDDQ 1.4~1.6 V Input High/Low Level VIH/VIL 1.25/0.25 V Input Reference Level VREF 0.75 V Input Rise/Fall Time TR/TF 0.3/0.3 ns VDDQ/2 V Parameter Output Timing Reference Level VREF 0.75V VDDQ/2 50Ω SRAM Zo=50Ω ZQ 250Ω Note: Parameters are tested with RQ=250Ω - 13 - Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM APPLICATION INRORMATION R=250Ω SRAM#1 Vt R SA R/W LD0 BW0 BW1 ZQ CQ CQ DQ K K R=250Ω SRAM#4 SA R/WLD3BW0 BW1 ZQ CQ CQ DQ K K DQ Address R/W LD BW R Vt MEMORY CONTROLLER Return CLK Source CLK Return CLK Source CLK R=50Ω Vt=VREF SRAM1 Input CQ SRAM1 Input CQ SRAM4 Input CQ SRAM4 Input CQ - 14 - Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM TIMING WAVE FORMS OF READ, WRITE AND NOP NOP NOP READ WRITE NOP READ READ NOP NOP NOP WRITE WRITE (Note3) 1 2 3 4 5 6 7 A2 A3 A4 9 8 10 11 12 A5 A6 K tKHKL tKHKH tKHKH K tIVKH tKLKH tKHIX LD R/W SA A1 tQVLD QVLD tKHQV DQ Q1-1 Q1-2 tKHQX D2-1 D2-2 Q3-1 Q3-2 Q4-1 Q4-2 D5-1 D5-2 tCQHQV tKHCQV CQ CQ DON′T CARE UNDEFINED NOTE 1. Q1-1 refers to output from address A1. Q1-2 refers to output from the next internal burst address following A, etc. 2. Outputs are disabled(High-Z) two clock cycle after a NOP . 3. Two NOP cycle is the mandatory and 3rd NOP cycle is not necessary for correct DDRII+ READ/WRITE operation. However at high clock frequencies, considering the delay of real system board condition, it may be required to prevent bus contention. - 15 - Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Block Diagram JTAG Instruction Coding IR2 IR1 IR0 0 SRAM CORE TDI BYPASS Reg. TDO Identification Reg. Instruction Reg. Control Signals TMS TCK TAP Controller 0 0 TDO Output Notes EXTEST Instruction Boundary Scan Register 1 0 0 1 IDCODE Identification Register 3 0 1 0 SAMPLE-Z Boundary Scan Register 2 0 1 1 RESERVED Do Not Use 6 1 0 0 SAMPLE Boundary Scan Register 5 1 0 1 RESERVED Do Not Use 6 1 1 0 RESERVED Do Not Use 6 1 1 1 BYPASS Bypass Register 4 NOTE : 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. This instruction is not IEEE 1149.1 compliant. 2. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 3. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 4. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 5. SAMPLE instruction dose not places DQs in Hi-Z. 6. This instruction is reserved for future use. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 1 1 Select DR 0 1 Capture DR 0 Shift DR 1 Exit2 DR 1 Update DR 0 - 16 - Select IR 0 1 Capture IR 0 0 1 Exit1 DR 0 Pause DR 1 1 1 0 0 Shift IR 1 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register Boundary Scan 1Mx36 3 bits 1 bit 32 bits 109 bits 2Mx18 3 bits 1 bit 32 bits 109 bits ID REGISTER DEFINITION Part Revision Number (31:29) Part Configuration (28:12) Samsung JEDEC Code (11: 1) Start Bit(0) 1Mx36 000 00def0wx0t0q0b0s0 00011001110 1 2Mx18 000 00def0wx0t0q0b0s0 00011001110 1 Note : Part Configuration /def=010 for 36Mb, /wx=11 for x36, 10 for x18 /t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O BOUNDARY SCAN EXIT ORDER ORDER PIN ID ORDER PIN ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D Note: 1. NC pins are read as "X" ( i.e. don′t care.) - 17 - ORDER 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 PIN ID 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM JTAG DC OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit V Power Supply Voltage VDD 1.7 1.8 1.9 Input High Level VIH 1.3 - VDD+0.3 V Input Low Level VIL -0.3 - 0.5 V Output High Voltage(IOH=-2mA) VOH 1.4 - VDD V Output Low Voltage(IOL=2mA) VOL VSS - 0.4 V Note Note: 1. The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Symbol Min Unit Input High/Low Level Parameter VIH/VIL 1.8/0.0 V Input Rise/Fall Time TR/TF 1.0/1.0 ns 0.9 V Input and Output Timing Reference Level Note 1 Note: 1. See SRAM AC test output load on page 11. JTAG AC Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns Note JTAG TIMING DIAGRAM TCK tCHCH tCHCL tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLCH TMS TDI PI (SRAM) tCLQV TDO - 18 - Rev. 1.0 August 2008 K7K3236U2C K7K3218U2C 1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM 165 FBGA PACKAGE DIMENSIONS 15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array B Top View A Side View C D A G E B F Bottom View ∅H E Symbol Value Units Note Symbol A 15 ± 0.1 mm E 1.0 mm B 17 ± 0.1 mm F 14.0 mm C 1.3 ± 0.1 mm G 10.0 mm D 0.35 ± 0.05 mm H 0.5 ± 0.05 mm - 19 - Value Units Note Rev. 1.0 August 2008