K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Draft Date Remark Rev. 0.0 - Preliminary specification release Oct. 2002 Preliminary Rev. 0.1 - Update DC CHARACTERISTICS x36 : IDD6 : TBD -> 300, IDD65 -> 290, IDD7 -> 280. x18 : IDD6 : TBD -> 290, IDD65 -> 280, IDD7 -> 270. Jan. 2003 Preliminary Feb. 2003 Preliminary Rev. 0.2 - Change simbol in DC CHARACTERISTICS IDD6, IDD65, IDD7 -> IDD65, IDD70, IDD75 Rev. 1.0 - Final Version Jun. 2003 Final Rev. 1.1 - Add Single ended differential clock on clock comment. Jun. 2003 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters. -1- Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM 128Kx36 & 256Kx18 Synchronous Pipelined SRAM FEATURES • • • • • • • • • • • • 128Kx36 or 256Kx18 Organizations. 3.3V VDD, 2.5/3.3V VDDQ. LVTTL 2.5/3.3V Input and Output Levels. Differential, PECL clock / Single ended or differential LVTTL clock Inputs Synchronous Read and Write Operation Registered Input and Latched Output Internal Pipeline Latches to Support Late Write. Byte Write Capability(four byte write selects, one for each 9 bits) Synchronous or Asynchronous Output Enable. Power Down Mode via ZZ Signal. JTAG 1149.1 Compatible Test Access port. 119(7x17) Pin Ball Grid Array Package(14mmx22mm). Organization 128Kx36 256Kx18 Cycle Time Access Time K7P403623B-H65 6 6.5 K7P403623B-H70 6.5 7.0 Part Number K7P403623B-H75 7 7.5 K7P401823B-H65 6 6.5 K7P401823B-H70 6.5 7.0 K7P401823B-H75 7 7.5 Read Address Register SA[0:16] or SA[0:17] 1 Write Address Register CK Latch SS SW SW Register SW Register SWx Register SWx Register 0 Row Decoder FUNCTIONAL BLOCK DIAGRAM Column Decoder Write/Read Circuit Latch SWx (x=a, b, c, d) or (x=a, b) 128Kx36 or 256Kx18 Array 0 1 Data In Register SS Register SS Register Data Out Latch G ZZ K DQx[1:9] (x=a, b, c, d) or (x=a, b) CK K PIN DESCRIPTION Pin Name Pin Description K, K Differential Clocks(PECL or LVTTL Level) SAn Synchronous Address Input DQn Bi-directional Data Bus Pin Name VDDQ M1, M2 Pin Description Output Power Supply Read Protocol Mode Pins ( M1=VDD, M2=VSS ) G Asynchronous Output Enable Synchronous Select SW Synchronous Global Write Enable SS SWa Synchronous Byte a Write Enable TCK SWb Synchronous Byte b Write Enable TMS JTAG Test Mode Select SWc Synchronous Byte c Write Enable TDI JTAG Test Data Input SWd JTAG Test Clock Synchronous Byte d Write Enable TDO JTAG Test Data Output ZZ Asynchronous Power Down VSS GND VDD Core Power Supply NC No Connection -2- Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7P403623B(128Kx36) 1 2 3 4 5 6 7 A VDDQ SA13 SA10 NC SA7 SA4 VDDQ B NC NC SA9 NC SA8 NC NC C NC SA12 SA11 VDD SA6 SA5 NC D DQc8 DQc9 VSS NC* VSS DQb9 DQb8 E DQc6 DQc7 VSS SS VSS DQb7 DQb6 F VDDQ DQc5 VSS G VSS DQb5 VDDQ G DQc3 DQc4 SWc NC* SWb DQb4 DQb3 H DQc1 DQc2 VSS NC* VSS DQb2 DQb1 J VDDQ VDD NC*** VDD NC*** VDD VDDQ K DQd1 DQd2 VSS K VSS DQa2 DQa1 L DQd3 DQd4 SWd K SWa DQa4 DQa3 M VDDQ DQd5 VSS SW VSS DQa5 VDDQ N DQd6 DQd7 VSS SA16 VSS DQa7 DQa6 P DQd8 DQd9 VSS SA0 VSS DQa9 DQa8 R NC SA15 M1 VDD M2 SA2 NC T NC NC SA14 SA1 SA3 NC ZZ U VDDQ TMS TDI TCK TDO NC** VDDQ NOTE : 1. NC* is used for the Boundary Scan. 2. NC** is reserved for TRST input. 3. NC*** is reserved for HSTL interface. KM718FV4022(256Kx18) A 1 2 3 4 5 6 7 VDDQ SA13 SA10 NC SA7 SA4 VDDQ B NC NC SA9 NC SA8 NC NC C NC SA12 SA11 VDD SA6 SA5 NC D DQb1 NC VSS NC* VSS DQa9 NC E NC DQb2 VSS SS VSS NC DQa8 F VDDQ NC VSS G VSS DQa7 VDDQ G NC DQb3 SWb NC* NC NC DQa6 H DQb4 NC VSS NC* VSS DQa5 NC J VDDQ VDD NC*** VDD NC*** VDD VDDQ K NC DQb5 VSS K VSS NC DQa4 L DQb6 NC NC K SWa DQa3 NC M VDDQ DQb7 VSS SW VSS NC VDDQ N DQb8 NC VSS SA16 VSS DQa2 NC P NC DQb9 VSS SA1 VSS NC DQa1 R NC SA15 M1 VDD M2 SA2 NC T NC SA17 SA14 NC SA3 SA0 ZZ U VDDQ TMS TDI TCK TDO NC** VDDQ NOTE : 1. NC* is used for the Boundary Scan. 2. NC** is reserved for TRST input. 3. NC*** is reserved for HSTL interface. -3- Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM FUNCTION DESCRIPTION The K7P403623B andK7P401823B are 4,718,592 bit Synchronous SRAM. It is organized as 131,072 words of 36 bits(or 262,144 words of 18 bits) and is implemented in SAMSUNG's advanced CMOS technology. Single differential PECL level K clocks or single ended or differential LVCMOS/LVTTL clock are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of K clock, all addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outputs are updated from output latches of the falling edge of K clock. An internal write data buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch. Read Operation During reads, the address is registered during the clock rising edge and the internal array is read. The data is driven to the CPU in the following cycle. SS is driven low during this cycle, signaling that the SRAM should drive out the data. During consecutive read cycles where the address is the same, the data output must be held constantly without any glitches. This characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multiple SRAM cycles to perform a single read operation. Write(Store) Operation All addresses and SW are both sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock, one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the Address, SW and SW[a:d] are valid to signal that a valid operations is on the Address and Control Input. Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the same as the SW signal. Bypass Read Operation Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have new byte data from the write data buffer and the other bytes from the SRAM array. Low Power Dissipation Mode During normal operation, asynchronous signal ZZ must be pulled low. Low Power Mode is enabled by switching ZZ high. When the SRAM is in Power Down Mode, the outputs will go to a Hi-Z state and the SRAM will draw standby current. SRAM data will be preserved and a recovery time(tZZR) is required before the SRAM resumes to normal operation. TRUTH TABLE K ZZ G SS SW SWa SWb SWc SWd DQa DQb DQc DQd Operation X H X X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Power Down Mode. No Operation X L H X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled. No Operation ↑ L L H X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled. No Operation ↑ L L L H X X X X DOUT DOUT DOUT DOUT Read Cycle ↑ L X L L H H H H Hi-Z Hi-Z Hi-Z Hi-Z ↑ L X L L L H H H DIN Hi-Z Hi-Z Hi-Z Write first byte ↑ L X L L H L H H Hi-Z DIN Hi-Z Hi-Z Write second byte No Bytes Written ↑ L X L L H H L H Hi-Z Hi-Z DIN Hi-Z Write third byte ↑ L X L L H H H L Hi-Z Hi-Z Hi-Z DIN Write fourth byte ↑ L X L L L L L L DIN DIN DIN DIN Write all byte -4- Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VDD -0.3 to 4.6 V Core Supply Voltage Relative to VSS Output Supply Voltage Relative to VSS VDDQ VDD V Voltage on any I/O pin Relative to VSS VTERM -0.3 to VDD+0.3 V Maximum Power Dissipation PD 1.5 W Output Short-Circuit Current IOUT 25 mA Operating Temperature TOPR 0 to 70 °C Storage Temperature TSTG -65 to 150 °C NOTE : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS Symbol Min Typ Max Unit Core Power Supply Voltage Parameter VDD 3.15 3.3 3.45 V Output Power Supply Voltage (for 2.5V I/O) VDDQ 2.375 2.5 2.9 V Output Power Supply Voltage (for 3.3V I/O) VDDQ 3.135 3.3 3.6 V Note Input High Level (for 2.5V I/O) VIH 1.7 - VDD+0.3 V Input Low Level (for 2.5V I/O) VIL -0.3 - 0.7 V Input High Level (for 3.3V I/O) VIH 2.0 - VDD+0.3 V Input Low Level (for 3.3V I/O) VIL -0.3 - 0.8 V PECL Clock Input High Level VIH-PECL 2.135 - 2.420 V 1 PECL Clock Input Low Level VIL-PECL 1.490 - 1.825 V 1 VIN -0.3 - 3.45 V 2 Clock Input Signal Voltage Clock Input Differential Voltage VDIF-CLK 0.2 - VDD+0.6 V 2 Clock Input Common Mode Voltage VCM-CLK 1.1 - 2.1 V 2 TJ 10 - 110 °C Operating Junction Temperature NOTE 1. For operation with differential PECL clock inputs. 2. For operation with single ended or differential LVCMOS / LVTTL clock input. -5- Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM DC CHARACTERISTICS Symbol Min Max Unit Note Average Power Supply Operating Current-x36 (VIN=VIH or VIL, ZZ & SS=VIL) IDD65 IDD70 IDD75 - 300 290 280 mA 1, 2 Average Power Supply Operating Current-x18 (VIN=VIH or VIL, ZZ & SS=VIL) IDD65 IDD70 IDD75 - 290 280 270 mA 1, 2 Power Supply Standby Current (VIN=VIH or VIL, ZZ=VIH) ISB - 120 mA 1 Input Leakage Current (VIN=VSS or VDDQ) ILI -1 1 µA Output Leakage Current (VOUT=VSS or VDDQ, ZZ=VIH, G=VIH) ILO -1 1 µA Parameter Output High Voltage(IOH=-4mA) for VDDQ=3.3V VOH1 Output High Voltage(IOH=-4mA) for VDDQ=2.5V VOH2 2.4 2.0 VDDQ V Output Low Voltage(IOL=4mA) VOL VSS 0.4 V NOTE :1. Minimum cycle. IOUT=0mA. 2. 50% read cycles. PIN CAPACITANCE Parameter Input Capacitance Output Capacitance Symbol Typ Max Unit CIN - 5 pF COUT - 7 pF NOTE : Periodically sampled and not 100% tested.(dV=0V, f=1MHz) -6- Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM AC TEST CONDITIONS Parameter AC TEST OUTPUT LOAD Symbol Value Unit Core Power Supply Voltage VDD 3.15~3.45 V Output Power Supply Voltage VDDQ 2.4~2.6 V Input High/Low Level VIH/VIL 1.7/0.7 V Clock Input High/Low Level(PECL) VIH/VIL 2.4/1.5 V Input Rise/Fall Time TR/TF 1.0/1.0 ns Clock Input Rise/Fall Time(PECL) TR/TF 1.0/1.0 ns 1.25 V Cross Point V Input and Out Timing Reference Level Clock Input Timing Reference Level Dout Z0=50Ω 20pF* 50Ω 1.25V *Capacitive load consists of all components of the tester environment AC CHARACTERISTICS Parameter Symbol -65 -70 -75 Min Max Min Max Min Max Unit Clock Cycle Time tKHKH 6.0 - 6.5 - 7.0 - ns Clock High Pulse Width tKHKL 2.0 - 2.0 - 2.0 - ns Clock Low Pulse Width tKLKH 2.0 - 2.0 - 2.0 - ns Clock High to Output Valid tKHQV - 6.5 - 7.0 - 7.5 ns Clock Low to Output Valid tKLQV - 2.5 - 2.5 - 3.0 ns Clock Low to Output Hold tKLQX 0.5 - 0.5 - 0.5 - ns Address Setup Time tAVKH 0.5 - 0.5 - 0.5 - ns Address Hold Time tKHAX 1.0 - 1.0 - 1.0 - ns Write Data Setup Time tDVKH 0.5 - 0.5 - 0.5 - ns Write Data Hold Time tKHDX 1.0 - 1.0 - 1.0 - ns SW, SW[a:d] Setup Time tWVKH 0.5 - 0.5 - 0.5 - ns SW, SW[a:d] Hold Time tKHWX 1.0 - 1.0 - 1.0 - ns SS Setup Time tSVKH 0.5 - 0.5 - 0.5 - ns SS Hold Time tKHSX 1.0 - 1.0 - 1.0 - ns Clock High to Output Hi-Z tKHQZ - 2.5 - 3.0 - 3.5 ns Clock Low to Output Low-Z tKLQX1 0.5 - 0.5 - 0.5 - ns G High to Output High-Z tGHQZ - 2.5 - 3.0 - 3.5 ns G Low to Output Low-Z tGLQX 0.5 - 0.5 - 0.5 - ns G Low to Output Valid tGLQV - 2.5 - 3.0 - 3.5 ns ZZ High to Power Down(Sleep Time) tZZE - 15 - 15 - 15 ns ZZ Low to Recovery(Wake-up Time) tZZR - 20 - 20 - 20 ns -7- Note Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES 1 2 tKHKH tAVKH tKHAX 3 5 4 6 7 9 8 K tKHKL tKLKH A1 A1 SAn A2 A3 A4 A5 A4 A6 A7 tKHSX tSVKH SS tWVKH tKHWX tWVKH tKHWX tKHWX tWVKH SW SWx tKLQV tKLQV tKHQV tKLQX G tGHQZ tKHQZ tDVKH tKHDX tGLQV tKLQX1 tKLQV tKHQZ tKLQX1 tGLQX Q1 DQn Q2 D3 D4 Q5 Q4 NOTE 1. D3 is the input data written in memory location A3. 2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last write cycle address. 3. Data is valid at the output at the later of tKHQV following the rising clock edge, or tKLQV following the fallowing clock edge. 4. When SS is sampled high or SW is sampled low on the rising edge of clock, the outputs go into Hi-Z state no later than tKHQZ following the rising clock edge. 5. When SS is low and SW is high on the rising edge of clock, the outputs go into Low-Z state(being driven) no earlier than tKLQX1 following the next falling edge of clock. 6. When the SRAM is deselected, the output goes Hi-Z at tKHQZ following the rising clock edge. On the next read cycle, note that the SRAM output do not leave the Hi-Z state until tKLQX1 after the falling clock edge. -8- Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM TIMING WAVEFORMS OF STANDBY CYCLES 1 2 3 4 5 6 7 8 K tKHKH SAn A1 A2 A3 A1 A2 A3 Q1 Q2 SS SW SWx tZZR tZZE ZZ tKHQV tKHQV DQn Q1 Q2 Q3 -9- Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Teat Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a resistor. TDO should be left unconnected. JTAG Instruction Coding JTAG Block Diagram IR2 IR1 IR0 Instruction SRAM CORE M2 M1 TDI BYPASS Reg. Identification Reg. Instruction Reg. TDO Control Signals TMS TCK TDO Output Notes 0 0 0 SAMPLE-Z Boundary Scan Register 1 0 0 1 IDCODE 2 0 1 0 SAMPLE-Z Boundary Scan Register 1 0 1 1 BYPASS 3 1 0 0 SAMPLE Boundary Scan Register 4 1 0 1 BYPASS Bypass Register 3 1 1 0 BYPASS Bypass Register 3 1 1 1 BYPASS Bypass Register 3 Identification Register Bypass Register NOTE 1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. Bypass register is initiated to VSS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states. 4. SAMPLE instruction dose not places DQs in Hi-Z. TAP Controller TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test Idle 1 Select DR 0 1 1 Shift DR 1 0 1 Exit1 DR 0 Exit2 DR 1 Update DR 0 - 10 Select IR 0 1 Capture DR 0 Pause DR 1 1 1 0 0 1 Capture IR 0 Shift IR 1 0 Exit1 IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 0 Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM SCAN REGISTER DEFINITION Part Instruction Register Bypass Register ID Register Boundary Scan 128Kx36 3 bits 1 bits 32 bits 70 bits 256Kx18 3 bits 1 bits 32 bits 51 bits ID REGISTER DEFINITION Part Revision Number (31:28) Part Configuration (27:18) Vendor Definition (17:12) Samsung JEDEC Code (11: 1) Start Bit(0) 128Kx36 0000 00101 00100 xxxxxx 00001001110 1 256Kx18 0000 00110 00011 xxxxxx 00001001110 1 BOUNDARY SCAN EXIT ORDER(x36) BOUNDARY SCAN EXIT ORDER(x18) 36 3B SA9 SA8 5B 35 26 3B SA9 SA8 5B 25 37 2B NC NC 6B 34 27 2B NC NC 6B 24 38 3A SA10 SA7 5A 33 28 3A SA10 SA7 5A 23 39 3C SA11 SA6 5C 32 29 3C SA11 SA6 5C 22 40 2C SA12 SA5 6C 31 30 2C SA12 SA5 6C 21 41 2A SA13 SA4 6A 30 31 2A SA13 SA4 6A 20 42 2D DQc9 DQb9 6D 29 DQa9 6D 19 43 1D DQc8 DQb8 7D 28 32 1D DQb1 44 2E DQc7 DQb7 6E 27 33 2E DQb2 45 1E DQc6 DQb6 7E 26 DQa8 7E 18 46 2F DQc5 DQb5 6F 25 DQa7 6F 17 47 2G DQc4 DQb4 6G 24 48 1G DQc3 DQb3 7G 23 DQa6 7G 16 49 2H DQc2 DQb2 6H 22 DQa5 6H 15 50 1H DQc1 DQb1 7H 21 35 1H DQb4 51 3G SWc SWb 5G 20 36 3G SWb 52 4D NC G 4F 19 37 4D NC G 4F 14 53 4E SS K 4K 18 38 4E SS K 4K 13 54 4G NC K 4L 17 39 4G NC K 4L 12 34 2G DQb3 55 4H NC SWa 5L 16 40 4H NC SWa 5L 11 56 4M SW DQa1 7K 15 41 4M SW DQa4 7K 10 DQa3 6L 9 57 3L SWd DQa2 6K 14 58 1K DQd1 DQa3 7L 13 59 2K DQd2 DQa4 6L 12 42 2K DQb5 60 1L DQd3 DQa5 6M 11 43 1L DQb6 61 2L DQd4 DQa6 7N 10 62 2M DQd5 DQa7 6N 9 44 2M DQb7 DQa2 6N 8 63 1N DQd6 DQa8 7P 8 45 1N DQb8 DQa1 7P 7 64 2N DQd7 DQa9 6P 7 65 1P DQd8 ZZ 7T 6 ZZ 7T 6 66 2P DQd9 SA3 5T 5 46 2P DQb9 SA3 5T 5 67 3T SA14 SA2 6R 4 47 3T SA14 SA2 6R 4 68 2R SA15 SA1 4T 3 48 2R SA15 69 4N SA16 SA0 4P 2 49 4N SA16 SA1 4P 3 50 2T SA17 SA0 6T 2 51 3R M1 M2 5R 1 70 3R M1 M2 5R 1 NOTE : 1. Pins 6B and 2B are no connection pin to internal chip. These pins are place holders for 16M part and the scanned data are fixed to "0" for this 4M parts. - 11 Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM JTAG DC OPERATING CONDITIONS Symbol Min Typ Max Unit Power Supply Voltage Parameter VDD 3.15 3.3 3.45 V Input High Level VIH 1.7 - VDD+0.3 V Input Low Level VIL -0.3 - 0.8 V Output High Voltage(IOH=-2mA) VOH 2.1 - VDD V Output Low Voltage(IOL=2mA) VOL VSS - 0.2 V Note NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Parameter Symbol Min Unit Input High/Low Level VIH/VIL 2.5/0.0 V Input Rise/Fall Time TR/TF 1.0/1.0 ns 1.5 V Input and Output Timing Reference Level Note 1 NOTE : 1. See SRAM AC test output load. JTAG AC Characteristics Parameter Symbol Min Max Unit tCHCH 50 - ns TCK High Pulse Width tCHCL 20 - ns TCK Low Pulse Width tCLCH 20 - ns TMS Input Setup Time tMVCH 5 - ns TMS Input Hold Time tCHMX 5 - ns TDI Input Setup Time tDVCH 5 - ns TDI Input Hold Time tCHDX 5 - ns SRAM Input Setup Time tSVCH 5 - ns SRAM Input Hold Time tCHSX 5 - ns Clock Low to Output Valid tCLQV 0 10 ns TCK Cycle Time Note JTAG TIMING DIAGRAM TCK tCHCH tCHCL tMVCH tCHMX tDVCH tCHDX tCLCH TMS TDI tCLQV TDO - 12 Jul. 2003 Rev 1.1 K7P403623B K7P401823B 128Kx36 & 256Kx18 SRAM 119 BGA PACKAGE DIMENSIONS 14.00±0.10 1.27 1.27 22.00±0.10 Indicator of Ball(1A) Location 20.50±0.10 C0.70 C1.00 0.750±0.15 1.50REF 0.60±0.10 0.60±0.10 NOTE : 12.50±0.10 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX. 119 BGA PACKAGE THERMAL CHARACTERISTICS Symbol Thermal Resistance Unit Junction to Ambient Parameter Theta_JA TBD °C/W Junction to Case Theta_JC TBD °C/W Junction to Solder Ball Theta_JB TBD °C/W Note NOTE : 1. Junction temperature can be calculated by : TJ = TA + PD x Theta_JA. - 13 Jul. 2003 Rev 1.1