K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial issue.
Apr. 25th 2002
Advance
1.0
1.Pin assignment of TBGA dummy ball is changed.
(before) DNU --> (after) N.C
Dec.14th 2002
Preliminary
2. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 36)
3. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 37)
4. Add the specification of Block Lock scheme.(Page 32~35)
5. Pin assignment of TBGA A3 ball is changed.
(before) N.C --> (after) Vss
6. Pin assignment of WSOP #38 pin is changed.
(before) LOCKPRE --> (after) N.C
2.0
1. The Maximum operating current is changed.
Program : Icc2 20mA-->25mA
Erase : Icc3 20mA-->25mA
Jan. 17th 2003
Preliminary
2.1
The min. Vcc value 1.8V devices is changed.
K9F56XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V
Mar. 5th 2003
Preliminary
2.2
Pb-free Package is added.
K9F5608U0C-FCB0,FIB0
K9F5608Q0C-HCB0,HIB0
K9F5616U0C-HCB0,HIB0
K9F5616U0C-PCB0,PIB0
K9F5616Q0C-HCB0,HIB0
K9F5608U0C-HCB0,HIB0
K9F5608U0C-PCB0,PIB0
Mar. 13rd 2003
2.3
Errata is added.(Front Page)-K9F56XXQ0C
Mar. 26th 2003
tWC tWH tWP tRC tREH tRP tREA tCEA
Specification
45 15 25 50 15 25 30
45
Relaxed value 60 20 40 60 20 40 40
55
2.4
New definition of the number of invalid blocks is added.
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
2.5
Apr. 4th 2003
Jun. 30th 2003
1. The guidence of LOCKPRE pin usage is changed.
Don’t leave it N.C. Not using LOCK MECHANISM & POWER-ON AUTOREAD, connect it Vss.(Before)
--> Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect
it Vss or leave it N.C(After)
2. 2.65V device is added.
3.Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
2.6
Draft Date
1. tREA value of 1.8V device is changed.
K9F56XXQ0C : tREA 30ns --> 35ns
2. Errata is deleted.
Remark
Aug. 18th 2003
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
2
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
32M x 8 Bit / 16M x 16 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F5608Q0C-D,H
Vcc Range
Organization
X8
1.70 ~ 1.95V
K9F5616Q0C-D,H
X8
TSOP1
TBGA
2.4 ~ 2.9V
K9F5616D0C-Y,P
X16
K9F5616D0C-D,H
TSOP1
TBGA
K9F5608U0C-Y,P
TSOP1
X8
K9F5608U0C-D,H
K9F5608U0C-V,F
TBGA
X16
K9F5608D0C-Y,P
K9F5608D0C-D,H
PKG Type
2.7 ~ 3.6V
TBGA
WSOP1
K9F5616U0C-Y,P
X16
K9F5616U0C-D,H
TSOP1
TBGA
FEATURES
• Voltage Supply
- 1.8V device(K9F56XXQ0C) : 1.70~1.95V
- 2.65V device(K9F56XXD0C) : 2.4~2.9V
- 3.3V device(K9F56XXU0C) : 2.7 ~ 3.6 V
• Organization
- Memory Cell Array
- X8 device(K9F5608X0C) : (32M + 1024K)bit x 8 bit
- X16 device(K9F5616X0C) : (16M + 512K)bit x 16bit
- Data Register
- X8 device(K9F5608X0C) : (512 + 16)bit x 8bit
- X16 device(K9F5616X0C) : (256 + 8)bit x16bit
• Automatic Program and Erase
- Page Program
- X8 device(K9F5608X0C) : (512 + 16)Byte
- X16 device(K9F5616X0C) : (256 + 8)Word
- Block Erase :
- X8 device(K9F5608X0C) : (16K + 512)Byte
- X16 device(K9F5616X0C) : ( 8K + 256)Word
• Page Read Operation
- Page Size
- X8 device(K9F5608X0C) : (512 + 16)Byte
- X16 device(K9F5616X0C) : (256 + 8)Word
- Random Access
: 10µs(Max.)
- Serial Page Access : 50ns(Min.)
• Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- Data Retention : 10 Years
• Command Register Operation
• Intelligent Copy-Back
• Unique ID for Copyright Protection
• Power-On Auto-Read Operation
• Safe Lock Mechanism
• Package
- K9F56XXX0C-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F56XXX0C-DCB0/DIB0
63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- K9F5608U0C-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F56XXX0C-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package
- K9F56XXX0C-HCB0/HIB0
63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- Pb-free Package
- K9F5608U0C-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package
* K9F5608U0C-V,F(WSOPI ) is the same device as
K9F5608U0C-Y,P(TSOP1) except package type.
GENERAL DESCRIPTION
Offered in 32Mx8bit or 16Mx16bit, the K9F56XXX0C is 256M bit with spare 8M bit capacity. The device is offered in 1.8V, 2.65V,
3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can
be performed in typical 200µs on a 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in
typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per word.
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all
program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the
write-intensive systems can take advantage of the K9F56XXX0C′s extended reliability of 100K program/erase cycles by providing
ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F56XXX0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
3
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9F56XXU0C-YCB0,PCB0/YIB0,PIB0
X16
X8
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X8
X16
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
LOCKPRE
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
LOCKPRE
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
0.10
MAX
0.004
Unit :mm/Inch
#48
#24
#25
0.50
0.0197
12.40
0.488 MAX
( 0.25 )
0.010
#1
12.00
0.472
+0.003
0.008-0.001
0.20 -0.03
+0.075
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
0.25
0.010 TYP
1.00±0.05
0.039±0.002
0.125 0.035
+0.07
20.00±0.20
0.787±0.008
( 0.50 )
0.020
4
1.20
0.047MAX
0.05
0.002 MIN
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
PIN CONFIGURATION (TBGA)
K9F56XXX0C-DCB0,HCB0/DIB0,HIB0
X8
1
2
3
4
X16
5
N.C
N.C N.C
/WP
ALE
Vss
/CE
/WE
R/B
NC
/RE
CLE
NC
NC
NC
3
4
5
6
N.C N.C
N.C
A
N.C N.C
/WP
ALE
Vss
/CE
/WE
R/B
NC
/RE
CLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O5
I/O7 LOCKPRE
B
B
C
C
NC
NC
NC
NC
NC
NC
D
D
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC LOCKPRE
NC
I/O0
NC
E
E
F
F
NC
NC
NC
VccQ
NC
Vcc
NC
Vss
I/O1
I/O5
I/O7
I/O2
I/O3 I/O4
I/O6
Vcc
I/O8 I/O1 I/O10 I/O12 IO14
G
G
H
2
N.C N.C
N.C N.C
N.C N.C
A
1
6
I/O0
I/O9 I/O3 VccQ I/O6 I/O15
Vss
I/O2 I/O11 I/O4 I/O13 Vss
H
Vss
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
N.C N.C
Top View
Top View
PACKAGE DIMENSIONS
63-Ball TBGA (measured in millimeters)
Top View
Bottom View
9.00±0.10
0.80 x 9= 7.20
0.80 x 5= 4.00
9.00±0.10
6
5
0.80
4
3
2
B
1
0.80
(Datum A)
A
#A1
A
D
2.80
E
F
G
H
63-∅0.45±0.05
2.00
0.32±0.05
Side View
9.00±0.10
0.08MAX
5
0.45±0.05
0.90±0.10
∅ 0.20 M A B
11.00±0.10
C
0.80 x7= 5.60
11.00±0.10
(Datum B)
0.80 x11= 8.80
B
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
PIN CONFIGURATION (WSOP1)
K9F5608U0C-VCB0,FCB0/VIB0,FIB0
N.C
N.C
DNU
N.C
N.C
N.C
R/B
RE
CE
DNU
N.C
Vcc
Vss
N.C
DNU
CLE
ALE
WE
WP
N.C
N.C
DNU
N.C
N.C
N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F
Unit :mm
0.70 MAX
0.58±0.04
15.40±0.10
#48
#24
#25
+0.07
-0.03
0.16
+0.07
-0.03
#1
0.50TYP
(0.50±0.06)
0.20
12.00±0.10
8°
0°~
0.10 +0.075
-0.035
(0.1Min)
0.45~0.75
17.00±0.20
6
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
PIN DESCRIPTION
Pin NAME
Pin Function
I/O0 ~ I/O7
(K9F5608X0C)
I/O0 ~ I/O15
(K9F5616X0C)
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 operation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’section of Device operation.
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power tra nsitions. The internal high voltage
generator is reset when the WP pin is active low. When LOCKPRE is a logic high and WP is a logic low, the
all blocks go to lock state.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
DNU
DO NOT USE
Leave it disconnected
LOCKPRE
LOCK MECHANISM & POWER-ON AUTO-READ ENABLE
To Enable and disable the Lock mechanism and Power On Auto Read. When LOCKPRE is a logic high,
Block Lock mode and Power-On Auto-Read mode are enabled, and when LOCKPRE is a logic low, Block
Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on
3.3V device(K9F56XXU0C).
Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
7
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Figure 1-1. K9F5608X0C (X8) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A9 - A24
X-Buffers
Latches
& Decoders
A0 - A 7
Y-Buffers
Latches
& Decoders
256M + 8M Bit
NAND Flash
ARRAY
(512 + 16)Byte x 65536
Page Register & S/A
A8
Y-Gating
Command
Command
Register
CE
RE
WE
VCC/VCCQ
VSS
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
Figure 2-1. K9F5608X0C (X8) ARRAY ORGANIZATION
1 Block =32 Pages
= (16K + 512) Byte
64K Pages
(=2,048 Blocks)
1st half Page Register
2nd half Page Register
(=256 Bytes)
(=256 Bytes)
1 Page = 528 Byte
1 Block = 528 Byte x 32 Pages
= (16K + 512) Byte
1 Device = 528Bytes x 32Pages x 2048 Blocks
= 264 Mbits
8 bit
512Byte
16 Byte
I/O 0 ~ I/O 7
Page Register
512 Byte
I/O 0
I/O 1
16 Byte
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
3rd Cycle
A17
A18
A19
A20
A21
A22
A23
A24
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* The device ignores any additional input of address cycles than reguired.
8
Column Address
Row Address
(Page Address)
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Figure 1-2. K9F5616X0C (X16) FUNCTIONAL BLOCK DIAGRAM
VCC
VSS
A9 - A24
X-Buffers
Latches
& Decoders
A0 - A 7
Y-Buffers
Latches
& Decoders
256M + 8M Bit
NAND Flash
ARRAY
(256 + 8)Word x 65536
Page Register & S/A
Y-Gating
Command
Command
Register
CE
RE
WE
VCC/VCCQ
VSS
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
I/0 0
I/0 15
CLE ALE WP
Figure 2-2. K9F5616X0C (X16) ARRAY ORGANIZATION
1 Block =32 Pages
= (8K + 256) Word
64K Pages
(=2,048 Blocks)
1 Page = 264 Word
1 Block = 264 Word x 32 Pages
= (8K + 256) Word
1 Device = 264Words x 32Pages x 2048 Blocks
= 264 Mbits
Page Register
(=256 Words)
16 bit
256Word
8 Word
I/O 0 ~ I/O 15
Page Register
256 Word
I/O 0
I/O 1
I/O 2
8 Word
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O8 to 15
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
L*
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
L*
3rd Cycle
A17
A18
A19
A20
A21
A22
A23
A24
L*
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
9
Column Address
Row Address
(Page Address)
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
PRODUCT INTRODUCTION
The K9F56XXX0C is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528(X8 device) or 264(X16 device)
columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8
device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations.The memory array is made up of 16 cells that are serially connected
to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND structured strings. A NAND
structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in Figure 2-1,2-2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array
consists of 2048 separately erasable 16K-Byte(X8 device) or 8K-Word(X16 device) blocks. It indicates that the bit by bit erase operation is prohibited on the K9F56XXX0C.
The K9F56XXX0C has addresses multiplexed into 8 I/Os(X16 device case : lower 8 I/Os). K9F5616X0C allows sixteen bit wide data
transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows
systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written
through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one
bus cycle. For example, Reset command, Read command, Status Read command, etc require just one cycle bus. Some other commands like Page Program and Copy-back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for
execution. The 32M-byte(X8 device) or 16M-word(X16 device) physical space requires 24 addresses(X8 device) or 23
addresses(X16 device), thereby requiring three cycles for word-level addressing: column address, low row address and high row
address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In
Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F56XXX0C.
The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by contact with Samsung.
Table 1. COMMAND SETS
Function
Read 1
Read 2
1st. Cycle
00h/01h
2nd. Cycle
Acceptable Command during Busy
-
(1)
50h
-
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Copy-Back Program
00h
8Ah
Lock
2Ah
-
Unlock
23h
24h
Lock-tight
2Ch
-
Read Block Lock Status
7Ah
-
Block Erase
60h
D0h
Read Status
70h
-
NOTE : 1. The 01h command is available only on X8 device(K9F5608X0C).
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
10
O
O
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Temperature Under Bias
Rating
Symbol
K9F56XXX0C-XCB0
3.3V/2.65V DEVICE
VIN/OUT
-0.6 to + 2.45
-0.6 to + 4.6
VCC
-0.2 to + 2.45
-0.6 to + 4.6
VCCQ
-0.2 to + 2.45
K9F56XXX0C-XCB0
V
-0.6 to + 4.6
-10 to +125
TBIAS
K9F56XXX0C-XIB0
Storage Temperature
Unit
1.8V DEVICE
°C
-40 to +125
TSTG
-65 to +150
°C
Ios
5
mA
K9F56XXX0C-XIB0
Short Circuit Current
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F56XXX0C-XCB0 :TA=0 to 70°C, K9F56XXX0C-XIB0:TA=-40 to 85°C)
Parameter
Symbol
K9F56XXQ0C(1.8V)
K9F56XXD0C(2.65V)
K9F56XXU0C(3.3V)
Min
Typ.
Max
Min
Typ.
Max
Min
Typ.
Max
Unit
Supply Voltage
VCC
1.70
1.8
1.95
2.4
2.65
2.9
2.7
3.3
3.6
V
Supply Voltage
VCCQ
1.70
1.8
1.95
2.4
2.65
2.9
2.7
3.3
3.6
V
Supply Voltage
VSS
0
0
0
0
0
0
0
0
0
V
11
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
K9F56XXX0C
Parameter
Symbol
Test Conditions
tRC=50ns, CE=VIL
IOUT=0mA
1.8V
2.65V
3.3V
Unit
Min
Typ
Max
Min
Typ
Max
Min Typ Max
-
8
15
-
10
20
-
10
20
Operating Sequential Read
Current
Program
ICC1
ICC2
-
-
8
15
-
10
20
-
10
25
Erase
ICC3
-
-
8
15
-
10
20
-
10
25
Stand-by Current(TTL)
ISB1
CE=VIH, WP=0V/VCC
-
-
1
-
-
1
-
-
1
Stand-by Current(CMOS)
ISB2
CE=VCC-0.2, WP=0V/VCC
-
10
50
-
10
50
-
10
50
-
-
±10
-
-
±10
-
-
±10
-
-
±10
-
-
±10
-
-
Input Leakage Current
ILI
VIN=0 to Vcc(max)
Output Leakage Current
ILO
VOUT=0 to Vcc(max)
VccQ
I/O pins
Input High Voltage
-0.4
VIH*
Except I/O pins
Input Low Voltage, All
inputs
VIL*
K9F56XXQ0C :IOH=-100µA
Output High Voltage Level
VOH
K9F56XXD0C :IOH=-100µA
K9F56XXU0C :IOH=-400µA
VCC
-0.4
-0.3
-
VCCQ VCCQ
+0.3
-0.4
VCC
VCC
+0.3
-0.4
0.4
-0.3
-
VCCQ
+0.3
VCC
+0.3
0.5
2.0
-
2.0
-
-0.3
-
mA
µA
±10
VCCQ
+0.3
VCC
+0.3
0.8
V
VCCQ
-
-
-
-
0.1
3
4
-
-0.1
VCCQ
-
-
2.4
-
-
-
-
0.4
-
-
0.4
3
4
-
8
10
-
-0.4
K9F56XXQ0C :IOL=100uA
Output Low Voltage Level
VOL
K9F56XXD0C :IOL=100µA
K9F56XXU0C :IOL=2.1mA
K9F56XXQ0C :VOL=0.1V
Output Low Current(R/B)
IOL(R/B) K9F56XXD0C :VOL=0.1V
K9F56XXU0C :VOL=0.4V
NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
12
mA
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
NVB
2013
-
2048
Blocks
Valid Block Number
NOTE :
1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(K9F56XXX0C-XCB0 :TA=0 to 70°C, K9F56XXX0C-XIB0:TA=-40 to 85°C
K9F56XXQ0C : Vcc=1.70V~1.95V , K9F56XXD0C : Vcc=2.4V~2.9V , K9F56XXU0C : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
Input Pulse Levels
K9F56XXQ0C
K9F56XXD0C
K9F56XXU0C
0V to VccQ
0V to VccQ
0.4V to 2.4V
Input Rise and Fall Times
Input and Output Timing Levels
5ns
5ns
5ns
VccQ/2
VccQ/2
1.5V
K9F56XXQ0C:Output Load (VccQ:1.8V +/-10%)
K9F56XXD0C:Output Load (VccQ:2.65V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
K9F56XXU0C:Output Load (VccQ:3.0V +/-10%)
K9F56XXU0C:Output Load (VccQ:3.3V +/-10%)
-
-
1 TTL GATE and CL=100pF
CAPACITANCE(TA=25°C, VCC=1.8V/2.65V/3.3V, f=1.0MHz)
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
Item
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
H
L
L
H
WE
RE
PRE
WP
L
H
X
X
L
H
X
X
H
L
L
H
X
H
L
H
L
H
X
H
L
L
L
L
L
L
H
H
X
X
X
X
L
L
L
X
X
X
X
X
X
Mode
Read Mode
Command Input
Address Input(3clock)
Write Mode
Command Input
Address Input(3clock)
X
H
Data Input
X
X
Data Output
H
X
X
During Read(Busy) on K9F5608U0C_Y,P or K9F5608U0C_V,F
H
H
X
X
During Read(Busy) on the devices except K9F5608U0C_Y,P and
K9F5608U0C_V,F
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X(1)
X
X
X
X
L
Write Protect
H
X
X
0V/V
CC(2)
0V/V
CC(2)
Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
13
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
PROGRAM/ERASE CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG
-
200
500
µs
Dummy Busy Time for the Lock or Lock-tight Block
tLBSY
-
5
10
µs
-
-
2
cycles
-
-
3
cycles
-
2
3
ms
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
Spare Array
Block Erase Time
tBERS
AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT
Parameter
Symbol
Min
Max
Unit
CLE Set-up Time
tCLS
0
-
ns
CLE Hold Time
tCLH
10
-
ns
CE Setup Time
tCS
0
.-
ns
CE Hold Time
tCH
10
-
ns
WE Pulse Width
tWP
25 (1)
-
ns
ALE Setup Time
tALS
0
-
ns
ALE Hold Time
tALH
10
-
ns
Data Setup Time
tDS
20
-
ns
Data Hold Time
tDH
10
-
ns
Write Cycle Time
tWC
45
-
ns
WE High Hold Time
tWH
15
-
ns
NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns.
AC CHARACTERISTICS FOR OPERATION
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
Parameter
tR
-
10
µs
ALE to RE Delay
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
25
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
50
-
ns
CE Access Time
tCEA
-
45
ns
tREA
-
K9F56XXQ0C
RE Access Time
K9F56XXU0C
35
ns
30
RE High to Output Hi-Z
tRHZ
-
30
ns
CE High to Output Hi-Z
tCHZ
-
20
ns
RE or CE High to Output hold
tOH
15
-
ns
RE High Hold Time
tREH
15
-
ns
tIR
0
-
ns
ns
Output Hi-Z to RE Low
WE High to RE Low
tWHR1
60
-
WE High to RE Low in Block Lcok Mode
tWHR2
100
-
Device Resetting Time(Read/Program/Erase)
K9F5608U0CY,V,P,F only
tRST
-
Last RE High to Busy(at sequential read)
tRB
-
CE High to Ready(in case of interception by CE at read)
tCRY
-
CE High Hold Time(at the last serial read)(2)
tCEH
100
NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.
14
ns
(1)
5/10/500
100
50 +tr(R/B)
-
µs
ns
(3)
ns
ns
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is so called as the invalid block information. Devices with invalid block(s) have the same quality
level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design
must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block(s) information is written prior to shipping. The invalid
block(s) status is defined by the 6th byte(X8 device) or 1st word(X16 device) in the spare area. Samsung makes sure that either the
1st or 2nd page of every invalid block has non-FFh(X8 device) or non-FFFFh(X16 device) data at the column address of 517(X8
device) or 256 and 261(X16 device). Since the invalid block information is also erasable in most cases, it is impossible to recover the
information once it has been erased. Therefore, the system must be able to recognize the invalid block(s) based on the original
invalid block information and create the invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of
the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
*
Create (or update)
Invalid Block(s) Table
No
Check "FFh" at the column address
517(X8 device) or 256 and 261(X16 device)
of the 1st and 2nd page in the block
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create invalid block table.
15
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Read back ( Verify after Program) --> Block Replacement
or ECC Correction
Single Bit Failure
Verify ECC -> ECC Correction
Write
Read
Detection and Countermeasure sequence
Erase Failure
ECC
: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection
Program Flow Chart
If ECC is used, this verification
operation is not needed.
Start
Write 00h
Write 80h
Write Address
Write Address
Wait for tR Time
Write Data
Write 10h
Verify Data
No
*
Program Error
Read Status Register
Yes
Program Completed
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
Yes
No
No
*
I/O 0 = 0 ?
Yes
16
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Read Data
Read Status Register
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
Reclaim the Error
No
Verify ECC
Yes
Yes
*
Erase Error
No
Page Read Completed
I/O 0 = 0 ?
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
{
nth
Block A
2
an error occurs.
(page)
1st
∼
(n-1)th
nth
Buffer memory of the controller.
{
Block B
1
(page)
* Step1
When an error happens in the nth page of the Block ’A’during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not further erase Block ’A’by creating an ’invalid Block’table or other appropriate scheme.
17
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Pointer Operation of K9F5608X0C(X8)
Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’
command sets the pointer to ’A’area(0~255byte), ’01h’command sets the pointer to ’B’area(256~511byte), and ’50h’command sets
the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole
page(0~527byte). ’00h’or ’50h’is sustained until another address pointer command is inputted. ’01h’command, however, is effective
only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the
address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted
before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from
’B’area, ’01h’command must be inputted right before ’80h’command is written.
Table 2. Destination of the pointer
Command
Pointer position
Area
00h
01h
50h
0 ~ 255 byte
256 ~ 511 byte
512 ~ 527 byte
1st half array(A)
2nd half array(B)
spare array(C)
"A" area
(00h plane)
"B" area
(01h plane)
256 Byte
256 Byte
"A"
"B"
"C" area
(50h plane)
16 Byte
"C"
Internal
Page Register
Pointer select
commnad
(00h, 01h, 50h)
Pointer
Figure 4. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’,’C’area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’area(256~512), and will be reset to
’A’area after every program operation is executed.
Address / Data input
01h
80h
Address / Data input
10h
01h
’B’, ’C’area can be programmed.
It depends on how many data are inputted.
80h
10h
’01h’command must be rewritten before
every program operation
(3) Command input sequence for programming ’C’ area
The address pointer is set to ’C’area(512~527), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’C’area can be programmed.
80h
’50h’command can be omitted.
18
10h
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Pointer Operation of K9F5616X0C(X16)
Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’command
sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the
starting column address can be set to any of a whole page(0~263word). ’00h’or ’50h’is sustained until another address pointer command is inputted. To program data starting from ’A’ or ’B’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is
written. A complete read operation prior to ’80h’command is not necessary.
Table 3. Destination of the pointer
Command
Pointer position
Area
00h
50h
0 ~ 255 word
256 ~ 263 word
main array(A)
spare array(B)
"A" area
(00h plane)
"B" area
(50h plane)
256 Word
8 Word
"A"
"B"
Internal
Page Register
Pointer select
command
(00h, 50h)
Pointer
Figure 5. Block Diagram of Pointer Operation
(1) Command input sequence for programming ’A’ area
The address pointer is set to ’A’area(0~255), and sustained
Address / Data input
00h
80h
Address / Data input
10h
00h
’A’,’B’area can be programmed.
It depends on how many data are inputted.
80h
10h
’00h’command can be omitted.
(2) Command input sequence for programming ’B’ area
The address pointer is set to ’B’area(256~263), and sustained
Address / Data input
50h
80h
Address / Data input
10h
50h
Only ’B’area can be programmed.
80h
’50h’command can be omitted.
19
10h
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte(x8 device), 264word(x16 device) page registers are utilized as seperate buffers for this operation and the system design gets
more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during
the data-loading and reading would provide significant savings in power consumption.
Figure 6. Program Operation with CE don’t-care.
CLE
CE don’t-care
≈
≈
CE
WE
ALE
I/Ox
80h
Start Add.(3Cycle)
tCS
Data Input
tCH
Data Input
10h
tCEA
CE
CE
tREA
RE
tWP
tOH
WE
I/O0~15
out
Figure 7. Read Operation with CE don’t-care.
CLE
On K9F5608U0C_Y,P or K9F5608U0C_V,F
CE must be held
low during tR
CE don’t-care
≈
CE
RE
ALE
tR
R/B
WE
I/Ox
00h
Data Output(sequential)
Start Add.(3Cycle)
20
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Device
K9F5608X0C(X8 device)
I/O
DATA
I/Ox
Data In/Out
I/O 0 ~ I/O 7
K9F5616X0C(X16 device)
I/O 0 ~ I/O 15
~528byte
~264word
1)
NOTE: 1. I/O8~15 must be set to "0" during command or address input.
I/O8~15 are used only for data bus.
Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
I/Ox
Address Latch Cycle
tCLS
CLE
tWC
tCS
tWC
CE
tCH
tWP
tWP
tWP
WE
tWH
tALH tALS
tWH
tALH tALS
tALS
tALH
ALE
tDS
I/Ox
tDH
tDS
tDH
A9~A16
AO~A7
21
tDS
tDH
A17~A24
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
tWP
≈
ALE
tWP
tWP
WE
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
I/Ox
DIN n
DIN 1
≈
DIN 0
Sequential Out Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tCHZ*
tOH
tREH
≈
tREA
tREA
tRP
RE
tREA
I/Ox
Dout
Dout
≈
tRHZ*
tRHZ*
tOH
Dout
≈
tRR
R/B
NOTES : Transition is measured ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
22
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tOH
tWHR1
RE
tDH
tDS
I/Ox
tIR
tRHZ
tOH
tREA
Status Output
70h
READ1 OPERATION(READ ONE PAGE)
CLE
1)
tCEH
On K9F5608U0C_Y,P or K9F5608U0C_V,F
CE must be held
low during tR
CE
tCHZ
tOH
tWC
WE
tWB
tCRY
tAR
ALE
tR
RE
tRHZ
tOH
tRC
≈
N Address
I/Ox
Read
CMD
A0~A7
Column
Address
R/B
A9~A16
Dout N
A17~A24
Dout N+1
Dout N+2
Dout N+3
≈ ≈
tRR
Dout m
tRB
Page(Row)
Address
Busy
1)
X8 device : m = 528 , Read CMD = 00h or 01h
X16 device : m = 264 , Read CMD = 00h
NOTES : 1) is only valid on K9F5608U0C_Y,P or K9F5608U0C_V,F
23
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
READ1 OPERATION (INTERCEPTED BY CE)
CLE
On K9F5608U0C_Y,P or K9F5608U0C_V,F
CE must be held
low during tR
CE
WE
tWB
tCHZ
tOH
tAR
ALE
tRC
tR
RE
N Address
tRR
I/Ox
Read
CMD
Col. Add
Row Add1
Column
Address
Dout N
Row Add2
Dout N+1
Dout N+2
Dout N+3
Page(Row)
Address
Busy
R/B
READ2 OPERATION (READ ONE PAGE)
CLE
On K9F5608U0C_Y,P or K9F5608U0C_V,F
CE must be held
low during tR
CE
WE
tR
tWB
tAR
ALE
≈
tRR
I/Ox
50h
Col. Add
Row Add1
Dout
n+M
Row Add2
R/B
Dout
n+M+1
≈
RE
Dout n+m
Selected
Row
M Address
X8 device : A0~A3 are Valid Address & A4~A7 are Don′t care
X16 device : A0~A2 are Valid Address & A3~A7 are "L"
X8 device : n = 512, m = 16
X16 device : n = 256, m = 8
n
m
Start
address M
24
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
SEQUENTIAL ROW READ OPERATION (only for K9F5608U0C-Y,P or K9F5608U0C-V,F)
CLE
CE
WE
≈
≈
ALE
Col. Add
Row Add1
Dout
N
Row Add2
Dout
N+1
Dout
N+2
≈
Ready
Dout
0
Dout
527
Busy
R/B
Dout
1
≈
00h
Dout
2
Dout
527
≈
I/Ox
≈
RE
Busy
M
M+1
N
Output
Output
PAGE PROGRAM OPERATION
CLE
CE
tWC
tWC
tWC
WE
tWB
tPROG
ALE
RE
80h
Col. Add
Sequential Data Column
Input Command Address
Row Add1
Row Add2
Page(Row)
Address
≈ ≈
I/Ox
N Address
Din
Din
N
N+1
1 up to m Data
Serial Input
Din
m
70h
Read Status
Command
≈
R/B
10h
Program
Command
X8 device : m = 528 byte
X16 device : m = 264 word
25
I/O0
I/O0=0 Successful Program
I/O0=1 Error in Program
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
COPY-BACK PROGRAM OPERATION
CLE
CE
tWC
WE
tWB
tWB
tPROG
ALE
tR
RE
I/Ox
00h
Col. Add
Row Add1
8Ah
Row Add2
70h
A0~A7 A9~A16 A17~A24
Program Column Page(Row)
Column Page(Row)
Address Address
≈
R/B
Address
≈
CommandAddress
Busy
Busy
I/O0
Read Status
Command
I/O0=0 Successful Program
I/O0=1 Error in Program
BLOCK ERASE OPERATION (ERASE ONE BLOCK)
CLE
CE
tWC
WE
tBERS
tWB
ALE
RE
I/Ox
60h
A9~A16
A17~A24
DOh
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
≈
Page(Row)
Address
Read Status
Command
26
I/O0=0 Successful Erase
I/O0=1 Error in Erase
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
MANUFACTURE & DEVICE ID READ OPERATION
CLE
CE
WE
ALE
tAR
RE
tREA
I/Ox
90h
Read ID Command
00h
ECh
Address. 1cycle
Maker Code
Device
Code*
Device Code
Device
Device Code*
K9F5608Q0C
35h
K9F5608D0C
75h
K9F5608U0C
75h
K9F5616Q0C
XX45h
K9F5616D0C
XX55h
K9F5616U0C
XX55h
27
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes(X8 device) or 264 words(X16 device) of data
within the selected page are transferred to the data registers in less than 10µs(tR). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in
50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data starting from the selected column
address up to the last column address[column 511/ 527(X8 device) 255 /263(X16 device) depending on the state of GND input pin].
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
~527 bytes(X8 device) or 256~263 words(X16 device) may be selectively accessed by writing the Read2 command with GND input
pin low. Addresses A0~A3(X8 device) or A0~A2(X16 device) set the starting address of the spare area while addresses A4~A7 are
ignored in X8 device case or A3~A7 must be "L" in X16 device case. The Read1 command is needed to move the pointer back to the
main area. Figures 8,9 show typical sequence and timings for each read operation.
Sequential Row Read is available only on K9F5608U0C_Y,P or K9F5608U0C_V,F :
After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10µs
again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation
is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of
each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of
a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the
next block, read command and address must be given. Figures 8-1, 9-1 show typical sequence and timings for sequential row read
operation.
Figure8. Read1 Operation
CLE
On K9F5608U0C_Y,P or K9F5608U0C_V,F
CE must be held
low during tR
CE
WE
ALE
tR
R/B
RE
I/Ox
00h
Start Add.(3Cycle)
X8 device : A0 ~ A7 & A9 ~ A24
X16 device : A0 ~ A7 & A9 ~ A24
Data Output(Sequential)
(00h Command)
1)
(01h Command)
1st half array
Main array
Data Field
Spare Field
2st half array
Data Field
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
array (00h) at next cycle.
01h command is only available on X8 device(K9F5608X0C).
28
Spare Field
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Figure 9. Read2 Operation
CLE
On K9F5608U0C_Y,P or K9F5608U0C_V,F
CE must be held
low during tR
CE
WE
ALE
tR
R/B
RE
I/Ox
50h
Start Add.(3Cycle)
Data Output(Sequential)
X8 device : A0 ~ A3 & A9 ~ A24
X16 device : A0 ~ A2 & A9 ~ A24
Spare Field
X8 device : A4 ~ A7 Don’t care
X16 device : A3 ~ A7 are "L"
Main array
Data Field
Spare Field
I/Ox
tR
tR
R/B
00h
≈
Figure 8-1. Sequential Row Read1 Operation (only for K9F5608U0C-Y,P or K9F5608U0C-V,F)
Data Output
Start Add.(3Cycle)
Data Output
1st
01h
2nd half array
1st half array
2nd half array
1st
2nd
Nth
Data Field
Nth
(528 Byte)
(01h Command)
(00h Command)
Block
Data Output
2nd
(528 Byte)
A0 ~ A7 & A9 ~ A24
1st half array
tR
1st
2nd
Nth
Data Field
Spare Field
29
Spare Field
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
I/Ox
tR
tR
R/B
50h
Start Add.(3Cycle)
≈
Figure 9-1. Sequential Row Read2 Operation (only for K9F5608U0C-Y,P or K9F5608U0C-V,F)
Data Output
1st
A0 ~ A3 & A9 ~ A24
Data Output
Data Output
2nd
(16Byte)
Nth
(16Byte)
(A4 ~ A7 :
Don′t Care)
1st
Block
Nth
Data Field
Spare Field
30
tR
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive
bytes/words up to 528(X8 device) or 264(X16 device), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array.
The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which
up to 528 bytes(X8 device) or 264 words(X16 device) of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. About the pointer operation, please refer to the attached
technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and
then serial data loading. The words other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid
while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10). The
internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read
Status command mode until another valid command is written to the command register.
Figure 10. Program Operation
tPROG
R/B
I/Ox
80h
Address & Data Input
10h
I/O0
70h
Pass
Fail
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execution
of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with
"00h" command with the address of the source page moves the whole 528bytes/264words(X8 device:528bytes, X16
device:264words) data into the internal buffer. As soon as the Flash returns to Ready state, copy-back programming command "8Ah"
may be given with three address cycles of target page followed. The data stored in the internal buffer is then programmed directly into
the memory cells of the destination page. Once the Copy-Back Program is finished, any additional partial page programming into the
copied pages is prohibited before erase. Since the memory array is internally partitioned into two different planes, copy-back program
is allowed only within the same memory plane. Thus, A14, the plane address, of source and destination page address must be the
same.
Figure 11. Copy-Back Program Operation
tR
tPROG
R/B
I/Ox
00h
Add.(3Cycles)
Source Address
8Ah
Add.(3Cycles)
70h
I/O0
Destination Address
Fail
31
Pass
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A 14 to A24 is valid while A 9 to A13 is ignored. The Erase Confirm command(D0h) following the block address
loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory
contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
Figure 12. Block Erase Operation
tBERS
R/B
I/Ox
60h
Address Input(2Cycle)
I/O0
70h
D0h
Pass
Block Add. : A9 ~ A24
Fail
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, a read command(00h or 50h) should be given before sequential page read cycle.
Table4. Read Status Register Definition
I/O #
I/O 0
Status
Definition
"0" : Successful Program / Erase
Program / Erase
"1" : Error in Program / Erase
"0"
I/O 1
I/O 2
I/O 3
"0"
Reserved for Future
Use
"0"
I/O 4
"0"
I/O 5
"0"
I/O 6
Device Operation
I/O 7
Write Protect
I/O 8~15
Not use
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
Don’t care
32
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
READ ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register
remains in Read ID mode until further commands are issued to it. Figure 13 shows the operation sequence.
Figure 13. Read ID Operation
CLE
tCEA
CE
WE
tAR
ALE
RE
I/Ox
tWHR1
tREA
ECh
00h
90h
Address. 1cycle
Maker code
Device
Code*
Device code
Device
Device Code*
K9F5608Q0C
35h
K9F5608D0C
75h
K9F5608U0C
75h
K9F5616Q0C
XX45h
K9F5616D0C
XX55h
K9F5616U0C
XX55h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 14 below.
Figure 14. RESET Operation
tRST
R/B
I/Ox
FFh
Table5. Device Status
Operation Mode
After Power-up
After Reset
Read 1
Waiting for next command
33
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
> In high state of LOCKPRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is
regarded as NAND Flash without LOCKPRE pin.
Block Lock Mode
Block Lock mode is enabled while LOCKPRE pin state is high, which is to offer protection features for NAND Flash data. The Block
Lock mode is divided into Unlock, Lock, Lock-tight operation. Consecutive blocks protects data by allowing those blocks to be locked
or lock-tighten with no latency. This block lock scheme offers two levels of protection. The first allows software control(command input
method) of block locking that is useful for frequently changed data blocks, while the second requires hardware control(WP low pulse
input method) before locking can be changed that is useful for protecting infrequently changed code blocks.
The followings summarized the locking functionality.
- All blocks are in a locked state on power-up. Unlock sequence can unlock the locked blocks.
- The Lock-tight command locks blocks and prevents from being unlocked.
And Lock-tight state can be returned to lock state only by Hardware control(WP low pulse input).
1. Block lock operation
1) Lock
- Command Sequence: Lock block Command(2Ah)
- All blocks default to locked by power-up and Hardware control(WP low pulse input)
- Partial block lock is not available; Lock block operation is based on all block unit
- Unlocked blocks can be locked by using the Lock block command, and a lock block’s status can be changed to unlock or lock-tight
using the appropriate commands
WP
CLE
CE
WE
I/Ox
2Ah
Lock Command
34
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
2) Unlock
- Command Sequence: Unlock block Command(23h) + Start block address + Command(24h) + End block address
- Unlocked blocks can be programmed or erased.
- An unlocked block’s status can be changed to the locked or lock-tighten state using the appropriate commands.
- Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available.
- Start block address must be nearer to the logical LSB(Least Significant Bit) than End blcok address.
- One block is selected for unlocking block when Start block address is same as End block address.
WP
CLE
CE
WE
ALE
I/Ox
23h
Unock Command
Add.1
Add.2
24h
Unlock Command
Start Block Address 2cycles
Add.1
Add.2
End Block Address 2 cycles
3) Lock-tight
- Command Sequence: Lock-tight block Command(2Ch)
- Lock-tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. A block that is locktighten can’t have it’s state changed by software control, only by hardware control(WP low pulse input); Unlocking multi area is not
available
- Only locked blocks can be lock-tighten by lock-tight command.
WP
CLE
CE
WE
I/Ox
2Ch
Lock-tight Command
35
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
WPx = H &
Unlock block Command (23h) + Start Block Address
+ Command (24h) + End Block Address
Lock
unlock
Lock
Block Lock reset
WPx = L (>100ns)
WPx = H &
Lock block command (2Ah)
WPx = H &
Unlock block Command (23h) + Start Block Address
+ Command (24h) + End Block Address
Lock
Power-up
Lock
unlock
WPx = H &
Lock-tight block command (2Ch)
WPx = H &
Lock-tight block command (2Ch)
Block Lock reset
WPx = L (>100ns)
Lock-tight
unlock
Lock-tight
Lock-tight
Figure 15. State diagram of Block Lock
Program/Erase OPERATION(In Locked or Lock-tighten Block)
tLBSY
R/B
I/Ox
60h(80h)
Address(&Data Input)
Lock
D0h(10h)
Locked or Lock-tighten Block address
On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10µs(tLBSY)
36
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
2. Block Lock Status Read
Block Lock Status can be read on a block basis, which may be read to find out whether designated block is available to be programmed or erased. After writing 7Ah command to the command register. and block address to be checked, a read cycle outputs the
content of the Block Lock Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control
allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or
CE does not need to be toggled for updated status. Blcok Lock Status Read is prohibited while the device is busy state.
Refer to table 6 for specific Status Register definitions. The command register remains in Block Lock Status Read mode until further
commands are issued to it. In high state of LOCKPRE pin, write protection status can be checked by Block Lock Status
Read(7Ah) while in low state by Status Read(70h).
IO7~IO3
IO2(Unlock)
IO1(Lock)
IO0(Lock-tight)
Read 1) block
case
X
0
1
0
Read 2) block
case
X
1
1
0
Read 3) block
case
X
0
0
1
Read 4) block
case
X
1
0
1
(1)Lock
(3)Lock-tight
(2)unlock
(4)unlock
(1)Lock
(3)Lock-tight
(1)Lock
(2)Unlock
Table6. Block Lock Status Register definitions
WP
CLE
CE
WE
ALE
tWHR2
RE
I/Ox
7Ah
Read Block Lock
status Command
Add.1
Add.2
Dout
Block Lock Status
Block Address 2cycle
37
(3)Lock-tight
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Power-On Auto-Read
The device is designed to offer automatic reading of the first page without command and address input sequence during power-on.
An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. LOCKPRE pin controls activation of
auto- page read function. Auto-page read function is enabled only when LOCKPRE pin is logic high state. Serial access may be done
after power-on without latency. Power-On Auto Read mode is available only on 3.3V device(K9F56XXU0C).
≈
Figure 16. Power-On Auto-Read (3.3V device only)
~ 1.8V
VCC
≈
CLE
≈≈
CE
WE
≈≈
ALE
tR
≈
R/B
≈
LOCKPRE
≈
RE
I/OX
1st
38
2nd
3rd
....
n th
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin
is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B)
and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 17). Its value can
be determined by the following guidance.
Rp
VCC
ibusy
1.8V device - VOL : 0.1V, VOH : VccQ-0.1V
2.65V device - VOL : 0.4V, VOH : VccQ-0.4V
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
GND
Device
Figure 17. Rp vs tr ,tf & Rp vs ibusy
39
tr
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Ibusy
300n
200n
1.7
2m
tr
100n
3m
30
0.85
120
90
60
0.57
1.7
1.7
1.7
2K
3K
Rp(ohm)
tf
1K
Ibusy [A]
tr,tf [s]
@ Vcc = 1.8V, Ta = 25°C , CL = 30pF
1m
0.43
1.7
4K
300n
3m
2.3
Ibusy
200n
100n
2m
1.1
tr
30
2.3
1K
2K
1m
0.75
2.3
2.3
tf
120
90
60
Ibusy [A]
tr,tf [s]
@ Vcc = 2.65V, Ta = 25°C , CL = 30pF
2.3
0.55
4K
3K
Rp(ohm)
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
tr,tf [s]
Ibusy
300n
200n
300
3m
1.2
200
0.8
2m
tr
100n
100
0.6
3.6 tf
3.6
3.6
3.6
1K
2K
3K
Rp(ohm)
4K
Rp value guidance
Rp(min, 1.8V part) =
Rp(min, 2.65V part) =
Rp(min, 3.3V part) =
1.85V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
2.5V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
3mA + ΣIL
3.2V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
3mA + ΣIL
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
40
1m
Ibusy [A]
400
2.4
K9F5608Q0C
K9F5608D0C
K9F5608U0C
K9F5616Q0C
K9F5616D0C
K9F5616U0C
FLASH MEMORY
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down and recovery time of minimum 10µs is
required before internal circuit gets ready for any command sequences as shown in Figure 18. The two step command sequence for
program/erase provides additional software protection.
Figure 18. AC Waveforms for Power Transition
≈
1.8V device : ~ 1.5V
2.65V device : ~ 2.0V
3.3V device : ~ 2.5V
VCC
≈
High
≈
WP
WE
≈
10µs
41
1.8V device : ~ 1.5V
2.65V device : ~ 2.0V
3.3V device : ~ 2.5V