SANYO LC72137

Ordering number : ENN5743B
CMOS IC
LC72137, 72137M
PLL Frequency Synthesizer
for Electronic Tuning
Overview
Package Dimensions
unit: mm
3059-DIP22S
[LC72137]
12
0.25
7.62
6.4
22
1
11
0.95
0.48
1.78
3.3
3.9max
21.2
1.7
SANYO: DIP22S
unit: mm
3036B-MFP20
[LC72137M]
10
1
12.6
0.15
7.6
0.625
5.4
6.35
11
20
1.5
• High-speed programmable frequency divider
— FMIN: 10 to 160 MHz ..Pulse swallower
(divide-by-two prescaler built in)
— AMIN: 2 to 40 MHz ......Pulse swallower
0.5 to 10 MHz ...Direct division
• IF counter
— IFIN: 0.4 to 12 MHz ......For use as an AM/FM IF
counter
• Reference frequency
— Selectable from one of eight frequencies (crystal
oscillator: 75 kHz)
1, 3, 5, 3.125, 6.25, 12.5, 15, and 25 kHz
• Phase comparator
— Supports dead zone control
— Built-in unlock detection circuit
— Built-in deadlock clear circuit
• Built-in MOS transistor for forming an active low-pass
filter
• I/O ports
— Dedicated output ports: 4
— I/O ports: 2
— Supports clock time base output
• Serial Data I/O
— Supports CCB format communication with the
system controller.
1.8 max
Features
• Operating ranges
— Supply voltage: 2.5 to 3.6 V
— Operating temperature: –20 to +70°C
• Packages
—DIP22S/MFP20
0.51min 3.25
The LC72137 and LC72137M are high input sensitivity
(FMIN: 10 mVrms at 130 MHz) PLL frequency
synthesizers for 3 V systems. They allow highperformance AM/FM tuners to be implemented easily.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
0.1
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
0.35
1.27
0.59
SANYO: MFP20
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
91099TH (OT)/N3098HA (OT)/70398RM (OT) No. 5743-1/22
LC72137, 72137M
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Conditions
Ratings
Unit
VDD max
VDD
–0.3 to +7.0
VIN1 max
CE, CL, DI, AIN
–0.3 to +7.0
V
V
VIN2 max
XIN, FMIN, AMIN, IFIN
–0.3 to VDD + 0.3
V
VIN3 max
IO1, IO2
–0.3 to +15
V
VO1 max
DO
–0.3 to +7.0
V
VO2 max
XOUT, PD
–0.3 to VDD + 0.3
V
VO3 max
BO1 to BO4, IO1, IO2, AOUT
Maximum output current
IO max
Allowable power dissipation
Pd max
–0.3 to +15
BO1 to BO4, IO1, IO2, DO, AOUT
V
0 to 6.0
mA
Ta ≤ 70°C: DIP22S
350
mW
Ta ≤ 70°C: MFP20
180
mW
Operating temperature
Topr
–20 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Allowable Operating Ranges at Ta = –20 to +70°C, VSS = 0 V
Parameter
Symbol
Ratings
Conditions
min
Supply voltage
Input high-level voltage
Input low-level voltage
Output voltage
Input frequency
Input amplitude
Guaranteed crystal
oscillator frequency
typ
Unit
max
VDD
VDD
2.5
3.6
VIH1
CE, CL, DI
0.7 VDD
6.5
V
V
VIH2
IO1, IO2
0.7 VDD
13
V
VIL
CE, CL, DI, IO1, IO2
0
0.3 VDD
V
VO 1
DO
0
6.5
V
VO 2
BO1 to BO4, IO1, IO2, AOUT
0
fIN1
XIN: VIN1
fIN2
FMIN: VIN2
10
160
fIN3
AMIN: VIN3, SNS = 1
2
40
MHz
fIN4
AMIN: VIN4, SNS = 0
0.5
10
MHz
fIN5
IFIN: VIN5
0.4
12
MHz
VIN1
XIN: fIN1
200
800
mVrms
13
75
V
kHz
MHz
VIN2-1
FMIN: f = 10 to 40 MHz
20
800
mVrms
VIN2-2
FMIN: f = 40 to 130 MHz
10
800
mVrms
VIN2-3
FMIN: f = 130 to 160 MHz
40
800
mVrms
VIN3
AMIN: fIN3, SNS = 1
40
800
mVrms
VIN4
AMIN: fIN4, SNS = 0
40
800
mVrms
VIN5-1
IFIN: fIN5, IFS = 1
40
800
mVrms
VIN5-2
IFIN: fIN6, IFS = 0
70
800
mVrms
Xtal
XIN, XOUT *
75
kHz
* Note : Recommended crystal oscillator CI value : CI ≤ 35 kΩ (for a 75kHz crystal )
The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed sircuit board pattem, and other items. Therefore we
recommend consulting with the manfacturer of the crystal for evaluation and reliability.
The extremely high input impedance of the XIN pins means that applications must take the possibility of leakage into account.
No. 5743-2/22
LC72137, 72137M
Electrical Characteristics within the allowable operating ranges
Parameter
Symbol
Ratings
Conditions
min
Internal feedback resistors
Internal pull-down resistors
Internal output resistor
XIN
8.0
Rf2
FMIN
500
kΩ
Rf3
AMIN
500
kΩ
kΩ
Rf4
IFIN
250
FMIN
200
kΩ
Rpd2
AMIN
200
kΩ
250
kΩ
Rd
XOUT
CE, CL, DI, IO1, IO2
Output high-level voltage
VOH1
PD: IO = –1 mA
VOL1
PD: IO = 1 mA
VOL2
VOL3
VOL4
Input low-level current
MΩ
Rpd1
VHIS
Input high-level voltage
Unit
max
Rf1
Hysteresis
Output low-level voltage
typ
0.1 VDD
V
VDD – 1.0
V
1.0
V
BO1 to BO4, IO1, IO2; IO = 1 mA
0.25
V
BO1 to BO4, IO1, IO2; IO = 5 mA
1.25
V
DO: IO = 1 mA
0.25
V
AOUT, IO = 1 mA, AIN = 1.3 V
0.5
V
IIH1
CE, CL, DI: VI = 6.5 V
5.0
μA
IIH2
IO1, IO2: VI = 13 V
IIH3
XIN: VI = VDD
5.0
μA
0.16
0.9
μA
IIH4
IIH5
FMIN, AMIN: VI = VDD
2.5
15
μA
IFIN: VI = VDD
5.0
30
IIH6
AIN: VI = 6.5 V
μA
200
nA
IIL1
CE, CL, DI: VI = 0 V
5.0
μA
IIL2
IO1, IO2: VI = 0 V
5.0
μA
IIL3
XIN: VI = 0 V
0.16
0.9
μA
IIL4
FMIN, AMIN: VI = 0 V
2.5
15
μA
IIL5
IFIN: VI = 0 V
5.0
30
μA
IIL6
AIN: VI = 0 V
200
nA
IOFF1
BO1 to BO4, AOUT, IO1, IO2: VO = 13 V
5.0
μA
IOFF2
DO: VO = 6.5 V
5.0
μA
High-level three-state off
leakage current
IOFFH
PD: VO = VDD
0.01
200
nA
Low-level three-state off
leakage current
IOFFL
PD: VO = 0 V
0.01
200
nA
6
mA
Output off leakage current
Input capacitance
Current drain
CIN
FMIN
IDD1
VDD: Xtal = 75 kHz, fIN2 = 130 MHz, VIN2 = 10 mVrms
2.5
IDD2
VDD: PLL block stopped (PLL inhibit),
Xtal oscillator operating (Xtal = 75 kHz)
20
IDD3
VDD: PLL block stopped, Xtal oscillator stopped
6
pF
μA
10
μA
No. 5743-3/22
LC72137, 72137M
Pin Assignments
Block Diagram
No. 5743-4/22
LC72137, 72137M
Pin Descriptions
Symbol
Pin No.
(MFP pin numbers
are in parentheses.)
XIN
20 (19)
XOUT
21 (20)
FMIN
13 (12)
Type
Functions
Xtal
• Crystal oscillator connections (75 kHz)
Local oscillator
signal input
• FMIN is selected when the serial data input DVS bit is
set to 1.
• The input frequency range is from 10 to 160 MHz.
• The input signal passes through the internal divide-bytwo prescaler and is input to the swallow counter.
• The divisor can be in the range 272 to 65535. However,
since the signal has passed through the divide-by-two
prescaler, the actual divisor is twice the set value.
Local oscillator
signal input
• AMIN is selected when the serial data input DVS bit is
set to 0.
• When the serial data input SNS bit is set to 1:
— The input frequency range is 2 to 40 MHz.
— The signal is directly input to the swallow counter.
— The divisor can be in the range 272 to 65535, and
the divisor used will be the value set.
• When the serial data input SNS bit is set to 0:
— The input frequency range is 0.5 to 10 MHz.
— The signal is directly input to a 12-bit programmable
divider.
— The divisor can be in the range 4 to 4095, and the
divisor used will be the value set.
AMIN
12 (11)
CE
2 (1)
Chip enable
• Set this pin high when inputting (DI) or outputting (DO)
serial data.
DI
3 (2)
Input data
• Inputs serial data transferred from the controller to the
LC72137.
CL
4 (3)
Clock
• Used as the synchronization clock when inputting (DI) or
outputting (DO) serial data.
DO
5 (4)
Output data
• Outputs serial data transferred from the LC72137 to the
controller. The data output is determined by the DOC0 to
DOC2 bits in the serial data.
VDD
15 (14)
Power supply
• The LC72137 power supply pin. (VDD = 2.5 to 3.6 V)
• The power on reset circuit operates when power is first
applied.
VSS
16 (15)
Ground
• The LC72137 ground
Circuit configuration
Continued on next page.
No. 5743-5/22
LC72137, 72137M
Continued from preceding page.
Symbol
Pin No.
(MFP pin numbers
are in parentheses.)
BO1
6 (5)
BO2
7 (6)
BO3
8 (7)
BO4
14 (13)
IO1
9 (8)
IO2
10 (9)
PD
17 (16)
AIN
18 (17)
AOUT
19 (18)
Type
Functions
Output ports
• Dedicated outputs
• The output states are determined by the BO1 to BO4
bits in the serial data.
Data: 0 = open, 1= low
• A time base signal (8 Hz) can be output from the BO1
pin. (When the serial data TBC bit is set to 1.)
Input or output
ports
• I/O dual-use pins
• The direction (input or output) is determined by bits IOC1
and IOC2 in the serial data.
Data: 0 = input port, 1 = output port
• When specified for use as input ports:
The state of the input pin is transmitted to the controller
over the DO pin.
Input state: low = 0 data value
high = 1 data value
• When specified for use as output ports:
The output states are determined by the IO1 and IO2
bits in the serial data.
Data: 0 = open, 1 = low
• These pins function as input pins following a power on
reset.
Charge pump
output
• PLL charge pump output
When the frequency generated by dividing the local
oscillator signal frequency by N is higher than the
reference frequency, a high level is output from the PD
pin. Similarly, when that frequency is lower, a low level is
output. The PD pin goes to the high-impedance state
when the frequencies match.
LPF amplifier
transistor
connections
• The n-channel MOS transistor used for the PLL active
low-pass filter.
IFIN
10 (9)
IF counter
• Accepts an input in the frequency range 0.4 to 12 MHz.
• The input signal is directly transmitted to the IF counter.
• The result is output starting the MSB of the IF counter
using the DO pin.
• Four measurement periods are supported: 4, 8, 16, and
32 ms.
NC
1 (–)
22 (–)
NC Pin
• No connection
Circuit configuration
No. 5743-6/22
LC72137, 72137M
Serial Data I/O Procedures
The LC72137 inputs and outputs data using the Sanyo CCB (computer control bus) audio IC serial bus format. This IC
adopts an 8-bit address format CCB.
I/O mode
Address
B0
B1
B2
B3
A0
A1
A2
A3
Function
1
IN1 (82)
0
0
0
1
0
1
0
0
• Control data input mode (serial data input)
• 24 data bits are input.
• See the “DI Control Data (serial data input) Structure”
item for details on the meaning of the input data.
2
IN2 (92)
1
0
0
1
0
1
0
0
• Control data input mode (serial data input)
• 24 data bits are input.
• See the “DI Control Data (serial data input) Structure”
item for details on the meaning of the input data.
0
• Data output mode (serial data output)
• The number of bits output is equal to the number of clock
cycles.
• See the “DO Output Data (Serial Data Output) Structure”
item for details on the meaning of the output data.
3
OUT (A2)
0
1
0
1
0
1
0
No. 5743-7/22
LC72137, 72137M
DI Control Data (serial data input) Structure
1. IN1 Mode
2. IN2 Mode
No. 5743-8/22
LC72137, 72137M
DI Control Data Descriptions
No.
Control block/data
Description
Related data
Programmable divider data • Data that sets the programmable divider
P0 to P15
A binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS.
(*: Don’t care.)
DVS
SNS
LSB
Divisor setting (N)
1
*
P0
272 to 65535
Twice the value of the setting
Actual divisor
0
1
P0
272 to 65535
The value of the setting
0
0
P4
4 to 4095
The value of the setting
Note: P0 to P3 are ignored when P4 is the LSB.
(1)
DVS, SNS
• Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches the
frequency range. (*: Don’t care.)
DVS
SNS
Input pin
Input frequency range
1
*
FMIN
10 to 160 MHz
0
1
AMIN
2 to 40 MHz
0
0
AMIN
0.5 to 10 MHz
Note: See the “Programmable Divider” item for details.
Reference divider data
R0 to R3
(2)
• Reference frequency (fref) selection data
R3
R2
R1
R0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reference frequency (kHz)
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
5
5
5
1
1
1
1
1
0
0
0
1
3
15
1
1
1
0
PLL INHIBIT + Xtal OSC STOP
1
1
1
1
PLL INHIBIT
25
25
25
25
12.5
6.25
3.125
3.125
Note: PLL INHIBIT
The programmable divider and IF counter blocks are stopped, the FMIN, AMIN,
and IFIN pins go to the pulled-down state, and the charge pump output pin goes to
the high-impedance state.
IF counter control data
CTE
• IF counter measurement start specification
CTE = 1: Counter start
CTE = 0: Counter reset
GT0, GT1
• IF counter measurement time determination
(3)
GT1
GT0
0
0
0
1
1
Measurement time (ms)
Wait time (ms)
4
3 to 4
1
8
3 to 4
0
16
3 to 4
1
32
3 to 4
IFS
Note: See the “IF Counter Structure” item for details.
(4)
(5)
I/O port specification data
IOC1, IOC2
• Data that specifies input or output for the I/O dual-use pins (IO1, IO2)
Data: 0 = input mode, 1 = output mode
Output port data
BO1 to BO4, IO1, IO2
• BO1 to BO4, IO1, and IO2 output state data
Data: 0 = open, 1 = low
• “Data = 0: Open” is selected following a power-on reset.
IOC1
IOC2
Continued on next page.
No. 5743-9/22
LC72137, 72137M
Continued from preceding page.
No.
Control block/data
DO pin control data
DOC0, DOC1, DOC2
Description
Related data
• Data that determines DO pin output
DOC2
DOC1
DOC0
0
0
0
0
0
0
1
1
0
1
0
1
Open
Low when the unlock state is detected
end-UC*1
Open
DO pin state
1
1
1
1
0
0
1
1
0
1
0
1
Open
The IO1 pin state*2
The IO2 pin state*2
Open
The open state is selected following a power-on reset.
Note: 1. end-UC: IF counter measurement completion check
UL0, UL1,
CTE,
IOC1, IOC2
(6)
➀ When end-UC is set and an IF count is started (CTE = 0 → 1), the DO pin
automatically goes to the open state.
➁ When the IF count measurement completes, the DO pin goes low and
the count completion check operation is enabled.
➂ The DO pin goes to the open state due to serial data I/O (CE: high).
2. Goes to the open state if the IO pin itself is set to be an output port.
Caution: The DO pin always goes to the open state during the data input period (during the
period when CE is high in mode IN1 or IN2), regardless of the values of the DO pin
control data (DOC0 to DOC2). Also, the DO pin outputs the content of the internal
DO serial data in synchronization with the CL pin signal during the data output period
(during the period when CE is high in the OUT mode) regardless of the values of
the DO pin control data (DOC0 to DOC2).
Unlock detection data
UL0, UL1
(7)
• Selects the phase error (øE) detection range for PLL lock discrimination.
When a phase error greater than the specified range occurs, the LC72137 determines
that the PLL is unlocked. (*: Don’t care.)
UL1
UL0
øE detection width
Detector output
0
0
Stopped
Open
0
1
0
øE is output directly
1
*
±6.67 μs
øE is extended by 1 to 2 ms
DOC0,
DOC1,
DOC2
Note: When unlocked, the DO pin goes low and the serial data output UL bit is 0.
Phase comparator
control data
DZ0, DZ1
(8)
• Phase comparator dead zone control data
DZ1
DZ0
0
0
DZA
Dead zone mode
0
1
DZB
1
0
DZC
1
1
DZD
Dead zone width: DZA < DZB < DZC < DZD
(9)
Clock time base
TBC
• An 8 Hz 40% duty clock time base signal can be output from BO1 by setting TBC to 1.
(The BO1 data will be ignored.)
Charge pump control data
DLC
• Data that forcibly controls the charge pump output
DLC
(10)
0
BO1
Charge pump output
Normal operation
1
Forced low
Note: The LC72137 provides a technique for escaping from deadlock by setting Vtune to
VCC (deadlock clear circuit). This is used when the circuit is deadlocked due to the
VCO oscillator being stopped by the VCO control voltage (Vtune) being 0 V.
Continued on next page.
No. 5743-10/22
LC72137, 72137M
Continued from preceding page.
No.
Control block/data
(11)
IF counter control data
IFS
LSI test data
TEST 0 to TEST2
(12)
Description
Related data
• This data should be set to 1 in normal operation. Setting this data to 0 switches
the LC72137 to a reduced input sensitivity mode in which the sensitivity is reduced by
10 to 30 mVrms.
• IC test data
TEST0
TEST1
All three bits must be set to 0.
TEST2
All the test data is set to 0 at a power-on reset.
(13)
DNC
Data is set to 0
DO Output Data (Serial Data Output) Structure
3. OUT mode
*
Note: * Data with a value of “0”
DO Output Data
No.
Control block/data
I/O port data
I2, I1
(1)
Description
• Data latched from the states of the I/O ports, pins IO1 and IO2.
• This data reflects the pin states, regardless of whether they are in input or output mode.
• The data is latched when OUT mode is selected.
I1 ← IO1 pin state
I2 ← IO2 pin state
Related data
IOC1,
IOC2
High: 1
Low: 0
(2)
PLL unlock data
UL
• Data latched from the state of the unlock detection circuit
UL ← 0: Unlocked
UL ← 1: Locked or in detection stopped mode
UL0,
UL1
(3)
IF counter binary data
C19 to C0
• Data latched from the state of the IF counter, which is a 20-bit binary counter.
C19 ← Binary counter MSB
C0 ← Binary counter LSB
CTE,
GT0,
GT1
No. 5743-11/22
LC72137, 72137M
Serial Data Input (IN1/IN2) tSU, tHD, tEL, tES, tEH, ≥ 0.75 μs, tLC < 0.75 μs
1. CL: Normal high
2. CL: Normal low
Serial Data Output (OUT) tSU, tHD, tEL, tES, tEH, ≥ 0.75 μs, tDC, tDH < 0.35 μs
1. CL: Normal high
2. CL: Normal low
Note: Since the DO pin is an n-channel open drain circuit, the times for the data to change (tDC and tDH) will differ depending on the value of the pull-up
resistor, printed circuit board capacitance.
No. 5743-12/22
LC72137, 72137M
Serial Data Timing
CL Stopped at the Low Level
CL Stopped at the High Level
Symbol
Pins
Data setup time
Parameter
tSU
DI, CL
0.75
μs
Data hold time
tHD
DI, CL
0.75
μs
Clock low-level time
tCL
CL
0.75
μs
Clock high-level time
tCH
CL
0.75
μs
CE wait time
tEL
CE, CL
0.75
μs
CE setup time
tES
CE, CL
0.75
μs
CE hold time
tEH
CE, CL
0.75
Data latch change time
tLC
Data output time
tDC
tDH
DO, CL
Conditions
These times depend on the pull-up resistance
DO, CE and the printed circuit board capacitances.
min
typ
max
Unit
μs
0.75
μs
0.35
μs
0.35
μs
No. 5743-13/22
LC72137, 72137M
Programmable Divider Structure
DVS
SNS
Input pin
Set divisor
Actual divisor: N
A
1
*
FMIN
272 to 65535
Twice the set value
Input frequency range (MHz)
B
0
1
AMIN
272 to 65535
The set value
2 to 40
C
0
0
AMIN
4 to 4095
The set value
0.5 to 10
10 to 160
Note: * Don’t care.
Sample Programmable Divider Divisor Calculations
1. For a 50 kHz FM step size (DVS = 1, SNS = *: FMIN selected)
• FM RF = 90.0 MHz (IF = +10.7 MHz)
FM VCO = 100.7 MHz
PLL fref = 25 kHz (R0 to R1 = 1, R2 to R3 = 0)
100.7 MHz (FM VCO) ÷ 25 kHz (fref) ÷ 2 (FMIN: divide-by-two prescaler) = 2014 → 07DE (HEX)
2. For a 5 kHz SW step size (DVS = 0, SNS = 1: AMIN high-speed side selected)
• SW RF = 21.75 MHz (IF = +450 kHz)
SW VCO = 22.20 MHz
PLL fref = 5 kHz (R0 = R2 = 0, R1 = R3 = 1)
22.2 MHz (SW VCO) ÷ 5 kHz (fref) = 4440 → 1158 (HEX)
3. For a 9 kHz MW step size (DVS = 0, SNS = 0: AMIN low-speed side selected)
• MW RF = 1008 kHz (IF = +450 kHz)
MW VCO = 1458 kHz
PLL fref = 3 kHz (R0 to R1 = 0, R2 to R3 = 1)
1458 kHz (MW VCO) ÷ 3 kHz (fref) = 486 → 1E6 (HEX)
No. 5743-14/22
LC72137, 72137M
IF Counter Structure
The LC72137 IF counter is a 20-bit binary counter, and takes the IF signal from the IFIN pin as its input. The result of
the count can be read out serially, MSB first, from the DO pin.
Measurement time
GT1
GT0
0
0
4
3 to 4
0
1
8
3 to 4
1
0
16
3 to 4
1
1
32
3 to 4
Measurement period (GT) (ms)
Wait time (tWU) (ms)
The IF frequency (Fc) is measured by determining how many pulses were input to the IF counter in the stipulated
measurement time, GT.
Fc =
C
GT
(C = Fc × GT)
C: count value (number of pulses)
Sample IF Counter Frequency Calculations
1. For a measurement time (GT) of 32 ms and a count value (C) of 53980 (hexadecimal), which is 342,400 (decimal)
IF frequency (Fc) = 342,400 ÷ 32 ms = 10.7 MHz
2. For a measurement time (GT) of 8 ms and a count value (C) of E10 (hexadecimal), which is 3600 (decimal)
IF frequency (Fc) = 3600 ÷ 8 ms = 450 kHz
No. 5743-15/22
LC72137, 72137M
IF Counter Operation
Before starting the IF count, the IF counter must be reset in advance by setting CTE in the serial data to 0.
The IF count is started by changing the CTE bit in the serial data from 0 to 1. The serial data is latched by the LC72137
when the CE pin is dropped from high to low. The IF signal must be supplied to the IFIN pin in the period between the
point the CE pin goes low and the end of the wait time at the latest. Next, the value of the IF count at the end of the
measurement period must be read out during the period CTE is 1. This is because the IF counter is reset when CTE is set
to 0.
Note: When operating the IF counter, the control microcontroller must first check the state of the IF-IC SD (station
detect) signal and only after determining that the SD signal is present turn on IF buffer output and execute an IF
count operation. Auto-search techniques that use only the IF counter are not recommended, since it is possible for
IF buffer leakage output to cause incorrect stops at points where there is no station.
If the auto-search technique is implemented using only the IF counter in combination with an IF-IC without SD
output, sensitivity-degradation mode ( IFS = 0 ) should be selected.
IFIN Minimum Sensitivity Ratings
f(MHz)
IFS
0.4 ≤ f < 0.5
0.5 ≤ f < 8
8 ≤ f ≤ 12
1: Normal mode
40mVrms
(0.1 to 1mVrms)
40mVrms
40mVrms
(1 to 10mVrms)
0: Degradation mode
70mVrms
(5 to 15mVrms)
70mVrms
70mVrms
(20 to 40mVrms)
Note:Values in parentheses are actual performance values presented as reference data.
No. 5743-16/22
LC72137, 72137M
Unlock Detection Timing
1. Unlock Detection Determination Timing
Unlock detection is performed in the reference frequency (fref) period (interval). Therefore, in principle, unlock
determination requires a time longer than the period of the reference frequency. However, immediately after changing
the divisor N (frequency) unlock detection must be performed after waiting at least two periods of the reference
frequency.
Figure 1 Unlock Detection Timing
For example, if fref is 1 kHz (and thus the period is 1 ms), after changing the divisor N, the system must wait at least
2 ms before checking for the unlocked state.
Figure 2 Circuit Structure
No. 5743-17/22
LC72137, 72137M
2. Unlock Detection Software
Figure 3
3. When Outputting Unlock Data Using Serial Data Output:
Once the LC72137 detects an unlocked state, it does not reset the unlock data (UL) until the next data output (or data
input) operation is performed. At the data output ① point in Figure 3, although the VCO frequency is stable (locked),
the unlock data remains set to the unlocked state since no data output has been performed since the value of N was
changed. Thus, even though the frequency became stable (locked), from the point of view of the data, the circuit is in
the unlocked state. Therefore, the data output ① immediately following a change to the value of N should be seen as
a dummy data, and the data from the second data output (data output ②) and later outputs should be seen as valid
data.
Lock Determination Flowchart
No. 5743-18/22
LC72137, 72137M
When directly outputting data from the DO pin (set up by the DO pin control data)
Since the DO pin outputs the unlocked state (locked: high, unlocked: low) the timing considerations in the technique
described in the previous section are not necessary. After changing the value of N, the locked state can be determined
after waiting at least two periods of the reference frequency.
Notes on Clock Time Base Usage
When the clock time base output is used, the value of the pull-up resistor for the output pin (BO1) must be at least 100 kΩ.
We recommend the use of a Schmitt input on the receiving controller (microprocessor) to prevent chattering.This is to
avoid degradation of the VCO C/N characteristics when using the built-in low-pass filter transistor to form the loop
filter. Since the clock time base output pin and the low-pass filter transistor ground are the same mode in the IC, the time
base output pin current fluctuations must be suppressed to limit the influence on the low-pass filter.
Other Items
1. Notes on the Phase Comparator Dead Zone
DZ1
DZ0
Dead-zone mode
Charge pump
0
0
DZA
ON/ON
Dead zone
0
1
DZB
ON/ON
–0 s
1
0
DZC
OFF/OFF
+0 s
1
1
DZD
OFF/OFF
+ +0 s
– –0 s
Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the
ON/ON state, the loop can easily become unstable. This point requires special care when designing application
circuits.
The following problems may occur in the ON/ON state.
• Side band generation due to reference frequency leakage
• Side band generation due to both the correction pulse envelope and low frequency leakage
No. 5743-19/22
LC72137, 72137M
Schemes in which a dead zone is present (OFF/OFF) have good loop stability, but have the problem that acquiring a
high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with schemes in
which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective to select DZA
or DZB, which have no dead zone, in applications which require an FM S/N ratio in excess of 90 to 100 dB, or in
which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting DZC or DZD,
which provide a dead zone, for applications which do not require such a high FM signal-to-noise ratio and in which
either AM stereo is not used or an adequate AM stereo pilot margin can be achieved.
Dead Zone
The phase comparator compares fp to a reference frequency (fr) as shown in Figure 4. Although the characteristics of
this circuit (see Figure 5) are such that the output voltage is proportional to the phase difference ø (line A), a region
(the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal
circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide
a high S/N ratio.
However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularlypriced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the
VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit
outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF
signal.
Figure 4
Figure 5
2. Notes on the FMIN, AMIN, and IFIN Pins
Coupling capacitors must be placed as close as possible to their respective pin. A capacitance of about 100 pF is
desirable. In particular, if a capacitance of 1000 pF or over is used for the IF pin, the time to reach the bias level will
increase and incorrect counting may occur due to the relationship with the wait time.
3. Notes on IF Counting → SD must be used in conjunction with the IF counting time
When using IF counting, always implement IF counting by having the microprocessor determine the presence of the
IF-IC SD (station detect) signal and turn on the IF counter buffer only if the SD signal is present. Schemes in which
auto-searches are performed with only IF counting are not recommended, since they can stop at points where there is
no signal due to leakage output from the IF counter buffer.
No. 5743-20/22
LC72137, 72137M
4. DO Pin Usage Techniques
In addition to data output mode times, the DO pin can also be used to check for IF counter count completion and for
unlock detection output. Also, an input pin state can be output unchanged through the DO pin and input to the
controller.
5. Power Supply Pins
A capacitor of at least 2000 pF must be inserted between the power supply VDD and VSS pins for noise exclusion.
This capacitor must be placed as close as possible to the VDD and VSS pins.
6. Note on VCO designing
VCO ( local oscillator ) must keep its oscillation even if the control voltage ( Vtune ) goes to 0V. When there is a
possibility of oscillation halt, Vtune must be forcibly set to VCC temporarily to prevent the PLL from being
deadlocked. ( Deadlock clear circuit )
7. Front end connection example
Since this product is designed with the relatively high resistance of 200 kΩ for the pull-down (on) resistors built in to
the FMIN and AMIN pins, a common AM/FM local oscillator buffer can be used as shown in the following circuit.
FMIN
FM OSC
OSC buffer out
On resistance: 200 kΩ
AMIN
AM OSC
On resistance: 200 kΩ
FE
PLL
A10186
Pin States at a Power-On Reset
No. 5743-21/22
LC72137, 72137M
Sample Application System
(Using the MFP20 package)
Unlock
SD
end-UC
IF COUNT
ST-indic
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
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or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of September, 1999. Specifications and information herein are
subject to change without notice.
PS. No. 5743-22/22