Ordering number : ENN6675 CMOS IC LC72147V PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems Package Dimensions unit: mm 3175A-SSOP24 1.0 [LC72147V] 13 24 7.6 0.5 • High-speed programmable divider — FMIN: 10 to 180 MHz: Pulse swallower type • IF counter — HCTR: 0.4 to 25 MHz: Frequency measurement • Crystal oscillator: One of the following 4 frequencies may be selected: 10.35, 10.25, 7.2, and 4.5 MHz Reference frequency — One of 12 frequencies may be selected (when a 7.2 or 4.5 MHz crystal is used) 100*1, 50, 30*2, 25, 12.5, 6.25, 3.125, 10, 9*2, 5, 3*2, 1 kHz Notes: 1. Cannot be used when a 10.35 or 10.25 MHz crystal is used 2. Cannot be used when a 10.25 MHz crystal is used • Phase comparator — Supports dead band control — Built-in unlock detection circuit — Sub-charge pump for fast locking — Built-in deadlock clearing circuit • Built-in MOS transistor for forming an active low-pass filter 5.6 Functions 1 12 1.6max The LC72147V is a PLL frequency synthesizer for car audio systems. It can implement high-performance multifunction tuners and features a crystal oscillator circuit that supports AM up-conversion, a fast locking circuit, an A/D converter, and an LA1783/1750 IF counter buffer control pin. • I/O ports — General-purpose I/O: 5 pins — Output: n-channel: 3 pins, CMOS: 2 pins — IFBC pin (LA1783/1750 IF counter buffer control pin) • Serial data I/O — Supports communication with the controller in the CCB format. • Operating ranges — Supply voltage (VDD): 4.5 to 6.5 V — Built-in regulator voltage (Vreg): 3.0 V (±10%) — Operating temperature: –40 to +85°C • Package — SSOP-24 8.0 0.15 0.1 Overview 0.22 0.65 0.43 SANYO: SSOP24 • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN O1300RM (OT) No. 6675-1/22 LC72147V CE DI CL DO ADC1 ADC0 I/O-2 I/O-1 HCTR IFBC I/O-5 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 XIN I/O-3 XBUF VDD Vreg VSS PD AIN AOUT AVSS I/O-4 FMIN XOUT Pin Assignment Block Diagram XBUF 3 XIN XOUT 14 bits PROGRAMMABLE REFERENCE 1 PHASE DETECTOR CHARGE PUMP 24 7 PD 8 AIN PDS FMIN 9 AOUT SWALLOW COUNTER 1/16, 1/17 4 bits 12 10 AVSS 15 HCTR 12 bits PROGRAMMABLE DIVIDER UNIVERSAL COUNTER CE 23 DI 22 CL 21 DO 20 VDD 4 VSS 6 18 ADC0 CCB I/F A/D CONVERTER DATA SHIFT REGISTER LATCH 19 ADC1 POWER ON RESET VOLTAGE REGULATOR 3V 5 16 17 2 11 13 14 Vreg I/O-1 I/O-2 I/O-3 I/O-4 I/O-5 IFBC No. 6675-2/22 LC72147V Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Supply voltage Maximum input voltage Maximum output voltage Maximum output current Allowable power dissipation Symbol Pin Conditions Ratings Unit VDD max VDD –0.3 to +7.0 VIN1 max CE, CL, DI, AIN –0.3 to +7.0 VIN2 max XIN, FMIN, HCTR, I/O-4, I/O-5, ADC0, ADC1 VIN3 max I/O-1 to I/O-3 VO1 max DO VO2 max XOUT, IFBC, I/O-4, I/O-5, PD, XBUF VO3 max I/O-1 to I/O-3, AOUT IO1 max IFBC IO2 max I/O-4, I/O-5, XBUF 0 to 3.0 IO3 max DO 0 to 6.0 IO4 max I/O-1 to I/O-3 0 to 10 IO5 max AOUT V –0.3 to Vreg + 0.3 V –0.3 to +15 –0.3 to +7.0 –0.3 to Vreg + 0.3 V –0.3 to +15 0 to 1.0 mA 0 to 35 Ta ≤ 85°C Pd max 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Note: Power supply VDD - VSS, Vreg - VSS: Capacitors of at least 2000 pF must be inserted between these pins when this device is used. Allowable Operating Ranges at Ta = –40 to 85°C, VSS = 0 V Parameter Supply voltage Regulator output voltage High-level input voltage Low-level input voltage Output voltage Input frequency Guaranteed crystal oscillator frequency ranges Input amplitude Symbol Conditions Ratings min typ max VDD1 VDD VDD2 VDD Serial data retention voltage 2.5 Vreg Vreg 4.5 ≤ VDD ≤ 6.5 V 2.7 VIH1 CE, CL, DI, I/O-1 to I/O-3 2.2 6.5 VIH2 I/O-4, I/O-5 2.2 Vreg 4.5 3.0 V 3.3 V V CE, CL, DI, I/O-1 to I/O-5 0 0.8 VO1 DO 0 6.5 VO2 I/O-1 to I/O-3 0 13 fIN1 XIN Sine wave, capacitance coupled 1.0 8.0 fIN2 FMIN Sine wave, capacitance coupled 10 180 fIN3 HCTR Sine wave, capacitance coupled 0.4 25 X’tal1 XIN, XOUT *1 4.0 7.0 X’tal2 XIN, XOUT *1 7.1 10.5 VIN1 XIN 10 ≤ f < 130 MHz *2 200 900 40 900 VIN2-1 FMIN VIN2-2 FMIN 130 ≤ f ≤ 180 MHz *2 70 900 VIN3-1 HCTR 0.4 ≤ f ≤ 25 MHz *3 70 900 HCTR 8 ≤ f ≤ 12 MHz *4 VIN4 Unit 6.5 VIL VIN3-2 Input voltage range Pin ADC0, ADC1 100 900 0 Vreg V V MHz MHz mVrms V Data setup time tSU DI, CL *5 0.45 µs Data hold time tHD DI, CL *5 0.45 µs Clock low-level period tCL CL *5 0.45 µs Clock high-level period tCH CL *5 0.45 µs CE wait time tEL CE, CL *5 0.45 µs CE setup time tES CE, CL *5 0.45 µs CE hold time tEH CE, CL *5 0.45 Data latch change time tLC Data output time *5 tDC DO, CL tDH DO, CE Depends on the value of the pull-up resistor used. µs 0.45 µs 0.2 µs Notes:1. Recommended crystal oscillator CI values CI ≤ 120 Ω (Crystal: 4.5 MHz), CI ≤ 70 Ω (Crystal: 7.2, 10.25, or 10.35 MHz) Note that the crystal oscillator circuit characteristics depend on the printed circuit board and the particular components used. We recommend consulting the manufacturer of the crystal when designing this circuit. 2. Refer to the description of the structure of the programmable divider. 3. Serial data: CTC = 0 4. Serial data: CTC = 1 5. See the timing chart for serial data transfers. No. 6675-3/22 LC72147V Electrical Characteristics in the Allowable Operating Ranges Parameter Internal feedback resistance Hysteresis Symbol Low-level output voltage Mid-level output voltage Conditions Ratings min typ XIN 1.0 Rf2 FMIN 500 Rf3 HCTR 250 VHIS CE, CL, DI I/O-4, I/O-5 Unit max Rf1 VOH1 High-level output voltage Pin MΩ kΩ 0.1 Vreg IO = – 0.5 mA Vreg – 0.5 IO = – 1 mA Vreg – 1.0 IO = – 1 mA Vreg – 0.5 VOH2 PD, AIN IO = – 2 mA Vreg – 1.0 VOH3 XBUF IO = – 0.5 mA Vreg – 0.5 VOH4 IFBC IO = – 0.1 mA Vreg – 0.5 V V V V IO = 0.5 mA 0.5 IO = 1 mA 1.0 IO = 1 mA 0.5 IO = 2 mA 1.0 V VOL1 I/O-4, I/O-5 VOL2 PD, AIN VOL3 XBUF IO = 0.5 mA 0.5 V VOL4 IFBC IO = 0.1 mA 0.5 V IO = 1 mA 0.2 V IO = 2.5 mA 0.5 IO = 5 mA 1.0 IO = 9 mA 1.8 IO = 5 mA 1.0 AOUT IO = 30 mA, AIN = 2.0 V 1.5 V VOM IFBC IO = 20 µA 1.8 V VOL5 I/O-1 to I/O-3 VOL6 DO VOL7 1.2 1.5 V V IIH1 CE, CL, DI VI = 6.5 V 5.0 IIH2 I/O-1 to I/O-3 VI = 13 V 5.0 IIH3 I/O-4, I/O-5, ADC0, ADC1, HCTR VI = Vreg 5.0 IIH4 XIN VI = Vreg 1.3 7 IIH5 FMIN VI = Vreg 2.5 14 IIH6 HCTR VI = Vreg 5.0 IIH7 AIN VI = Vreg 200 IIL1 CE, CL, DI VI = 0 V 5.0 IIL2 I/O-1 to I/O-3 VI = 0 V 5.0 IIL3 I/O-4, I/O-5, ADC0, ADC1, HCTR VI = 0 V 5.0 IIL4 XIN VI = 0 V 1.3 7 IIL5 FMIN VI = 0 V 2.5 14 IIL6 HCTR VI = 0 V 5.0 IIL7 AIN VI = 0 V 200 IOFF1 I/O-1 to I/O-3 VO = 13 V 5.0 IOFF2 DO VO = 6.5 V 5.0 High-level 3-state off leakage current IOFFH PD VO = Vreg 0.01 200 nA Low-level 3-state off leakage current IOFFL PD VO = 0 V 0.01 200 nA 1/2 LSB 600 kΩ High-level input current Low-level input current Output off leakage current Input capacitance CIN FMIN A/D converter linearity error Err ADC0, ADC1 Pull-down transistor on resistance Rpd FMIN Supply current IDD VDD 28 6 80 nA µA 28 –1/2 X’tal = 10.35 MHz fIN2 = 180 MHz VIN2 – 2 = 70 mVrms fIN3 = 25 MHz VIN3 – 1 = 70 mVrms µA 200 12 nA µA PF mA No. 6675-4/22 LC72147V Pin Functions Pin No. Symbol 1 XIN 24 XOUT Usage X’tal OSC Function Pin circuit • Crystal oscillator connection. (4.5, 7.2, 10.25, or 10.35 MHz) • FMIN is selected by setting DVS in the control data to 1. 12 FMIN Local oscillator signal input • Input frequency: 10 to 180 MHz • The signal is transmitted to the swallow counter. • The divisor can be set to a value in the range 272 to 65,535. 23 CE Chip enable • This pin must be set to the high level when inputting serial data to the LC72147V DI pin and when outputting serial data from the DO pin. S 21 CL Clock • Data synchronization clock signal used when inputting serial data to the LC72147V DI pin and when outputting serial data from the DO pin. S 22 DI Input data • Serial data input for transferring data from the controller to the LC72147V. S 20 DO Output data • Serial data output for transferring data from the LC72147V to the controller. 4 VDD Power • LC72147V power supply. A voltage in the range 4.5 to 6.5 V must be provided when the PLL circuit is operating. ——— • The power-on reset circuit operates when power is first applied. 5 Vreg Regulator output • Regulator output. A capacitor must be inserted between Vreg and VSS. ——— • The output voltage (3.0 V ±10%) is supplied to internal circuits. 6 VSS Ground 14 IFBC IF buffer control • LC72147V ground. ——— • The LC72147V can control the LA1783/1750 IF buffer output. • This is a 3-state output. (0 V, Vreg/2 = 1.5 V, and Vreg = 3 V) • General-purpose I/O ports. 16 I/O-1 17 I/O-2 2 I/O-3 • The outputs are open-drain circuits. General-purpose I/O ports • After the power-on reset, I/O-1 and I/O-2 function as input ports. I/O3 functions as an output port fixed at the low level. • The input/output state of these ports can be set using the I/O-1 to I/O-3 bits in the serial data sent from the controller. Continued on next page. No. 6675-5/22 LC72147V Continued from preceding page. Pin No. Symbol Usage Function Pin circuit • General-purpose I/O ports. 11 I/O-4 13 I/O-5 • The outputs are complementary output circuits. General-purpose I/O ports • After the power-on reset, these ports function as input ports. • The input/output state of these ports can be set using the I/O-4 and I/O-5 bits in the serial data sent from the controller. 18 ADC0 19 ADC1 • A/D converter input A/D converter input The A/D converter is a 6-bit successive-approximation circuit. See the item on the structure of the A/D converter for details. • PLL charge pump output 7 PD Charge pump output When the frequency created by dividing the local oscillator signal frequency by N is higher than the reference frequency, a high level is output from the PD pin. When lower, a low level is output. The PD pin goes to the high-impedance state when the frequencies match. • HCTR is selected by setting CTS in the control data to 1. Input frequency: 0.4 to 25 MHz 15 HCTR General-purpose counter The signal is input to a divide-by-2 circuit and the result is input to a general-purpose counter. This counter can also be used as an integrating counter. The counter value is output as the result of the count, MSB first, from the DO pin. See the item describing the structure of the general-purpose counter for details. • Output buffer for the crystal oscillator circuit 3 XBUF Crystal oscillator buffer • When XB in the serial data is set to 1, the output buffer operates and the crystal oscillator signal (a pulse signal) is output. XOUT When XB is 0, XBUF outputs a low level. (After the power-on reset, XB is set to 0 and the output buffer is fixed at the low level.) No. 6675-6/22 LC72147V Serial Data I/O Methods Data is input to and output from the LC72147V using the Sanyo CCB (Computer Control Bus) format, which is the serial bus format used by Sanyo audio ICs. This IC adopts a CCB format with an 8-bit address. I/O mode Address B0 B1 B2 B3 A0 A1 A2 Content A3 • Control data input (serial input) mode. [1] IN1 (82) 0 0 0 1 0 0 1 0 • 32 bits of data are input. • See the “DI Control Data (Serial Data Input) Structure” item for details on the content of the input data. • Control data input (serial input) mode. [2] IN2 (92) 1 0 0 1 0 0 1 0 • 32 bits of data are input. • See the “DI Control Data (Serial Data Input) Structure” item for details on the content of the input data. • Data output (serial data output) mode. [3] OUT (A2) 0 1 0 1 0 0 1 0 • The number of bits output is equal to the number of clock cycles. • See the “DO Output Data (Serial Data Output) Structure” item for details on the content of the output data. I/O mode determined CE CL DI B0 B1 B2 B3 A0 A1 A2 A3 First data in1/2 DO First data out No. 6675-7/22 (13) PD-L (14) TEST (12) DZ-C (11) XTAL (10) UNLOCK (4) DO-C (6) U-CTR (8) O-PORT (9) IFB-C (5) ADC (7) I/O-C DI IFB0 I/O-1 I/O-2 I/O-3 I/O-4 I/O-5 ADI0 ADI1 IFB1 OUT1 OUT2 OUT3 OUT4 OUT5 CTP CTC * * IL0 IL1 ULD UL0 UL1 XS0 XS1 XB DZ0 DZ1 TEST0 TEST1 TEST2 DLC (6) U-CTR (5) ADC (4) DO-C (3) R-CTR (2) PD-C (1) P-CTR P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 * DVS PDC0 PDC1 R0 R1 R2 R3 DT0 DT1 ADS CTE * CTS GT0 GT1 DI (9) IFB-C LC72147V DI control data (serial data input) structure (1) IN1 Address 0 0 0 1 0 1 0 0 First data IN1 (2) IN2 Address 1 0 0 1 0 1 0 0 First data IN2 *: Don't care No. 6675-8/22 LC72147V DI control data description No. Control block/data Content Related data • This data sets the divisor for the programmable divider P0 is the LSB, and P15 is the MSB of this binary value. (1) Programmable divider data DVS = 0: The FMIN pin is pulled down. P0 to P15 1: Selects the FMIN pin. Divisor setting (N): 272 to 65,536 DVS Input frequency range: 10 to 180 MHz *: See the “Programmable Divider Structure” item for details. • This data controls the sub-charge pump. (2) Sub-charge pump control data (* : don’t care) PDC1 PDC0 0 * High impedance Sub-charge pump state 1 0 Charge pump operating (PLL unlocked) 1 1 Charge pump operating (normal operation) UL0, UL1, DLC PDC0, PDC1 *: The sub-charge pump output is connected internally to the gate of the transistor used for low-pass filter formation. The sub-charge pump can be used in conjunction with the PD pin (main charge pump pin) to form a high-speed locking circuit. See the “Charge Pump Structure” item for details. • Reference frequency selection data R3 R2 R1 R0 (3) Reference divider data R0 to R3 Reference frequency (kHz) 100 *1 0 0 0 0 0 0 0 1 50 0 0 1 0 25 0 0 1 1 25 0 1 0 0 12.5 0 1 0 1 6.25 0 1 1 0 3.125 0 1 1 1 1 0 0 0 1 0 0 1 9 *2 1 0 1 0 5 1 0 1 1 1 1 1 0 0 3 *2 1 1 0 1 30 *2 3.125 10 1 1 1 0 *3 PLL inhibit + X’tal OSC stop 1 1 1 1 *3 PLL inhibit Notes: 1. Illegal value when a crystal oscillator frequency of 10.25 or 10.35 MHz is selected. 2. Illegal value when a crystal oscillator frequency of 10.25 MHz is selected. 3. PLL inhibit (backup mode) The programmable divider block is stopped, the FMIN pin is pulled down to ground, and the charge pump output is set to the floating state. Continued on next page. No. 6675-9/22 LC72147V Continued from preceding page. No. Control block/data Content Related data • Data that determines the output of the DO and I/O-5 pins ULD DT1 DT0 DO pin 0 0 0 Low when unlocked I/O-5 pin 0 0 1 end-AD 0 1 0 end-UC 0 1 1 IN *1 1 0 0 Open 1 0 1 end-AD 1 1 0 end-UC 1 1 1 IN *1 OUT5 *2 Low when unlocked *2 end-AD: A/D converter operation completion end-UC: General-purpose counter operation completion OUT5 DO, I/O-5 pin control data (4) I/O-1 ULD DO DT0, DT1 I/O-2 IL0, IL1 Start Completion (I-1 change) I/O-5 CE : Hi Note: 1. IL1 IL0 0 0 Open IN 0 1 I-1 (pin state) 1 0 I-2 (pin state) 1 1 DO goes low when I-1 changes. * However, if I/O-1 and I/O-2 are set to output mode, they go to the open state. Note: 2. Invalid if the I/O-5 pin is set to input mode. Caution: Cannot be used in crystal oscillator stop mode (The DO pin will not change state.) [When the reference divider data is R3 = R2 = R1 = 1, and R0 = 0.] • A/D converter conversion start data ADS = 1: Resets and starts the A/D converter ADS = 0: Resets the A/D converter A/D converter control data (5) ADS ADI0 ADI1 ADI1 ADI0 1 1 Stopped A/D converter input pin 1 0 ADC0 0 1 ADC1 0 0 ADC0, ADC1 If both the ADC0 and ADC1 pins are specified as A/D converter inputs, the levels are converted sequentially in the order ADC0 first and the ADC1. See the “A/D Converter Structure” item for details. Continued on next page. No. 6675-10/22 LC72147V Continued from preceding page. No. Control block/data Content Related data • Selects the general-purpose counter input pin (HCTR). CTS = 1: Selects the HSTR pin. CTS = 0: Pulls down the HCTR pin. • General-purpose counter measurement start data CTE = 1: Starts the counter. CTE = 0: Resets the counter. • Determines the measurement time (frequency mode) and number of periods (period mode). General-purpose counter control data (6) CTS, CTE GT0, GT1 CTP CTC Frequency measurement GT1 GT0 Measurement time Wait time CTP = 0 CTP = 1 Period measurement mode 0 0 4 ms 3 to 4 ms 1 to 2 ms One period 0 1 8 3 to 4 ms 1 to 2 ms One period 1 0 32 7 to 8 ms 1 to 2 ms Two periods 1 1 64 7 to 8 ms 1 to 2 ms Two periods • CTP = 0: When the counter has been reset (CTE = 0), pulls down the general-purpose counter input. CTP = 1: When the counter has been reset (CTE = 0), does not pull down the generalpurpose counter input, and shortens the wait time. However, immediately after CTP is set to 1, the counter start must be delayed until the general-purpose counter input pin has been biased. • The input sensitivity is reduced when CTC is set to 1. (Sensitivity: 10 to 30 mV rms) • Data that specifies the I/O direction of the I/O ports. (7) I/O port control data [Data] = 0: Input port OUT1 to OUT5 1: Output port IO-1 to I/O-5 ULD *: After the power-on reset, the I/O-1, I/O-2, I/O-4, and I/O-5 are set up as input ports. I/O-3 is set up as an output port. • Data that determines the output from output ports O-1 to O-5. (8) Output port data [Data] = 1: Open or high level. I/O-1 to I/O-5 0: Low OUT1 to OUT5 ULD *: Invalid when the corresponding port is set up as an input port or as the unlock state indicator output. • Determines the 3-value output of the IFBC port. (9) IFB0 IFB1 IFBC output 0 0 Mid (Vreg/2 = 1.5 V) IFBC port control data 0 1 Low (0 V) IFB0, IFB1 1 0 Mid (Vreg/2 = 1.5 V) 1 1 High (Vreg = 3.0 V) *: When PLL inhibit and crystal oscillator stop mode (R0 = 0, R1 = R2 = R3 = 1), the IFBC output is set to the open state. This output goes to the mid level after the power-on reset. Continued on next page. No. 6675-11/22 LC72147V Continued from preceding page. No. Control block/data Content Related data • Width selection for the phase error (øE) detection function used to determine the PLL locked/unlocked state. When a phase error greater than the øE detection width from the table occurs, the PLL circuit is seen as in the unlocked state. When unlocked, the detection pin (DO or I/O-5) goes to the low state. (10) UL1 UL0 øE detection width 0 0 Stopped Detection pin output Open 0 1 0 øE is output directly Unlock state detection data 1 0 ±0.5 µs øE is extended by 1 to 2 ms. ULD UL0, UL1 1 1 ±1 µs øE is extended by 1 to 2 ms. DT0, DT1 øE Extended D0 I/O5 1 to 2 ms Unlocked state output • Crystal oscillator selection data Crystal oscillator circuit (11) XS0, XS1 XS1 XS0 X’tal OSC 0 0 4.5 MHz 0 1 7.2 MHz 1 0 10.25 MHz 1 1 10.35 MHz R0 to R3 XB *: After the power-on reset, 10.25 MHz is selected. • Crystal oscillator buffer (XBUF) output control data XB = 0: Buffer output is turned off. (This mode is selected after the power-on reset.) XB = 1: Buffer output is turned on. • Controls the phase comparator dead band. (12) Phase comparator control data DZ0, DZ1 DZ1 DZ0 Dead band mode 0 0 DZA 0 1 DZB 1 0 DZC 1 1 DZD *: The phase comparator operates in DZA mode after the power-on reset. • Bit that forcible sets the charge pump output to the low level. DLC = 1: Low level (13) Charge pump control data DLC DLC = 0: Normal operation *: If a deadlock occurs due to the VCO control voltage (Vtune) going to zero and stopping the VCO oscillator, set the charge pump output to the low level and set Vtune to VCC to escape from the deadlocked state. Normal operation is selected after the power-on reset. • IC test control data IC test data (14) These bits must be set as follows during normal operation. TEST0 TEST0 = 0 TEST1 TEST1 = 0 TEST2 TEST2 = 0 *: After the power-on reset, the test data is all set to zero. No. 6675-12/22 LC72147V Structure of the DO Output Data (serial output data) (3) OUT Address DI 0 1 0 1 0 1 0 0 Control block/data * * * * AD15 AD14 AD13 AD12 AD11 AD10 (4) ADC1 (3) ADC0 * * (2) U-CTR AD05 AD04 AD03 AD02 AD01 AD00 * * *: Bits that are set to 0. No. C3 C2 C1 C0 * C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 (1) IN-PORT I5 I4 I3 I2 I1 DO * * First data out Content Related data • The bits I1 to I5 are set to the latched states of the I/O pins I/O-1 to I/O-5. These states are latched at the point the IC enters data output mode. (1) I/O port data I5 to I1 The pin states are latched regardless of the pin mode (input or output). I/O-1 to I/O-5 Pin state = high: 1 low: 0 General-purpose (2) counter binary data C19 to C0 (3) (4) A/D converter ADC0 data AD05 to AD00 A/D converter ADC1 data AD15 to AD10 • The bits C19 to C0 are set to the latched content of the 20-bit binary general-purpose counter. CTS0 C19 ← MSB of the binary counter CTS1 C0 ← LSB of the binary counter CTE • The bits AD05 to AD00 are set to the latched result of the A/D conversion of the ADC0 pin input signal. ADI0 AD05 ← MSB ADI1 AD00 ← LSB ADS • The bits AD15 to AD10 are set to the latched result of the A/D conversion of the ADC1 pin input signal. ADI0 AD15 ← MSB ADI1 AD10 ← LSB ADS No. 6675-13/22 LC72147V Serial data input (IN1/IN2) tSU, tHD, tES, tEC, tEH, > 0.45 µs tLC < 0.45 µs tEH tEC tES CE CL tSU tHD B0 DI B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 * CTS GT0 GT1 tLC Internal data Serial data output (OUT) tSU, tHD, tES, tEC > 0.45 µs tDC, tDH < 0.2 µs *1 tES tEH tEC CE CL tSU DI tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC DO *2 tDH I5 I4 AD13 AD12 AD11 AD10 *2 Notes: 1. The DO pin is an n-channel open drain output, and thus the data switching time will differ depending on the value of the pull-up resistor used and the printed circuit board capacitance. 2. The DO pin is normally open. No. 6675-14/22 LC72147V Serial data timing VIH CE tCH tCL VIH VIL CL VIL VIH VIL VIH tEL VIH tES VIH tEH DI VIL tSU tHD VIL tLC Internal data latch operation Old New <When CL is stopped at the low level> VIH CE tCL CL VIL tCH VIH VIH VIL VIH VIH VIL tEL VIH tEH tES DI VIL tSU tHD VIL tDC tDH DO tLC Internal data latch operation Old New <When CL is stopped at the high level> No. 6675-15/22 LC72147V Programmable divider structure 4 bits 12 bits fvco/N FMIN PD Programmable divider Swallow counter DVS øE ferf fvco = ferf × N DVS Set divisor (N) 1 272 to 65535 0 — Input frequency range (f(MHz)) Minimum input sensitivity FMIN 10 ≤ f < 130 130 ≤ f ≤ 180 40 mVrms 70 mVrms — — Selected Pulled down General-purpose counter structure The LC72147V’s general-purpose counter is a 20-bit binary counter. The result of the count operation can be read out MSB first from the DO pin. General-purpose counter (20-bit binary counter) 1 2 HCTR CTS L S B ( FIF ) M S B 0 to 3 4 to 7 DO pin 8 to 11 12 to 15 16 to 19 CT 4/8/32/64 msec GT C = FIF × GT GT1, GT0 The measurement time when the general-purpose counter is used for frequency measurement is set to either 4, 8, 32, or 64 ms by the GT0 and GT1 bits. The frequency of the input to the HCTR pin can be measured by determining how many pulses were input to the general-purpose counter during this measurement time. Check signal frequency X’tal OSC 4.5 MHz 7.2 MHz 10.25 MHz Check signal 900 kHz 900 kHz 1025 kHz 10.35 MHz fref = 30, 9, 3 kHz fref : other than 30, 9, 3 kHz 1030 kHz 1150 kHz The CTC data switches the input sensitivity. The input sensitivity is reduced when CTC is set to 1. CTC HCTR: Minimum input sensitivity rating 0.4 ≤ f < 8 8 ≤ f < 12 12 ≤ f < 25 0 (Normal mode) 70 mVrms 70 mVrms (10 to 20 mVrms) 70 mVrms 1 (Reduced sensitivity mode) — 100 mVrms (30 to 40 mVrms) — —: No sensitivity rating (not guaranteed) ( ): Rated value (reference value) No. 6675-16/22 LC72147V CTP data: Determines the state of the general-purpose counter input pin (HCTR) when the general-purpose counter is reset (CTE = 0). CTP = 0: The general-purpose counter input pin is pulled down. 1: The general-purpose counter input pin is not pulled down, and the wait time is shortened by 1 to 2 ms. IF CTP is to be set to 1, set CTP to 1 at least 4 ms before the counter is started by setting CTE to 1. Leave CTP set to 0 if the counter will not be used. Frequency measurement mode GT1 GT0 Measurement time 0 0 4 ms 0 1 8 ms 1 0 32 ms 1 1 64 ms Wait time CTP = 0 CTP = 1 3 to 4 ms 1 to 2 ms 7 to 8 ms IF counter operation Reset the general-purpose counter in advance by setting CTE to 0 before starting the counter. A general-purpose counter count operation is started by setting the CTE bit in the serial data to 1. The serial data takes effect internally to the LC72147V when the CE pin input level is changed from high to low. The input to the HCTR pin must be provided before the wait time has elapsed after CE was set low. Next, the result of the general-purpose counter count after the measurement completes must be read out while CTE is still set to 1. This is because the general-purpose counter is reset when CTE is set to 0. Note that the signal input to the HCTR pin is first divided by 2 internally to the IC and then input to the general-purpose counter. Therefore, the result of the general-purpose counter count is a value that corresponds to 1/2 of the frequency actually input to the HCTR pin. CE Data with CTE = 1 Wait time Frequency measurement time Measurement time At least 70 mV rms *: When CTC = 0: 70 mV rms When CTC = 1: 100 mV rms HCTR Input signal When used as an integrating counter CTE = 1* CTE = 1* CTE = 0* CE Internal data latch (CTE) GT General-purpose counter (Integrates) Start Restart Reset end-UC (DO) End of the count operation *CTE: 0 → 1 → End of the count operation • Resets the general-purpose counter • Starts the general-purpose counter • Restarts the counter if set to 1 again. In integrating count mode, the count value of the general-purpose counter is accumulated. Care must be taken to handle counter overflow correctly. The count value will be in the range 0H to FFFFFH. An integrating count operation is performed by sending the serial data (IN1) again with the CTE bit still set to 1. This restarts the general-purpose counter measurement operation and adds the new counts to the previous counter value. No. 6675-17/22 LC72147V A/D converter structure The LC72147V A/D converter is a 6-bit successive-approximation converter. It features a conversion time of about 17 µs. The full-scale voltage level is the Vreg level, which corresponds to a data value of 3FH. ADC1 Selector Discrimination circuit Comparator ADC0 Vref ADI0 ADI1 Selector ADS Decoder AD10 AD11 AD13 AD12 AD14 * AD15 * AD00 AD01 AD02 AD03 AD04 * AD05 * Vref max = Vreg Register Do pin ADI1 ADI0 Input pin 1 1 Illegal setting 1 0 ADC0 0 1 ADC1 0 0 ADC0/ADC1 CE *: These bits are always 0. CTS = 1 tWA1 : 0.5 to 2.0 µs Conversion ADC0 tWA1 tWA2 tAD Conversion starts tAW2 : 1.0 to 2.2 µs ADC1 Conversion completes tAD : 7.3 to 16.7 µs tAD end-AD No. 6675-18/22 LC72147V Charge pump structure DLC (MAIN) fvco/N Phase Detector PD0 fref DZ1 DZ0 (SUB) AIN AOUT R1S Unlock detector and subcharge pump cont Clock UL0 UL1 PDC1 PDC0 PDC1 PDC0 PDS AVSS Unlock DO, I/O-5 pin PDS (Sub-charge pump state) DLC PD1, PD0, PDS High impedance 0 Normal operation 0 Charge pump operating (PLL unlocked) 1 Forcibly set to the low level 1 Charge pump operating (normal operation) 0 * 1 1 When the unlocked state is detected when the channel is changed, the PDS (sub-charge pump) operates, R1 goes to RIM/R1S (R1S = 100 Ω), the low-pass filter time constant is reduced, and PLL locking is accelerated. R1M VCC PD0 Vtune PDS R1S *: The unlock state detection bit UL1 must be set to 1. The unlock detection width is set to either ±0.5 µs or ±1.0 µs and when a phase difference larger than this is detected, the unlocked state is recognized and the sub-charge pump operates. When the state approaches the locked state and the phase difference becomes less than the amount set as the unlock detection width, the sub-charge pump stops operating and the pin goes to the high-impedance state. Other items (1) Notes on the phase detector dead band DZ1 DZ0 Dead band mode Charge pump Dead band 0 0 DZA ON/ON – –0 s 0 1 DZB ON/ON –0 s 1 0 DZC OFF/OFF +0 s 1 1 DZD OFF/OFF ++0 s When the charge pump operates in ON/ON mode, the charge pump generates correction pulses even when the PLL is locked. Here, it is easy for the loop to become unstable, and special care is required in designs that use this mode. The following problems may occur in ON/ON mode. • Side bands may be generated due to reference frequency leakage. • Side bands may be generated due low-frequency leakage due to the envelope of the correction pulses. No. 6675-19/22 LC72147V When a dead band is present (OFF/OFF mode), the loop will be stable, but it will be harder to acquire a good C/N ratio. On the other hand, with the mode that does not have a dead band (ON/ON mode), it will be easier to acquire a high C/N ratio, but harder to acquire loop stability. Therefore, the DZA and DZB modes, in which there is no dead band, can be effective if either a high signal-to-noise ratio of 90 to 100 dB in FM reception or an increased pilot margin in AM stereo reception is required. Inversely, if such a high FM signal-to-noise ratio is not required for FM reception, or an adequate pilot margin can be acquired for AM stereo reception, then the DZC and DZD modes, in which a dead band is present, may be more effective. Dead zone (dead band) definition The phase comparator compares fp with the reference frequency (fr) as shown in figure 1. This circuit outputs a voltage V (A) that is proportional to the phase difference ø as shown in figure 2. However, due to internal delays and other factors, the actual IC is unable to compare small phase differences, and thus a dead zone (B) appears in the output. To achieve a high signal-to-noise ratio in the end product, the dead zone should be as small as possible. However, in popularly-priced models, there are cases where a somewhat wider dead zone may be easier to work with. This is because in some situations, such as when a powerful signal is applied to the RF input, in popularly-priced models there may be RF leakage from the mixer to the VCC. When the dead zone is narrow, outputs to correct this leakage are output, that output in turn modulates the VCO, and generates a beat signal with the RF. RF (A) Leakage fr MIX (B) Reference divider fp Phase detector LPF VCO ø (nsec) Programmable divider Dead zone Figure 1 Figure 2 (2) Notes on the FMIN and HCTR pins The coupling capacitor must be located as close as possible to these pins. A capacitance of approximately 100 pF is desirable. In particular, if the HCTR pin capacitor is over about 1000 pF, the time required to reach the bias level may become excessive, and incorrect counting may occur due to the relationship with the wait time. (3) Notes on the IF counting → SD must be used in conjunction with IF counting. If the general-purpose counter is used to count the IF frequency, the application microcontroller must test the state of the IF IC SD (station detect) signal, and only if the SD signal is present, turn on the IF counter buffer output and perform an IF count operation. Methods in which auto-search operations are implemented only using the IF count may incorrectly stop at frequencies where no station is present due to leakage from the IF counter buffer. (4) Using the DO pin At times other than data output mode, the DO pin can also be used to check for general-purpose counter count operation completion, to output the unlock state detection signal, and to check for changes in the input pins. Note that the states of the input pins (I/O-1 and I/O-2) can be directly input to the system microcontroller through the DO pin. (5) Power supply pins Capacitors of over 2000 pF must be inserted between the VDD and VSS power supply pins and between Vreg and VSS to reduce noise. These capacitors must be located as close to the VDD, Vreg, and VSS pins as possible. No. 6675-20/22 LC72147V (6) Notes on VCO design The VCO must be designed so that the VCO oscillation does not stop if the control voltage (Vtune) becomes 0 V. If it is possible for this oscillator to stop, use the charge pump control data (DLC) to forcible set Vtune to VCC temporarily to prevent the PLL circuit from deadlocking. (This function is called a deadlock clear circuit.) Pin states during a power-on reset State Power-on reset Power-on reset XIN O-3 F I/O-3 CE XBUF DI VDD CL Vreg DO VSS PD F I-4 XOUT LC72147V L State ADC1 ADC0 AIN I/O-2 I-2 F AOUT I/O-1 I-1 F AVSS HCTR I/O-4 IFBC FMIN I/O-5 M I-5 F F : Floating L : Low M : Medium No. 6675-21/22 LC72147V Sample Application Circuit 1st IF: 10.7 MHz Second mixer input: 10.25 MHz 2nd IF: 450 kHz VCC (6 V) 10.25 MHz 2nd Mixer XIN 1 24 XOUT I/O-3 2 23 CE XBUF 3 22 DI VDD 4 21 CL Vreg 5 20 DO VSS 6 19 ADC1 18 ADC0 Microcontroller 3V GND GND Vtune VCO (LO) LC72147V PD 7 AIN 8 17 I/O-2 AOUT 9 16 I/O-1 AVSS 10 15 HCTR I/O-4 11 14 IFBC FMIN 12 13 I/O-5 IF-Buffer Signal level Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 2000. Specifications and information herein are subject to change without notice. PS No. 6675-22/22