SANYO LC72151V

Ordering number : ENN6976A
CMOS IC
LC72151V
PLL Frequency Synthesizer for Electronic Tuning
in Car Audio Systems
Package Dimensions
unit: mm
3191A-SSOP30
[LC72151V]
30
16
7.6
0.5
• High-speed programmable divider
— FMIN: 10 to 160 MHz: Pulse swallower type
— AMIN: 2 to 40 MHz: Pulse swallower type
0.5 to 10 MHz: Direct division type
• IF counter
— HCTR: 0.4 to 25 MHz: for FM IF count
— LCTR: 10 to 500 kHz: for AM IF count
1.0 to 20 × 103 Hz: for frequency
measurement
• Reference frequency
— One of 11 frequencies may be selected (when a
10.25 or 10.35 MHz crystal is used)
50, 30*, 25, 12.5, 10, 9*, 6.25, 5, 3.125, 3*, 1 kHz
Note: Cannot be used when a 10.25 MHz crystal is
used
• Phase comparator
— Supports dead band control
— Built-in unlock detection circuit
— Built-in deadlock clearing circuit
• Built-in amplifier for forming an active low-pass filter
— Built-in operational amplifier for FM high-speed
locking
— Built-in MOS transistor for AM tuning
• Built-in crystal oscillator output buffer
5.6
Functions
1
15
9.75
(1.3)
1.5max
The LC72151V is a PLL frequency synthesizer for car
audio systems. It can implement high-performance
multifunction tuners such as RDS tuners and features a
fast locking circuit.
• I/O ports — General-purpose I/O: 2 pins
— Four input ports (maximum)
— Three output ports (maximum)
• Serial data I/O
— Supports communication with the controller in the
CCB format.
• Operating ranges
— Supply voltage: 4.5 to 5.5 V (VDD)
7.5 to 9.5 V (AVDD)
— Operating temperature: –40 to +85°C
• Package
— SSOP30
0.15
0.1
Overview
0.22
0.65
(0.43)
SANYO: SSOP30
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
82102TN (OT) / 83101RM (OT) No. 6976-1/29
LC72151V
Pin Assignment
LC72151V
XOUT
1
30 XIN
I/O-1
2
S
29 CE
I/O-2
3
S
28 DI
XBUF
4
S
27 CL
O-3
5
26 DO
VDD
6
25 AOUT2
VSS
7
FMIN
8
23 PDM2
AMIN
9
22 PDF
AVSS
24 AIN2
HCTR/I-3 10
21 PDM1
LCTR/I-4 11
20 PDS
AREF 12
19 AIN1
AVDD 13
AVSS 14
AOUT1 15
–
+
18 TGI1
17 TGI2
16 TGO
(Top view)
No. 6976-2/29
LC72151V
Block Diagram
XBUF
REFERENCE
DIVIDER
XIN
PHASE DETECTOR
CHARGE PUMP
XOUT
PDM1
PDS
PDM2
PDS
SWALLOW COUNTER
1/16,1/17 4bits
FMIN
UNLOCK
DETECTOR
TGI1
TGI2
TGO
12bits PROGRAMMABLE
DIVIDER
AMIN
CHARGE PUMP
for FAST LOCK
PDF
AIN2
HCTR/I-3
UNIVERSAL
COUNTER
DATA SHIFT REGISTER
LATCH
FAST LOCK UP
CONTROL
AOUT2
AVDD
AIN1
LCTR/I-4
AREF
CCB
I/F
VDD
VSS
AVSS
AOUT1
POWER
ON
RESET
CE
DI
CL
DO
I/O-1 I/O-2
O-3
No. 6976-3/29
LC72151V
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = AVSS = 0 V
Parameter
Supply voltage
Maximum input voltage
Maximum output voltage
Maximum output current
Allowable power dissipation
Symbol
VDD max
Pin
Ratings
Unit
–0.3 to +6.5
VDD *
AVDD *
–0.3 to +11.0
VIN1 max
CE, CL, DI
VIN2 max
XIN, FMIN, AMIN, HCTR/I-3, LCTR/I-4,
AIN2, TGI1, TGI2, TGO
VIN3 max
I/O-1, I/O-2
–0.3 to +15.0
VIN4 max
AIN1, AREF
–0.3 to +6.5
VO1 max
DO
–0.3 to +7.0
VO2 max
XOUT, PDM1, PDM2, PDS, PDF, XBUF, TGI1,
TGI2, TGO
VO3 max
I/O-1, I/O-2, O-3, AOUT2
–0.3 to +15.0
VO4 max
AOUT1
–0.3 to +11.0
IO1 max
I/O-1, I/O-2, O-3
IO2 max
DO, TGI1, TGI2, TGO, AOUT1, AOUT2
0 to 5.0
IO3 max
XBUF
0 to 3.0
Pd max
(Ta ≤ 85°C)
V
–0.3 to +7.0
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
V
V
0 to 10.0
SSOP30 :160
mA
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Note: Power must be applied to AVDD before applying to VDD and AVDD must be higher than or equal to VDD.
Capacitors of at least 0.1 µF must be inserted between the VDD and VSS, and between the AVDD and AVSS power supply pins.
Allowable Operating Ranges at Ta = –40 to 85°C, VSS = AVSS = 0 V
Parameter
Supply voltage
High-level input voltage
Low-level input voltage
Output voltage
Input frequency
Symbol
Pin
Conditions
Ratings
min
typ
max
VDD1
VDD
VDD ≤ AVDD
4.5
VDD2
AVDD
VDD ≤ AVDD
7.5
VDD3
VDD
Serial data retention voltage
2.0
VIH1
CE, CL, DI
0.7VDD
6.5
VIH2
I/O-1, I/O-2
0.7VDD
13
VIH3
HCTR/I-3,
LCTR/I-4
0.7VDD
VDD
0
0.3VDD
5.5
8.5
9.5
VIL2
CE, CL, DI,
I/O-1, I/O-2,
LCTR/I-4
HCTR/I-3
0
0.2VDD
VO1
DO
0
6.5
VO2
AOUT1
0
9.5
VO3
I/O-1, I/O-2, O-3,
AOUT2
0
13
fIN1
XIN
VIN1 *1
7
11
fIN2
FMIN
VIN2 *1
10
160
VIL1
Unit
V
V
V
V
fIN3
AMIN (SNS=1)
VIN3 *1
2
40
fIN4
AMIN (SNS=0)
VIN4 *1
0.5
10
fIN5
HCTR/I-3
VIN5 *1
0.4
25
fIN6
LCTR/I-4
VIN6 *1
10
500
kHz
fIN7
LCTR/I-4
VIN7 *2
1.0
20 × 103
Hz
MHz
Continued on next page.
No. 6976-4/29
LC72151V
Continued from preceding page.
Parameter
Symbol
VIN1
Input amplitude
Guaranteed crystal oscillator
frequency ranges
Pin
Conditions
Ratings
min
typ
max
XIN
fIN1
200
1500
VIN2-1
FMIN
f = 10 to 50 MHz
40
1500
VIN2-2
FMIN
f = 50 to 130 MHz
20
1500
VIN2-3
FMIN
f = 130 to 160 MHz
40
1500
VIN3
AMIN (SNS=1)
fIN3
40
1500
VIN4
AMIN (SNS=0)
fIN4
40
1500
VIN5-1
HCTR/I-3
f = 0.4 to 25 MHz *3
40
1500
VIN5-2
HCTR/I-3
f = 8 to 12 MHz *4
70
1500
VIN6-1
LCTR/I-4
f = 10 to 400 kHz *3
40
1500
VIN6-2
LCTR/I-4
f = 400 to 500 kHz *3
20
1500
VIN6-3
LCTR/I-4
f = 400 to 500 kHz *4
70
1500
XIN, XOUT
*5
10.25
10.35
X’tal
Unit
mVrms
MHz
Notes: 1. Sine wave with capacitor coupled.
2. Pulse wave with DC coupled.
3. Serial data: CTC = 0
4. Serial data: CTC = 1
5. Recomended CI value for the crystal oscillator: CI ≤ 70 Ω
The circuit constants for the crystal oscillator circuit depend on the crystal used, the printed circuit board pattern, and other items.
Therefore we recommend consulting with the manufacturer of the crystal for evaluation and reliability.
Electrical Characteristics in the Allowable Operating Ranges
Parameter
Internal feedback resistance
Symbol
Rf1
XIN
Rf2
FMIN
Hysteresis
High-level output voltage
Low-level output voltage
High-level input current
Conditions
Ratings
min
typ
max
1
Rf3
AMIN
500
HCTR/I-3
500
MΩ
LCTR/I-4
kΩ
500
Rpd1
FMIN
50
100
300
Rpd2
AMIN
50
100
300
VHIS
CE, CL, DI, LCTR/I-4
0.1 VDD
IO = – 1 mA
PDM1, PDM2, PDS, PDF
IO = – 2 mA
VDD – 2.0
VOH2
AOUT1
IO = – 1 mA
AVDD – 1.0
VOH3
XBUF
IO = – 0.5 mA
V
V
VDD – 1.5
IO = 1 mA
1.0
IO = 2 mA
2.0
VOL1
PDM1, PDM2, PDS, PDF
VOL2
AOUT1
IO = 1 mA
1.0
VOL3
XBUF
IO = 0.5 mA
1.5
IO = 1 mA
0.2
IO = 5 mA
1.0
I/O-1, I/O-2, O-3
kΩ
VDD – 1.0
VOH1
VOL4
Unit
500
Rf4
Rf5
Internal pull-down resistance
Pin
IO = 8 mA
1.6
IO =1 mA
0.2
IO = 5 mA
1.0
VOL5
DO
VOL6
AOUT2
IO = 1 mA, AIN2 = 1.3 V
0.5
IIH1
CE, CL, DI
VI = 6.5 V
5.0
IIH2
I/O-1, I/O-2
VI = 13 V
5.0
IIH3
HCTR/I-3, LCTR/I-4
VI = VDD
IIH4
XIN
VI = VDD
0.11
0.9
IIH5
FMIN, AMIN, HCTR/I-3,
LCTR/I-4
VI = VDD
1.8
15
IIH6
AIN1, AREF
VI = 5.5 V
IIH7
TGI1, TGI2, TGO
VI = VDD
5.0
0.01
V
µA
100
nA
3.0
µA
Continued on next page.
No. 6976-5/29
LC72151V
Continued from preceding page.
Parameter
Low-level input current
Analog switch on resistance
Symbol
Pin
Conditions
Ratings
min
typ
max
IIL1
CE, CL, DI
VI = 0 V
5.0
IIL2
I/O-1, I/O-2
VI = 0 V
5.0
IIL3
HCTR/I-3, LCTR/I-4
VI = 0 V
IIL4
XIN
VI = 0 V
0.11
0.9
IIL5
FMIN, AMIN, HCTR/I-3,
LCTR/I-4
VI = 0 V
1.8
15
IIL6
AIN1, AREF
VI = 0 V
IIL7
TGI1, TGI2, TGO
VI = 0 V
RON
TGI1, TGI2, TGO
5.0
0.01
Unit
µA
100
nA
3.0
µA
VIN = 8.5 V, I = ±3 mA,
AVDD = 8.5 V
70
140
VIN = 4.5 V, I = ±3 mA,
AVDD = 8.5 V
50
100
VIN = 0.5 V, I = ±3 mA,
AVDD = 8.5 V
70
140
Ω
IOFF1
AOUT1
VO = 6.5 V
5.0
IOFF2
I/O-1, I/O-2, O-3, AOUT2
VO = 13 V
5.0
IOFF3
DO
VO = 6.5 V
5.0
High-level 3-state off leakage current
IOFFH
PDM1, PDM2, PDS, PDF VO = VDD
0.01
200
nA
Low-level 3-state off leakage current
IOFFL
PDM1, PDM2, PDS, PDF VO = 0 V
0.01
200
nA
Output off leakage current
Input capacitance
CIN
FMIN
6
pF
IDD1
VDD
X’tal = 10.35 MHz
fIN2 = 160 MHz
VIN2 = 40 mVrms
IDD2
VDD
PLL block stopped
(PLL INHIBIT)
X’tal OSC operating
(X’tal = 10.35 MHz)
IDD3
AVDD
PLL block stopped
(PLL INHIBIT)
X’tal OSC stopped
On-chip op-amp stopped
1.5
VDD
PLL block stopped
(PLL INHIBIT)
X’tal OSC stopped
On-chip op-amp stopped
10
Supply current
IDD4
µA
10
18
0.5
1.5
mA
µA
No. 6976-6/29
LC72151V
Pin Functions
Pin No.
Symbol
30
XIN
1
XOUT
Usage
X’tal OSC
Function
Pin circuit
• Crystal oscillator connection.
(10.25 or 10.35 MHz)
• FMIN is selected by setting DVS in the control data to 1.
• Enters high-speed locking mode by setting SNS in the control data
to 1.
8
FMIN
Local oscillator signal input
• Enters normal mode by setting SNS in the control data to 0.
• Input frequency: 10 to 160 MHz
• The signal is transmitted to the swallow counter.
• The divisor can be set to a value in the range 272 to 65,535.
• AMIN is selected by setting DVS in the control data to 0.
• When SNS in the control data is set to 1:
Input frequency: 2 to 40 MHz
9
AMIN
Local oscillator signal input
The signal is directly transmitted to the swallow counter.
• When SNS in the control data is set to 0:
Input frequency: 0.5 to 10 MHz
The signal is directly transmitted to the 12-bit programmable divider.
The divisor can be set to a value in the range 5 to 4,095.
29
CE
Chip enable
• This pin must be set to the high level when inputting serial data to the
LC72151V DI pin and when outputting serial data from the DO pin.
S
28
DI
Input data
• Serial data input for transferring data from the controller to the
LC72151V.
S
27
CL
Clock
• Data synchronization clock signal used when inputting serial data to
the LC72151V DI pin and when outputting serial data from the DO pin.
S
26
DO
Output data
• Serial data output for transferring data from the LC72151V to the
controller.
• LC72151V power supply. A voltage in the range 4.5 to 5.5 V must be
provided when the PLL circuit is operating.
6
VDD
Power
• The power-on reset circuit operates when power is first applied.
———
Note: Power must be applied to AVDD before applied to VDD and
AVDD must be higher than or equal to VDD.
7
VSS
Ground
• LC72151V ground.
———
• Input/output dual function pins
• The function will be selected according to IOC1 and IOC2 in the
control data.
Data = 0: Input port
1: Output port
• When specified as an input port:
2
I/O-1
3
I/O-2
The input pin state is transmitted to the system microcontroller from
DO pin.
I/O ports
Input state = Low: data is 0
= High: data is 1.
• When specified as an output port:
The output state will be determined according to I/O-1 and I/O-2 in
the control data.
Data = 0: Low
= 1: Open
• These pin function as an input port at a power-on reset.
Continued on next page.
No. 6976-7/29
LC72151V
Continued from preceding page.
Pin No.
Symbol
5
O-3
Usage
Function
Pin circuit
• Dedicated output pin
Output port
• Latches OUT3 in the control data and outputs data from O-3 pin.
• This pin goes open state at a power-on reset.
19
AIN1
12
AREF
13
AVDD
14
AVSS
15
AOUT1
AVDD
• Op-amp for PLL active low-pass filter
• AVSS is the analog system ground pin shared with low-pass filter Nch
MOS transistor.
Op-amp for low-pass filter amp
AIN1
–
+
• Voltage applied to AREF pin must be 1/2 that to VDD pin.
Note: Power must be applied to AVDD before applied to VDD, and AVDD
must be higher than or equal to VDD.
AOUT1
AREF
AVSS
• PLL active low-pass filter Nch MOS transistor
24
AIN2
25
AOUT2
Transistor for low-pass
filter amp
• Source of the transistor is connected to AVSS pin.
Note: Connect AVSS pin to ground in use.
AVSS
• PLL charge pump output
21
PDM1
23
PDM2
20
PDS
Charge pump output
When the frequency created by dividing the local oscillator signal
frequency by N is higher than the reference frequency, a high level is
output from the PD pin. When lower, a low level is output. The PD pin
goes to the high-impedance state when the frequencies match.
• PLL high-speed locking charge pump output
22
PDF
18
TGI1
17
TGI2
16
TGO
PLL high-speed locking charge
pump output
When the high-speed locking mode is selected, signal pulses is
output according to the frequency variation. This pin enters highimpedance state when the local oscillation frequency enters the set
frequency range.
TGI1
PLL high-speed locking TG
• PLL high-speed locking active low-pass filter transmission gate
input/output dual function pins
TGO
TGI2
Note: Connect AVSS pin to ground in use.
• HCTR is selected by setting CTS1 in the control data to 1.
Input frequency: 0.4 to 25 MHz
10
HCTR/I-3
General-purpose counter
The signal is input to a divide-by-2 circuit and the result is input to a
general-purpose counter. This counter can also be used as an
integrating counter.
The counter value is output as the result of the count, MSB first, from
the DO pin.
There are four measurement periods: 4, 8, 32, and 64 ms.
• When H/I-3 in the control data is set, this pin functions as an input
port, and the value is output from the output pin DO.
• LCTR is selected by setting CTS1 in the control data to 1.
• When the LCTR is selected as described above and CTS0 is set to 1:
This pin enters the frequency measurement mode.
Input frequency: 10 to 500 kHz
The signal is directly transmitted to the general-purpose counter.
• When CTS0 is set to 0
This pin enters period measurement mode.
11
LCTR/I-4
General-purpose counter
Input frequency: 1 Hz to 20 kHz
Period can be measured either in single period or in double period. If
double period measurement is selected, the frequency is 2 Hz to
40 kHz.
The counter value is output as the result of the count, MSB first, from
the DO pin.
• When L/I-4 in the control data is set:
This pin functions as an input port, the value is output from the output
pin DO.
Continued on next page.
No. 6976-8/29
LC72151V
Continued from preceding page.
Pin No.
Symbol
Usage
Function
Pin circuit
• Output buffer for the crystal oscillator circuit
4
XBUF
Crystal oscillator buffer
• When XB in the serial data is set to 1, the output buffer operates and
the crystal oscillator signal (a pulse signal) is output.
XOUT
When XB is 0, XBUF outputs a low level.
After the power-on reset, the output buffer is fixed at the low level.
Serial Data I/O Methods
Data is input to and output from the LC72151V using the Sanyo CCB (Computer Control Bus) format, which is the serial
bus format used by SANYO audio ICs. This IC adopts a CCB format with an 8-bit address.
I/O mode
Address
B0
B1
B2
B3
A0
A1
A2
Content
A3
• Control data input (serial input) mode.
[1]
IN1 (82)
0
0
0
1
0
1
0
0
• 32 bits of data are input.
• See the “DI Control Data (Serial Data Input) Structure” item for details on the content of
the input data.
• Control data input (serial input) mode.
[2]
IN2 (92)
1
0
0
1
0
1
0
0
• 32 bits of data are input.
• See the “DI Control Data (Serial Data Input) Structure” item for details on the content of
the input data.
• Data output (serial data output) mode.
[3]
OUT (A2)
0
1
0
1
0
1
0
0
• The number of bits output is equal to the number of clock cycles.
• See the “DO Output Data (Serial Data Output) Structure” item for details on the content
of the output data.
I/O mode determined
CE
1
CL
2
DI
B0
B1
B2
B3
A0
A1
A2
A3
First Data IN1/2
1
First Data OUT
DO
2
First Data OUT
1 CL: Normally Hi
2 CL: Normally Low
No. 6976-9/29
(15) TEST
(11) DZ-C
(10) PD-L
(9) Unlock
(4) DO-C
(5) U-CTR
(8) U/I-C
(14) HSTMR
(13) CWS-D
(12) TLR-D
(17) Don't Care
(18) XTAL
(7) O-PORT
(17) Don't Care
TEST2
TEST3
IL1
ULD
UL0
UL1
DLC
DZ0
DZ1
TEST0
TEST1
L/I-4
CTP
CTC
IL0
TLR0
TLR1
CWS0
CWS1
HSE0
HSE1
H/I-3
*
OUT1
OUT2
OUT3
XB
XS
*
*
DI
I/O-1
I/O-2
(5) U-CTR
(16) Reset
(4) DO-C
(3) R-CTR
(2) PD-C
(1) P-CTR
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
SNS
DVS
PDC0
PDC1
R0
R1
R2
R3
DT0
DT1
RST
CTE
CTS0
CTS1
GT0
GT1
P4
P5
P2
P3
P0
P1
DI
(6) I/O-C
LC72151V
DI control data (serial data input) structure
(1) IN1 mode
Address
0 0 0 1 0 1 0 0
(2) IN2 mode
Address
1 0 0 1 0 1 0 0
* : Don’t care
No. 6976-10/29
LC72151V
DI control data description
No.
Control block/data
Content
Related data
• This data sets the divisor for the programmable divider and P15 is the MSB of this binary
value. LSB will change according to the DVS and SNS.
Programmable divider data
(1)
P0 to P15
DVS, SNS
DVS
SNS
LSB
Set divisor (N)
1
1
P0
272 to 65535
1
0
P0
272 to 65535
0
1
P0
272 to 65535
0
0
P4
4 to 4095
*: When the LSB is P4, P0 to P3 are invalid.
• Used to select programmable divider signal input pins (FMIN, AMIN) and to switch the
input frequency range.
DVS
SNS
Input pin
Input pin frequency range
1
1
FMIN
10 to 160 MHz (High-speed mode)
1
0
FMIN
10 to 160 MHz (Normal mode)
0
1
AMIN
2 to 40 MHz
0
0
AMIN
0.5 to 10 MHz
*: When the DVS and SNS are set to 1, the high-speed locking mode is selected, the highspeed control data becomes valid.
By setting DVS to 1 and SNS to 0 this pin enters FMIN mode, the sub-charge pump
control data is valid, the high-speed locking control data becomes invalid.
• This data controls the sub-charge pump.
PDC1
(2)
Sub-charge pump control data
PDC0, PDC1
PDC0
(* : don’t care)
Sub-charge pump state
0
*
1
1
High impedance
Charge pump operating (at all times)
1
0
Charge pump operating (when PLL unlocked)
HSE0
• The sub-charge pump can be used in conjunction with the PDM1 or the PDM2 pin (main
charge pump pin) to form a high-speed locking circuit.
HSE1
*: FMIN(High-speed mode): Setting DVS and SNS to 1 forces the sub-charge pump to
operate for the time set due to the high-speed locking end flag output wait time, and
allows the locking time to be reduced after switching to the normal PLL mode.
See the “Charge Pump Structure” item for details.
• Reference frequency selection data
(3)
Reference divider data
R0 to R3
R3
R2
R1
R0
Reference frequency (kHz)
0
0
0
0
50
0
0
0
1
50
0
0
1
0
25
0
0
1
1
25
0
1
0
0
12.5
0
1
0
1
6.25
0
1
1
0
3.125
0
1
1
1
1
0
0
0
10
1
0
0
1
9
1
0
1
0
5
1
0
1
1
1
1
1
0
0
3
1
1
0
1
30
1
1
1
0
PLL inhibit + X’tal OSC stop
1
1
1
1
PLL inhibit
3.125
Note: PLL inhibit (backup mode)
The programmable divider block is stopped, the FMIN and AMIN pins are pulled down
to ground, and the charge pump output is set to the floating state.
Continued on next page.
No. 6976-11/29
LC72151V
Continued from preceding page.
No.
Control block/data
Content
Related data
• Data that determines the output of the DO pin
ULD
DT1
DT0
DO pin
0
0
0
Low when unlocked
0
0
1
Open
0
1
0
end-UC *1
0
1
1
IN *2
1
0
0
Open
1
0
1
Open
1
1
0
end-UC *1
1
1
1
IN *2
*Note: Open state will be selected at the power-on reset.
Note: *1. end-UC: General-purpose counter operation completion check
DO
(1) Start
DO pin control data
(4)
(2) Completion
(3) CE: HI
CTE
ULD
DT0, DT1
IL0, IL1
(1) When the count operation starts by setting end-UC with CTE set to 1 from 0, DO pin
automatically goes to open state.
I/O-1
I/O-2
(2) When the general-purpose counter operation ends, the DO pin goes low, it is allowed to
check the count end.
(3) DO pin goes to open state according to the serial data input/output state: CE pin = high.
Note: *2.
IL1
IL0
0
0
Open
IN
0
1
I-1 (pin state)
1
0
I-2 (pin state)
1
1
DO goes low when I-1 changes.
However, if I/O-1 and I/O-2 are set to output mode, they change from IN to the open
state.
*: DO pin state during data input (IN1, IN2 modes, CE = high) keeps open regardless of the
DO pin control data.
In addition, Do pin during data input (OUT mode, CE = high) outputs the value for the
internal DO serial data synchronized with the CL regardless of the DO pin control data.
Caution: Cannot be used in crystal oscillator stop mode: R0 = 0, R1 = R2 = R3 = 1 (The DO
pin will not change state.)
Continued on next page.
No. 6976-12/29
LC72151V
Continued from preceding page.
No.
Control block/data
Content
Related data
• Selects the general-purpose counter input pins (HCTR, LCTR).
CTS1
CTS0
Input pin
1
*
HCTR
Measurement mode
Frequency
0
1
LCTR
Frequency
0
0
LCTR
Period
• General-purpose counter measurement start data
CTE = 1: Starts the counter.
CTE = 0: Resets the counter.
General-purpose counter
• Determines the measurement time (frequency mode) and number of periods (period
mode).
control data
Frequency measurement
CTS0, CTS1
(5)
CTE
GT1
GT0
Measurement time
GT0, GT1
Wait time
CTP = 0
CTP = 1
Period measurement
mode
CTP
0
0
4 ms
3 to 4 ms 1 to 2 ms
CTC
0
1
8
3 to 4 ms 1 to 2 ms
One period
One period
1
0
32
7 to 8 ms 1 to 2 ms
Two periods
1
1
64
7 to 8 ms 1 to 2 ms
Two periods
• When CTE = 0, input pull-down is disabied by setting CTP to 1
Note: Wait time: 1 to 2ms.
However, CTP must be set to 1 4ms before CTE is set to 1.
• The input sensitivity is reduced when CTC is set to 1. (Sensitivity: 10 to 30 mV rms)
*: Refer to the General-purpose counter stracture on page 22 for details.
• Data that specifies the I/O direction of the I/O ports (I/O-1, I/O-2).
(6)
I/O port control data
[Data] = 0: Input port
1: Output port
IO-1, I/O-2
OUT1, OUT2
*: After the power-on reset, the I/O-1 and I/O-2 are set up as input ports.
• Data that determines the output from output ports O-1 to O-3.
(7)
Output port data
OUT1 to OUT3
[Data] = 0: Open
1: Low
I/O-1, I/O-2
*: Invalid when the corresponding port is set up as an input port.
*: At a power-on reset, open state is selected by selling the data to 0
• Data that switch the function between general-purpose counter and input port.
General-purpose counter
(8)
H/I-3 = 0: I-3 (input port)
1: HCTR (gereal-purpose counter)
control data
H/I-3, L/I-4
L/I-4 =
CTS0, CTS1
0: I-4 (input port)
1: LCTR (gereal-purpose counter)
Continued on next page.
No. 6976-13/29
LC72151V
Continued from preceding page.
No.
Control block/data
Content
Related data
• Width selection for the phase error (øE) detection function used to determine the PLL
locked/unlocked state. When a phase error greater than the øE detection width from the
table occurs, the PLL circuit is seen as in the unlocked state.
UL1
UL0
øE detection width
Detection output
X’tal
0
0
Stopped
Open
10.25 M/10.35 MHz
0
1
0
Directly outputs øE
10.25 M/10.35 MHz
±0.49 µs
øE is extended by
0.1 to 0.2 ms.
10.25 MHz
±0.49 µs
øE is extended by
0.11 to 0.22 ms.
10.35 MHz
(fr = 30/9/3 k)
±0.43 µs
øE is extended by
0.1 to 0.2 ms.
10.35 MHz (Other
than fr = 30/9/3 k)
±0.98 µs
øE is extended by
0.1 to 0.2 ms.
10.25 MHz
±0.97 µs
øE is extended by
0.11 to 0.22 ms.
10.35 MHz
(fr = 30/9/3 k)
±0.87 µs
øE is extended by
0.1 to 0.2 ms.
10.35 MHz (Other
than fr = 30/9/3 k)
1
(9)
0
Unlock state detection data
UL0, UL1
1
1
ULD
DT0, DT1
øE
0.1 to 0.22ms
DO
Extended
Unlock state output
*: When unlocked, the DO pin goes low and the serial data output is UL = 0.
• Bit that forcible sets the charge pump output to the low level.
DLC = 1: Low level
(10)
Charge pump control data
DLC
DLC = 0: Normal operation
*: If a deadlock occurs due to the VCO control voltage (Vtune) going to zero and stopping
the VCO oscillator, set the charge pump output to the low level and set Vtune to VCC to
escape from the deadlocked state (deadlock clearing circuit). Normal operation is
selected after the power-on reset.
• Controls the phase comparator dead band.
(11)
DZ1
DZ0
Dead band mode
0
0
DZA
Phase comparator control data
0
1
DZB
DZ0, DZ1
1
0
DZC
1
1
DZD
*: The phase comparator operates in DZA mode after the power-on reset. (Recomended
modes: DZD, DZC)
• Data to control the frequency in the convergence range to judge the high-speed locking
control completion. This data is valid when FMIN (high-speed mode) is selected by
setting DVS and SNS to 1.
TLR1 TLR0
(12)
High-speed locking convergence
range control data
TLR0, TLR1
Convergence range [kHz]
0
0
50
DVS
0
1
100
SNS
1
0
150
1
1
200
*:The convergence range is 200 kHz at a power-on reset.
Refer to Description of the High-Speed Locking Control System (P.19) for details.
Continued on next page.
No. 6976-14/29
LC72151V
Continued from preceding page.
No.
Control block/data
Content
Related data
• Data to control the wait time in the high-speed locking. This data is valid when the FMIN
(high-speed mode) is selected by setting DVS and SNS to 1.
CWS1 CWS0
(13)
High-speed locking charge wait
time control data
CWS0, CWS1
Wait time [µs]
0
0
2.5
DVS
0
1
5
SNS
1
0
10
1
1
20
*:The wait time is 20 µs at a power on reset.
Refer to Description of the High-Speed Locking Control System (P.19) for details.
• Data to control the wait time after the high-speed locking control completes till the
operation is switched to the normal PLL operation. This data is valid when the FMIN
(high-speed mode) is selected by setting DVS and SNS to 1.
During the wait time, the unlock signal is forcibly output, the sub-charge pump allows to
be operated. Thereby, reduces the locking time after switching to the normal PLL
operation.
(14)
High-speed locking completion
flag output wait time control data
HSE0, HSE1
HSE1 HSE0
DVS
Wait time [µs]
SNS
0
0
0
PDC0
0
1
200
PDC1
1
0
400
1
1
800
*:The wait time is 400 µs at a power on reset.
Refer to Description of the High-Speed Locking Control System (P.19) for details.
• IC test control data
IC test data
(15)
These bits must be set as follows during normal operation.
TEST0
TEST0 = 0
TEST1
TEST1 = 0
TEST2
TEST2 = 0
TEST3
TEST3 = 0
*: After the power-on reset, the test data is all set to zero.†
(16)
(17)
Reset
RST
DNC
• This data resets the LC72151V.
*: After the power is first applied, the power-on reset circuit initializes the IC. However,
the data must be set to 1 to ensure the initialization.
• Set data to 0
• Crystal oscillator selection data
XS = 0: 10.25 MHz
Crystal oscillator circuit
(18)
XS
XB
= 1: 10.35 MHz
• Crystal oscillator buffer (XBUF)
R0 to R3
XB = 0: Buffer output is turned off.
XB = 1: Buffer output is turned on.
*: XB = 0: Buffer output is turned off at a power-on reset.
†Note: After power is first applied, the power-on reset circuit initializes the IC. However, the CCB data (RST) must be input to the IC to ensure the
initialization.
No. 6976-15/29
LC72151V
Structure of the DO Output Data (serial output data)
(3) OUT mode
Address
No.
(1)
I4 to I1
(3)
PLL unlock data
UL
IF counter binary counter
C19 to C0
C0
C1
C2
C3
C4
C5
C6
C7
C8
(3) IF-CTR
Content
Related data
• The bits I1 to I4 are set to the latched states of the I/O pins I/O-1 and I/O-2 and the input
pins HCTR/I-3 and LCTR/I-4. These states are latched at the point the IC enters data
output mode.
I/O-1
I/O-2
The pin states are latched regardless of the pin mode (input or output).
H/I-3
I1, I2 ← I/O-1 and I/O-2 pin states
L/I-4
I3, I4 ← HCTR/I-3 and LCTR/I-4 pin states
(2)
* * * *
*: Bits that are set to 0.
Control block/data
I/O port data
C9
C10
C11
C12
C13
C14
(2) UNLOCK
C15
I1
I2
I3
0
C16
0
C17
1
C18
0
C19
1
UL
0
*
*
*
1
(1) IN-PORT
DO
0
I4
DI
Pin state =
high: 1
low: 0
• Data created by latching the value for the unlock detection circuit
UL ← 0: Unlocked
1: Locked or in detection halt mode
• Data created by latching the value for the IF counter (20-bit binary counter)
UL0
UL1
CTE
C19 ← MSB of the binary counter
GT0
C0 ← LSB of the binary counter
GT1
No. 6976-16/29
LC72151V
Serial data input (IN1/IN2)
tSU, tHD, tEL, tES, tEH, > 0.45 µs
tLC < 0.45 µs
(1) CL: Normally high
tEL
tES
tEH
CE
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
P0
P1
P2
P3
R0
R1
R2
R3
tLC
Internal data
(2) CL: Normally low
tEL
tES
tEH
CE
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
P0
P1
P2
P3
R0
R1
R2
R3
tLC
Internal data
Serial data output (OUT)
tSU, tHD, tEL, tES, tEH > 0.45 µs
tDC, tDH < 0.2 µs
(1) CL: Normally high
tEL
tES
tEH
CE
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
tDC
DO
tDC
I4
I3
tDH
I2
I1
C3
C2
C1
C0
(2) CL: Normally low
tEL
tES
tEH
CE
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
tDC
DO
tDC
I4
I3
tDH
I2
I1
C3
C2
C1
C0
Note: The DO pin is an n-channel open drain output, and thus the data switching time will differ depending on the value of the pull-up resistor used and the
printed circuit board capacitance.
No. 6976-17/29
LC72151V
Serial data timing
VIH
CE
VIH
VIL
CL
VIL
tCL
tCH
VIH
VIL
VIH
VIH
tEL
VIH
VIL
tES
tEH
DI
VIL
tSU
tHD
VIL
tDC
tDC
tDH
DO
tLC
Internal
data latch
operation
Old
New
<When CL is stopped at the low level>
VIH
CE
tCH
tCL
VIH
VIH
VIL
CL
VIL
VIH
VIH
VIH
VIL
tES
tEL
tEH
DI
VIL
tSU
VIL
tHD
tDC
tDH
DO
tLC
Internal
data latch
operation
Old
New
<When CL is stopped at the high level>
Allowable Operating Ranges at Ta = –40 to 85°C, VSS = 0 V
Parameter
Symbol
Pin
Conditions
Ratings
min
typ
max
Unit
Data setup time
tSU
DI, CL
0.45
µs
Data hold time
tHD
DI, CL
0.45
µs
Clock low-level period
tCL
CL
0.45
µs
Clock high-level period
tCH
CL
0.45
µs
CE wait time
tEL
CE, CL
0.45
µs
CE setup time
tES
CE, CL
0.45
µs
CE hold time
tEH
CE, CL
0.45
Data latch change time
tLC
Data output time
tDC
DO, CL
tDH
DO, CE
Depends on the value of the pull-up
resistor used.
µs
0.45
µs
0.2
µs
Note: See the timing chart for serial data transfers.
No. 6976-18/29
LC72151V
Description of the High-Speed Locking Control System
The LC72151V realizes the maximum inter-band edge high-speed locking time 500 µs by optimizing the filter constants
and internal status setting when the FMIN (high-speed mode) by setting DVS and SNS to 1. The following describes the
high-speed locking control system.
Procedure
The LC72151V operates as shown below when selecting FMIN (high-speed mode) and setting sub-charge pump
operation during unlocked.
PDF/PDM1/PDM2/PDS/TGI1/TGI2 pin states
PDF
PDM1
PDM2
PDS
TGI1
TGI2
Change value N
→
New high-speed locking control
(When the value N variation is under 16,
only operates the normal PLL.)
→
Operates normal PLL when the local oscillation frequency
enters the high-speed locking frequency range.
(The sub-charge pump operates for the time set by the
high-speed locking completion flag output wait time.)
→
Stops the sub-charge pump and only the main-charge
pump operates. (Normal locking state)
*:
: operating;
: stopped (high-impedance)
Control Data
Setting data (CCB) necessary for the new high-speed locking control is described below.
This data is valid when the FMIN (high-speed mode) is selected by setting DVS and SNS to 1.
CCB data
Name (Selectable set value)
Description
The new high-speed locking control controls the convergence of the
target frequency into the set frequency range.
TLR0/TLR1
High-speed locking convergence range
(±50/100/150/200 kHz)
This data can be used to set the frequency range for convergence
judgement.
*: As the convergence range narrower, the locking time tends to be
shorter.
During the new high-speed locking control, charge application from
the PDF pin and local oscillation frequency measurement for the
FMIN pin are repeatedly implemented.
CWS0/CWS1
High-speed locking charge wait time
(0/2.5/5/10 µs)
This data can be used to set the Vt voltage stable time after the
charge is applied until the local oscillator frequency is measured.
Recommended value
TLR0 = 0
TLR1 = 0
(±50 kHz)
CWS0 = 1
CWS1 = 0
(5 µs)
*: Voltage stable time Vt changes according to the peripheral
circuit.
HSE0/HSE1
High-speed locking completion flag output
wait time
(0/100/200/400 µs)
After the new high-speed locking control ends, since the phase
remains in convergence state in the internal unlock detection circuit
until the locking judgement is implemented, the sub-charge pump
will not operate by the sub-charge pump operation setting during
unlocked.
This data can be used to set the time to force the sub-charge pump
to operate for after the new high-speed locking control completes.
HSE0 = 0
HSE1 = 1
(400 µs)
*: After the new high-speed locking control completes, the locking
time tends to be shortened by operating the sub-charge pump for
an adequate time.
*: The recommended values are for reference purpose only, not the guarantee values for the fastest locking time.
No. 6976-19/29
LC72151V
Block Diagram
XIN
Reference Divider
Phase
Detector
FMIN
PDM2
PDM1
Programmable Divider
CCB
(CE,DI,CL)
Register <value N (New)>
Unlock
Register <value N (Old)>
Register <Count value>
Unlock
Detector
and
Subcharge
Pump Cont
PDS
Fast Lock Up
PDF
Control
Frequency Counter
Gate Time
System Clock for Fast Lock Up Control
TGI1
TGI2
–
+
TGO
AOUT
AVSS
AREF
AIN1
AVDD
VCO
No. 6976-20/29
LC72151V
Charge Pump Structure
TLR0,TLR1
Fast Lock Up
CWS0,CWS1
PDF
New high-speed
locking charge pump
PDM1
Main-charge pump
PDM2
Main-charge pump
PDS
Conventional high-speed
locking sub-charge pump
Control
(High Speed)
HSE0,HSE1
DLC
(MAIN)
fvco/N
Phase
Detector
fref
(MAIN)
DZ0
Clock
UL0
UL1
DZ1
Unlock
Detector
and
Subcharge
Pump Cont
PDC0
Unlock
PDC1
(SUB)
DO
PDC1
PDC0
0
*
PDS(Sub-charge pump state)
High impedance
1
1
Charge pump operating (at all times)
1
0
Charge pump operating (when PLL unlocked)
DLC
PDM1, PDM2, PDS
0
Normal operation
1
Forced low
Note: If the unlock state is detected when the channel changes, the sub-charge pump (PDS) operates. Since the subcharge pump operates concurrently with the main-charge pump, decrease the time constants for the low-pass filter
to accelerate the locking.
However, note that when the FMIN (high-speed mode) is selected and when the channel changes (during highspeed locking control), both the main- and the sub-charge pumps do not operate and enter the high impedance
state, and forcibly implement an unlock judgement. When locked at a high-speed locking control completion, the
output is not extended but locking is instantaneously judged. By selecting sub-charge operation (during unlocked)
with FMIN (high-speed mode) selected, the sub-charge pump is forcibly operated to shorten the locking time for
the time set by the high-speed locking completion flag output wait time control data (HSE0, HSE1) after switching
from high-speed locking control to normal PLL operation.
No. 6976-21/29
LC72151V
General-purpose counter structure
I/O signal
switching gate
1
2
HCTR
General-purpose counter
(20-bit binary counter)
S1
(FIF)
L
S
B
S2
LCTR
S3
Single period/
double period
extraction circuit
M
S
B
0–3
(T)
8–11
DO pin
12–15 16–19
CTE
CTS1
Check signal
CTS0
C = FIF × GT
C = (1/T) ÷ 900kHz
4/8/32/64
ms
4–7
GT
GT1,GT0
Parameter
LCTR period measurement mode check signal frequency
X’tal OSC
10.25 MHz
Check signal
1025 kHz
10.35 MHz
fref = 30, 9, 3 kHz
fref = other than 30, 9, 3 kHz
1030 kHz
1150 kHz
CTS1
CTS0
Input pin
Measurement mode
Frequency range
S1
1
*
HCTR
Frequency
0.4 to 25.0 MHz
Input sensitivity
40 mVrms *1
S2
0
1
LCTR
Frequency
10 to 500 kHz
40 mVrms *1
S3
0
0
LCTR
Period
1.0 to 20 × 103 Hz
(Pulse)
*1: CTC = 0: 40 mVrms
CTC = 1: 70 mVrms
HCTR: Minimum input sensitivity regulation
f [MHz]
CTC
0.4 ≤ f < 8
8 ≤ f < 12
12 ≤ f ≤ 25
0 (Normal mode)
40 mVrms
40 mVrms
(5 to 15 mVrms)
40 mVrms
1 (Degrade mode)
—
70 mVrms
(40 to 60 mVrms)
—
LCTR: Minimum input sensitivity regulation
f [MHz]
CTC
10 ≤ f< 400
400 ≤ f ≤ 500
0 (Normal mode)
40 mVrms
20 mVrms
(1 to 10 mVrms)
1 (Degrade mode)
—
70 mVrms
(15 to 30 mVrms)
GT1
GT0
0
0
Frequency measurement mode
—: No stipulation ( Not guaranteed)
( ): Actual value (Reference value)
Period measurement mode
Measurement time
Wait time
0
4 ms
3 to 4 ms
1 period
1
8
1
0
32
7 to 8 ms
2 periods
1
1
64
CTC: Input sensitivity select data. Input sensitivity is degraded by setting CTC to 1.
However, the actual value for HCTR is in the range 40 to 60 mVrms at 10.7 MHz, for LCTR is in the range 15 to
30 mVrms at 450 kHz.
CTP: Input pull-down can be inhibited by setting CTP to 1.
Set CTP to 1 4 ms before setting CTE to 1. Set CTP to 0 when the counter is not used.
Wait time will be reduced to 1 to 2 ms by setting CTP to 1.
No. 6976-22/29
LC72151V
The LC72151V’s general-purpose counter is a 20-bit binary counter.
The result of the count operation can be read out MSB first from the DO pin.
The measurement time when the general-purpose counter is used for frequency measurement is set to either 4, 8, 32, or
64 ms by the GT0 and GT1 bits. The frequency of the input to the HCTR pin can be measured by determining how many
pulses were input to the general-purpose counter during this measurement time.
When the general-purpose counter is used to measure the frequency, the period of the signal input to LCTR pin can be
measured by counting the number of check signals input to the general-purpose counter for the one or two periods of the
signal input to the LCTR pin.
Reset the general-purpose counter in advance by setting CTE to 0 before starting the counter.
A general-purpose counter count operation is started by setting the CTE bit in the serial data to 1. The serial data takes
effect internally to the LC72151V when the CE pin input level is changed from high to low. The input to the HCTR pin
must be provided before the wait time has elapsed after CE was set low.
Next, the result of the general-purpose counter count after the measurement completes must be read out while CTE is still
set to 1. This is because the general-purpose counter is reset when CTE is set to 1.
Never fail to reset the general-purpose counter before starting the count operation of the general-purpose counter. In
addition, the signal input to LCTR pin is directly transmitted to the general-purpose counter.
Note that the signal input to the HCTR pin is first divided by 2 internally to the IC and then input to the general-purpose
counter. Therefore, the result of the general-purpose counter count is a value that corresponds to 1/2 of the frequency
actually input to the HCTR pin.
CE
CTE=1
Measurement
time
GT
tWU
Completion
Start
TWU : Wait time
end-UC
When used as an integrating counter
CTE=1
CTE=1
CTE=0
CE
Internal data
latch
(CTE)
GT
Generalpurpose
counter
end-UC
(DO)
Integrates
Restart
Start
End of the count operation
*CTE: 0 →
1 →
Reset
End of the count operation
• Resets the general-purpose counter
• Starts the general-purpose counter
• Restarts the counter if set to 1 again.
In integrating count mode, the count value of the general-purpose counter is accumulated. Care must be taken to handle
counter overflow correctly. The count value will be in the range 0H to FFFFFH.
No. 6976-23/29
LC72151V
Other items
(1) Notes on the phase detector dead band
DZ1
DZ0
Dead band mode
Charge pump
Dead band
0
0
DZA
ON/ON
– –0 s
0
1
DZB
ON/ON
–0 s
1
0
DZC
OFF/OFF
+0 s
1
1
DZD
OFF/OFF
++0 s
When the charge pump operates in ON/ON mode, the charge pump generates correction pulses even when the PLL is
locked. Here, it is easy for the loop to become unstable, and special care is required in designs that use this mode.
The following problems may occur in ON/ON mode.
• Side bands may be generated due to reference frequency leakage.
• Side bands may be generated due low-frequency leakage due to the envelope of the correction pulses.
When a dead band is present (OFF/OFF mode), the loop will be stable, but it will be harder to acquire a good C/N ratio.
On the other hand, with the mode that does not have a dead band (ON/ON mode), it will be easier to acquire a high C/N
ratio, but harder to acquire loop stability.
Therefore, the DZA and DZB modes, in which there is no dead band, can be effective if either a high signal-to-noise ratio
of 90 to 100 dB in FM reception or an increased pilot margin in AM stereo reception is required.
Inversely, if such a high FM signal-to-noise ratio is not required for FM reception, or an adequate pilot margin can be
acquired for AM stereo reception, then the DZC and DZD modes, in which a dead band is present, may be more
effective.
Dead zone (dead band) definition
The phase comparator compares fp with the reference frequency (fr) as shown in figure 1. This circuit outputs a voltage
V (A) that is proportional to the phase difference ø as shown in figure 2. However, due to internal delays and other
factors, the actual IC is unable to compare small phase differences, and thus a dead zone (B) appears in the output. To
achieve a high signal-to-noise ratio in the end product, the dead zone should be as small as possible.
However, in popularly-priced models, there are cases where a somewhat wider dead zone may be easier to work with.
This is because in some situations, such as when a powerful signal is applied to the RF input, in popularly-priced models
there may be RF leakage from the mixer to the VCC. When the dead zone is narrow, outputs to correct this leakage are
output, that output in turn modulates the VCO, and generates a beat signal with the RF.
V
RF
(A)
Leakage
fr
MIX
(B)
Reference divider
fp
Phase
detector
LPF
VCO
ø (nsec)
Programmable divider
Dead zone
Figure 1
Figure 2
(2) Notes on the FMIN, AMIN, HCTR/I-3, and LCTR/I-4 pins
The coupling capacitor must be located as close as possible to these pins. A capacitance of approximately 100 pF is
desirable.
In particular, if the HCTR/I-3 and LCTR/I-4 pin capacitor is over about 1000 pF, the time required to reach the bias level
may become excessive, and incorrect counting may occur due to the relationship with the wait time.
No. 6976-24/29
LC72151V
(3) Notes on the IF counting using HCTR/I-3 and LCTR/I-4 pins
When counting the IF frequency, the application microcontroller must test the state of the IF IC SD (station detect)
signal, and only if the SD signal is present, turn on the IF counter buffer output and perform an IF count operation.
Methods in which auto-search operations are implemented only using the IF count may incorrectly stop at frequencies
where no station is present due to leakage from the IF counter buffer.
(4) Using the DO pin
At times other than data output mode, the DO pin can also be used to check for general-purpose counter count operation
completion, to output the unlock state detection signal, and to check for changes in the input pins.
Note that the states of the input pins (I/O-1 and I/O-2) can be directly input to the system microcontroller through the DO
pin.
(5) Power supply pins
Capacitors of at least 0.1 µF must be inserted between the VDD and VSS power supply pins and between AVDD and AVSS
to reduce noise.
These capacitors must be located as close to the VDD and VSS, AVDD and AVSS pins as possible.
Additionally, power must be applied to AVDD before applying to VDD, and AVDD must be higher than or equal to VDD.
(6) Note on power application
After power is first applied, the power-on reset circuit initializes the IC. However, the CCB data RST must be set to 1 to
ensure the initialization.
(7) Notes on VCO design
The VCO must be designed so that the VCO oscillation does not stop if the control voltage (Vtune) becomes 0 V. If it is
possible for this oscillator to stop, use the charge pump control data (DLC) to forcible set Vtune to VCC temporarily to
prevent the PLL circuit from deadlocking. (This function is called a deadlock clear circuit.)
Pin states during a power-on reset
State
Power-on state
Power-on state
XOUT
XIN
F
I-1
I/O-1
CE
F
I-2
I/O-2
DI
XBUF
CL
O-3
DO
O
AOUT2
VDD
VSS
O: Open
L: Low
State
LC72151V
AIN2
FMIN
PDM2
AMIN
PDF
HCTR/I-3
PDM1
LCTR/I-4
PDS
AREF
AIN1
AVDD
TGI1
AVSS
TGI2
AOUT1
TGO
F: Floating
No. 6976-25/29
LC72151V
Sample Application Circuit
10.25M/10.35MHz
2nd Mixer
XOUT
1
30 XIN
I/O-1
2
S
29 CE
CE
I/O-2
3
S
28 DI
DI
XBUF
4
S
27 CL
CL
µ-COM
330Ω
33pF
O-3
VDD
26 DO
5
DO
VCC=8V
3.9kΩ
0.068µF
3.3kΩ
Unlock
SD
end-UC
U-Count
ST-Indic
25 AOUT2
6
Tuner-System
VSS
AVSS
7
24 AIN2
100pF
4.3kΩ
FMIN
8
23 PDM2
AMIN
9
22 PDF
100pF
VCC
=8V
0.01µF
200Ω
100pF
22kΩ
AMVCO
5.6kΩ
8.2kΩ
HCTR/I-3 10
21 PDM1
LCTR/I-4 11
VCC=8V
20 PDS
AREF 12
19 AIN1
10kΩ
100Ω
AVDD 13
18 TGI1
AVSS 14
17 TGI2
AOUT1 15
16 TGO
4700pF
2kΩ
0.033µF
100Ω
FMVCO
1000pF
ST-Indicate
FM/AM-IF
FM/AM
IF-Request
SD
*: The constants shown are for reference purpose only, but do not guarantee the operation.
Notes: 1. Power must be applied to AVDD before applying to VDD, and AVDD must be higher than or equal to VDD.
2. AREF is an op-amp reference input voltage pin and must be applied a voltage 1/2 VDD. The applied voltage requires to be applied
from another power supply from VDD to prevent affections due to logic system noise or other factors.
No. 6976-26/29
LC72151V
LC72151V State Setting Examples
1. In the case of FMRF 87.5 MHz reception (X’tal = 10.35 MHz/IF = +10.8 MHz)
FM VCO = 98.3 MHz
X’tal = 10.35 MHz, fref = 50 kHz
: XS = 1, R0 = R1 = R2 = R3 = 0
FMIN (high-speed mode) selected
: DVS = 1, SNS = 1
Dead-zone mode = DZD
: DZ0 = DZ1 = 1
Programmable divider divisor
98.3 MHz ÷ 50 kHz = 1966 → 07AE (Hex)
High-speed locking control conditions
High-speed locking convergence range = ±50 kHz
: TLR0 = TLR1 = 0
High-speed locking charge wait time = 5 µs
: CWS0 = 1, CWS1 = 0
High-speed locking completion flag output wait time = 400 µs : HSE0 = 0, HSE1 = 1
Unlock detection width = ±0.43 µs
: UL0 = 0, UL1 = 1
[IN1]
Address
8
DI
2
0 0 0 1 0 1 0 0
First Data IN1
MS B
LSB
GT0
GT1
CTS0
CTS1
DT1
RST
CTE
R1
R2
R3
DT0
R0
SNS
DVS
PDC0
PDC1
P8
P9
P10
P11
P12
P13
P14
P15
P4
P5
P6
P7
P0
P1
P2
P3
E
A
7
0
B
0
0
0
0 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Transmitted data
[IN2]
Address
9
DI
2
1 0 0 1 0 1 0 0
First Data IN2
MS B
TEST2
TEST3
TEST0
TEST1
DLC
DZ0
DZ1
IL1
ULD
UL0
UL1
IL0
H/I-3
L/I-4
CTP
CTC
*
TLR0
TLR1
CWS0
CWS1
HSE0
HSE1
1
9
0
0
D
0
0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0
OUT1
OUT2
OUT3
XB
*
*
0
*
* 0 0 * * *
I/O-1
I/O-2
*
XS
LSB
Transmitted data
No. 6976-27/29
LC72151V
2. In the case of AMRF 530 kHz reception (X’tal = 10.35 MHz/IF = 10.8 MHz)
AM VCO = 11.330 MHz
X’tal = 10.35 MHz, fref = 10 kHz
: XS = 1, R0 = R1 = R2 = 0, R3 = 1
X’tal Buffer ON
: XB = 1
AMIN selected
: DVS = 0, SNS = 1
Dead-zone mode = DZD
: DZ0 = DZ1 = 1
Programmable divider divisor
11.330 MHz ÷ 10 kHz = 1133 → 046D (Hex)
[IN1]
Address
8
DI
2
0 0 0 1 0 1 0 0
First Data IN1
MSB
LSB
GT0
GT1
CTS0
CTS1
DT1
RST
CTE
R1
R2
R3
DT0
R0
DVS
PDC0
PDC1
SNS
P10
P11
P12
P13
P14
P15
P4
P5
P6
P7
P8
P9
P0
P1
P2
P3
D
6
4
0
1
8
0
0
1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Transmitted data
[IN2]
Address
9
DI
2
1 0 0 1 0 1 0 0
First Data IN2
MSB
TEST2
TEST3
TEST0
TEST1
DLC
DZ0
DZ1
IL1
ULD
UL0
UL1
IL0
L/I-4
CTP
CTC
H/I-3
1
0
0
0
D
0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0
*
8
* *
OUT1
OUT2
OUT3
XB
XS
*
*
*
* 0 0 *
I/O-1
I/O-2
*
TLR0
TLR1
CWS0
CWS1
HSE0
HSE1
LSB
Transmitted data
No. 6976-28/29
LC72151V
Locking time (Reference data)
98.2MHz → 118.7MHz
118.7MHz → 98.2MHz
ZOOM
ZOOM
0.41ms
0.39ms
±10kHz
±10kHz
*: Data here are measured using a SANYO evaluation board with the peripheral circuits and state setting shown in the
Sample Application Circuit and the LC72151V State Setting Examples.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of August, 2002. Specifications and information herein are subject to
change without notice.
PS No. 6976-29/29