SANYO LC749460W

Ordering number : ENA1187A
LC749460W
CMOS IC
Silicon gate
Digital RGB Processor LSI
Overview
The LC749460W is RGB processor LSI which converts the interlace TV signal such as NTSC or PAL into progressive
signal, optimizes and adjusts the image quality of these TV signals to the FPD devices such as LCD-TV, and output the
signal that converts the resolution according to the connected panel. It optimizes LSI for the pixel display device
which deals with image quality and high resolution image. A video signal processing system for flat panel display can be
formatted easily by combining with microcomputer and LCD panel.
Features
(1) Analog input
• Built-in 4ch A/D converter
• CVBS × 2ch, S-Video, YCbCr/YPbPr input (supports 480i/576i, 480p/576p, 1080i, 720p) × 2ch
(2) Digital input/output
• Support digital video input: YCbCr 24-bit or YCbCr 16-bit (4:2:2) signal or ITU-R BT656 (8-bit) input
• Support DTV (480i/576i, 480p/576p, 1080i, 720p) input: YCbCr/YPbPr/RGB digital 24-bit signal input
• Digital RGB 30-bit (24-bit)/YCbCr 30-bit (24-bit) signal output
(3) YC separation video decoder (NTSC, PAL, SECAM)
• Adaptive 3D YC separation (NTSC)/Adaptive 3 or 5 line YC separation (PAL).
• Digital AGC. Digital ACC
(4) De-interlacing
• Motion adaptive Jaggy-less De-interlacing
• 2:3 pull-down, 2:2 pull-down
Continued on next page.
: SANYO Digital Picture Improvement Core
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
62508HKIM / 52808HKIM B8-9279 No.A1187-1/20
LC749460W
Continued from preceding page.
(5) Resolution Conversion
• Resolution conversion (to WXGA)
• PIP/POP.
(6) Picture quality improvement
• Noise reduction (3D NR)
• Cross color/Cross luminance canceller
• Horizontal edge correction (LTI/CTI), Sharpness (horizontal/vertical), Shadow adjuster
• White/black stretch. Flesh tone improvement.
• Hue/Color gain adjustment/Color exciter (6 phase RGBYMC Independent saturation correction).
• Brightness/Contrast adjustment. White balance/Black balance adjustment.
• γ correction (RGB independent, LUT system programmable). Dithering (10-bit/8-bit). Clamp control.
• Clock generator (PLL)/various of Built-in interface (SDRAM IF, I2C bus, 3 wire-bus)
• YUV to RGB conversion/YCbCr to RGB conversion/YPbPr to RGB conversion/RGB to YCbCr conversion
LSI Specifications
• Supply voltage Core: 1.2V, I/O block: 3.3V
• Maximum operating frequency: 85MHz
• Package: LQFP256
Principal Applications
• LCD TVs, monitors, and projectors, PDP TVs, progressive scan TVs, and projection TVs
1. Input
1-1 Input signal format (Digital input)
Digital data port supports the following signal input formats.
24bit (4:4:4) YCbCr/RGB: NTSC/PAL (480i/576i), 480p, 576p, HD (1080i/720p)
16bit (4:2:2) YCbCr: NTSC/PAL (480i/576i), 480p, 576p, HD (1080i/720p)
8bit Based on ITU-R BT656system (H/V sync input is needed): NTSC/PAL (480i/576i)
Digital 2 system input such as 16bit (4:2:2) YCbCr + 8bit (ITU-R BT656), 8bit (ITU-R BT656) +
8bit (ITU-R BT656) are possible
1-2 Input signal format (Analog input)
Analog port can be connected to all of the following input.
CVBS × 2ch: Composite input 2CH
S-Video: S video input 1CH
YPbPr input (Supports 480i/576i, 480p/576p, 1080i, 720p input): Component input 2 system
2. Digital Video Decoder Block
This LSI carries video decoder which converts the video signal of NTSC, PAL and SECAM or Component
video signal into digital picture signal.
It decodes Digital picture data by inputting the video signals of NTSC, PAL and SECAM which are converted
from Analog to Digital. It supports composite video signal, S video signal and component signal (480i).
3. De-interlacing Block
When inputting NTSC (480i) and PAL (576i), it can implement motion adaptive De-interlacing, cinema mode
de-interlace, 3D noise reduction and cross color/cross luminance canceller. At 480p, 576p, 1080i, 720p, this block is
set to the through state.
3-1. Motion adaptive De-interlacing
At De-interlacing block, it operates the movement detection to every pixel that inputted. As a result, it does
interpolation between front and back field to the pixel that judged as static, and does interpolation inside field
to the pixel that judged as move. So de-interlacing can be done. In that case, as for interpolation in between
field of move part, it is possible to produce less notched (less-jaggy) and smooth image because of interpolation
that considers the correlation of oblique direction.
No.A1187-2/20
LC749460W
3-2. Cinema mode De-interlacing (3-2/2-2 pull-down)
When NTSC/PAL interlace signal generated from film (cinema) source or 30p source such as cartoon are
inputted, it does auto-discriminate cinema/30p source and cinema mode de-interlace that suitable for source.
3-3. 3D Noise reduction
This has built-in round type 3D noise reduction function that decreases the noise between frames. In this block
luminance signal and color difference signal can be processed independently.
3-4. Cross color/Cross luminance canceller
This function can decrease the cross color, noise and cross luminance which are generated when NTSC input
signal from composite terminal. By using this function, it can produce vivid image without color blotting and
dot interruption.
4. Scaler block
It implement the up/down scaling of the various input signal of analog and digital that fixed to XGA, WXGA of
output resolution. Full/panorama/zoom display is possible and maximum resolution is WXGA (1366 × 768 and
85MHz pixel clock). Additionally, this has built-in 2scaler system and enable to display 2screen such as POP/PIP.
5. Image quality adjustment block
This has various image quality blocks and enables to implement the image quality adjustment to fix with flat panel
TV.
5-1. Horizontal edge correction (LTI/CTI)
LTI/CTI does edge correction of input signal. It improves the sharpness of image by making the transients of
input signal steep. In this case, it is possible to make natural image because there is no peak such as overshoot
and undershoot attached at the edge part of image. This function operates independently luminance signal and
color difference signal.
5-2. Sharpness (Horizontal/Vertical)
Sharpness can do edge correction of input signal. In this function, unlike the above function, the moderate
peak is added around edge correction. In this case, coring which emphasizes neither an amount of peak nor
slight noise can be controlled by register. This function is operated only for luminance signal.
5-3. Shadow adjuster
Shadow adjuster add the moderate peak at front and back of detected edge of input signal and with added
shadow of image, so it can produce sharpness image.
5-4.White/Black Stretch
As far as White-black stretch is concerned, it stretches the level of white side and black side of Y signal of
YCbCr signal according to white-black peak inside picture of just before field, APL (Average Picture Level) of
luminance, distribution information and microcomputer setting information. White and black peak are the max
value and min value of input data in 1 field. When using white/black stretch, each setting value should be set
properly.
5-5. Flesh color correction
Flesh color correction can extract flesh color and adjust the fresh color without influencing other colors.
5-6. Color phase/Color gain adjustment
The phase adjustment can adjust the hue on entire screen. The color gain adjustment can adjust the density of
colors by controlling the gain of color phase signal. This function can adjust independently by Cb and Cr.
5-7. Color exciter
Color exciter can control the gain of chroma in red, green, blue, magenta, yellow, cyan respectively.
5-8. Brightness/Contrast
Brightness can adjust the brightness of entire screen, and contrast can adjust gain of brightness.
5-9. White balance/Black balance adjustment
This function can do white adjustment and black adjustment of LCD panel.
5-10. Gamma correction
It is possible to make the optional gamma curve that fix to LCD panel characteristic. It is also possible to adjust
R, G and B independently by writing the adjustment value in LUT inside LSI
5-11. Dither
When the signal processing of internal 10/12bit is output by 8/10bits, the dither rounds the 2/4bits of LSB and
output it.
No.A1187-3/20
LC749460W
6. Built-in OSD block
This function can do OSD (On Screen Display) on the image data after adjusting image quality.
The amount of the expression per pixel can be selected from 16 indexes (4 bits: CLUT4) and 256 indexes (8 bits:
CLUT8). The color pallet of the index can set alfa 4-bit of blending coefficient and 8-bit of green, blue, and the red.
Displayed character and icon, etc. need to set the αGBR color to the color pallet and transmit the BMP data in the
state of CLUT 4/8. The drawing engine is built-in, besides, it is possible not only to draw the transmitted BMP data
to SDRAM but also do the rectangle drawing (including point and line drawing) and copy inside SDRAM.
7. Output/I/F/others
7-1. Matrix conversion
The following Matrix conversion is possible for 2 systems after digital and analog input are selected.
YCbCr to RGB
YPbPr to RGB
YPbPr to YCbCr
RGB to YCbCr
7-2. Output format
Output is possible with the following format.
Digital RGB (30-bit/24-bit)
Digital YCbCr (30-bit/24-bit)
7-3. Clamp control
This can generate clamp signal in external LSI or in the built-in AD converter. In addition, it can generate
optional pulse(“H”, “L”, “Hi-Z”) by comparing to the threshold value in the inside the LSI.
7-4. SDRAM interface
This built-in SDRAM interface, the system can be made up easily by connecting
64Mbits SDRAM (512word × 32bit × 4bank) 1 piece or 128Mbits SDRAM (1024word × 32bit × 4bank) 1 piece
in directly. In this case, more than“-60” speed grade of SDRAM is recommended.
7-5. External OSD interface
This allows the interface with external OSD microcomputer using input pin 41 to 45 and output pin 36 to 38. It
can display closed caption and teletext data.
7-6. I2C interface/3 wire bus interface
It basically controls the internal register using I2C interface.
The slave address can be a switch by controlling pin53 (I2C SEL) according to the system.
The slave address is as follows.
I2CSEL “L” “0111000+(R/W)”
I2CSEL “H” “0111001+(R/W)”
A part of register can be controlled by 3wire bus interface as well.
No.A1187-4/20
LC749460W
I/O Specifications
1. Input Signals
The Kinds of Signals
Video signal
Sync signal
Data enable signal
The Number of Pins
Pin Symbol
1
CVBS1
Explanation
1
CVBS2
NTSC/PAL input 2
1
ASYIN
S-Video input Y
1
ASCIN
S-Video input C
1
AYIN1
Component input Y1
Analog video signal
Remarks
NTSC/PAL input 1
1
ACBIN1
1
ACRIN1
Component input Cb1
Component input Cr1
1
AYIN2
Component input Y2
1
ACBIN2
Component input Cb2
1
ACRIN2
Component input Cr2
8
YGI
Digital video signal
Y or G or SY input
8
CBI
Cb or B or YC input
8
CRI
Cr or R or ITU-R BT656 input
1
HS1I
Horizontal sync signal
Horizontal sync signal for digital input 1
1
VS1I
Vertical sync signal
Vertical sync signal for digital input 1
1
HS2I
Horizontal sync signal
Horizontal sync signal for digital input 2
1
VS2I
Vertical sync signal
Vertical sync signal for digital input 2
1
SHSI
Horizontal sync signal
Horizontal sync signal for analog input
1
SVSI
Vertical sync signal
Vertical sync signal for analog input
1
HE1I
Data enable
Data enable (Horizontal/Composite) for
digital input 1
Field signal
OSD signal
1
VE1I
Vertical data enable
1
FLD1I
Field
Data enable (Vertical) for digital input 1
Field signal input for digital input 1
1
FLD2I
Field
Field signal input for digital input 2
1
OSDG
External OSD signal G
1
OSDB
External OSD signal B
1
OSDR
External OSD signal R
1
OSDEN
External OSD enable
1
OSDAL
External OSD blending enable
Pixel clock
1
CK1I
Pixel clock
fixled oscillation
1
CK2I
Pixel clock
Pixel clock input for digital input 2
1
XTAL1
System clock
Fixed clock input 1
1
XTAL2
System clock
Fixed clock input 2
System reset
1
XRST
System reset
System reset input negative-logic
Total
56
-
-
-
The Number of Pins
Pin Symbol
10
YGO
10
CBO
10
CRO
Pixel clock input for digital input 1
2. Output signal
The Kinds of Signals
Video signal
Explanation
Digital video signal
Remarks
RGB/YCbCr output
Dithered 8bit output is possible.
1
SVO
Analog video signal
Sync signal
1
HSO
Horizontal sync signal
1
VSO
Vertical sync signal
Data enable signal
1
DEO
Data enable
Field signal
1
FLDO
Field
Pixel clock
1
CKO
Pixel clock
OSD signal
1
OSDHO
External OSD Horizontal sync signal
1
OSDVO
External OSD Vertical sync signal
1
OSDCKO
Monitor output
Field output or vertical data enable output
External OSD pixel clock
Continued on next page.
No.A1187-5/20
LC749460W
Continued from preceding page.
The Number of Pins
Pin Symbol
Clamp pulse
The Kinds of Signals
1
CLPP
Explanation
Clamp level
1
1
1
CLPSY
1
CLPSC
Clamp level for SC
1
CLPY1
Clamp level for Y1
1
CLPCB1
Clamp level for CB1
1
CLPCR1
Clamp level for CR1
1
CLPY2
1
CLPCB2
Clamp level for CB2
Clamp level for CR2
Remarks
Clamp pulse for External ADC
Pulse output to check AD clamp period
CLPCVBS1
Clamp level for CVBS1
Clamp level discriminator output
CLPCVBS2
Clamp level for CVBS2
(large: L, small: H, Coincident: Hi-Z)
Clamp level for SY
Clamp level for Y2
1
CLPCR2
PWM output
1
PWMO
Charge pump output
1
CHPMPDO
Total
52
-
The Number of Pins
Pin Symbol
1
SDA
I2C data
1
SCL
I2C clock
1
I2CSEL
PWM
Charge pump for built-in PLL
-
-
3. Control signal
The Kinds of Signals
I2C bus
Explanation
I2C slave address switch
Remarks
Low: “0111000+(R/W)”
High: “0111001+(R/W)”
Normally “L”
3-wire bus
Total
1
AIDA
3-wire bus data input/output
1
AICS
3-wire bus chip select
1
AICK
3-wire bus clock
6
-
-
-
4. SDRAM control signal
The Kinds of Signals
clock
The Number of Pins
Pin Symbol
1
SDCKI
Clock input
Explanation
1
SDCKO
Clock output
Control system
1
SDRAS
Row address strobe signal output
signal
1
SDCAS
Column address strobe signal
1
SDWE
Write enable signal output
11
SDAD
Address signal output
4
SDBS
Bank select signal output
Remarks
output
Address system
Data system
Total
4
SDDQM
32
SDDQ
56
-
SDRAM data mask signal output
Data input/output
-
-
5. Other signals
The Number of Pins
Pin Symbol
SCAN test
The Kinds of Signals
1
SCANMD
1
Test
2
ADC/AFE
4
Total
Explanation
Remarks
SCAN test
Generally fixed as “L”
SCANEN
SCAN test
Generally fixed as “L”
TEST
Test setting
Generally fixed as “L”
VRT
Reference input for ADC
4
VRB
4
DACREFP
4
DACREFM
20
-
Reference output for ADC
-
-
No.A1187-6/20
LC749460W
Package Dimensions
unit : mm (typ)
3365
30.0
28.0
30.0
0.5
28.0
256
1
0.4
0.16
0.125
(1.4)
0.1
1.6 MAX
(1.4)
SANYO : LQFP256K(28X28)
No.A1187-7/20
LC749460W
130
129
135
140
145
150
155
160
165
170
175
180
185
193
128
195
125
200
120
205
115
210
110
215
105
220
100
LC749460W
225
95
230
90
235
85
240
80
245
75
250
70
255
256
64
60
55
50
45
40
35
30
25
20
15
10
5
1
65
SDDQ14
SDDQ15
SDDQ7
SDDQ6
DVSS33
DVDD33
SDDQ5
SDDQ4
SDDQ3
SDDQ2
SDDQ1
SDDQ0
DVSS33
DVDD33
DVSS12
DVDD12
PWMO
FLDO/VEO
DEO/HEO
CKO
HSO
VSO
CRO0
CRO1
CRO2
CRO3
CRO4
DVSS33
DVDD33
CRO5
CRO6
CRO7
CRO8
CRO9
CBO0
CBO1
CBO2
CBO3
CBO4
CBO5
CBO6
CBO7
DVSS33
DVDD33
DVSS12
DVDD12
CBO8
CBO9
YGO0
YGO1
YGO2
YGO3
YGO4
YGO5
YGO6
YGO7
YGO8
YGO9
XRST
DVSS33
DVDD33
DPVSS2
DPVDD2
APVSS2
VRT3
DACREFP3
ATBP
ATBM
DVDD12
DVSS12
SHSI
SVSI
CRI7
CRI6
CRI5
CRI4
CRI3
CRI2
CRI1
CRI0
HS2I
VS2I
CK2I
FLD2I
DVDD12
DVSS12
DVDD33
DVSS33
CLPP
CLPY1
DTBO0
DTBO1
DTBO2
CLPCB2
CLPCB1
DTBO3
CLPCR2
CLPCR1
CLPY2
OSDHO
OSDVO
OSDCKO
DVDD33
DVSS33
OSDG
OSDB
OSDR
OSDEN
OSDAL
AICK
AIDA
AICS
SDA
SCL
DVDD12
DV
SS12
I2CSEL
XTAL1
SCANMD
SCANEN
XTAL2
TEST0
TEST1
DPVSS1
DPVDD1
APVSS1
APVDD1
APVDD2
DVDD33
DVSS33
CK1I
VS1I
FLD1I
YGI7
YGI6
YGI5
YGI4
YGI3
YGI2
YGI1
YGI0
DVDD12
DVSS12
CBI7
CBI6
CBI5
CBI4
CBI3
CBI2
CBI1
CBI0
APVDD0
CHPMPDO
APVSS0
AVDD33_0
AYIN2
AVSS33_0
AYIN1
VRB0
DACREFM0
VRT0
DACREFP0
ACBIN2
AVDD33_1
ACBIN1
AVSS33_1
ASCIN
VRB1
DACREFM1
VRT1
DACREFP1
SVO
ATBI0
GUARD
ASYIN
AVDD33_2
ACVBS1
AVSS33_2
ACVBS2
VRB2
DACREFM2
VRT2
DACREFP2
ACRIN2
AVDD33_3
ACRIN1
AVSS33_3
VRB3
DACREFM3
NC
NC
NC
190
192
HS1I
VE1I
HE1I
SDDQ16
SDDQ17
SDDQ18
SDDQ19
DVSS33
DVDD33
SDDQ20
SDDQ21
SDDQ22
SDDQ23
SDDQ24
SDDQ25
DVSS33
DVDD33
DVSS12
DVDD12
SDDQ26
SDDQ27
SDDQ28
SDDQ29
SDDQ30
SDDQ31
DVSS33
DVDD33
SDDQM3
SDDQM2
SDAD3
SDAD4
SDAD5
SDAD6
SDAD7
SDAD8
SDAD9
DVSS33
DVDD33
SDAD2
SDAD1
SDAD0
SDAD10
SDBS1
SDBS0
SDAD11
SDRAS
SDCAS
SDWE
DVSS12
SDCKI
DVDD12
DVSS33
SDCKO
DVDD33
SDDQM1
SDDQM0
SDDQ8
SDDQ9
SDDQ10
SDDQ11
DVSS33
DVDD33
SDDQ12
SDDQ13
Pin Assignment
Top view
No.A1187-8/20
LC749460W
Pin Functions
Pin No.
Pin symbol
In/output format
I/O
Format
Connecting
Remarks
destination
1
VRT3
I
I
ADC3 reference power supply input
2
DACREFP3
O
I
ADC3 reference power supply output
3
ATBP
I
I
Open
ADC ATB (Analog Test Bus) Analog input + terminal
4
ATBM
I
I
Open
ADC ATB (Analog Test Bus) Analog input - terminal
5
DVDD12
P
Power supply
Digital 1.2V system power supply
6
DVSS12
P
7
SHSI
I
C
External horizontal sync signal input
8
SVSI
I
D
External vertical sync signal input
C
Cr/R signal input
GND
Digital 1.2V system GND
9
CRI7
I
10
CRI6
I
11
CRI5
I
12
CRI4
I
13
CRI3
I
14
CRI2
I
15
CRI1
I
16
CRI0
I
17
HS2I
I
C
Horizontal sync signal input terminal for D2 input
18
VS2I
I
C
Vertical sync signal input terminal for D2 input
19
CK2I
I
A
Clock input terminal for D2 input
20
FLD2I
I
C
21
DVDD12
P
Power supply
22
DVSS12
P
GND
Digital 1.2V GND
23
DVDD33
P
Power supply
Digital 3.3V power supply
24
DVSS33
P
GND
Digital 3.3V GND
Field signal input terminal for D2 input
Digital 1.2V power supply
25
CLPP
O
E
Clamp pulse output terminal
26
CLPY1
O
F
Clamp control terminal
27
DTBO0
O
Open
28
DTBO1
O
Open
Open
29
DTBO2
O
30
CLPCB2
O
31
CLPCB1
O
Digital test output terminal
Clamp control terminal
32
DTBO3
O
33
CLPCR2
O
Open
Digital test output terminal
34
CLPCR1
O
35
CLPY2
O
36
OSDHO
O
37
OSDVO
O
38
OSDCKO
O
39
DVDD33
P
Power supply
Digital 3.3V system power supply
40
DVSS33
P
GND
Digital 3.3V system GND
41
OSDG
I
42
OSDB
I
B signal input for OSD
43
OSDR
I
R signal input for OSD
44
OSDEN
I
OSD input enable
45
OSDAL
I
OSD blending enable
Clamp control terminal
E
External OSD Hsync signal output terminal
External OSD Vsync signal output terminal
External OSD output pixel clock
C
G signal input for OSD
46
AICK
I
D
3-wire bus clock terminal
47
AIDA
B
H
3-wire bus data input/output terminal
48
AICS
I
D
49
SDA
B
H
50
SCL
I
D
51
DVDD12
P
3-wire bus chip select terminal
I2C bus
I2C bus data input/output terminal
I2C bus clock terminal
Power supply
Digital 1.2V system power supply
Continued on next page.
No.A1187-9/20
LC749460W
Continued from preceding page.
Pin No.
Pin symbol
In/output format
I/O
Format
Connecting
Remarks
destination
52
DVSS12
P
53
I2CSEL
I
D
GND
I2C bus slave address selection input
54
XTAL1
I
A
XTAL (for PLL1) input terminal
55
SCANMD
I
D
56
SCANEN
I
D
57
XTAL2
I
A
58
TEST0
I
D
59
TEST1
I
60
DPVSS1
P
61
DPVDD1
62
APVSS1
63
APVDD1
P
64
APVDD2
65
APVSS2
66
DPVDD2
67
68
69
DVSS33
P
70
XRST
I
B
71
YGO9
O
E
Digital G signal output terminal
72
YGO8
O
73
YGO7
O
74
YGO6
O
75
YGO5
O
76
YGO4
O
77
YGO3
O
78
YGO2
O
79
YGO1
O
80
YGO0
O
81
CBO9
O
E
Digital B signal output terminal
82
CBO8
O
83
DVDD12
P
Power supply
Digital 1.2V system power supply
84
DVSS12
P
GND
Digital 1.2V system GND
85
DVDD33
P
Power supply
Digital 3.3V system power supply
86
DVDD33
P
GND
87
CBO7
O
88
CBO6
O
89
CBO5
O
90
CBO4
O
91
CBO3
O
92
CBO2
O
93
CBO1
O
94
CBO0
O
95
CRO9
O
96
CRO8
O
97
CRO7
O
98
CRO6
O
99
CRO5
O
100
DVDD33
P
101
DVSS33
P
102
CRO4
O
103
CRO3
O
104
CRO2
O
Open
Digital 1.2V system GND
Test terminal
XTAL (for PLL2) input terminal
Open
Test terminal
GND
Digital GND for PLL1
P
Power supply
Digital 1.2V system power supply for PLL1
P
GND
Analog GND for PLL1
Power supply
Analog 3.3V system power supply for PLL1
P
Power supply
Analog 3.3V system power supply for PLL2
P
GND
Analog GND for PLL2
P
Power supply
Digital 1.2V system power supply for PLL2
DPVSS2
P
GND
Digital GND for PLL2
DVDD33
P
Power supply
Digital 3.3V system power supply
GND
Digital 3.3V system GND
Initial circuit
System reset terminal (“L” reset)
Digital 3.3V system GND
E
Digital B signal output terminal
E
Digital R signal output terminal
Power supply
GND
E
Digital 3.3V system power supply
Digital 3.3V system GND
Digital R signal input terminal
Continued on next page.
No.A1187-10/20
LC749460W
Continued from preceding page.
Terminal
No.
Terminal symbol
In/output format
Connection
Remarks
destination
I/O
Format
E
Digital R signal input terminal
Vertical sync signal output terminal
105
CRO1
O
106
CRO0
O
107
VSO
O
E
108
HSO
O
E
Horizontal sync signal output terminal
109
CKO
O
G
Pixel clock output terminal
110
DEO/HEO
O
E
Data enable /horizontal data enable output terminal
111
FLDO/VEO
O
E
Field signal/vertical data enable output terminal
112
PWMO
O
G
PWM output terminal
113
DVDD12
P
Power supply
114
DVSS12
P
GND
Digital 1.2V system GND
115
DVDD33
P
Power supply
Digital 3.3V system power supply
116
DVSS33
P
GND
Digital 3.3V system GND
117
SDDQ0
B
SDRAM
SDRAM data input/output terminal
118
SDDQ1
B
119
SDDQ2
B
120
SDDQ3
B
121
SDDQ4
B
122
SDDQ5
B
123
DVDD33
P
Power supply
Digital 3.3V system power supply
124
DVSS33
P
GND
Digital 3.3V system GND
125
SDDQ6
B
SDRAM
SDRAM data input/output terminal
126
SDDQ7
B
127
SDDQ15
B
128
SDDQ14
B
129
SDDQ13
B
130
SDDQ12
B
131
DVDD33
P
Power supply
Digital 3.3V system power supply
132
DVSS33
P
133
SDDQ11
B
134
SDDQ10
B
135
SDDQ9
B
136
SDDQ8
B
137
SDDQM0
O
138
SDDQM1
O
139
DVDD33
P
140
SDCKO
O
141
DVSS33
142
DVDD12
H
H
Digital 1.2V system power supply
GND
Digital 3.3V system GND
H
SDRAM
SDRAM data input/output terminal
G
SDRAM
SDRAM DQM0 output terminal
SDRAM DQM1 output terminal
Power supply
Digital 3.3V system power supply
SDRAM
SDRAM clock output terminal
P
GND
Digital 3.3V system GND
P
Power supply
Digital 1.2V system power supply
SDRAM
SDRAM clock input terminal
143
SDCKI
I
144
DVSS12
P
145
SDWE
O
G
A
G
GND
Digital 1.2V system GND
SDRAM
SDRAM write enable output terminal
146
SDCAS
O
SDRAM column address strobe output terminal
147
SDRAS
O
SDRAM low address strobe output terminal
148
SDAD11
O
G
SDRAM
149
SDBS0
O
G
SDRAM
150
SDBS1
O
151
SDAD10
O
152
SDAD0
O
153
SDAD1
O
154
SDAD2
O
155
DVDD33
156
DVSS33
157
SDAD9
O
158
SDAD8
O
SDRAM address output terminal
SDRAM bank 0 selection output terminal
SDRAM bank 1 selection output terminal
G
SDRAM
SDRAM address output terminal
P
Power supply
Digital 3.3V system power supply
P
GND
Digital 3.3V system GND
SDRAM
SDRAM address output terminal
G
Continued on next page
No.A1187-11/20
LC749460W
Continued from preceding page.
Terminal
No.
Terminal symbol
In/output format
Connection
Remarks
destination
I/O
Format
G
SDRAM
SDRAM address output terminal
G
SDRAM
SDRAM DQM2 output terminal
159
SDAD7
O
160
SDAD6
O
161
SDAD5
O
162
SDAD4
O
163
SDAD3
O
164
SDDQM2
O
165
SDDQM3
O
166
DVDD33
P
Power supply
Digital 3.3V system power supply
167
DVSS33
P
GND
Digital 3.3V system GND
168
SDDQ31
B
SDRAM
SDRAM data input/output terminal
169
SDDQ30
B
170
SDDQ29
B
171
SDDQ28
B
172
SDDQ27
B
173
SDDQ26
B
174
DVDD12
P
Power supply
Digital 1.2V system power supply
175
DVSS12
P
GND
Digital 1.2V system GND
176
DVDD33
P
Power supply
Digital 3.3V system power supply
177
DVSS33
P
GND
Digital 3.3V system GND
178
SDDQ25
B
SDRAM
SDRAM data input/output terminal
179
SDDQ24
B
180
SDDQ23
B
181
SDDQ22
B
182
SDDQ21
B
183
SDDQ20
B
184
DVDD33
P
Power supply
Digital 3.3V system power supply
185
DVSS33
P
GND
Digital 3.3V system GND
186
SDDQ19
B
SDRAM
SDRAM data input/output terminal
187
SDDQ18
B
188
SDDQ17
B
189
SDDQ16
B
190
HE1I
I
C
Horizontal data enable signal input terminal for digital input 1
191
VE1I
I
C
Vertical data enable signal input terminal for digital input 1
192
HS1I
I
C
193
DVDD33
P
Power Supply
Digital 3.3V system power supply
194
DVSS33
P
GND
Digital 3.3V system GND
195
CK1I
I
A
Pixel clock input terminal for digital input 1
196
VS1I
I
C
Vertical sync signal input terminal for digital input 1
197
FLD1I
I
C
Field discrimination signal input terminal for digital input 1
198
YGI7
I
C
SY/Y/G signal input
199
YGI6
I
200
YGI5
I
201
YGI4
I
202
YGI3
I
203
YGI2
I
204
YGI1
I
SDRAM DQM3 output terminal
H
H
H
Horizontal sync signal input terminal for digital input 1
205
YGI0
I
206
DVDD12
P
Power Supply
1.2V system power supply
207
DVSS12
P
GND
1.2V system GND
208
CBI7
I
209
CBI6
I
210
CBI5
I
C
C/Cb/B signal input
Continued on next page
No.A1187-12/20
LC749460W
Continued from preceding page.
Terminal
No.
Terminal symbol
In/output format
I/O
Format
C
211
CBI4
I
212
CBI3
I
213
CBI2
I
214
CBI1
I
215
CBI0
I
216
APVDD0
P
217
CHPMPDO
O
218
APVSS0
219
AVDD33_0
Connection
Remark
destination
C/Cb/B signal input
Power Supply
Analog power supply for PLL0
P
GND
Analog GND for PLL0
P
Power Supply
Analog 3.3V system power supply for ADC0
Analog I/F
Analog Y2 signal input
I
220
AYIN2
I
221
AVSS33_0
P
I
222
AYIN1
I
I
Charge pump output
GND
Analog 3.3V system GND for ADC0
Analog I/F
Analog Y1 signal input
223
VRB0
I
I
224
DACREFM0
O
I
ADC0 reference power supply output
225
VRT0
I
I
ADC0 reference power supply output
226
DACREFP0
O
I
ADC0 reference power supply output
I
227
ACBIN2
I
228
AVDD33_1
P
229
ACBIN1
I
230
AVSS33_1
P
231
ASCIN
232
ADC0 reference power supply output
Analog I/F
Analog Cb2 signal input
Power supply
Analog 3.3V system power supply for ADC1
I
Analog I/F
Analog Cb1 signal input
GND
Analog 3.3V system GND for ADC1
I
I
Analog I/F
Analog SC signal input
VRB1
I
I
233
DACREFM1
O
I
ADC1 reference power supply output
234
VRT1
I
I
ADC1 reference power supply input
235
DACREFP1
O
I
ADC1 reference power supply output
236
SVO
O
I
Analog I/F
237
ATBI0
I
I
Open
Analog test input terminal
238
GUARD
I
I
GND
Analog guard band terminal
I
Analog I/F
Analog SY signal input
Power supply
Analog 3.3V system power supply for ADC2
239
ASYIN
I
240
AVDD33_2
P
I
ADC1 reference power supply input
Analog signal input
241
ACVBS1
I
242
AVSS33_2
P
Analog I/F
Analog CVBS1 signal input
GND
Analog 3.3V system GND for ADC2
243
ACVBS2
I
I
244
VRB2
I
I
ADC2 reference power supply input
245
DACREFM2
O
I
ADC2 reference power supply output
ADC2 reference power supply input
Analog I/F
Analog CVBS2 signal input
246
VRT2
I
I
247
DACREFP2
O
I
248
ACRIN2
I
I
Analog I/F
Analog Cr2 signal input
249
AVDD33_3
P
Power supply
Analog 3.3V system power supply for ADC3
250
ACRIN1
I
I
Analog I/F
Analog Cr1 signal input
251
AVSS33_3
P
GND
Analog 3.3V system GND for ADC3
ADC2 reference power supply output
252
VRB3
I
I
ADC3 reference power supply input
253
DACREFM3
O
I
ADC3 reference power supply output
254
NC
255
NC
256
NC
No.A1187-13/20
LC749460W
Pin Type
In/Output form
Function
Equivalent circuit
Application Terminal
A
5V tolerant input
CK1I, CK2I, XTAL1, XTAL2, SDCKI,
B
5V tolerant schmitt
XRST
trigger input
C
5V tolerant with
YGI0 to 7, CBI0 to 7, CRI0 to 7,
pulldown input
HE1I, VE1I, HS1I, VS1I, FLD1I,
HS2I, VS2I, FLD2I,
SHSI, OSDG, OSDB, OSDR, OSDEN, OSDAL
D
E
5V tolerant with pull
SVSI, AICK, AICS, SCL, I2CSEL,
down schmitt trigger
SCANMD, SCANEN (*No use OPEN),
input
TEST0, TEST1
8mA 3-STATE
YGO0 to 9, CBO0 to 9, CRO0 to 9
drive input
VSO, HSO, DEO/HEO, FLDO/VEO,
CLPP, OSDHO, OSDVO, OSDCKO
F
G
8mA 3-STATE
DTBO0 to 3, CLPY1 CLPCB1, CLPCR1,
drive input
CLPY2 CLPCB2, CLPCR2
12mA 3-STATE
CKO, SDCKO, PWMO,
drive input
SDRAS, SDCAS, SDWE, SDAD0 to 11,
SDBS0 to 1, SDDQM0 to 3
H
5V tolerant
AIDA, SDA, SDDQ0 to 31
12mA 3-STATE drive
input/output
I
Analog input/output
VRT0 to 3, VRB0 to 3,
DACREFP0 to 3, DACREFM0 to 3,
ATBP, ATBM, CHPMPDO, SVO, GUARD,
ACVBS1, ACVBS2, ASYIN, ASCIN,
AYIN1, AYIN2, ACBIN1, ACBIN2,
ACRIN1, ACRIN2, ATBI0
No.A1187-14/20
LC749460W
Electrical Characteristics
Absolute Maximum Ratings VSS = 0V
Parameter
Symbol
Max supply voltage (I/O)
DVDD33
Max supply voltage (core)
AVDD33
DVDD12
Input voltage
AVDD12
VI
Rating
Unit
-0.3 to +3.96
V
-0.3 to +1.44
V
-0.5 to 6.0
V
VO
-0.3 to VDD +0.3
V
Storage temperature
Tstg
-55 to +125
°C
Operating temperature
Topr
-30 to +70
°C
TDB
W
Output voltage
Max supply current
Pd max
Allowable Operation Range at Ta = -30 to +70°C
Parameter
Symbol
Supply voltage (I/O)
min
typ
max
Unit
DVDD33
3.15
3.3
3.45
VDD12
1.08
1.2
1.32
V
Supply voltage (Analog)
AVDD33
3.15
3.3
3.45
V
Supply voltage (PLL)
APVDD
3.15
3.3
3.45
V
5.5
V
Supply voltage (core)
Input voltage range
VIN
0
V
I/O terminal Capacitance at Ta = 25°C, VDD = VI = 0V
Parameter
Input terminal
Output terminal
I/O terminal
Symbol
Conditions
min
typ
max
Unit
CIN
f=1MHz
10
pF
COUT
f=1MHz
10
pF
CI/O
f=1MHz
10
pF
DC Characteristics at Ta = -30 to +70°C, VDD33 = 3.15 to 3.45V, VDD12 = 1.08V to 1.32V
Parameter
Symbol
Input high-level voltage
VIH
Input low-level voltage
VIL
Input high-level current
IIH
Input low-level current
Conditions
typ
max
Unit
2.0
5.5
Schmitt input with 5V tolerant
2.0
5.5
V
Input with 5V tolerant
-0.3
+0.8
V
Schmitt input with 5V tolerant
-0.3
+0.8
V
VI=VDD
-10
+10
μA
VI=VDD, with pull-down resistance
+10
+100
μA
-10
+10
μA
2.4
IIL
VI=VSS
Output high-level voltage
VOH
CMOS
Output low-level voltage
VOL
CMOS
Output leak current
IOZ
At output of high-impedance
Pull-down resistor
min
Input with 5V tolerant
RDN
V
-10
50
V
97
0.4
V
+10
μA
272
kΩ
Dynamic supply current
IDDOP
tCK=85MHz
TBD
mA
Static supply current *1
IDDST
Output release, VI=VSS or VDD
TBD
μA
*1: There is a input terminal which builds in pull down resistance. Please note that there is no guarantee about static
consumption current depending on circuit composition.
No.A1187-15/20
LC749460W
A/D Convertor Characteristics at Ta = -30 to +70°C, DVSS = 0V, AVSS = 0V
Electric characteristic
Parameter
Symbol
Conditions
min
FCLK
Sampling frequency
Clamp pulse width
Tcl
Analog input coupling capacitor
Cal
Analog input frequency
Fal
Analog input amplitude
Val
typ
max
10
unit
MHz
80
μs
0.45
μF
0.1
30
MHz
1.0
Vp-p
SVO amplifier bandwidth
FSVO
5
MHz
SVO amplifier output load capacitor
CSVO
20
pF
External between DACREFP/DACREFM capacitor
CEXT
1
μF
0.08
0.1
ADC Characteristics
Symbol
Parameter
resolution
Conditions
min
typ
NOB
ENOB
ENOB
Derivative linearity error
DNL
Integral linearity error
INL
Operation power current
Standby power current
max
Unit
10
bits
*1
8
bits
*2
7.5
bits
*1
0.5
LSB
*2
0.5
LSB
*1
2
LSB
*2
2
LSB
mA
3.3V power
IDD3
*2, *3
60
1.2V power
IDD
*2, *3
1.5
3.3V power
ISB3
*3
-10
+10
μA
1.2V power
ISB
*3
-10
+10
μA
mA
*1 VDD3=3.3V, Fclk=27MHz, Fin=100KHz
*2 VDD3=3.3V, Fclk=80MHz, Fin=100KHz
*3 It describes value per 1ch
Note: ADC cannot standby. Apply a square wave with a constant frequency when ADC is not to be used.
I/O Data Timing
(1) Input data timing 1
tCK
tHI
VDD33/2
CLK
tSU
tLO
tHD
VDD33/2
Input data
Pin name
CK1I, CK2I
YGI [7:0], CBI [7:0], CRI [7:0],
HE1I, VE1I, HS1I, VS1I,
FLD1I, HS2I, VS2I, FLD2I
Parameter
Clock L-level time
Symbol
tLO
min
max
Unit
6.25
ns
Clock H-level time
tHI
6.25
ns
Clock cycle
tCK
12.5
ns
Input data setup time
tSU
2
ns
Input data hold time
tHD
1
ns
* The recommended duty cycle of input clock is 50%
No.A1187-16/20
LC749460W
(2) Input data timing 2
tHI
tCK
VDD33/2
SDCKI
tSU
tLO
tHD
VDD33/2
Input data
Pin name
SDCKI
SDDQ [31:0]
Parameter
Symbol
min
max
Unit
Clock L-level time
tLO
3.00
ns
Clock H-level time
tHI
3.00
ns
Clock cycle
tCK
6.00
ns
Input data setup time
tSU
2
ns
Input data hold time
tHD
1
ns
(3) Output data timing 1
tCK
tHI
VDD33/2
CKO
tAC
tLO
tHD
VDD33/2
Output data
Pin name
Parameter
CKO
YGO [9:0], CBO [9:0], CRO [9:0], VSO,
HSO, DEO/HEO, FLDO/VEO, OSDHO,
OSDVO, OSDCKO
Symbol
min
max
Unit
Clock L-level time
tLO
5.88
ns
Clock H-level time
tHI
5.88
ns
Clock cycle
tCK
11.76
ns
Output data delay time
tAC
-1.5
Output data hold time
tHD
9.00
+1.5
ns
ns
(4) Output data timing 2
tCK
tHI
VDD33/2
SDCKO
tAC
tLO
tHD
VDD33/2
Output data
Pin name
SDCKO
Parameter
Clock L-level time
Symbol
tLO
min
max
Unit
ns
3.00
Clock H-level time
tHI
3.00
ns
Clock cycle
tCK
6.00
ns
SDRAS, SDCAS, SDWE, SDAD [11:0],
Output data delay time
tAC
-1.0
SDBS [1:0], SDDQM [3:0]
Output data hold time
tHD
4
+1.0
ns
ns
No.A1187-17/20
LC749460W
(5) Output data timing 3
tCK
tHI
OSDCKO
VDD33/2
tAC
tHD
tLO
VDD33/2
Output data
Pin name
OSDCKO
OSDHO, OSDVO, OSDCKO
Parameter
Symbol
min
max
Unit
Clock L-level time
tLO
5.88
ns
Clock H-level time
tHI
5.88
ns
Clock cycle
tCK
11.76
Output data delay time
tAC
-1.5
Output data hold time
tHD
9.00
ns
+1.5
ns
ns
No.A1187-18/20
LC749460W
Block Diagram
ITU-R BT656 (8bits)
Satellite/Terrestrial (Digital 16bits)
CVBS, Y-C, YCbCr, YPbPr
64Mbit SDRAM
(512kword×32bit×4banks)
or
128Mbit SDRAM
(1024kword×32bit×4banks)
LC749460W
4ch
10bit
ADCs
&
AFE
Memory I/F
Video
Decoder
3D-NR
S
W
DeInterlacer
MotionDet.
Film mode
CrossColor
Luminance
Cancel
Picture
Quality
Improvement
POP
PIP
Scaler
OSD
Gamma
Dithering
LVDS
Tx
White/Black
Stretch
FTI
16
Brightness
Contrast
8
CLK
PLL
I²C
I²C BUS
3wire BUS
3wire BUS
Ext. OSD
No.A1187-19/20
LCD
Panel
(WXGA)
LC749460W
Application Circuit example
LC749460W
SDRAM
CVBS
Tuner
CVBS
CVBS
Y
Y/C
SW ADC
CH2
Y
C
Cb
Y/Cb/Cr
Cb
Y/Cb/Cr
Cr
Cr
Y
SW
Video decoder
De-Interlacer
Scaler
POP/PIP
Picture Improve
ADC
CH1
WXGA
LCD-Panel
LVDS
Tx
SW ADC
CH3
ADC
CH0
8
Sub Video
Decoder
16
Hs/Vs
MPEG2
Decoder
LV78200
Sync Sep
Micro-controller
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
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product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of June, 2008. Specifications and information herein are subject
to change without notice.
PS No.A1187-20/20