Dual HDMI Fast Switching Receiver with 12-Bit, 170 MHz Video and Graphics Digitizer and 3D Comb Filter Decoder ADV7842 Vertical peaking and horizontal peaking filters Robust synchronization extraction for poor video source Advanced VBI data slicer General Highly flexible 36-bit pixel output interface Internal EDID RAM for HDMI and graphics Dual STDI (standard identification) function support Any-to-any, 3 × 3 color space conversion (CSC) matrix 2 programmable interrupt request output pins Simultaneous analog processing and HDMI monitoring APPLICATIONS Advanced TVs PDP HDTVs, LCD TVs (HDTV ready) LCD/DLP® rear projection HDTVs CRT HDTVs, LCoS™ HDTVs AVR video receivers LCD/DLP front projectors HDTV STBs with PVR Projectors FUNCTIONAL BLOCK DIAGRAM SDRAM SCART RGB + CVBS ADC CVBS YC SD/PS YPbPr 48 CVBS ADC ADC ADC CVBS SCART G SCART B SCART R HS/VS SDP CVBS 3D YC S-VIDEO SCART FIELD/DE CLK DATA HS/VS CP YPbPr 525p/625p Pb/B 720p/1080i 1080p/ Pr/R UXGA RGB Y/G HD YPbPr GRAPHICS RGB FIELD/DE OUTPUT MUX SCART CVBS HS/VS FIELD/DE CLK 36-BIT YCbCr/RGB CLK DATA 36 HDMI 2 TMDS DDC TMDS DDC 4 I2S S/PDIF DEEP COLOR HDMI Rx DSD HBR MCLK FAST SWITCH HDCP KEYS SCLK ADV7842 AUDIO OUTPUT 5 MCLK SCLK TO AUDIO PROCESSOR 08849-001 HDMI 1 OUTPUT MUX Dual HDMI® 1.4a fast switching receiver HDMI support 3D TV support Content type bits CEC 1.4-compatible Extended colorimetry 256-ball, 17 mm × 17 mm BGA package HDMI 225 MHz receiver Xpressview fast switching of HDMI ports 3D video format support including frame packing 1080p 24 Hz, 720p 50 Hz, 720p 60 Hz Full colorimetry support including sYCC601, Adobe RGB, Adobe YCC 601 36-/30-bit Deep Color and 24-bit color support HDCP 1.4 support with internal HDCP keys Adaptive HDMI equalizer Integrated CEC controller HDMI repeater support 5 V detect and hot plug assert for each HDMI port HDMI audio support including HBR and DSD Advanced audio mute feature Flexible digital audio output interfaces Supports up to 5 S/PDIF outputs Supports up to 4 I2S outputs Video and graphics digitizer Four 170 MHz, 12-bit ADCs 12-channel analog input mux 525i-/625i-component analog input 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component HDTV support Low refresh rates (24 Hz/25 Hz/30 Hz) support for 720p/1080p Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA) SCART fast blank support 3D video decoder NTSC/PAL/SECAM color standards support NTSC/PAL 2D/3D motion detecting comb filter Advanced time-base correction (TBC) with frame synchronization Interlaced-to-progressive conversion for 525i and 625i IF compensation filters INPUT MUX FEATURES Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010-2011 Analog Devices, Inc. All rights reserved. ADV7842 TABLE OF CONTENTS Features .............................................................................................. 1 Power-Up Sequence ................................................................... 12 Applications ....................................................................................... 1 Power-Down Sequence .............................................................. 12 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions........................... 13 Revision History ............................................................................... 2 Functional Overview...................................................................... 20 General Description ......................................................................... 3 HDMI Receiver........................................................................... 20 Detailed Functional Block Diagram .............................................. 4 Analog Front End ....................................................................... 20 Specifications..................................................................................... 5 Standard Definition Processor ................................................. 21 Electrical Characteristics ............................................................. 5 Component Processor ............................................................... 21 Power Specifications .................................................................... 6 Other Features ............................................................................ 22 Analog Specifications ................................................................... 8 External Memory Requirements .................................................. 23 Video Specifications ..................................................................... 8 Single Data Rate (SDR).............................................................. 23 Timing Characteristics ................................................................ 9 Double Data Rate (DDR) .......................................................... 23 Timing Diagrams........................................................................ 10 Pixel Input/Output Formatting .................................................... 24 Absolute Maximum Ratings.......................................................... 11 Pixel Data Output Modes Features .......................................... 24 Package Thermal Performance ................................................. 11 Register Map Architecture ............................................................ 25 ESD Caution ................................................................................ 11 Outline Dimensions ....................................................................... 26 Power Supply Sequencing .............................................................. 12 Ordering Guide .......................................................................... 26 REVISION HISTORY 1/11—Rev. SpA to Rev. B Updated Revision Number ................................................ Universal Updated Publication Code ............................................................ 28 10/10—Rev. Sp0 to Rev. SpA Changes to Product Title and Features Section ............................ 1 Changes to Note 1, Table 1 ....................................................................... 5 Added Note 1, Table 5 ............................................................................... 9 Changes to Pin No. C11 Description, Table 7 .................................... 14 Changes to Pin No. N11 Description, Table 7 and Pin No. P11 Description, Table 7 ................................................................................. 18 6/10—Revision Sp0: Initial Version Rev. B | Page 2 of 28 ADV7842 GENERAL DESCRIPTION The ADV7842 is a high quality, single-chip, 2:1 multiplexed HDMI™ receiver and graphics digitizer with an integrated multiformat video decoder. The ADV7842 incorporates a dual input HDMI 1.4-compatible receiver that supports all HDTV formats up to 1080p and display resolutions up to UXGA (1600 × 1200 at 60 Hz). The ADV7842 incorporates Xpressview™ fast switching on both input HDMI ports. Using the Analog Devices, Inc., hardwarebased HDCP engine that minimizes software overhead, Xpressview technology allows fast switching between any HDMI input ports in less than 1 second. The ADV7842 supports all mandatory HDMI 1.4 3D TV formats in addition to all HDTV formats up to 1080p, 36-bit Deep Color. The multiformat 3D comb filter decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of a composite or an S-Video input signal into a digital ITU-R BT.656 format. SCART and overlay functionality are enabled by the ability of the ADV7842 to process CVBS and standard definition RGB signals simultaneously. The ADV7842 contains one main component processor (CP) that processes YPbPr and RGB component formats, including RGB graphics. The CP also processes the video signals from the HDMI receiver. The ADV7842 can operate in dual HDMI and analog input mode, thus allowing for fast switching between the ADCs and HDMI. The ADV7842 also integrates an HDMI v1.4 CEC controller that supports the capability discovery and control (CDC) feature. The ADV7842 supports the decoding of a component RGB/ YPbPr video signal into a digital YCbCr or RGB pixel output stream. The support for component video includes 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as many other SMPTE and HD standards. The ADV7842 offers a flexible audio output port for the audio data decoded from the HDMI stream. HDMI audio formats, including super audio CD (SACD) via DSD and HBR are supported. The ADV7842 supports graphics digitization. The ADV7842 is capable of digitizing RGB graphics signals from VGA to UXGA rates and converting them into a digital RGB or YCbCr pixel output stream. Internal EDID is available for one graphic port. Each HDMI port has dedicated 5 V detect and hot plug assert pins. The HDMI receiver also includes an integrated equalizer that ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has advanced audio functionality, such as a mute controller, that prevents audible extraneous noise in the audio output. Fabricated in an advanced CMOS process, the ADV7842 is provided in a 17 mm × 17 mm, 256-ball, BGA, surface-mount, RoHS-compliant package and is specified over the −10°C to +70°C temperature range. Rev. B | Page 3 of 28 Figure 2. Detailed Functional Block Diagram Rev. B | Page 4 of 28 CLAMP CLAMP CLAMP PLL EQUALIZER EQUALIZER RXA_0± RXA_1± RXA_2± RXB_0± RXB_1± RXB_2± HDCP BLOCK HDCP EEPROM SAMPLER SAMPLER EDID/ REPEATER CONTROLLER 5V DETECT AND HPA CONTROLLER CEC CONTROLLER AVLINK CONTROLLER I2C CONTROL INTERFACE TRI-LEVEL SLICER SYNC PROCESSING AND CLOCK GENERATION LLC GENERATION 12-CHANNEL INPUT MATRIX RXA_C± RXB_C± DDCA_SDA/DDCA_SC L DDCB_SDA/DDCB_SC L RXA_5V/HPA_A RXB_5V/HPA_B CEC AVLINK SCL SDA TRI1 TO TRI4 SYNC1 SYNC2 HS_IN1/TRI5 VS_IN1/TRI6 HS_IN2/TRI7 VS_IN2/TRI8 RGB YPrPb SCART RGB YC CLAMP CONTROL HS/CS, VS/FIELD 12 12 12 PACKET PROCESSOR FILTER 4:2:2 TO 4:4:4 CONVERSION DEEP COLOR CONVERSION CONTROL AND DATA ADC3 ADC2 ADC1 ADC0 FAST SWITCHING BLOCK + HDMI DECODE + MUX CVBS 12 MUX PACKET/ INFOFRAME MEMORY (A) (B) (C) (D) (C) (B) (A) INTERLACE TO PROGRESSIVE CONVERSION MACROVISION DETECTION ANCILLARY DATA FORMATTER AV CODE INSERTION FAST I2C INTERFACE AUDIO PROCESSOR INTERRUPT CONTROLLER ACTIVE PEAK AND HSYNC DEPTH OFFSET ADDER CP CSC AND DECIMATION FILTERS GAIN CONTROL NOISE AND CALIBRATION DIGITAL FINE CLAMP STANDARD IDENTIFICATION SYNC EXTRACT (ESDP) VIDEO DATA PROCESSOR READBACK I2C VSI DECODER PROGRAMMABLE DELAY MACROVISION AND CGMS DETECTION SYNC SOURCE AND POLARITY DETECT COMPONENT PROCESSOR FASTBLANK OVERLAY CONTROL COLOR SPACE CONVERSION DECIMATION FILTERS DDR/SDR-SDRAM INTERFACE STANDARD AUTODECTION DIGITAL PROCESSING BLOCK CTI AND LTI HORIZONTAL PEAKING VERTICAL PEAKING 3D COMB STANDARD DEFINITION PROCESSOR (SDP) 2D COMB TBC VIDEO OUTPUT FORMATTER AUDIO OUTPUT FORMATTER ANALOG FRONT END 12 12 12 MCLK SCLK AP2 AP3 AP4 AP5 AP0 AP1 INT1 INT2 TTX_SDA/TTX_SCL VS/FIELD FIELD/DE SYNC_OUT LLC HS/CS P24 TO P35 P12 TO P23 P0 TO P11 08849-002 AOUT ADV7842 DETAILED FUNCTIONAL BLOCK DIAGRAM ADV7842 SPECIFICATIONS AVDD = 1.8 V ± 5%, CVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%, PVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, TVDD = 3.3 V ± 5%, VDD_SDRAM = 3.2 V to 3.4 V (SDR), VDD_SDRAM = 2.35 V to 2.65 V (DDR). TMIN to TMAX = −10°C to +70°C, unless otherwise noted. ELECTRICAL CHARACTERISTICS Table 1. Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL INPUTS (5 V TOLERANT) 1 Input High Voltage Input Low Voltage Input Current DIGITAL OUTPUTS Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance 1 Symbol N INL DNL VIH VIL VIH VIL IIN Test Conditions/Comments Min 27 MHz (at a 12-bit level) 54 MHz (at a 12-bit level) 74.25 MHz (at a 12-bit level) 108 MHz (at a 11-bit level) 170 MHz (at a 9-bit level) 27 MHz (at a 12-bit level) 54 MHz (at a 12-bit level) 75 MHz (at a 12-bit level) 108 MHz (at a 11-bit level) 170 MHz (at a 9-bit level) XTALN and XTALP pins XTALN and XTALP pins Other digital inputs Other digital inputs RESET pin EP_MISO pin SPDIF_IN pin TEST4 pin TEST6 pin Other digital inputs Typ Unit 12 Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB −3.0 to +8.0 −3.0 to +8.0 −4.0 to +7.0 −3.5 to +8.0 −0.7 to +1.5 −0.7 to +0.8 −0.7 to +0.8 −0.7 to +0.8 −0.7 to +0.8 −0.6 to +0.5 1.2 0.8 ±60 ±60 ±60 ±60 ±60 ±10 10 V V V V µA µA µA µA µA µA pF 0.8 +82 V V µA 0.4 2 CIN VIH VIL IIN Max 2.6 −82 VOH VOL ILEAK COUT 2.4 0.4 10 20 V V µA pF The following pins are 5 V tolerant: HS_IN1/TRI5, HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, RXA_5V, RXB_5V, DDCA_SCL, DDCA_SDA, DDCB_SCL, and DDCB_SDA. Rev. B | Page 5 of 28 ADV7842 POWER SPECIFICATIONS Table 2. Parameter POWER REQUIREMENTS Digital Core Power Supply Digital I/O Power Supply SDRAM Power Supply PLL Power Supply Analog Power Supply Terminator Power Supply Comparator Power Supply CURRENT CONSUMPTION1, 2, 3 Digital Core Supply Current Digital I/O Supply Current Symbol Min Typ Max Unit VDD DVDDIO VDD_SDRAM VDD_SDRAM PVDD AVDD TVDD CVDD 1.75 3.14 3.2 2.35 1.71 1.71 3.14 1.71 1.8 3.3 3.3 2.5 1.8 1.8 3.3 1.8 1.85 3.46 3.4 2.65 1.89 1.89 3.46 1.89 V V V V V V V V 155 148 285 220 196 343 mA mA mA 163 216 176 273 mA mA 194 332 230 378 mA mA 57 197 72 224 mA mA 270 404 289 435 mA mA 51 41 45 109 129 117 mA mA mA 27 22 32 150 mA mA 9 10 11 11 mA mA 8 8 11 11 mA mA 10 10 11 12 mA mA IVDD IDVDDIO Rev. B | Page 6 of 28 Test Conditions/Comments SDR memory DDR memory Analog 1080p sampling at 148 MHz RGB graphics sampling at 162 MHz RGB graphics sampling at 162 MHz in simultaneous mode with both background ports enabled HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color in simultaneous mode with both background ports enabled CVBS processing CVBS processing in simultaneous mode with both background ports enabled SD 576i component processing SD 576i component processing in simultaneous mode with both background ports enabled SCART processing SCART processing in simultaneous mode with both background ports enabled Analog 1080p sampling at 148 MHz RGB graphics sampling at 162 MHz RGB graphics sampling at 162 MHz in simultaneous mode with both background ports enabled HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color in simultaneous mode with both background ports enabled CVBS processing CVBS processing in simultaneous mode with both background ports enabled SD 576i component processing SD 576i component processing in simultaneous mode with both background ports enabled SCART processing SCART processing in simultaneous mode with both background ports enabled ADV7842 Parameter PLL Supply Current Analog Supply Current Symbol IPVDD IAVDD Terminator Supply Current4 ITVDD Comparator Supply Current ICVDD Memory Interface Supply Current Power-Down Currents5 IVDD_SDRAM Power-Up Time IDVDDIO IVDD_SDRAM IVDD IAVDD ICVDD ITVDD IPVDD tPWRUP Min Typ Max Unit Test Conditions/Comments 28 25 25 30 27 28 mA mA mA 35 35 36 38 mA mA 34 35 37 37 mA mA 22 22 24 24 mA mA 34 35 37 37 mA mA 279 281 285 295 297 301 mA mA mA 0.1 0.1 0.3 0.3 mA mA 85 86 89 91 mA mA 267 270 281 285 mA mA 283 286 294 301 mA 85 120 120 220 95 135 130 250 mA mA mA mA 28 35 mA Analog 1080p sampling at 148 MHz RGB graphics sampling at 162 MHz RGB graphics sampling at 162 MHz in simultaneous mode with both background ports enabled HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color in simultaneous mode with both background ports enabled CVBS processing CVBS processing in simultaneous mode with both background ports enabled SD 576i component processing SD 576i component processing in simultaneous mode with both background ports enabled SCART processing SCART processing in simultaneous mode with both background ports enabled Analog 1080p sampling at 148 MHz RGB graphics sampling at 162 MHz RGB graphics sampling at 162 MHz in simultaneous mode with both background ports enabled HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color in simultaneous mode with both background ports enabled CVBS processing CVBS processing in simultaneous mode with both background ports enabled SD 576i component processing SD 576i component processing in simultaneous mode with both background ports enabled SCART processing SCART processing in simultaneous mode with both background ports enabled One port connected Two ports connected HDMI 1080p: 12-bit Deep Color HDMI 1080p: 12-bit Deep Color in simultaneous mode with both background ports enabled CVBS input sampling at 54 MHz 0.1 2.6 10 0.1 0.5 1.1 1.7 mA mA mA mA mA mA mA ms 25 All maximum current values are guaranteed by characterization to assist in power supply design. Typical current consumption values are recorded with nominal voltage supply levels, SMPTE bar video pattern, and at room temperature. 3 Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature. 4 Termination power supply includes TVDD current consumed off chip. 5 Power-down mode entered by setting Bit POWER_DOWN high. 1 2 Rev. B | Page 7 of 28 ADV7842 ANALOG SPECIFICATIONS Table 3. Parameter CLAMP CIRCUITRY1 Input Impedance Analog (AIN1 − AIN12) ADC Midscale (CML) ADC Full-Scale Level ADC Zero-Scale Level ADC Dynamic Range Clamp Level (When Locked) Test Conditions/Comments Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current 1 Min Typ Max Unit Clamps switched off 10 MΩ Component input, Y signal Component input, Pr signal Component input, Pb signal PC RGB input (R, G, B signals) CVBS input SCART RGB input (R, G, B signals) S-Video input (Y Signal) S-Video input (C Signal) SDP only SDP only SDP only SDP only 0.91 CML + 0.55 CML − 0.55 1.1 CML − 0.12 CML CML CML − 0.12 CML − 0.205 CML − 0.205 CML − 0.205 CML 0.3 0.4 9 8 V V V V V V V V V V V V mA mA μA μA Specified for external clamp capacitor of 100 nF. VIDEO SPECIFICATIONS Table 4. Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted SNR Unweighted Analog Front-End Crosstalk LOCK TIME SPECIFICATIONS (SDP) Horizontal Lock Range Vertical Lock Range Subcarrier Lock Range Color Lock-In Time Sync Depth Range1 Color Burst Range Vertical Lock Time Horizontal Lock Time CHROMA SPECIFICATIONS (SDP) Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation 1 Symbol Test Conditions/Comments DP DG LNL CVBS input (modulated five-step) CVBS input (modulated five-step) CVBS input (modulated five-step) Measured at 27 MHz LLC Luma ramp Luma flat field Min Typ Max 0.6 0.8 0.9 Degrees % % 63 64 60 dB dB dB ±5 300 100 % Hz kHz Lines % % ms Lines 0.9 0.3 0.3 % Degrees % 40 fSC 70 ±0.8 60 20 1 Nominal synchronization depth is 300 mV at 100% of the synchronization depth range. Rev. B | Page 8 of 28 Unit 200 200 ADV7842 TIMING CHARACTERISTICS Data and I2C Timing Characteristic Table 5. Parameter1 CLOCK AND CRYSTAL Crystal Frequency, XTAL Crystal Frequency Stability Horizontal Sync Input Frequency LLC Frequency Range I2C PORTS SCL Frequency SCL Minimum Pulse Width High SCL Minimum Pulse Width Low Start Condition Hold Time Start Condition Setup Time SDA Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Stop Condition Setup Time TTX I2C PORTS SCL Frequency SCL Minimum Pulse Width High SCL Minimum Pulse Width Low Start Condition Hold Time Start Condition Setup Time SDA Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Stop Condition Setup Time RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC Mark-Space Ratio Symbol Test Conditions/Comments Min Typ Max Unit ±50 110 170 MHz ppm kHz MHz 28.63636 10 12.825 400 t1 t2 t3 t4 t5 t6 t7 t8 600 1.3 600 600 100 t1 t2 t3 t4 t5 t6 t7 t8 60 160 160 160 10 10 10 160 1000 300 0.6 3.4 80 80 5 t9:t10 kHz ns µs ns ns ns ns ns µs MHz ns ns ns ns ns ns ns ns ms 45:55 55:45 % duty cycle 4.6 0.6 2.2 0.3 ns ns ns ns 55:45 10 10 5 5 % duty cycle ns ns ns ns DATA AND CONTROL OUTPUTS2 Data Output Transition Time SDR (SDP) Data Output Transition Time SDR (SDP) Data Output Transition Time SDR (CP) Data Output Transition Time SDR (CP) I2S PORT, MASTER MODE SCLK Mark-Space Ratio LRCLK Data Transition Time LRCLK Data Transition Time I2Sx Data Transition Time I2Sx Data Transition Time 1 2 t11 t12 t13 t14 End of valid data to negative clock edge Negative clock edge to start of valid data End of valid data to negative clock edge Negative clock edge to start of valid data t15:t16 t17 t18 t19 t20 End of valid data to negative SCLK edge Negative SCLK edge to start of valid data End of valid data to negative SCLK edge Negative SCLK edge to start of valid data 2.9 0.2 1.5 0.1 45:55 Guaranteed by characterization. With the DLL block on output clock bypassed. Rev. B | Page 9 of 28 ADV7842 TIMING DIAGRAMS t5 t3 t3 SDA t6 t1 t2 t4 t7 08849-003 SCL t8 Figure 3. I2C Timing t10 t9 LLC t11 08849-004 t12 P0 TO P35, HS/CS, VS/FIELD, FIELD/DE Figure 4. Pixel Port and Control SDR Output Timing (SDP) t9 t10 LLC t13 08849-005 t14 P0 TO P35, VS/FIELD, HS/CS, FIELD/DE Figure 5. Pixel Port and Control SDR Output Timing (CP) t15 SCLK t16 t17 LRCLK t18 t19 MSB MSB – 1 t20 I2Sx I2S MODE I2Sx RIGHT-JUSTIFIED MODE t19 MSB MSB – 1 t20 t19 MSB NOTES 1. THE SUFFIX x REFERS TO 0, 1, 2, AND 3 ENDING PIN NAMES. 2. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN. 3. I2Sx ARE SIGNALS ACCESSIBLE VIA AP1 TO AP4 PINS. Figure 6. I2S Timing Rev. B | Page 10 of 28 LSB t20 08849-006 I2Sx LEFT-JUSTIFIED MODE ADV7842 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to GND VDD to GND PVDD to GND DVDDIO to GND VDD_SDRAM to GND CVDD to GND TVDD to GND AVDD to PVDD AVDD to VDD TVDD to CVDD DVDDIO to VDD_SDRAM VDD_SDRAM to AVDD VDD_SDRAM to VDD Digital Inputs Voltage to GND Digital Outputs Voltage to GND 5 V Tolerant Digital Inputs to GND1 Analog Inputs to GND XTALN and XTALP to GND Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) 1 Rating 2.2 V 2.2 V 2.2 V 4.0 V 4.0 V 2.2 V 4.0 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +2.2 V −0.3 V to +3.3 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to DVDDIO + 0.3 V −0.3 V to DVDDIO + 0.3 V 5.5 V −0.3 V to AVDD + 0.3 V −0.3 V to PVDD + 0.3 V 125°C −65°C to +150°C 260°C The following inputs are 3.3 V inputs but are 5 V tolerant: HS_IN1/TRI5, HS_IN2/TRI7, VS_IN1/TRI6, VS_IN2/TRI8, DDCA_SCL, DDCA_SDA, DDCB_SCL and DDCB_SDA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL PERFORMANCE To reduce power consumption when using the ADV7842, the user is advised to turn off unused sections of the part. Due to PCB metal variation, and therefore variation in PCB heat conductivity, the value of θJA may differ for various PCBs. The most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the JA θvalue. The maximum junction temperature (TJ MAX) of 125°C must not be exceeded. The following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test (DUT): ( TJ = TS + Ψ JT × WTOTAL ) where: TS is the package surface temperature (°C). ΨJT = 0.5°C/W for the 256-ball BGA. WTOTAL = (PVDD × IPVDD) + (0.4 × TVDD × ITVDD) + (CVDD × ICVDD) + (AVDD × IAVDD) + (VDD × IVDD) + (A × DVDDIO × IDVDDIO) + (VDD_SDRAM × IVDD_SDRAM) where: 0.4 reflects the 40% of TVDD power that is dissipated on the part itself. A = 0.5 when the output pixel clock is >74 MHz. A = 0.75 when the output pixel clock is ≤74 MHz. ESD CAUTION Rev. B | Page 11 of 28 ADV7842 POWER SUPPLY SEQUENCING Notes POWER-UP SEQUENCE The recommended power-up sequence of the ADV7842 is as follows: 3.3 V supplies 2.5 V supply (applies only if using DDR memory) 1.8 V supplies 2.5V POWER SUPPLY (V) • In this case, care must be taken to ensure that a lower rated supply does not go above a higher rated supply level, because the supplies are being established. 2.5V SUPPLIES (IF ANY) 1.8V SUPPLIES 1.8V 3.3 V supplies should be powered up first. 2.5 V supply should be powered after the 3.3 V supplies are established but before the 1.8 V supplies. 1.8 V supplies should be powered up last. The ADV7842 can alternatively be powered up by simultaneously asserting all supplies. 3.3V SUPPLIES 3.3V • • POWER-DOWN SEQUENCE The ADV7842 supplies can be deasserted simultaneously as long as a higher rated supply does not go below a lower rated supply. 3.3V SUPPLIES POWER-UP 2.5V SUPPLIES 1.8V SUPPLIES POWER-UP POWER-UP 08849-009 1. 2. 3. Reset should be held low while the supplies are being powered up. Figure 7. Recommended Power-Up Sequence Rev. B | Page 12 of 28 ADV7842 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A GND P3 P1 P0 TVDD RXB_2– RXB_1– RXB_0– RXB_C– GND RXA_2– RXA_1– RXA_0– RXA_C– TVDD GND A B P5 P4 P2 SYNC_OUT TVDD RXB_2+ RXB_1+ RXB_0+ RXB_C+ GND RXA_2+ RXA_1+ RXA_0+ RXA_C+ TVDD XTALP B C P7 P6 VS/FIELD HS/CS GND HPA_B HPA_A RXB_5V RXA_5V PWRDN1 TEST8 CVDD CVDD CVDD GND XTALN C D P9 P8 EP_MISO FIELD/DE GND CEC DDCB_SD A DDCB_SC L DDCA_SD A DDCA_SC L RTERM CVDD VGA_SCL VGA_SDA PVDD PVDD D E GND P10 EP_CS EP_MOSI GND GND GND GND GND GND CVDD CVDD HS_IN2/TRI7 VS_IN2/TRI8 REFP REFN E F P12 P11 EP_SCK TTX_SCL DVDDIO GND GND GND GND GND GND AVDD AIN12 AIN11 TRI4 TRI3 F G P14 P13 TTX_SDA MCLK DVDDIO GND GND GND GND GND GND AVDD AIN10 SYNC4 AIN9 AIN8 G H P16 P15 AP0 AP5 DVDDIO GND GND GND GND GND GND AVDD TRI1 TRI2 AIN7 SYNC3 H J P18 P17 SCLK AP4 DVDDIO GND VDD GND GND GND GND AVDD AIN6 AIN4 SYNC2 GND J K P20 P19 AP3 AP1 DVDDIO VDD VDD VDD VDD GND GND AVDD AIN5 VS_IN1/TRI6 AIN2 AIN3 K L P22 P21 SCL AP2 DVDDIO VDD VDD VDD VDD GND GND AVDD AOUT HS_IN1/TRI5 AIN1 SYNC1 L M GND P23 SDA INT1 DVDDIO VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM GND GND GND GND GND GND M N LLC P24 INT2 TEST4 RESET TEST6 SDRAM_LDQS SDRAM_DQ4 SDRAM_DQ15 SDRAM_DQ11 SDRAM_CK SDRAM_CKE N P P25 P26 TEST5 AVLINK TEST7 SDRAM_A11 SDRAM_A7 SDRAM_A3 SDRAM_A10 SDRAM_RAS SDRAM_DQ7 SDRAM_DQ3 SDRAM_VREF SDRAM_DQ12 SDRAM_UDQS SDRAM_CK P R P27 P28 P30 P32 P34 SDRAM_A9 SDRAM_A6 SDRAM_A2 SDRAM_BA1 SDRAM_CAS SDRAM_DQ6 SDRAM_DQ2 SDRAM_DQ0 SDRAM_DQ13 SDRAM_DQ8 R T GND P29 P31 P33 P35 GND SDRAM_A5 SDRAM_A1 SDRAM_BA0 SDRAM_WE SDRAM_DQ5 GND SDRAM_DQ1 SDRAM_DQ14 SDRAM_DQ10 GND T 1 2 3 4 5 6 11 12 13 SDRAM_A8 SDRAM_A4 SDRAM_A0 SDRAM_CS 7 8 9 10 Figure 8. Pin Configuration (Top View) Rev. B | Page 13 of 28 14 SDRAM_DQ9 15 16 08849-007 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADV7842 Table 7. Pin Function Descriptions Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 Mnemonic GND P3 P1 P0 TVDD RXB_2− RXB_1− RXB_0− RXB_C− GND RXA_2− RXA_1− RXA_0− RXA_C− TVDD GND P5 P4 P2 SYNC_OUT TVDD RXB_2+ RXB_1+ RXB_0+ RXB_C+ GND RXA_2+ RXA_1+ RXA_0+ RXA_C+ TVDD XTALP Type Ground Digital video output Digital video output Digital video output Power HDMI input HDMI input HDMI input HDMI input Ground HDMI input HDMI input HDMI input HDMI input Power Ground Digital video output Digital video output Digital video output Miscellaneous digital Power HDMI input HDMI input HDMI input HDMI input Ground HDMI input HDMI input HDMI input HDMI input Power Miscellaneous analog C1 C2 C3 P7 P6 VS/FIELD Digital video output Digital video output Digital video output C4 HS/CS Digital video output C5 C6 C7 C8 C9 C10 GND HPA_B HPA_A RXB_5V RXA_5V PWRDN1 Ground Miscellaneous digital Miscellaneous digital HDMI input HDMI input Miscellaneous digital C11 C12 C13 C14 TEST8 CVDD CVDD CVDD Test pin Power Power Power Description Ground. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port B in the HDMI Interface. Digital Input Channel 1 Complement of Port B in the HDMI Interface. Digital Input Channel 0 Complement of Port B in the HDMI Interface. Digital Input Clock Complement of Port B in the HDMI Interface. Ground. Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Clock Complement of Port A in the HDMI Interface. Terminator Supply Voltage (3.3 V). Ground. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Sliced Synchronization Output Terminator Supply Voltage (3.3 V). Digital Input Channel 2 True of Port B in the HDMI Interface. Digital Input Channel 1 True of Port B in the HDMI Interface. Digital Input Channel 0 True of Port B in the HDMI Interface. Digital Input Clock True of Port B in the HDMI Interface. Ground. Digital Input Channel 2 True of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Terminator Supply Voltage (3.3 V). Input pin for 28.63636 MHz crystal or external 1.8V, 28.63636 MHz Clock Oscillator Source to Clock the ADV7842. Video Pixel Output Port. Video Pixel Output Port. Vertical Synchronization/Field Synchronization. VS is a vertical synchronization output signal in the CP and HDMI processor. FIELD is a field synchronization output signal in all interlaced video modes. VS or FIELD can be configured for this pin. Horizontal Synchronization/Composite Synchronization. HS is a horizontal synchronization output signal in the CP and HDMI processor. CS (composite synchronization) signal is a single signal containing both horizontal and vertical synchronization pulses. HS or CS can be configured for this pin. Ground. Hot Plug Assert Signal Output for HDMI Port B. Hot Plug Assert Signal Output for HDMI Port A. 5 V Detect Pin for Port B in the HDMI Interface. 5 V Detect Pin for Port A in the HDMI Interface. Controls the Power-Up of the ADV7842. Should be connected to a digital 3.3 V I/O supply to power up the ADV7842. Tie this pin to ground via 4.7 kΩ resistor. Comparator Supply Voltage (1.8 V). Comparator Supply Voltage (1.8 V). Comparator Supply Voltage (1.8 V). Rev. B | Page 14 of 28 ADV7842 Pin No. C15 C16 D1 D2 D3 D4 Mnemonic GND XTALN P9 P8 EP_MISO FIELD/DE Type Ground Miscellaneous analog Digital video output Digital video output Digital input Miscellaneous digital D5 D6 D7 D8 D9 D10 D11 GND CEC DDCB_SDA DDCB_SCL DDCA_SDA DDCA_SCL RTERM Ground Digital input/output Digital input/output Digital input Digital input/output Digital input Miscellaneous analog D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 CVDD VGA_SCL VGA_SDA PVDD PVDD GND P10 EP_CS EP_MOSI GND GND GND GND GND GND CVDD CVDD HS_IN2/TRI7 Power Miscellaneous digital Miscellaneous digital Power Power Ground Digital video output Digital output Digital output Ground Ground Ground Ground Ground Ground Power Power Miscellaneous analog E14 VS_IN2/TRI8 Miscellaneous analog E15 E16 F1 F2 F3 F4 REFP REFN P12 P11 EP_SCK TTX_SCL Miscellaneous analog Miscellaneous analog Digital video output Digital video output Digital output Miscellaneous digital F5 F6 F7 F8 F9 F10 F11 F12 DVDDIO GND GND GND GND GND GND AVDD Power Ground Ground Ground Ground Ground Ground Power Description Ground. Input Pin for 28.63636 MHz Crystal. Video Pixel Output Port. Video Pixel Output Port. SPI Master In/Slave Out for External EDID Interface. Data Enable (DE). DE is a signal that indicates active pixel data. Field Synchronization Output Signal in All Interlaced Video Modes (FIELD). DE or FIELD can be configured for this pin. Ground. Consumer Electronic Control Channel. HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant. HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant. HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. Sets Internal Termination Resistance. A 500 Ω resistor between this pin and GND should be used. Comparator Supply Voltage (1.8 V). DDC Port Serial Clock Input for VGA DDC Port Serial Data Input/Output for VGA PLL Supply Voltage (1.8 V). PLL Supply Voltage (1.8 V). Ground. Video Pixel Output Port. SPI Chip Select for External EDID Interface. SPI Master Out/Slave In for External EDID Interface. Ground. Ground. Ground. Ground. Ground. Ground. Comparator Supply Voltage (1.8 V). Comparator Supply Voltage (1.8 V). HS on Graphics Port 2 (HS_IN2). The HS input signal is used for 5-wire timing mode. Trilevel/Bilevel Input on the SCART or D-terminal Connector (TRI7). (Selection available via the I2C.) VS on Graphics Port 2 (VS_IN2). The VS input signal is used for 5-wire timing mode. Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI8). (Selection available via the I2C.) Internal Voltage Reference Output. Internal Voltage Reference Output. Video Pixel Output Port. Video Pixel Output Port. SPI Clock for External EDID Interface. Fast I2C Interface for Teletext Data Extraction. TTX_SCL is used as the I2C port serial clock input. Digital I/O Supply Voltage (3.3 V). Ground. Ground. Ground. Ground. Ground. Ground. Analog Supply Voltage (1.8 V). Rev. B | Page 15 of 28 ADV7842 Pin No. F13 F14 F15 Mnemonic AIN12 AIN11 TRI4 Type Analog video input Analog video input Miscellaneous analog F16 TRI3 Miscellaneous analog G1 G2 G3 P14 P13 TTX_SDA Digital video output Digital video output Miscellaneous digital G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 MCLK DVDDIO GND GND GND GND GND GND AVDD AIN10 SYNC4 Miscellaneous Power Ground Ground Ground Ground Ground Ground Power Analog video input Miscellaneous analog G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 AIN9 AIN8 P16 P15 AP0 AP5 DVDDIO GND GND GND GND GND GND AVDD TRI1 TRI2 AIN7 SYNC3 Analog video input Analog video input Digital video output Digital video output Miscellaneous Miscellaneous Power Ground Ground Ground Ground Ground Ground Power Miscellaneous analog Miscellaneous analog Analog video input Miscellaneous analog J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 P18 P17 SCLK AP4 DVDDIO GND VDD GND GND GND GND AVDD AIN6 Digital video output Digital video output Miscellaneous digital Miscellaneous Power Ground Power Ground Ground Ground Ground Power Analog video input Description Analog Video Input Channel. Analog Video Input Channel. Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via the I2C.) Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via the I2C.) Video Pixel Output Port. Video Pixel Output Port. Fast I2C Interface for Teletext Data Extraction. TTX_SDA is used as the I2C port serial data input/output pins. Audio Master Clock Output. Digital I/O Supply Voltage (3.3 V). Ground. Ground. Ground. Ground. Ground. Ground. Analog Supply Voltage (1.8 V). Analog Video Input Channel. This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. User configurable. Analog Video Input Channel. Analog Video Input Channel. Video Pixel Output Port. Video Pixel Output Port. Audio Output Pin. Audio Output Pin. Digital I/O Supply Voltage (3.3 V). Ground. Ground. Ground. Ground. Ground. Ground. Analog Supply Voltage (1.8 V). Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via I2C.) Trilevel or Bilevel Input on the SCART or D-Type Connector. (Selection available via I2C.) Analog Video Input Channel. This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. User configurable. Video Pixel Output Port. Video Pixel Output Port. Audio Serial Clock Output. Audio Output Pin. Digital I/O Supply Voltage (3.3 V). Ground. Digital Core Supply Voltage (1.8 V). Ground. Ground. Ground. Ground. Analog Supply Voltage (1.8 V). Analog Video Input Channel. Rev. B | Page 16 of 28 ADV7842 Pin No. J14 J15 Mnemonic AIN4 SYNC2 Type Analog video input Miscellaneous analog J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 GND P20 P19 AP3 AP1 DVDDIO VDD VDD VDD VDD GND GND AVDD AIN5 VS_IN1/TRI6 Ground Digital video output Digital video output Miscellaneous Miscellaneous Power Power Power Power Power Ground Ground Power Analog video input Miscellaneous analog K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 AIN2 AIN3 P22 P21 SCL AP2 DVDDIO VDD VDD VDD VDD GND GND AVDD AOUT L14 HS_IN1/TRI5 Analog video input Analog video input Digital video output Digital video output Miscellaneous digital Miscellaneous Power Power Power Power Power Ground Ground Power Analog monitor output Miscellaneous analog L15 L16 AIN1 SYNC1 Analog video input Miscellaneous analog M1 M2 M3 M4 GND P23 SDA INT1 Ground Digital video output Miscellaneous digital Miscellaneous digital M5 M6 M7 M8 M9 M10 M11 DVDDIO VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM VDD_SDRAM GND Power Power Power Power Power Power Ground Description Analog Video Input Channel. This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. User configurable. Ground. Video Pixel Output Port. Video Pixel Output Port. Audio Output Pin. Audio Output Pin. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Ground. Ground. Analog Supply Voltage (1.8 V). Analog Video Input Channel. VS on Graphics Port 1 (VS_IN1). The VS input signal is used for 5-wire timing mode. Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI6). (Selection available via the I2C.) Analog Video Input Channel. Analog Video Input Channel. Video Pixel Output Port. Video Pixel Output Port. I2C Port Serial Clock Input. SCL is the clock line for the control port. Audio Output Pin. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Digital Core Supply Voltage (1.8 V). Ground. Ground. Analog Supply Voltage (1.8 V). Analog Monitor Output. HS on Graphics Port 1 (HS_IN1). The HS input signal is used for 5-wire timing mode. Trilevel/Bilevel Input on the SCART or D-Terminal Connector (TRI5). (Selection available via the I2C.) Analog Video Input Channel. This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode. User configurable. Ground. Video Pixel Output Port. I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. Interrupt. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. Digital I/O Supply Voltage (3.3 V). External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). External Memory Interface Digital Input/Output Supply (DDR 2.5 V or SDR 3.3 V). Ground. Rev. B | Page 17 of 28 ADV7842 Pin No. M12 M13 M14 M15 M16 N1 N2 N3 Mnemonic GND GND GND GND GND LLC P24 INT2 Type Ground Ground Ground Ground Ground Digital video output Digital video output Miscellaneous digital N4 N5 TEST4 RESET Test Miscellaneous digital N6 N7 N8 N9 N10 TEST6 SDRAM_A8 SDRAM_A4 SDRAM_A0 SDRAM_CS Test SDRAM interface SDRAM interface SDRAM interface SDRAM interface N11 SDRAM_LDQS SDRAM interface N12 N13 N14 N15 SDRAM_DQ4 SDRAM_DQ15 SDRAM_DQ11 SDRAM_CK SDRAM interface SDRAM interface SDRAM interface SDRAM interface N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 SDRAM_CKE P25 P26 TEST5 AVLINK TEST7 SDRAM_A11 SDRAM_A7 SDRAM_A3 SDRAM_A10 SDRAM_RAS SDRAM interface Digital video output Digital video output Test Digital input/output Test SDRAM interface SDRAM interface SDRAM interface SDRAM interface SDRAM interface P11 P12 P13 P14 P15 SDRAM_DQ7 SDRAM_DQ3 SDRAM_VREF SDRAM_DQ12 SDRAM_UDQS SDRAM interface SDRAM interface SDRAM interface SDRAM interface SDRAM interface P16 SDRAM_CK SDRAM interface R1 R2 R3 R4 P27 P28 P30 P32 Digital video output Digital video output Digital video output Digital video output Description Ground. Ground. Ground. Ground. Ground. Line-Locked Output Clock for the Pixel Data. Video Pixel Output Port. Interrupt. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user control. Connect this pin to ground. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7842 circuitry. Float this pin. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Chip Select. SDRAM_CS enables and disables the command decoder on the RAM. One of four command signals to the external SDRAM. Lower Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an input when reading data from external memory and an output when writing data to external memory. It is edge aligned with data when reading from external memory and centered with data when writing to external memory. SDRAM_LDQS corresponds to the data on SDRAM_DQ7 to SDRAM_DQ0. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Differential Clock Output. All address and control output signals to the RAM should be sampled on the positive edge of SDRAM_CK and on the negative edge of SDRAM_CK. Clock Enable. This pin acts as an enable to the clock signals of the external RAM. Video Pixel Output Port. Video Pixel Output Port. Connect this pin to ground. Digital SCART Control Channel. Float this pin. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Row Address Select Command Signal. One of four command signals to the external SDRAM. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. 1.25 V Reference for DDR SDRAM Interface or 1.65 V for SDR SDRAM Interface. Data Bus. Interface to external RAM 16-bit data bus. Upper Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an input when reading data from external memory and an output when writing data to external memory. It is edge aligned with data when reading from external memory and centered with data when writing to external memory. SDRAM_UDQS corresponds to the data on SDRAM_DQ15 to SDRAM_DQ8. Differential Clock Output. All address and control output signals to the RAM should be sampled on the positive edge of SDRAM_CK and on the negative edge of SDRAM_CK. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Rev. B | Page 18 of 28 ADV7842 Pin No. R5 R6 R7 R8 R9 R10 Mnemonic P34 SDRAM_A9 SDRAM_A6 SDRAM_A2 SDRAM_BA1 SDRAM_CAS Type Digital video output SDRAM interface SDRAM interface SDRAM interface SDRAM interface SDRAM interface R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 SDRAM_DQ6 SDRAM_DQ2 SDRAM_DQ0 SDRAM_DQ13 SDRAM_DQ9 SDRAM_DQ8 GND P29 P31 P33 P35 GND SDRAM_A5 SDRAM_A1 SDRAM_BA0 SDRAM_WE SDRAM interface SDRAM interface SDRAM interface SDRAM interface SDRAM interface SDRAM interface Ground Digital video output Digital video output Digital video output Digital video output Ground SDRAM interface SDRAM interface SDRAM interface SDRAM interface T11 T12 T13 T14 T15 T16 SDRAM_DQ5 GND SDRAM_DQ1 SDRAM_DQ14 SDRAM_DQ10 GND SDRAM interface Ground SDRAM interface SDRAM interface SDRAM interface Ground Description Video Pixel Output Port. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Bank Address Output. Interface to external RAM bank address lines. Column Address Select Command Signal. One of four command signals to the external SDRAM. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Ground. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Ground. Address Output. Interface to external RAM address lines. Address Output. Interface to external RAM address lines. Bank Address Output. Interface to external RAM bank address lines. Write Enable Output Command Signal. One of four command signals to the external SDRAM. Data Bus. Interface to external RAM 16-bit data bus. Ground. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Data Bus. Interface to external RAM 16-bit data bus. Ground. Rev. B | Page 19 of 28 ADV7842 FUNCTIONAL OVERVIEW HDMI RECEIVER ANALOG FRONT END The ADV7842 front end incorporates a 2:1 multiplexed HDMI 1.4 receiver with Xpressview fast switching technology and support for HDMI 1.4 features such as 3D TV. Building on the feature set of Analog Device existing HDMI devices, the ADV7842 also offers support for all HD TV formats up to 12-bit, 1080p Deep Color and all display resolutions up to UXGA (1600 × 1200 at 60 Hz). Xpressview fast switching technology, using Analog Devices hardware-based HDCP engine that minimizes software overhead, allows switching between the two input ports in less than 1 second. The ADV7842 analog front end comprises four 170 MHz, 12-bit ADCs that digitize the analog video signal before applying it to the standard definition processor (SDP) or component processor (CP). The analog front end uses differential channels to each ADC to ensure high performance in a mixed-signal application. The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7842 without the requirement of an external mux. With the inclusion of HDCP 1.4, the ADV7842 can receive encrypted video content. The HDMI interface of the ADV7842 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewal of that authentication during transmission, as specified by the HDCP 1.4 protocol. Repeater support is also offered by the ADV7842. The HDMI receiver incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. It is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance at even the highest HDMI data rates. The HDMI receiver offers advanced audio functionality. It supports multichannel I2S audio for up to eight channels. It also supports a 6-DSD channel interface with each channel carrying an over-sampled 1-bit representation of the audio signal as delivered on SACD. The ADV7842 can also receive HBR audio packet streams and outputs them through the HBR interface in an SPDIF format conforming to the IEC60958 standard. The receiver contains an audio mute controller that can detect a variety of conditions that may result in audible extraneous noise in the audio output. On detection of these conditions, the audio signal can be ramped to mute to prevent audio clicks or pops. HDMI receiver features include: • • • • • • • • • • • • Current and voltage clamp control loops ensure that any DC offsets are removed from the video signal. The clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. The ADCs are configured to run up to 8× oversampling mode when decoding composite or S-Video inputs. For component 525i, 625i, 525p, and 625p sources, 4× oversampling is performed. All other video standards are 1× oversampled. Oversampling the video signals reduces the cost and complexity of external antialiasing filters with the benefit of an increased signal-tonoise ratio (SNR). Optional internal antialiasing filters with programmable bandwidth are positioned in front of each ADC. These filters can be used to band limit video signals, removing spurious, outof-band noise. The ADV7842 can support the simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed with the output under the control of I2C registers. Analog front-end features include: • • • 2:1 multiplexed HDMI receiver HDMI 1.4, 3D format support, DVI 1.0 225 MHz HDMI receiver Integrated equalizer High-bandwidth Digital Content Protection (HDCP 1.4) also on background ports Internal HDCP keys 36-/30-bit Deep Color support PCM, HBR, DSD audio packet support Repeater support Internal E-EDID RAM Hot plug assert output pin for each HDMI port CEC controller • • • Rev. B | Page 20 of 28 Four 170 MHz, NSV, 12-bit ADCs that enable true 12-bit video decoding 12-channel analog input mux that enables multiple source connections without the requirement of an external mux Four current and voltage clamp control loops that ensure any dc offsets are removed from the video signal SCART functionality and SD RGB overlay on CVBS controlled by fast blank input SCART source switching detection through TRI1-TRI8 input Four programmable antialiasing filters ADV7842 STANDARD DEFINITION PROCESSOR The SDP is capable of decoding a large selection of baseband video signals in composite and S-Video formats. The video standards supported by the SDP include PAL, PAL 60, PAL M, PAL N, PAL NC, NTSC M/J, NTSC 4.43, and SECAM. The ADV7842 can automatically detect the video standard and process it accordingly. The SDP has a 3D temporal comb filter and a five-line adaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality with no user intervention required. The SDP has an IF filter block that compensates for attenuation in the high frequency chroma spectrum due to a tuner SAW filter. The SDP has specific luminance and chrominance parameter controls for brightness, contrast, saturation, and hue. The ADV7842 implements a patented Adaptive Digital Line Length Tracking (ADLLT™) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7842 to track and decode poor quality video sources (such as VCRs) and noisy sources (such as tuner outputs, VCR players, and camcorders). Frame TBC ensures stable clock synchronization between the decoder and the downstream devices. The SDP also contains both a luma transient improvement (LTI) block and a chroma transient improvement (CTI) block. These increase the edge rate on the luma and chroma transitions, resulting in a sharper video image. The SDP has a Macrovision® detection circuit that allows Type I, Type II, and Type III Macrovision protection levels. The decoder is also fully robust to all Macrovision signal inputs. Advanced adaptive 3D comb (using either external DDR or SDR SDRAM memory) Adaptive 2D five-line comb filters for NTSC and PAL that give superior chrominance and luminance separation for composite video Full automatic detection and autoswitching of all worldwide standards (PAL, NTSC, and SECAM) Automatic gain control with white peak mode that ensures the video is always processed without loss of the video processing range Proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners IF filter block that compensates for high frequency luma attenuation due to tuner SAW filter LTI and CTI Vertical and horizontal programmable luma peaking filters 8× oversampling (108 MHz) for CVBS, and S-Video modes Line-locked clock (LLC) output Free run output mode that provides stable timing when no video input is present or video lock is lost Internal color bar test pattern Advanced TBC with frame synchronization, which ensures nominal clock and data for nonstandard input Interlace-to-progressive conversion for 525i and 625i formats, enabling direct drive of HDMI Tx devices Color controls that include hue, brightness, saturation, and contrast COMPONENT PROCESSOR The CP section of the ADV7842 is capable of decoding and digitizing a wide range of component video formats in any color space. Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and other standards. The any-to-any, 3 × 3 CSC matrix is placed between the analog front end and the CP section. This enables YPbPr to RGB and RGB to YCbCr conversions. Many other standards of color space can be implemented using the color space converter. The CP section contains circuitry to enable the detection of Macrovision encoded YPbPr signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals. VBI extraction of CGMS data is performed by the CP section of the ADV7842 for interlaced, progressive, and high definition scanning rates. The data extracted can be read back over the I2C interface. CP features include: SDP features include: Rev. B | Page 21 of 28 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats are supported Supports 720p 24 Hz/25 Hz formats Manual adjustments, including gain (contrast), offset (brightness), hue, and saturation Support for analog component YPbPr and RGB video formats with embedded synchronization, composite synchronization or separate HS and VS Any-to-any, 3 × 3 CSC matrix that supports YCbCr-toRGB and RGB-to-YCbCr, fully programmable or preprogrammable configurations Synchronization source polarity detector (SSPD) that determines the source and polarity of the synchronization signals that accompany the input video Macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) Free-run output mode that provides stable timing when no video input is present or video lock is lost Arbitrary pixel sampling support for nonstandard video sources 170 MHz conversion rate, which supports RGB input resolutions up to 1600 × 1200 at 60 Hz Standard identification enabled by STDI block RGB that can be color space converted to YCbCr and decimated to a 4:2:2 format for video-centric back-end IC interfacing ADV7842 Data enable (DE) output signal supplied for direct connection to HDMI/DVI Tx IC 32-phase DLL that allows optimum pixel clock sampling Automatic detection of synchronization source and polarity by SSPD block Contrast, brightness, hue, and saturation controls Automatic or manual clamp-and-gain controls for graphics modes OTHER FEATURES The ADV7842 has HS, VS, FIELD, and DE output signals with programmable position, polarity, and width, and two I2C host port interfaces (control and VBI). The ADV7842 has two programmable interrupt request output pins, INT1 and INT2. It also features a number of low power modes and a full powerdown mode. The ADV7842 is provided in a 17 mm × 17 mm, RoHS-compliant BGA package, and is specified over the −10°C to +70°C temperature range. For more detailed product information about the ADV7842, contact your local Analog Devices sales office. Rev. B | Page 22 of 28 ADV7842 EXTERNAL MEMORY REQUIREMENTS The ADV7842 uses external SDRAM for 3D comb and frame synchronizer. The ADV7842 supports either SDR or DDR SD RAM. SINGLE DATA RATE (SDR) The ADV7842 can use SDR external memory to provide 3D comb or frame synchronizer operation nonconcurrently. There is a 64 Mb SDR SDRAM minimum memory requirement. The required memory architecture is four banks of 1 Mb × 16 (4M16) with a speed grade of 133 MHz at CAS latency (CL) 3. Using 22 Ω series termination resistors is recommended for this configuration. Recommended SDR memory that is compatible with the ADV7842 includes Winbond W9864G6PH-7. DOUBLE DATA RATE (DDR) The ADV7842 can use DDR external memory to simultaneously provide 3D comb and frame synchronizer operation. There is a 128 Mb DDR SDRAM minimum memory requirement. The required memory architecture is four banks of 2 Mb × 16 (8M16) with a speed grade of 133 MHz at CL 2.5. Using 22 Ω series termination resistors is recommended for this configuration Recommended DDR memory that is compatible with the ADV7842 includes the K4H561638J-LCB3 from Samsung, the MT46V16M16P-6T from Micron Technology, Inc. and the H5DU1262GTR-E3C from Hynix Inc. Rev. B | Page 23 of 28 ADV7842 PIXEL INPUT/OUTPUT FORMATTING The output section of the ADV7842 is highly flexible. The pixel output bus can support up to 36-bit 4:4:4. The pixel data supports both single and double data rates modes. In SDR mode, a 16-/20-/24-bit 4:2:2 or 24-/30-/36-bit 4:4:4 output is possible. In DDR mode, the pixel output port can be configured in 8-/10-/12-bit 4:2:2 modes or 24-/30-/36-bit 4:4:4 modes. Bus rotation and bus inversion are also supported. All output modes are controlled via I2C controls. PIXEL DATA OUTPUT MODES FEATURES The output pixel port features include the following: • • • • 8-/10-/12-bit ITU-R BT.656 4:2:2 with embedded time codes and/or HS, VS, and FIELD output signals SDR 16-/20-/24-/30-/36 bit with embedded time codes and/or HS/CS and VS/FIELD pin timing DDR 8-/10-/12-bit 4:2:2 with embedded time codes and/or HS, VS, and FIELD output signals DDR 24-/30-/36 bit 4:4:4 with embedded time codes and/or HS, VS, and FIELD output signals Note that DDR modes are supported up to 54 MHz by characterization. Rev. B | Page 24 of 28 ADV7842 REGISTER MAP ARCHITECTURE map addresses must be programmed; this ensures no addressing clashes on the system. Figure 9 shows the register map architecture. The registers of the ADV7842 are controlled via a 2-wire serial (I2C-compatible) interface. The ADV7842 has 12 maps. The IO map has a static I2C address. All other Table 8. Register Map Name IO Map CP Map SDP Map SDP_IO Map VDP Map AVLINK Map CEC Map HDMI Map EDID Map Repeater Map AFE, DPLL Map InfoFrame Map Default Address 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Programmable Address Not programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Location at Which Address Can Be Programmed Not applicable IO map, Register 0xFD IO map, Register 0xF1 IO map, Register 0xF2 IO map, Register 0xFE IO map, Register 0xF3 IO map, Register 0xF4 IO map, Register 0xFB IO map, Register 0xFA IO map, Register 0xF9 IO map, Register 0xF8 IO map, Register 0xF5 IO MAP CP MAP SDP MAP SDP_IO MAP VDP MAP AVLINK MAP CEC MAP SLAVE ADDRESS: 0x40 SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SCL SDA SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE SLAVE ADDRESS: PROGRAMMABLE HDMI MAP EDID MAP REPEATER MAP AFE, DPLL MAP INFOFRAME MAP 08849-008 SLAVE ADDRESS: PROGRAMMABLE Figure 9. Register Map Architecture Rev. B | Page 25 of 28 ADV7842 OUTLINE DIMENSIONS A1 BALL CORNER 17.20 17.00 SQ 16.80 BALL A1 CORNER 14 16 15 12 13 10 11 8 9 6 7 4 5 2 3 1 A B C D E F G H J K L M N P R T 15.00 BSC SQ 1.00 BSC TOP VIEW BOTTOM VIEW DETAIL A DETAIL A 1.70 MAX 1.10 MAX 0.25 MIN 0.30 MIN COMPLIANT TO JEDEC STANDARDS MO-192-AAF-1 022007-A SEATING PLANE 0.70 COPLANARITY 0.60 0.20 0.50 BALL DIAMETER Figure 10. 256-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-256-3) Dimensions shown in millimeters ORDERING GUIDE Model1 ADV7842KBCZ-5 ADV7842KBCZ-5P EVAL-ADV7842EB1Z EVAL-ADV7842EB2Z Notes 2, 3 2, 4, 5 3, 6, 7 5, 6, 8 Temperature Range −10°C to +70°C −10°C to +70°C Package Description 256-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 256-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Front-End Evaluation Board Front-End Evaluation Board 1 Package Option BC-256-3 BC-256-3 Z = RoHS Compliant Part. Speed grade: 5 = 170 MHz. 3 This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to purchase any components with internal HDCP keys. 4 HDCP functionality: P = no HDCP functionality (professional version). 5 Professional version for non-HDCP encrypted applications. Purchaser is not required to be an HDCP adopter. 6 An ATV motherboard is also required to process the ADV7842 digital outputs and achieve video output. An ATV video output board is optional to evaluate performance through an HDMI transmitter and video encoder. 7 Front-end board for the ATV video evaluation platform, fitted with ADV7842KBCZ-5 decoder. 8 Front-end board for the ATV video evaluation platform, fitted with ADV7842KBCZ-5P decoder. 2 Rev. B | Page 26 of 28 ADV7842 NOTES Rev. B | Page 27 of 28 ADV7842 NOTES I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors). HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. ©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08849-0-1/11(B) Rev. B | Page 28 of 28