Ordering number : ENA0429
CMOS IC
LC75835W
1/3, 1/4-Duty General-Purpose
LCD Display Driver
Overview
The LC75835W is a 1/3, 1/4 duty general-purpose LCD display driver that can be used for displaying segments for
mobile devices and other such products under the control of a microcontroller. In addition to being able to directly drive
up to 136 LCD segments, the LC75835W can also control up to 16 general-purpose output ports. It incorporates an
oscillation circuit that reduces the external resistors and capacitors used for oscillation.
Features
• Either 1/4 or 1/3 duty can be selected with the serial control data.
1/4 duty drive: Up to 136 segments can be driven
1/3 duty drive: Up to 105 segments can be driven
• Either 1/3 or 1/2 bias can be selected with the serial control data.
• On, off, or blinking for each segment can be set with the serial control data.
• Serial data control of display switching in 40-bit units.
(As a general rule, the display can be switched in 12 segment-units.)
• Serial data control of current on/off to the LCD drive bias voltage generation divider resistors.
• Serial data control of the power-saving mode based backup function and the all segments forced off function.
• Serial data control of switching between the segment output port and general-purpose output port functions.
• Buzzer control signals (1 channel) can be output from the general-purpose output port.
• Serial data control of the frame frequency of the common and segment output waveforms.
• Serial data control of the segment blinking frequency.
• Serial data control of switching between the internal oscillator operating mode and external clock operating mode.
• Serial data input supports CCB* format communication with the system controller.
• Independent VLCD for the LCD driver block (VLCD can be set to any voltage in the range 2.7 to 5.5 volts without
regard to the logic block power supply VDD).
• The INH pin allows the display to be forced to the off state.
• Incorporation of an oscillator circuit
•
•
CCB is a trademark of SANYO Electric Co., Ltd.
CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
D1306HKIM 20060919-S00005 No.A0429-1/35
LC75835W
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0V
Parameter
Symbol
Maximum supply voltage
Conditions
Ratings
Unit
VDD max
VDD
-0.3 to +4.5
VLCD max
VLCD
-0.3 to +6.5
Input voltage
V
VIN1
CE, CL, DI, INH, OSCI
VIN2
VLCD1, VLCD2
-0.3 to VLCD+0.3
Output voltage
VOUT
S1 to S35, COM1 to COM4, P1 to P16
-0.3 to VLCD+0.3
V
Output current
IOUT1
S1 to S35
300
µA
Allowable power dissipation
-0.3 to +4.5
IOUT2
COM1 to COM4
3
IOUT3
P1 to P16 *1
5
Pd max
Ta = 75°C
V
mA
100
mW
Operating temperature
Topr
-30 to +75
°C
Storage temperature
Tstg
-55 to +125
°C
Note: *1 The sum of output current through P1 to P16 must be 40mA or less.
Allowable Operating Ranges at Ta = -30 to +75°C, VSS = 0V
Parameter
Symbol
Ratings
Conditions
min
Supply voltage
Input voltage
Input high-level voltage
Input low-level voltage
typ
Unit
max
VDD
VDD
2.7
3.6
VLCD
VLCD
2.7
5.5
VLCD1
VLCD1
2/3VLCD
VLCD
VLCD2
VLCD2
1/3VLCD
VLCD
VIH1
CE, CL, DI, INH
0.7VDD
3.6
VIH2
OSCI
0.7VDD
3.6
VIL1
CE, CL, DI, INH
0
0.2VDD
VIL2
OSCI
0
0.2VDD
External clock operating frequency
fCK
OSCI external clock operating mode [Figure 4]
15
32.8
65
External clock duty cycle
DCK
OSCI external clock operating mode [Figure 4]
30
50
70
V
V
V
V
kHz
%
Data setup time
tds
CL, DI
[Figure 2][Figure 3]
160
ns
Data hold time
tdh
CL, DI
[Figure 2][Figure 3]
160
ns
CE wait time
tcp
CE, CL
[Figure 2][Figure 3]
160
ns
CE setup time
tcs
CE, CL
[Figure 2][Figure 3]
160
ns
CE hold time
tch
CE, CL
[Figure 2][Figure 3]
160
ns
High-level clock pulse width
tφH
CL
[Figure 2][Figure 3]
160
ns
Low-level clock pulse width
tφL
CL
[Figure 2][Figure 3]
160
ns
Rise time
tr
CE, CL, DI
[Figure 2][Figure 3]
Fall time
tf
CE, CL, DI
[Figure 2][Figure 3]
INH switching time
tc
INH, CE
[Figure 5][Figure 6]
160
160
10
ns
ns
µs
No.A0429-2/35
LC75835W
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Pin
Ratings
Conditions
min
Unit
typ
max
Hysteresis
VH
CE, CL, DI, INH
Input high-level current
IIH1
CE, CL, DI, INH
VI = 3.6V
1.0
IIH2
OSCI
VI = 3.6V
1.0
IIL1
CE, CL, DI, INH
VI = 0V
-1.0
IIL2
OSCI
VI = 0V
-1.0
Input low-level current
Output high-level voltage
Output low-level voltage
Output middle-level
0.1VDD
S1 to S35
IO = -20µA
VOH2
COM1 to COM4
IO = -100µA
VLCD-0.9
VOH3
P1 to P16
IO = -1mA
VLCD-0.9
VOL1
S1 to S35
IO = 20µA
0.9
VOL2
COM1 to COM4
IO = 100µA
0.9
VOL3
P1 to P16
IO = 1mA
0.9
VMID1
COM1
1/2 bias IO = ±100µA
to COM4
VLCD-0.9
V
1/2VLCD
+0.9
2/3VLCD
S1 to S35
1/3 bias IO = ±20µA
2/3VLCD
-0.9
+0.9
VMID3
S1 to S35
1/3 bias IO = ±20µA
1/3VLCD
1/3VLCD
-0.9
+0.9
2/3VLCD
2/3VLCD
COM1
1/3 bias IO = ±100µA
to COM4
VMID5
COM1
VLCD1
VLCD1
1/3 bias IO = ±100µA
to COM4
V
1/2VLCD
-0.9
VMID2
VMID4
µA
µA
VOH1
voltage *2
LCD drive bias voltage
V
-0.9
+0.9
1/3VLCD
1/3VLCD
-0.9
+0.9
V
1/3 bias II = ±0µA
Current supply to bias voltage generation
divider resistors
2/3VLCD
-0.03VLCD
2/3VLCD
2/3VLCD
+0.03VLCD
1/3VLCD
-0.03VLCD
1/3VLCD
1/3VLCD
+0.03VLCD
1/2VLCD
-0.03VLCD
1/2VLCD
1/2VLCD
+0.03VLCD
236
295
354
Outputs open
VLCD2
VLCD2
1/3 bias II = ±0µA
Current supply to bias voltage generation
divider resistors
V
Outputs open
VLCD12
VLCD1,
VLCD2
1/2 bias II = ±0µA
Current supply to bias voltage generation
divider resistors
Outputs open
Oscillator frequency
fosc
Internal
Internal oscillator operating mode
oscillator circuit
Current drain
IDD1
VDD
Power-saving mode
IDD2
VDD
VDD = 3.3V normal mode
External clock operating mode *3
IDD3
VDD
VDD = 3.3V normal mode
External clock operating mode *3
kHz
1
5
10
90
180
50
100
135
270
Serial data transfer *4
IDD4
VDD
VDD = 3.3V normal mode
Internal oscillator operating mode
IDD5
VDD
VDD = 3.3V normal mode
Internal oscillator operating mode
µA
Serial data transfer *4
ILCD1
VLCD
Power-saving mode
ILCD2
VLCD
VLCD = 5.0V output open
Normal mode, 1/2 bias
85
170
ILCD3
VLCD
VLCD = 5.0V output open
Normal mode, 1/3 bias
55
110
ILCD4
VLCD
VLCD = 5.0V output open
Normal mode, current to bias voltage
10
20
1
generation divider resistors shut off
Note: *2 Excluding the bias voltage generation divider resistors (RLCD = 30kΩ typ.) built in the VLCD1 and VLCD2.
(See Figure 1.)
Note: *3 External clock operating mode (fCK = 32.8kHz, VIH2 = VDD, VIL2 = 0V, rise/fall time = 20ns)
Note: *4 Serial data transfer (data transfer frequency 2MHz, VIH1 = VDD, VIL1 = 0V, rise/fall time = 20ns)
No.A0429-3/35
LC75835W
VLCD
Except these resistors.
RLCD
To the common and segment drivers
RLCD
RLCD
VSS
VLCD1
RLCD = 30kΩ (±40%)
VLCD2
Figure 1
1. When CL is stopped at the low level
CL
tφL
tcp
≈ ≈
DI
tf
VIH1
VIL1
tds
≈ ≈ ≈
VIH1
50%
VIL1
tr
VIL1
≈ ≈
tφH
≈
VIH1
CE
tcs
tch
tdh
Figure 2
2. When CL is stopped at the high level
≈
VIH1
CE
VIL1
≈
tφH
≈
tφL
tf
tr
DI
VIL1
tds
tcp
tcs
≈ ≈
VIH1
≈ ≈ ≈
VIH1
50%
VIL1
CL
tch
tdh
Figure 3
3. OSCI pin clock timing in external clock operating mode
tCKH
OSCI
VIH2
50%
VIL2
tCKL
fCK =
1
tCKH+ tCKL
[kHz]
tCKH
×100[%]
DCK =
tCKH+ tCKL
Figure 4
No.A0429-4/35
LC75835W
Package Dimensions
unit : mm (typ)
3163B
36
0.5
9.0
7.0
25
24
48
13
7.0
9.0
37
1
12
0.5
0.15
0.18
(1.5)
0.1
1.7max
(0.75)
SANYO : SQFP48(7X7)
COM2
36
37
S25
S26
S27
S29
S28
S30
S31
S32
S33
COM4/S35
S34
COM3
Pin Assignment
25
24
S24
COM1
S23
VDD
S22
VLCD
VLCD1
S21
S20
VLCD2
S19
LC75835W
VSS
S18
OSCI
S17
S16/P16
INH
CE
S15/P15
CL
S14/P14
S13/P13
P12/S12
P11/S11
P10/S10
P9/S9
P8/S8
P7/S7
P6/S6
P5/S5
P4/S4
P3/S3
13
12
P2/S2
48
1
P1/S1
DI
Top view
No.A0429-5/35
LC75835W
COMMON
DRIVER
S1/P1
S2/P2
S16/P16
S17
S34
COM4/S35
COM3
COM2
COM1
Block Diagram
SEGMENT DRIVER & LATCH
INH
OSCI
CLOCK
GENERATOR
CONTROL
REGISTER
VDD
SHIFT REGISTER
VLCD
CCB INTERFACE
VSS
VLCD1
CE
CL
DI
VLCD2
No.A0429-6/35
LC75835W
Pin Functions
Handling
Symbol
Pin No.
Function
Active
I/O
when
unused
S1/P1 to S16/P16
1 to 16
Segment outputs for displaying the display data transferred by serial data input.
S17 to S34
17 to 34
The S1/P1 to S16/P16 pins can be used as general-purpose output ports when
COM1 to COM3
38 to 36
COM4/S35
35
OSCI
44
-
O
OPEN
-
O
OPEN
-
I
GND
H
I
GND
so set up by the control data.
Common driver output pins. The frame frequency is fo [Hz]. COM4/S35 can be
used as segment output in 1/3 duty mode.
External clock input pin. A 15 to 65kHz clock must be supplied to this pin in
external clock operating mode. This pin must be connected to ground in
internal oscillator operating mode.
CE
46
CL
47
CE: Chip enable
DI
48
CL: Synchronization clock
Serial data transfer inputs. Must be connected to the controller.
I
-
I
L
I
GND
-
I
OPEN
-
I
OPEN
-
-
-
-
-
-
-
-
-
DI: Transfer data
INH
45
Display off control input
• INH = low (VSS) ...Display forced off
S1/P1 to S16/P16 = low (VSS)
(These pins are forcibly set to the general-purpose output
port and held at the VSS level.)
S17 to S34 = low (VSS)
COM1 to COM3 = low (VSS)
COM4/S35 = low (VSS)
Shuts off current to the LCD drive bias voltage generation
divider resistors.
Stop the internal oscillation circuit.
• INH = high (VDD)...Display on
However, serial data transfer is possible when the display is forced off.
VLCD1
41
Used to apply the LCD drive 2/3 bias voltage externally.
Connect this pin to VLCD2 when using a 1/2-bias drive scheme.
VLCD2
42
Used to apply the LCD drive 1/3 bias voltage externally.
Connect this pin to VLCD1 when using a 1/2-bias drive scheme.
VDD
39
Power supply pin for the logic circuit block. A power voltage of 2.7V to 3.6V
must be applied to this pin.
VLCD
40
Power supply pin for the LCD driver block. A power voltage of 2.7V to 5.5 V
must be applied to this pin.
VSS
43
Power supply pin. Must be connected to ground.
No.A0429-7/35
LC75835W
Serial Data Transfer Formats
(1) 1/4 duty
1. When CL is stopped at the low level
• When the display data is transferred
CE
CL
DI
0 1 1 0 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 0 0 0 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 0 0 0 0 0 0 1 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 1 0 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 D211 D212 D213 D214 D215 D216 0 0 0 0 1 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
No.A0429-8/35
LC75835W
CE
CL
DI
0 1 1 0 0 0 1 0 D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240 0 0 0 0 1 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Fixed
data
4 bit
Display data
24 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
16 bit
Fixed data
12 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
16 bit
Fixed data
12 bit
DD
4 bit
• When the control data is transferred
CE
CL
DI
0 1 1 0 0 0 1 0
PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Control data
48 bit
PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0
Fixed
data
4 bit
DD
4 bit
Note: DD is the direction data.
• CCB address ....... "46H"
• D1 to D272 ......... Display data
• PC1 to PC16......... General-purpose output port state setting data
• PS1 to PS16 ......... Segment output port/general-purpose output port switching control data
• PZ0 to PZ4 ......... Buzzer control signal output selection data
• PZF ...................... Buzzer control signal frequency setting control data
• DR ...................... 1/3-bias drive or 1/2-bias drive switching control data
• DT ...................... 1/4-duty drive or 1/3-duty drive switching control data
• OC ...................... Internal oscillator operating mode/external clock operating mode switching control data
• FC0, FC1 ......... Common/segment output waveform frame frequency setting control data
• BF0, BF1 ......... Segment blinking frequency setting control data
• SC ...................... Segment on/off control data
• BC ...................... LCD drive bias voltage generation divider resistor current on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A0429-9/35
LC75835W
2. When CL is stopped at the high level
• When the display data is transferred
CE
CL
DI
0 1 1 0 0 0 1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 0 0 0 0 0 0 0 1
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 1 0
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 0 0 0 0 0 0 1 1
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 1 0 0
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 D211 D212 D213 D214 D215 D216 0 0 0 0 1 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
24 bit
Fixed
data
4 bit
DD
4 bit
No.A0429-10/35
LC75835W
CE
CL
DI
0 1 1 0 0 0 1
0 D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240 0 0 0 0 1 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Fixed
data
4 bit
Display data
24 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0 D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
16 bit
Fixed data
12 bit
DD
4 bit
CE
CL
DI
0 1 1 0 0 0 1
0 D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Display data
16 bit
Fixed data
12 bit
DD
4 bit
• When the control data is transferred
CE
CL
DI
0 1 1 0 0 0 1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16
Control data
48 bit
PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0
Fixed
data
4 bit
DD
4 bit
Note: DD is the direction data.
• CCB address ....... "46H"
• D1 to D272 ......... Display data
• PC1 to PC16......... General-purpose output port state setting data
• PS1 to PS16 ......... Segment output port/general-purpose output port switching control data
• PZ0 to PZ4 ......... Buzzer control signal output selection data
• PZF ...................... Buzzer control signal frequency setting control data
• DR ...................... 1/3-bias drive or 1/2-bias drive switching control data
• DT ...................... 1/4-duty drive or 1/3-duty drive switching control data
• OC ...................... Internal oscillator operating mode/external clock operating mode switching control data
• FC0, FC1 ......... Common/segment output waveform frame frequency setting control data
• BF0, BF1 ......... Segment blinking frequency setting control data
• SC ...................... Segment on/off control data
• BC ...................... LCD drive bias voltage generation divider resistor current on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A0429-11/35
LC75835W
(2) 1/3 duty
1. When CL is stopped at the low level
• When the display data is transferred
CE
CL
DI
0 1 1 0 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 0 0 0 0 0 0 0 1
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 1 0
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 0 0 0 0 0 0 1 1
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 1 0 0
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 0 0 0 0 0 0 0 0 0 0 1 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
Fixed data
DD
8 bit
18 bit
4 bit
10 bit
No.A0429-12/35
LC75835W
• When the control data is transferred
CE
CL
DI
0 1 1 0 0 0 1 0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Control data
8 bit
48 bit
PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0
Fixed
data
DD
4 bit
4 bit
Note: DD is the direction data.
• CCB address ....... "46H"
• D1 to D210 ......... Display data
• PC1 to PC16......... General-purpose output port state setting data
• PS1 to PS16 ......... Segment output port/general-purpose output port switching control data
• PZ0 to PZ4 ......... Buzzer control signal output selection data
• PZF ...................... Buzzer control signal frequency setting control data
• DR ...................... 1/3-bias drive or 1/2-bias drive switching control data
• DT ...................... 1/4-duty drive or 1/3-duty drive switching control data
• OC ...................... Internal oscillator operating mode/external clock operating mode switching control data
• FC0, FC1 ......... Common/segment output waveform frame frequency setting control data
• BF0, BF1 ......... Segment blinking frequency setting control data
• SC ...................... Segment on/off control data
• BC ...................... LCD drive bias voltage generation divider resistor current on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A0429-13/35
LC75835W
2. When CL is stopped at the high level
• When the display data is transferred
CE
CL
DI
0 1 1 0 0 0 1 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 0 0 0 0 0 0 0 1
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
CCB address
Display data
DD
4 bit
8 bit
24 bit
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 0 0 0 0 0 0 1 0
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
CCB address
Display data
DD
4 bit
8 bit
24 bit
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70 D71 D72 0 0 0 0 0 0 1 1
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
CCB address
Display data
DD
4 bit
8 bit
24 bit
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D73 D74 D75 D76 D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 0 0 0 0 0 1 0 0
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
CCB address
Display data
DD
4 bit
8 bit
24 bit
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
DD
CCB address
Display data
4 bit
4 bit
8 bit
24 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
CCB address
Display data
DD
4 bit
8 bit
24 bit
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0
Fixed
B0 B1 B2 B3 A0 A1 A2 A3
data
CCB address
Display data
DD
4 bit
8 bit
24 bit
4 bit
CE
CL
DI
0 1 1 0 0 0 1 0 D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 0 0 0 0 0 0 0 0 0 0 1 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
DD
CCB address
Display data
Fixed data
4 bit
8 bit
18 bit
10 bit
No.A0429-14/35
LC75835W
• When the control data is transferred
CE
CL
DI
0 1 1 0 0 0 1
0
PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bit
Control data
48 bit
PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0
Fixed
data
4 bit
DD
4 bit
Note: DD is the direction data.
• CCB address ....... "46H"
• D1 to D210 ......... Display data
• PC1 to PC16......... General-purpose output port state setting data
• PS1 to PS16 ......... Segment output port/general-purpose output port switching control data
• PZ0 to PZ4 ......... Buzzer control signal output selection data
• PZF ...................... Buzzer control signal frequency setting control data
• DR ...................... 1/3-bias drive or 1/2-bias drive switching control data
• DT ...................... 1/4-duty drive or 1/3-duty drive switching control data
• OC ...................... Internal oscillator operating mode/external clock operating mode switching control data
• FC0, FC1 ......... Common/segment output waveform frame frequency setting control data
• BF0, BF1 ......... Segment blinking frequency setting control data
• SC ...................... Segment on/off control data
• BC ...................... LCD drive bias voltage generation divider resistor current on/off control data
• BU ...................... Normal mode/power-saving mode control data
No.A0429-15/35
LC75835W
Serial Data Transfer Example
(1) 1/4 duty
• When 129 or more segments are used
All 544 bits of serial data (including CCB address) must be sent.
8 bit
0 1 1 0 0 0 1 0
56 bit
PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16
B0 B1 B2 B3 A0 A1 A2 A3
PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0
8 bit
0 1 1 0 0 0 1 0
32 bit
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13D14D15D16D17D18D19D20D21D22D23D24 0 0 0 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
D25 D26 D27 D28 D29 D30 D31 D32D33D34D35 D36D37D38D39D40D41D42D43D44D45D46D47D48 0 0 0 0 0 0 1 0
0 1 1 0 0 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
D49 D50 D51 D52 D53 D54 D55 D56D57D58D59 D60D61D62D63D64D65D66D67D68D69D70D71D72 0 0 0 0 0 0 1 1
0 1 1 0 0 0 1 0
D73 D74 D75 D76 D77 D78 D79 D80D81D82D83 D84D85D86D87D88D89D90D91D92D93D94D95D96 0 0 0 0 0 1 0 0
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 D211 D212 D213 D214 D215 D216 0 0 0 0 1 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D217 D218 D219 D220 D221 D222 D223 D224 D225 D226 D227 D228 D229 D230 D231 D232 D233 D234 D235 D236 D237 D238 D239 D240 0 0 0 0 1 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D241 D242 D243 D244 D245 D246 D247 D248 D249 D250 D251 D252 D253 D254 D255 D256 0 0 0 0 0 0 0 0
0 0 0 0 1 0 1 1
D257 D258 D259 D260 D261 D262 D263 D264 D265 D266 D267 D268 D269 D270 D271 D272 0 0 0 0 0 0 0 0
0 0 0 0 1 1 0 0
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 129 segments are used
Depending on the number of segments used, 104 bits, 144 bits, 184 bits, 224 bits, 264 bits, 304 bits, 344 bits,
384 bits, 424 bits, 464 bits or 504 bits (including the CCB address) must be sent as serial data. However, the
serial data (control data) shown in the figure below must be sent without fail.
8 bit
0 1 1 0 0 0 1 0
56 bit
PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16
B0 B1 B2 B3 A0 A1 A2 A3
PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0
Note: After the above serial data is sent, the contents of the display data can be changed by transferring only the serial
data (CCB addresses, display data, fixed data, and direction data) including the display data to be changed in
40-bit units.
No.A0429-16/35
LC75835W
(2) 1/3 duty
• When 97 or more segments are used
All 424 bits of serial data (including CCB addresses) must be sent.
8 bit
0 1 1 0 0 0 1 0
56 bit
PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16
B0 B1 B2 B3 A0 A1 A2 A3
PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0
8 bit
0 1 1 0 0 0 1 0
32 bit
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13D14D15D16D17D18D19D20D21D22D23D24 0 0 0 0 0 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
D25 D26 D27 D28 D29 D30 D31 D32D33D34D35 D36D37D38D39D40D41D42D43D44D45D46D47D48 0 0 0 0 0 0 1 0
0 1 1 0 0 0 1 0
B0 B1 B2 B3 A0 A1 A2 A3
D49 D50 D51 D52 D53 D54 D55 D56D57D58D59 D60D61D62D63D64D65D66D67D68D69D70D71D72 0 0 0 0 0 0 1 1
0 1 1 0 0 0 1 0
D73 D74 D75 D76 D77 D78 D79 D80D81D82D83 D84D85D86D87D88D89D90D91D92D93D94D95D96 0 0 0 0 0 1 0 0
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 0 0 0 0 0 1 0 1
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D121 D122 D123 D124 D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 0 0 0 0 0 1 1 0
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D145 D146 D147 D148 D149 D150 D151 D152 D153 D154 D155 D156 D157 D158 D159 D160 D161 D162 D163 D164 D165 D166 D167 D168 0 0 0 0 0 1 1 1
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D169 D170 D171 D172 D173 D174 D175 D176 D177 D178 D179 D180 D181 D182 D183 D184 D185 D186 D187 D188 D189 D190 D191 D192 0 0 0 0 1 0 0 0
B0 B1 B2 B3 A0 A1 A2 A3
0 1 1 0 0 0 1 0
D193 D194 D195 D196 D197 D198 D199 D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 0 0 0 0 0 0
0 0 0 0 1 0 0 1
B0 B1 B2 B3 A0 A1 A2 A3
• When fewer than 97 segments are used
Depending on the number of segments used, 104 bits, 144 bits, 184 bits, 224 bits, 264 bits, 304 bits, 344 bits or
384 bits (including the CCB address) must be sent as serial data. However, the serial data (control data) shown
in the figure below must be sent without fail.
8 bit
0 1 1 0 0 0 1 0
56 bit
PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 PS13 PS14 PS15 PS16
B0 B1 B2 B3 A0 A1 A2 A3
PZ0 PZ1 PZ2 PZ3 PZ4 PZF DR DT OC FC0 FC1 BF0 BF1 SC BC BU 0 0 0 0 0 0 0 0
Note: After the above serial data is sent, the contents of the display data can be changed by transferring only the serial
data (CCB addresses, display data, fixed data, and direction data) including the display data to be changed in
40-bit units.
No.A0429-17/35
LC75835W
Control Data Functions
1. PC1 to PC16: General-purpose output port state setting data
This control data is used to set the “H” and “L” status of general-purpose output ports P1 to P16.
Output pin
P1
P2
P3
P4
P5
P6
P7
P8
Control data
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
Output pin
P9
P10
P11
P12
P13
P14
P15
P16
Control data
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
Notes: PCn = “1”: “H” (VLCD) is output from output pin Pn (n = 1 to 16).
PCn = “0”: “L” (VSS) is output from output pin Pn (n = 1 to 16).
If, for instance, output pins S4/P4 and S5/P5 have been selected as the general-purpose output ports at PC4 = “1”
and PC5 = “0”, “H” (VLCD) is output from output pin P4 and “L” (VSS) is output from output pin P5.
2. PS1 to PS16: Segment output port/general-purpose output port switching control data
This control data is used to switch between segment output ports and general-purpose output ports for the S1/P1 to
S16/P16 output pins.
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
Control data
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
Output pin
S9/P9
S10/P10
S11/P11
S12/P12
S13/P13
S14/P14
S15/P15
S16/P16
Control data
PS9
PS10
PS11
PS12
PS13
PS14
PS15
PS16
Notes: PSn = “1”: General-purpose output port Pn is selected for output pin Sn/Pn (n = 1 to 16).
PSn = “0”: Segment output port Sn is selected for output pin Sn/Pn (n = 1 to 16).
If, for instance, PS1 to PS3 = “0”, PS4, PS5 = “1” and PS6 to PS16 = “0”, general-purpose output ports are selected
for output pins S4/P4 and S5/P5 and segment output ports are selected for output pins S1/P1 to S3/P3 and S6/P6 to
S16/P16.
3. PZ0 to PZ4: Buzzer control signal output selection data
This control data is used to select the general-purpose output ports from which the buzzer control signals (square
waves with a 50% duty ratio) are output.
General-purpose output
Control data
General-purpose output
Control data
ports from which buzzer
PZ0
PZ1
PZ2
PZ3
PZ4
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
ports from which buzzer
PZ0
PZ1
PZ2
PZ3
PZ4
P1
1
0
0
1
0
P9
0
P2
0
1
0
1
0
P10
0
P3
1
1
0
1
0
P11
0
0
P4
0
0
1
1
0
P12
1
0
0
P5
1
0
1
1
0
P13
1
0
0
P6
0
1
1
1
0
P14
1
1
0
0
P7
1
1
1
1
0
P15
0
0
1
0
P8
0
0
0
0
1
P16
control signals are output
control signals are output
Note: Data other than the data listed above must be set if the buzzer control signals are not to be output.
For example, set (PZ0, PZ1, PZ2, PZ3, PZ4) = (0, 0, 0, 0, 0).
4. PZF: Buzzer control signal frequency setting control data
This control data bit sets the frequency of the buzzer control signals (square waves with a 50% duty ratio).
PZF
Buzzer control signal frequency fz [Hz]
0
fosc/144, fCK/16
1
fosc/72, fCK/8
Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency
(32.8 [kHz] typ.)
No.A0429-18/35
LC75835W
5. DR: 1/3 bias drive or 1/2 bias drive switching control data
This control data bit selects either 1/3 bias drive or 1/2 bias drive.
DR
Bias drive scheme
0
1/3 bias drive
1
1/2 bias drive
6. DT: 1/4 duty drive or 1/3 duty drive switching control data
This control data bit selects either 1/4 duty drive or 1/3 duty drive.
DT
Duty drive scheme
Output pin (COM4/S35) status
0
1/4 duty drive
COM4 (common output)
1
1/3 duty drive
S35 (segment output)
7. OC: Internal oscillator operating mode/external clock operating mode switching control data
This control data bit selects either internal oscillator operating mode or external clock operating mode.
OC
Basic clock operation mode
Input pin (OSCI) status
0
Internal oscillator operating mode
Must be connected to GND.
1
External clock operating mode
The clock signal (15 to 65 [kHz]) must be input from an external source.
8. FC0, FC1: Common/segment output waveform frame frequency setting control data
These control data bits set the frame frequency for common and segment output waveforms.
Control data
Frame frequency fo [Hz]
FC0
FC1
1/4 duty drive
1/3 duty drive
0
0
fosc/5760, fCK/640
fosc/5670, fCK/630
1
0
fosc/4608, fCK/512
fosc/4536, fCK/504
0
1
fosc/3456, fCK/384
fosc/3402, fCK/378
1
1
fosc/2304, fCK/256
fosc/2268, fCK/252
Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency
(32.8 [kHz] typ.)
9. BF0, BF1: Segment blinking frequency setting control data
Theses control data bits control the segment blinking frequency.
Control data
Segment blinking frequency fb [Hz]
BF0
BF1
0
0
fosc/184320, fCK/20480
1
0
fosc/147456, fCK/16384
0
1
fosc/110592, fCK/12288
1
1
fosc/73728, fCK/8192
Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency
(32.8 [kHz] typ.)
10. SC: Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
1
Off
Note that when the segments are turned off by setting SC to “1”, the segments are turned off by outputting segment
off waveforms from the segment output pins.
11. BC: LCD drive bias voltage generation divider resistor current on/off control data
This control data is used to turn on/off the current to the LCD drive bias voltage generation divider resistors.
BC
LCD drive bias voltage generation divider resister state
0
Turns on current to the divider resistors.
1
Turns off current to the divider resistors.
No.A0429-19/35
LC75835W
12. BU: Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
Mode
0
Normal mode
Power-saving mode
In internal oscillator operating mode (OC = “0”), the oscillation of the internal oscillation circuit is stopped; in external
clock operating mode (OC = “1”), the acceptance of the external clock is stopped. The common or segment output
1
pins go to the VSS level. In addition, the current to the LCD drive bias voltage generation divider resistors is turned
off. However, the output pins S1/P1 to S16/P16 can be used as general-purpose output ports (the output of a buzzer
control signal is impossible.) under the control of control data bits PS1 to PS16.
Display Data and Output Pin Correspondence
1. 1/4 duty
Output pin
S1/P1
COM1
D1
COM2
D2
D3
COM3
COM4
D4
D5
D6
D7
D8
S2/P2
D9
D10
D11
D12
D13
D14
D15
D16
S3/P3
D17
D18
D19
D20
D21
D22
D23
D24
S4/P4
D25
D26
D27
D28
D29
D30
D31
D32
S5/P5
D33
D34
D35
D36
D37
D38
D39
D40
S6/P6
D41
D42
D43
D44
D45
D46
D47
D48
S7/P7
D49
D50
D51
D52
D53
D54
D55
D56
S8/P8
D57
D58
D59
D60
D61
D62
D63
D64
S9/P9
D65
D66
D67
D68
D69
D70
D71
D72
S10/P10
D73
D74
D75
D76
D77
D78
D79
D80
S11/P11
D81
D82
D83
D84
D85
D86
D87
D88
S12/P12
D89
D90
D91
D92
D93
D94
D95
D96
S13/P13
D97
D98
D99
D100
D101
D102
D103
D104
S14/P14
D105
D106
D107
D108
D109
D110
D111
D112
S15/P15
D113
D114
D115
D116
D117
D118
D119
D120
S16/P16
D121
D122
D123
D124
D125
D126
D127
D128
S17
D129
D130
D131
D132
D133
D134
D135
D136
S18
D137
D138
D139
D140
D141
D142
D143
D144
S19
D145
D146
D147
D148
D149
D150
D151
D152
S20
D153
D154
D155
D156
D157
D158
D159
D160
S21
D161
D162
D163
D164
D165
D166
D167
D168
S22
D169
D170
D171
D172
D173
D174
D175
D176
S23
D177
D178
D179
D180
D181
D182
D183
D184
S24
D185
D186
D187
D188
D189
D190
D191
D192
S25
D193
D194
D195
D196
D197
D198
D199
D200
S26
D201
D202
D203
D204
D205
D206
D207
D208
S27
D209
D210
D211
D212
D213
D214
D215
D216
S28
D217
D218
D219
D220
D221
D222
D223
D224
S29
D225
D226
D227
D228
D229
D230
D231
D232
S30
D233
D234
D235
D236
D237
D238
D239
D240
S31
D241
D242
D243
D244
D245
D246
D247
D248
S32
D249
D250
D251
D252
D253
D254
D255
D256
S33
D257
D258
D259
D260
D261
D262
D263
D264
S34
D265
D266
D267
D268
D269
D270
D271
D272
Note: The applies to the case where the S1/P1 to S16/P16 output pins are set to be segment output ports.
No.A0429-20/35
LC75835W
For example, the table below lists the segment output states for the S11 output pin.
Display data
Segment output pin (S11) state
D81
D82
D83
D84
D85
D86
D87
D88
0
0
0
0
0
0
0
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
1
0
1
0
1
0
1
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
X
1
X
1
X
1
X
1
The LCD segments for COM1, COM2, COM3, and COM4 are blinking.
1
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
X
1
1
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
X
1
0
0
0
0
The LCD segment corresponding to COM1 is on.
The LCD segments corresponding to COM2, COM3, and COM4 are off.
The LCD segment for COM1 is blinking.
The LCD segments corresponding to COM2, COM3, and COM4 are off.
The LCD segment corresponding to COM2 is on.
The LCD segments corresponding to COM1, COM3, and COM4 are off.
The LCD segment for COM2 is blinking.
The LCD segments corresponding to COM1, COM3, and COM4 are off.
The LCD segment corresponding to COM3 is on.
The LCD segments corresponding to COM1, COM2, and COM4 are off.
The LCD segment for COM3 is blinking.
The LCD segments corresponding to COM1, COM2, and COM4 are off.
The LCD segment corresponding to COM4 is on.
The LCD segments corresponding to COM1, COM2, and COM3 are off.
The LCD segment for COM4 is blinking.
The LCD segments corresponding to COM1, COM2, and COM3 are off.
The LCD segments corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM3 and COM4 are off.
The LCD segments corresponding to COM2 and COM3 are on.
The LCD segments corresponding to COM1 and COM4 are off.
The LCD segments corresponding to COM3 and COM4 are on.
The LCD segments corresponding to COM1 and COM2 are off.
The LCD segments corresponding to COM1 and COM4 are on.
The LCD segments corresponding to COM2 and COM3 are off.
The LCD segment corresponding to COM1 is on.
The LCD segment for COM2 is blinking.
The LCD segments corresponding to COM3 and COM4 are off.
The LCD segment corresponding to COM2 is on.
0
0
1
0
X
1
0
0
The LCD segment for COM3 is blinking.
The LCD segments corresponding to COM1 and COM4 are off.
The LCD segment corresponding to COM3 is on.
0
0
0
0
1
0
X
1
The LCD segment for COM4 is blinking.
The LCD segments corresponding to COM1 and COM2 are off.
The LCD segment corresponding to COM4 is on.
X
1
0
0
0
0
1
0
The LCD segment for COM1 is blinking.
The LCD segments corresponding to COM2 and COM3 are off.
Note: X: don’t care
No.A0429-21/35
LC75835W
2. 1/3 duty
Output pin
COM1
COM2
COM3
S1/P1
D1
D2
D3
D4
D5
D6
S2/P2
D7
D8
D9
D10
D11
D12
S3/P3
D13
D14
D15
D16
D17
D18
S4/P4
D19
D20
D21
D22
D23
D24
S5/P5
D25
D26
D27
D28
D29
D30
S6/P6
D31
D32
D33
D34
D35
D36
S7/P7
D37
D38
D39
D40
D41
D42
S8/P8
D43
D44
D45
D46
D47
D48
S9/P9
D49
D50
D51
D52
D53
D54
S10/P10
D55
D56
D57
D58
D59
D60
S11/P11
D61
D62
D63
D64
D65
D66
S12/P12
D67
D68
D69
D70
D71
D72
S13/P13
D73
D74
D75
D76
D77
D78
S14/P14
D79
D80
D81
D82
D83
D84
S15/P15
D85
D86
D87
D88
D89
D90
S16/P16
D91
D92
D93
D94
D95
D96
S17
D97
D98
D99
D100
D101
D102
S18
D103
D104
D105
D106
D107
D108
S19
D109
D110
D111
D112
D113
D114
S20
D115
D116
D117
D118
D119
D120
S21
D121
D122
D123
D124
D125
D126
S22
D127
D128
D129
D130
D131
D132
S23
D133
D134
D135
D136
D137
D138
S24
D139
D140
D141
D142
D143
D144
S25
D145
D146
D147
D148
D149
D150
S26
D151
D152
D153
D154
D155
D156
S27
D157
D158
D159
D160
D161
D162
S28
D163
D164
D165
D166
D167
D168
S29
D169
D170
D171
D172
D173
D174
S30
D175
D176
D177
D178
D179
D180
S31
D181
D182
D183
D184
D185
D186
S32
D187
D188
D189
D190
D191
D192
S33
D193
D194
D195
D196
D197
D198
S34
D199
D200
D201
D202
D203
D204
S35/COM4
D205
D206
D207
D208
D209
D210
Note: The applies to the case where the S1/P1 to S16/P16 and S35/COM4 output pins are set to be segment output
ports.
No.A0429-22/35
LC75835W
For example, the table below lists the segment output states for the S11 output pin.
Display data
Segment output pin (S11) state
D61
D62
D63
D64
D65
D66
0
0
0
0
0
0
The LCD segments corresponding to COM1, COM2, and COM3 are off.
1
0
1
0
1
0
The LCD segments corresponding to COM1, COM2, and COM3 are on.
X
1
X
1
X
1
The LCD segments for COM1, COM2, and COM3 are blinking.
1
0
0
0
0
0
X
1
0
0
0
0
0
0
1
0
0
0
0
0
X
1
0
0
0
0
0
0
1
0
0
0
0
0
X
1
1
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
X
1
0
0
The LCD segment corresponding to COM1 is on.
The LCD segments corresponding to COM2 and COM3 are off.
The LCD segment for COM1 is blinking.
The LCD segments corresponding to COM2 and COM3 are off.
The LCD segment corresponding to COM2 is on.
The LCD segments corresponding to COM1 and COM3 are off.
The LCD segment for COM2 is blinking.
The LCD segments corresponding to COM1 and COM3 are off.
The LCD segment corresponding to COM3 is on.
The LCD segments corresponding to COM1 and COM2 are off.
The LCD segment for COM3 is blinking.
The LCD segments corresponding to COM1 and COM2 are off.
The LCD segments corresponding to COM1 and COM2 are on.
The LCD segment corresponding to COM3 is off.
The LCD segments corresponding to COM2 and COM3 are on.
The LCD segment corresponding to COM1 is off.
The LCD segments corresponding to COM1 and COM3 are on.
The LCD segment corresponding to COM2 is off.
The LCD segment corresponding to COM1 is on.
The LCD segment for COM2 is blinking.
The LCD segment corresponding to COM3 is off.
The LCD segment corresponding to COM2 is on.
0
0
1
0
X
1
The LCD segment for COM3 is blinking.
The LCD segment corresponding to COM1 is off.
The LCD segment corresponding to COM3 is on.
X
1
0
0
1
0
The LCD segment for COM1 is blinking.
The LCD segment corresponding to COM2 is off.
Note: X: don’t care
No.A0429-23/35
LC75835W
Output Waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz]
COM1
COM2
COM3
COM4
LCD driver output when all LCD segments corresponding
to COM1, COM2, COM3, and COM4 are off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3 are on.
LCD driver output when only LCD segments
corresponding to COM4 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
LCD driver output when all LCD segments corresponding
to COM1, COM2, COM3, and COM4 are on.
Control data
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
Frame frequency fo [Hz]
FC0
FC1
0
0
fosc/5760, fCK/640
1
0
fosc/4608, fCK/512
0
1
fosc/3456, fCK/384
1
1
fosc/2304, fCK/256
Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency
(32.8 [kHz] typ.)
No.A0429-24/35
LC75835W
Output Waveforms (1/4-Duty 1/2-Bias Drive Scheme)
fo[Hz]
COM1
VLCD
VLCD1,VLCD2
0V
COM2
VLCD
VLCD1,VLCD2
0V
COM3
VLCD
VLCD1,VLCD2
0V
COM4
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments corresponding
to COM1, COM2, COM3, and COM4 are off.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments corresponding
to COM1, COM2, and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM4 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments corresponding
to COM1, COM2, COM3, and COM4 are on.
VLCD
VLCD1,VLCD2
0V
Control data
Frame frequency fo [Hz]
FC0
FC1
0
0
fosc/5760, fCK/640
1
0
fosc/4608, fCK/512
0
1
fosc/3456, fCK/384
1
1
fosc/2304, fCK/256
Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency
(32.8 [kHz] typ.)
No.A0429-25/35
LC75835W
Output Waveforms (1/3-Duty 1/3-Bias Drive Scheme)
fo[Hz]
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
VLCD
VLCD1
VLCD2
0V
COM1
COM2
COM3
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3 are off.
LCD driver output when only LCD segments
corresponding to COM1 are on.
LCD driver output when only LCD segments
corresponding to COM2 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments
corresponding to COM3 are on.
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3 are on.
Control data
Frame frequency fo [Hz]
FC0
FC1
0
0
fosc/5670, fCK/630
1
0
fosc/4536, fCK/504
0
1
fosc/3402, fCK/378
1
1
fosc/2268, fCK/252
Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency
(32.8 [kHz] typ.)
No.A0429-26/35
LC75835W
Output Waveforms (1/3-Duty 1/2-Bias Drive Scheme)
fo[Hz]
COM1
VLCD
VLCD1,VLCD2
0V
COM2
VLCD
VLCD1,VLCD2
0V
COM3
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3 are off.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM1 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when only LCD segments
corresponding to COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
VLCD
VLCD1,VLCD2
0V
LCD driver output when all LCD segments
corresponding to COM1, COM2, and COM3 are on.
VLCD
VLCD1,VLCD2
0V
Control data
Frame frequency fo [Hz]
FC0
FC1
0
0
fosc/5670, fCK/630
1
0
fosc/4536, fCK/504
0
1
fosc/3402, fCK/378
1
1
fosc/2268, fCK/252
Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency
(32.8 [kHz] typ.)
No.A0429-27/35
LC75835W
The INH pin and Display Control
Since the IC internal data (1/4 duty: the display data D1 to D272 and the control data, 1/3 duty: the display data D1 to
D210 and the control data) is undefined when power is first applied, applications should set the INH pin low at the same
time as power is applied to turn off the display (This sets the S1/P1 to S16/P16, S17 to S34, COM1 to COM3, and
COM4/S35 to the VSS level.) and during this period send serial data from the controller. The controller should then set
the INH pin high after the data transfer has completed. This procedure prevents meaningless displays at power on. (See
Figures 5 and 6.)
Notes on the Power On/Off Sequences
Applications should observe the following sequences when turning the LC75835W power on and off.
(See Figures 5 and 6)
• At power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on
• At power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and
off at the same time.
1. 1/4 duty
t2
≈
t1
t3
≈
VDD
≈
VLCD
INH
tc
CE
VIL1
≈ ≈ ≈ ≈ ≈ ≈ ≈
VIL1
Display data and control data transfer
Undefined
Defined
Undefined
Internal data (D1 to D24)
Undefined
Defined
Undefined
Internal data (D25 to D48)
Undefined
Defined
Undefined
Internal data (D241 to D256)
Undefined
Internal data (D257 to D272)
Undefined
≈ ≈ ≈ ≈
PC1 to PC16,PS1 to PS16,
Internal data PZ0 to PZ4,PZF,DR,DT,OC,
FC0,FC1,BF0,BF1,SC,BC,BU
Defined
Defined
Undefined
Undefined
Note: t1≥0
t2>0
t3≥0 (t2>t3)
tc⋅⋅⋅10µs min
Figure 5
No.A0429-28/35
LC75835W
2. 1/3 duty
t2
t3
≈
t1
≈
VDD
≈
VLCD
INH
tc
CE
VIL1
Display data and control data transfer
≈ ≈ ≈ ≈ ≈ ≈ ≈
VIL1
Undefined
Defined
Undefined
Internal data (D1 to D24)
Undefined
Defined
Undefined
Internal data (D25 to D48)
Undefined
Defined
Undefined
Internal data (D169 to D192)
Undefined
Defined
Undefined
Internal data (D193 to D210)
Undefined
Defined
Undefined
≈ ≈ ≈ ≈
PC1 to PC16,PS1 to PS16,
Internal data PZ0 to PZ4,PZF,DR,DT,OC,
FC0,FC1,BF0,BF1,SC,BC,BU
Note: t1≥0
t2>0
t3≥0 (t2>t3)
tc⋅⋅⋅10µs min
Figure 6
No.A0429-29/35
LC75835W
Notes on Controller Transfer of Display Data
Since the LC75835W accepts the display data (D1 to D272) divided into 12 separate transfer operations when using 1/4
duty drive scheme and data (D1 to D210) divided into 9 separate transfer operations when using 1/3 duty drive scheme,
we recommend that the applications transfer all of the display data within a period of less than 30ms to prevent
observable degradation of display quality.
Generation of Buzzer Control Signal
A square wave with a 50% duty ratio is output from the general-purpose output port selected for the output of the
buzzer control signal between the start and end of the buzzer control signal output. If, for example, general-purpose
output port P1 has been selected as the output of the buzzer control signal (PC1 = “0”, PS1 = “1”), the waveform shown
below will be output.
Tz
Tz/2
Tz/2
Tz
Tz/2
Tz
Tz/2
Tz/2
Tz
Tz/2
Tz/2
Tz/2
P1
Beginning of buzzer control signal generation
(Send control data PZ0, PZ1, PZ2, PZ3, PZ4 ("1,0,0,0,0"))
End of buzzer control signal generation
(Send control data PZ0, PZ1, PZ2, PZ3, PZ4 ("0,0,0,0,0"))
Control data PZF
Buzzer control signal frequency fz(=1/Tz)[Hz]
0
fosc/144, fCK/16
1
fosc/72, fCK/8
Note: fosc: Internal oscillation frequency (295 [kHz] typ.), fCK: External clock operating frequency
(32.8 [kHz] typ.)
Oscillation Stabilization Time of the Internal Oscillation Circuit
It must be noted that the oscillation of the internal oscillation circuit is unstable for a maximum of 100µs (oscillation
stabilization time) after oscillation has started.
Internal oscillation
circuit
Oscillation stopped
Oscillation
stabilization time
(100 [µs] max.)
Oscillation operation
(under normal conditions)
<Oscillation start>
1. If the INH pin status is switched from “L” to “H”
when control data OC = “0” and BU = “0”
2. If the control data BU is set from “1” to “0”
when INH = “H” and control data OC = “0”
No.A0429-30/35
LC75835W
Sample Application Circuit 1
1/4 Duty, 1/3 Bias
(When the LCD drive bias voltage is not supplied from an external source)
(P1)
(P2)
(P16)
COM1
COM2
COM3
S35/COM4
P1/S1
P2/S2
VSS
VLCD
+5V
VLCD1
P16/S16
S17
VLCD2
C≥0.047µF
C
C
INH
CE
CL
DI
From the controller
Used for functions
such as backlight
control
LCD panel (up to 136 segments)
VDD
+3.3V
General-purpose
Output ports
S33
S34
*5
OSCI
External clock input
*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = “0”) has been selected;
the clock must be input from an external source when the external clock operating mode (OC = “1”) has been
selected.
*6: Control data BC must be set to “0”.
Sample Application Circuit 2
(P1)
+3.3V
VDD
COM1
COM2
COM3
S35/COM4
P1/S1
P2/S2
VSS
+5V
VLCD
R
VLCD1
100kΩ≥R≥1kΩ
C≥0.047µF
From the controller
R
P16/S16
S17
VLCD2
C
C
R
INH
CE
CL
DI
*5
OSCI
(P2)
General-purpose
Output ports
(P16)
Used for functions
such as backlight
control
LCD panel (up to 136 segments)
1/4 Duty, 1/3 Bias
(When the LCD drive bias voltage is supplied from an external source)
S33
S34
External clock input
*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = “0”) has been selected;
the clock must be input from an external source when the external clock operating mode (OC = “1”) has been
selected.
*6: Control data BC must be set to “1”.
No.A0429-31/35
LC75835W
Sample Application Circuit 3
(P1)
1/4 Duty, 1/2 Bias
(When the LCD drive bias voltage is not supplied from an external source)
(P2)
(P16)
COM1
COM2
COM3
S35/COM4
P1/S1
P2/S2
VSS
+5V
VLCD
VLCD1
P16/S16
S17
VLCD2
C≥0.047µF
C
INH
CE
CL
DI
From the controller
Used for functions
such as backlight
control
LCD panel (up to 136 segments)
VDD
+3.3V
General-purpose
Output ports
S33
S34
*5
OSCI
External clock input
*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = “0”) has been selected;
the clock must be input from an external source when the external clock operating mode (OC = “1”) has been
selected.
*6: Control data BC must be set to “0”.
(P1)
1/4 Duty, 1/2 Bias
(When the LCD drive bias voltage is supplied from an external source)
+3.3V
VDD
COM1
COM2
COM3
S35/COM4
P1/S1
P2/S2
VSS
+5V
VLCD
R
100kΩ≥R≥1kΩ
C≥0.047µF
From the controller
C
R
VLCD1
P16/S16
S17
VLCD2
INH
CE
CL
DI
*5
OSCI
(P2)
General-purpose
Output ports
(P16)
Used for functions
such as backlight
control
LCD panel (up to 136 segments)
Sample Application Circuit 4
S33
S34
External clock input
*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = “0”) has been selected;
the clock must be input from an external source when the external clock operating mode (OC = “1”) has been
selected.
*6: Control data BC must be set to “1”.
No.A0429-32/35
LC75835W
Sample Application Circuit 5
(P1)
1/3 Duty, 1/3 Bias
(When the LCD drive bias voltage is not supplied from an external source)
(P2)
(P16)
COM1
COM2
COM3
P1/S1
P2/S2
VSS
+5V
VLCD
VLCD1
P16/S16
S17
VLCD2
C≥0.047µF
C
C
INH
CE
CL
DI
From the controller
*5
OSCI
Used for functions
such as backlight
control
LCD panel (up to 105 segments)
VDD
+3.3V
General-purpose
Output ports
S33
S34
COM4/S35
External clock input
*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = “0”) has been selected;
the clock must be input from an external source when the external clock operating mode (OC = “1”) has been
selected.
*6: Control data BC must be set to “0”.
(P1)
1/3 Duty, 1/3 Bias
(When the LCD drive bias voltage is supplied from an external source)
(P2)
(P16)
VDD
+3.3V
COM1
COM2
COM3
P1/S1
P2/S2
VSS
+5V
VLCD
R
VLCD1
R
100kΩ≥R≥1kΩ
C≥0.047µF
From the controller
P16/S16
S17
VLCD2
C
C
R
INH
CE
CL
DI
*5
OSCI
General-purpose
Output ports
Used for functions
such as backlight
control
LCD panel (up to 105 segments)
Sample Application Circuit 6
S33
S34
COM4/S35
External clock input
*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = “0”) has been selected;
the clock must be input from an external source when the external clock operating mode (OC = “1”) has been
selected.
*6: Control data BC must be set to “1”.
No.A0429-33/35
LC75835W
Sample Application Circuit 7
1/3 Duty, 1/2 Bias
(When the LCD drive bias voltage is not supplied from an external source)
(P1)
(P2)
(P16)
VDD
COM1
COM2
COM3
P1/S1
P2/S2
VSS
+5V
VLCD
VLCD1
P16/S16
S17
VLCD2
C
C≥0.047µF
INH
CE
CL
DI
From the controller
*5
OSCI
Used for functions
such as backlight
control
LCD panel (up to 105 segments)
+3.3V
General-purpose
Output ports
S33
S34
COM4/S35
External clock input
*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = “0”) has been selected;
the clock must be input from an external source when the external clock operating mode (OC = “1”) has been
selected.
*6: Control data BC must be set to “0”.
(P1)
1/3 Duty, 1/2 Bias
(When the LCD drive bias voltage is supplied from an external source)
(P2)
(P16)
VDD
+3.3V
COM1
COM2
COM3
P1/S1
P2/S2
VSS
+5V
VLCD
R
100kΩ≥R≥1kΩ
C≥0.047µF
From the controller
C
R
VLCD1
P16/S16
S17
VLCD2
INH
CE
CL
DI
*5
OSCI
General-purpose
Output ports
Used for functions
such as backlight
control
LCD panel (up to 105 segments)
Sample Application Circuit 8
S33
S34
COM4/S35
External clock input
*5: The OSCI pin must be connected to GND when the internal oscillator operating mode (OC = “0”) has been selected;
the clock must be input from an external source when the external clock operating mode (OC = “1”) has been
selected.
*6: Control data BC must be set to “1”.
No.A0429-34/35
LC75835W
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performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
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for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
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reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
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This catalog provides information as of December, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0429-35/35