Ordering number : ENA0712A LC75832E LC75832W http://onsemi.com CMOS IC Static Drive, 1/2-Duty Drive General-Purpose LCD Display Driver Overview The LC75832E and 75832W are static drive or 1/2-duty drive, microcontroller-controlled general-purpose LCD drivers that can be used in applications such as frequency display in products with electronic tuning. In addition to being capable to drive up to 108 segments directly, they can control up to 4 general-purpose output ports. Since the LC75832E and LC75832W use separate power supply systems for the LCD drive block and the logic block, the LCD driver block power-supply voltage can be set to any voltage in the range 2.7 to 6.0 volts, regardless of the logic block power-supply voltage. Features • Serial data control of switching between static drive mode and 1/2 duty drive mode. • Up to 54 segments can be displayed in static drive (1/1 duty) mode and up to 108 segments can be displayed in 1/2 duty drive mode. • Serial data input supports CCB* format communication with the system controller. • Serial data control of the power-saving mode based backup function and the all segments forced off function. • Serial data control of switching between the segment output port and general-purpose output port functions (up to 4 general-purpose output ports). • Serial data control of the frame frequency of the common and segment output waveforms. • Either RC oscillator operating or external clock operating mode can be selected with the serial control data. • High generality, since display data is displayed directly without the intervention of a decoder circuit. • Independent VLCD for the LCD driver block (VLCD can be set to any voltage in the range of 2.7 to 6.0 volts.) regardless of the logic block supply-voltage. • The INH pin allows the display to be forced to the off state. • Allows compatible operation with the LC75822 (822 mode transfer function). • CCB is ON Semiconductor® ’s original format. All addresses are managed by ON Semiconductor® for this format. • CCB is a registered trademark of Semiconductor Components Industries, LLC. Semiconductor Components Industries, LLC, 2013 July, 2013 O1309HKPC 20070621-S00005,20070621-S00006/30707HKIM No.A0712-1/22 LC75832E, 75832W Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Maximum supply voltage Symbol Conditions Ratings Unit VDD max VDD -0.3 to +7.0 VLCD max VLCD -0.3 to +7.0 Input voltage Output voltage VIN1 CE, CL, DI, INH VIN2 OSC VOUT1 OSC VOUT2 S1 to S54, COM1, COM2, P1 to P4 Output current Allowable power dissipation V -0.3 to +7.0 V -0.3 to VDD+0.3 -0.3 to VDD+0.3 V -0.3 to VLCD+0.3 IOUT1 S1 to S54 IOUT2 COM1, COM2 3 IOUT3 P1 to P4 5 Pd max Ta=105°C μA 300 mA 100 mW Operating temperature Topr -40 to +105 °C Storage temperature Tstg -55 to +125 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Allowable Operating Ranges at Ta = -40 to +105°C, VSS = 0V Parameter Symbol Ratings Conditions min Supply voltage typ unit max VDD VDD 2.7 6.0 VLCD VLCD 2.7 6.0 VIH1 CE, CL, DI, INH 0.8VDD 6.0 VIH2 OSC external clock operating mode 0.7VDD VDD VIL1 CE, CL, DI, INH 0 0.2VDD VIL2 OSC external clock operating mode 0 0.3VDD Rosc OSC RC oscillator operating mode Cosc OSC RC oscillator operating mode fosc OSC RC oscillator operating mode External clock operating frequency fCK OSC external clock operating mode [Figure 3] 19 External clock duty cycle DCK OSC external clock operating mode [Figure 3] 30 Input high-level voltage Input low-level voltage Recommended external resistor for RC oscillation Recommended external capacitor for RC oscillation Guaranteed range of RC oscillation 19 V V V 39 kΩ 1000 pF 38 76 kHz 38 76 kHz 50 70 % Data setup time tds CL, DI [Figure 1][Figure 2] 160 ns Data hold time tdh CL, DI [Figure 1][Figure 2] 160 ns CE wait time tcp CE, CL [Figure 1][Figure 2] 160 ns CE setup time tcs CE, CL [Figure 1][Figure 2] 160 ns CE hold time tch CE, CL [Figure 1][Figure 2] 160 ns High-level clock pulse width tφH CL [Figure 1][Figure 2] 160 ns Low-level clock pulse width tφL CL [Figure 1][Figure 2] 160 ns Rise time tr CE, CL, DI [Figure 1][Figure 2] 160 ns Fall time tf CE, CL, DI [Figure 1][Figure 2] 160 ns INH switching time tc INH, CE [Figure 4] to [Figure 7] 10 μs No.A0712-2/22 LC75832E, 75832W Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Pin Ratings Conditions min unit typ max Hysteresis VH CE, CL, DI, INH Input high-level current IIH1 CE, CL, DI, INH VI=6.0V 5.0 IIH2 OSC VI=VDD external clock operating mode 5.0 IIL1 CE, CL, DI, INH VI=0V -5.0 IIL2 OSC VI=0V external clock operating mode -5.0 Input low-level current Output high-level voltage Output low-level voltage Output middle-level 0.1VDD VOH1 S1 to S54 IO=-20μA VLCD-0.9 VOH2 COM1, COM2 IO=-100μA VLCD-0.9 VOH3 P1 to P4 IO=-1mA VLCD-0.9 S1 to S54 IO=20μA COM1, COM2 IO=100μA 0.9 VOL3 P1 to P4 IO=1mA 0.9 VMID COM1, COM2 1/2 bias IO=±100μA 0.9 1/2VLCD 1/2VLCD -0.9 +0.9 OSC RC oscillator operating mode 30.4 Rosc=39kΩ, Cosc=1000pF Current drain V VOL2 fosc μA μA VOL1 voltage Oscillator frequency V IDD1 VDD Power-saving mode IDD2 VDD VDD=6.0V output open fosc=38kHz ILCD1 VLCD Power-saving mode ILCD2 VLCD VLCD=6.0V output open Static 38 45.6 V V kHz 10 250 500 15 μA 100 200 1300 2600 fosc=38kHz ILCD3 VLCD VLCD=6.0V output open 1/2 duty fosc=38kHz 1. When CL is stopped at the low level tφL tcp ≈ ≈ DI tf VIH1 VIL1 tds ≈ ≈ ≈ VIH1 50% VIL1 tr VIL1 ≈ ≈ tφH CL ≈ VIH1 CE tcs tch tdh Figure 1 2. When CL is stopped at the high level ≈ VIH1 CE ≈ VIL1 tφH ≈ tφL tf tr tcp tcs VIH1 DI VIL1 tds ≈ ≈ ≈ ≈ ≈ VIH1 50% VIL1 CL tch tdh Figure 2 No.A0712-3/22 LC75832E, 75832W 3. OSC pin clock timing in external clock operating mode tCKH tCKL fCK= VIH2 50% VIL2 OSC 1 tCKH+ tCKL [kHz] tCKH ×100[%] DCK= tCKH+ tCKL Figure 3 Package Dimensions Package Dimensions unit:mm (typ) 3159A [LC75832E] unit:mm (typ) 3190A [LC75832W] 17.2 14.0 12.0 48 32 32 10.0 49 17.2 14.0 49 33 64 64 0.5 0.35 0.18 0.15 (1.25) 16 0.8 16 0.15 (1.5) 1 17 1 17 12.0 33 0.5 10.0 0.8 48 3.0max 0.1 (2.7) 1.7max (1.0) 0.1 SANYO : SQFP64(10X10) SANYO : QIP64E(14X14) No.A0712-4/22 LC75832E, 75832W S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 Pin Assignment 48 33 49 32 S49 S32 S50 S31 S51 S52 S30 S53 S29 S28 S54 S27 OSC S26 LC75832E LC75832W VDD INH S25 VLCD S24 S23 VSS S22 CE S21 CL S20 DI S19 COM2 COM1 S18 S17 64 17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 P4/S4 P3/S3 P2/S2 16 P1/S1 1 Top view LC75832E: QIP64E(14×14) LC75832W: SQFP64(10×10) COMMON DRIVER S1/P1 S2/P2 S3/P3 S4/P4 S5 S53 S54 COM2 COM1 Block Diagram SEGMENT DRIVER & LATCH INH OSC CLOCK GENERATOR CONTROL REGISTER SHIFT REGISTER VDD VLCD CCB INTERFACE CE CL DI VSS No.A0712-5/22 LC75832E, 75832W Pin Functions Handling Symbol Pin No. Function Active I/O when unused S1/P1 to 1 to 4 S4/P4 Segment outputs for displaying the display data transferred by serial data input. - O OPEN Common driver outputs. The frame frequency is fo [Hz]. - O OPEN Oscillator connection. An oscillator circuit is formed by connecting an external - I/O VDD H I GND The S1/P1 to S4/P4 pins can be used as general-purpose output ports when so set S5 to S54 5 to 54 COM1 64 COM2 63 OSC 55 up by the control data. resistor and capacitor to this pin. This pin can be used as the external clock input pin if external clock operating mode is selected with the control data. CE 60 CL 61 CE: Chip enable DI 62 CL: Synchronization clock Serial data transfer inputs. Must be connected to the controller. I - I L I GND DI: Transfer data INH 57 Display off control input • INH = low (VSS) ...Display forced off S1/P1 to S4/P4 = low (VSS) (These pins are forcibly set to the segment output port function and held at the VSS level.) S5 to S54 = low (VSS) COM1, COM2 = low (VSS) OSC = Z (high impedance) RC oscillation stopped Inhibits external clock input. • INH = high (VDD)...Display on RC oscillation enabled (RC oscillator operating mode) Enables external clock input (external clock operating mode). However, serial data transfer is possible when the display is forced off. VDD 56 Logic block power supply. Provide a voltage in the range 2.7 to 6.0V. - - - VLCD 58 LCD driver block power supply. Provide a voltage in the range 2.7 to 6.0V. - - - VSS 59 Ground pin. Must be connected to ground. - - - No.A0712-6/22 LC75832E, 75832W Serial Data Transfer Formats (1) Static drive mode 1. When CL is stopped at the low level ∼ CE DI 0 1 0 0 0 1 0 1 ∼∼∼ CL D1 D2 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 54 bit Control data 17 bit DD 1 bit 2. When CL is stopped at the high level CL DI 0 1 0 0 0 1 0 1 D1 D2 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 54 bit Control data 17 bit ∼∼ ∼∼ CE DD 1 bit Note: DD is the direction data. • CCB address ....... "A2H" • D1 to D54 ......... Display data • P0 to P2 .............. Segment output port/general-purpose output port switching control data • DT ...................... Static drive or 1/2 duty drive switching control data • FC0 to FC2 ......... Common/segment output waveform frame frequency control data • OC ...................... RC oscillator operating mode/external clock operating mode switching control data • SC ...................... Segments on/off control data • BU ...................... Normal mode/power-saving mode control data No.A0712-7/22 LC75832E, 75832W (2) 1/2 duty drive mode 1. When CL is stopped at the low level CL 0 1 0 0 0 1 0 1 D1 D2 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 Control data 17 bit DD 1 bit ∼∼∼ ∼ Display data 54 bit ∼ CCB address 8 bit 0 1 0 0 0 1 0 1 D55 D56 D101 D102 D103 D104 D105 D106 D107 D108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 54 bit Fixed data 17 bit ∼∼∼ DI ∼∼∼ ∼ CE DD 1 bit 2. When CL is stopped at the high level CL 0 1 0 0 0 1 0 1 D1 D2 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 P0 P1 P2 DT FC0 FC1 FC2 OC SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit DD 1 bit ∼∼ ∼∼ Control data 17 bit ∼∼ Display data 54 bit 0 1 0 0 0 1 0 1 D55 D56 D101 D102 D103 D104 D105 D106 D107 D108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 54 bit Fixed data 17 bit ∼∼ DI ∼∼ ∼∼ CE DD 1 bit Note: DD is the direction data. • CCB address ....... "A2H" • D1 to D108 ......... Display data • P0 to P2 .............. Segment output port/general-purpose output port switching control data • DT ...................... Static drive or 1/2 duty drive switching control data • FC0 to FC2 ......... Common/segment output waveform frame frequency control data • OC ...................... RC oscillator operating mode/external clock operating mode switching control data • SC ...................... Segments on/off control data • BU ...................... Normal mode/power-saving mode control data No.A0712-8/22 LC75832E, 75832W Serial Data Transfer Formats (When in 822 mode data transfer) (1) Static drive mode (When in 822 mode data transfer) 1. When CL is stopped at the low level CL 0 1 0 0 0 1 0 1 D1 D2 D20 D21 D22 D23 D25 D26 D27 D28 D29 D30 D31 D32 D50 D51 D52 D53 D54 DT 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 53 bit DD 1 bit Control data 2 bit 2. When CL is stopped at the high level ∼∼ CE CL DI 0 1 0 0 0 1 0 1 D1 D2 D20 D21 D22 D23 D25 D26 D27 D28 D29 D30 D31 D32 D50 D51 D52 D53 D54 DT 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 53 bit ∼∼ DI ∼∼∼ ∼ CE DD 1 bit Control data 2 bit Note: DD is the direction data. • CCB address …………….. "A2H" • D1 to D23, D25 to D54 …. Display data • DT ……………………….. Static drive or 1/2 duty drive switching control data No.A0712-9/22 LC75832E, 75832W (2) 1/2 duty drive mode (When in 822 mode data transfer) 1. When CL is stopped at the low level CL DI 0 1 0 0 0 1 0 1 D1 D2 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D49 D50 D51 D52 D53 D54 0 DT 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit ∼∼∼ ∼ CE DD 1 bit Display data 52 bit 0 1 0 0 0 1 0 1 D55 D56 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 52 bit Fixed data 3 bit ∼∼∼ ∼∼∼ ∼ ∼ Control data 3 bit DD 1 bit 2. When CL is stopped at the high level CL DI 0 1 0 0 0 1 0 1 D1 D2 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D49 D50 D51 D52 D53 D54 0 DT 0 0 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 52 bit ∼∼ ∼∼ CE DD 1 bit 0 1 0 0 0 1 0 1 D55 D56 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 CCB address 8 bit Display data 52 bit Fixed data 3 bit ∼∼ ∼∼ ∼∼ ∼∼ Control data 3 bit DD 1 bit Note: DD is the direction data. • CCB address …………….... "A2H" • D1 to D46, D49 to D106 …. Display data • DT ……………………….... Static drive or 1/2 duty drive switching control data No.A0712-10/22 LC75832E, 75832W Serial Data Transfer Examples (1) Static drive mode The serial data shown in the figure below must be sent. 8 bit 0 1 0 0 0 1 0 1 72 bit D1 D2 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 P0 P1 P2 DT FC0 FC1 FC2 0C SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 (2) 1/2 duty drive mode • When 55 or more segments are used 160 bits of serial data (including CCB address bits) must be sent. 8 bit 0 1 0 0 0 1 0 1 72 bit D1 D2 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 P0 P1 P2 DT FC0 FC1 FC2 0C SC BU 0 D55 D56 D101 D102 D103 D104 D105 D106 D107 D108 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 1 0 1 B0 B1 B2 B3 A0 A1 A2 A3 • When fewer than 55 segments are used The serial data shown below (the D1 to D54 display data and the control data) must always be sent. 8 bit 0 1 0 0 0 1 0 1 72 bit D1 D2 D47 D48 D49 D50 D51 D52 D53 D54 0 0 0 0 0 0 0 P0 P1 P2 DT FC0 FC1 FC2 0C SC BU 0 B0 B1 B2 B3 A0 A1 A2 A3 No.A0712-11/22 LC75832E, 75832W Serial Data Transfer Example (When in 822 mode data transfer) (1) Static drive mode The serial data shown in the figure below must be sent. 8 bit 0 1 0 0 0 1 0 1 56 bit D1 D2 D17 D18 D19 D20 D21 D22 D23 D25 D26 D27 D28 D29 D30 D31 D32 D50 D51 D52 D53 D54 DT 0 0 B0 B1 B2 B3 A0 A1 A2 A3 (2) 1/2 duty drive mode • When 53 or more segments are used 128 bits of serial data (including CCB address bits) must be sent. 56 bit 8 bit 0 1 0 0 0 1 0 1 D1 D2 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D49 D50 D51 D52 D53 D54 0 DT 0 0 D55 D56 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96 D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 1 0 1 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 • When fewer than 53 segments are used The serial data shown in the figure below (the D1 to D46 and D49 to D54 display data, and the control data) must be sent. 8 bit 0 1 0 0 0 1 0 1 56 bit D1 D2 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D49 D50 D51 D52 D53 D54 0 DT 0 0 B0 B1 B2 B3 A0 A1 A2 A3 No.A0712-12/22 LC75832E, 75832W Control Data Functions 1. P0 to P2: Segment output port/general-purpose output port switching control data These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to S4/P4 output pins. However, segment output port is forcibly selected when in 822 mode data transfer. Control data Output pin state P0 P1 P2 S1/P1 S2/P2 S3/P3 S4/P4 0 0 0 S1 S2 S3 S4 0 0 1 P1 S2 S3 S4 0 1 0 P1 P2 S3 S4 0 1 1 P1 P2 P3 S4 1 0 0 P1 P2 P3 P4 Note: Sn (n = 1 to 4): Segment output ports Pn (n = 1 to 4): General-purpose output ports Note that when the general-purpose output port function is selected, the correspondence between the output pins and the display data will be that shown in the table. Corresponding display data Output pin Static drive mode 1/2 duty drive mode S1/P1 D1 D1 S2/P2 D2 D3 S3/P3 D3 D5 S4/P4 D4 D7 For example, if the general-purpose output port function is selected for the S4/P4 output pin in 1/2 duty drive mode, it will output a high level (VLCD) when display data D7 is 1, and a low level (VSS) when D7 is 0. 2. DT: Static drive mode/1/2 duty drive mode switching control data This control data bit selects either static drive mode or 1/2 duty drive mode. DT Duty drive mode Output pin state (COM2) 0 Static drive mode VSS level 1 1/2 duty drive mode COM2 3. FC0 to FC2: Common/segment output waveform frame frequency control data These control data bits set the frame frequency of the common and segment output waveforms. However, fo=fosc/384 is forcibly selected when in 822 mode data transfer. Control data Frame frequency fo [Hz] FC0 FC1 FC2 1 1 0 fosc/768, fCK/768 1 1 1 fosc/576, fCK/576 0 0 0 fosc/384, fCK/384 0 0 1 fosc/288, fCK/288 0 1 0 fosc/192, fCK/192 4. OC: RC oscillator operating mode/external clock operating mode switching control data. This control data bit switches the OSC pin function (either RC oscillator operating mode or external clock operating mode). However RC oscillator operating mode is forcibly selected when in 822 mode data transfer. OC OSC pin function 0 RC oscillator operating mode 1 External clock operating mode Note: An external resistor, Rosc, and an external capacitor, Cosc, must be connected to the OSC pin if RC oscillator operating mode is selected. No.A0712-13/22 LC75832E, 75832W 5. SC: Segment on/off control data This control data bit controls the on/off state of the segments. However, the segment on state is forcibly selected when in 822 mode data transfer. SC Display state 0 On 1 Off Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 6. BU: Normal mode/power-saving mode control data This control data bit selects either normal mode or power-saving mode. However, the normal mode is forcibly selected when in 822 mode data transfer. BU 0 Mode Normal mode Power-saving mode. In RC oscillator operating mode (OC = 0), the OSC pin oscillator is stopped, and in external clock operating mode 1 (OC = 1), acceptance of the external clock is stopped. In this mode the common and segment output pins go to the VSS levels. However, S1/P1 to S4/P4 output pins that are set to be general-purpose output ports by the control data P0 to P2 can be used as general-purpose output ports. No.A0712-14/22 LC75832E, 75832W Display Data and Output Pin Correspondence (1) Static drive mode Output pin COM1 Output pin COM1 Output pin COM1 S1/P1 D1 S21 D21 S41 D41 S2/P2 D2 S22 D22 S42 D42 S3/P3 D3 S23 D23 S43 D43 S4/P4 D4 S24 D24 S44 D44 S5 D5 S25 D25 S45 D45 S6 D6 S26 D26 S46 D46 S7 D7 S27 D27 S47 D47 S8 D8 S28 D28 S48 D48 S9 D9 S29 D29 S49 D49 S10 D10 S30 D30 S50 D50 S11 D11 S31 D31 S51 D51 S12 D12 S32 D32 S52 D52 S13 D13 S33 D33 S53 D53 S14 D14 S34 D34 S54 D54 S15 D15 S35 D35 S16 D16 S36 D36 S17 D17 S37 D37 S18 D18 S38 D38 S19 D19 S39 D39 S20 D20 S40 D40 Note 1: This applies to the case where the S1/P1 to S4/P4 output pins are set to be segment output ports. Note 2: The S24 output pin outputs a low level (VSS level) when in 822 mode data transfer. For example, the table below lists the output states for the S21 output pin. Display data Output pin (S21) state D21 0 The LCD segment corresponding to COM1 is off 1 The LCD segment corresponding to COM1 is on No.A0712-15/22 LC75832E, 75832W (2)1/2 duty drive mode Output pin COM1 COM2 Output pin COM1 COM2 Output pin COM1 COM2 S1/P1 D1 D2 S21 D41 D42 S41 D81 D82 S2/P2 D3 D4 S22 D43 D44 S42 D83 D84 S3/P3 D5 D6 S23 D45 D46 S43 D85 D86 S4/P4 D7 D8 S24 D47 D48 S44 D87 D88 S5 D9 D10 S25 D49 D50 S45 D89 D90 S6 D11 D12 S26 D51 D52 S46 D91 D92 S7 D13 D14 S27 D53 D54 S47 D93 D94 S8 D15 D16 S28 D55 D56 S48 D95 D96 S9 D17 D18 S29 D57 D58 S49 D97 D98 S10 D19 D20 S30 D59 D60 S50 D99 D100 S11 D21 D22 S31 D61 D62 S51 D101 D102 S12 D23 D24 S32 D63 D64 S52 D103 D104 S13 D25 D26 S33 D65 D66 S53 D105 D106 S54 D107 D108 S14 D27 D28 S34 D67 D68 S15 D29 D30 S35 D69 D70 S16 D31 D32 S36 D71 D72 S17 D33 D34 S37 D73 D74 S18 D35 D36 S38 D75 D76 S19 D37 D38 S39 D77 D78 S20 D39 D40 S40 D79 D80 Note 1: Applies when the S1/P1 to S4/P4 output pins are to their segment output function. Note 2: The S24 output pin outputs a low level (VSS level) when in 822 mode data transfer. Note 3: The S54 output pin outputs an all-segment-on waveform when in 822 mode data transfer. For example, the table below lists the output states for the S21 output pin. Display data Output pin (S21) state D41 D42 0 0 The LCD segments corresponding to COM1 and COM2 are off 0 1 The LCD segment corresponding to COM2 is on 1 0 The LCD segment corresponding to COM1 is on 1 1 The LCD segments corresponding to COM1 and COM2 are on No.A0712-16/22 LC75832E, 75832W Output Waveforms (Static drive mode) fo[Hz] VLCD COM1 0V VLCD LCD driver output when off 0V VLCD LCD driver output when on 0V Output Waveforms (1/2 duty, 1/2 bias drive mode) fo[Hz] COM1 VLCD 1/2VLCD 0V COM2 VLCD 1/2VLCD 0V VLCD LCD driver output when all LCD segments corresponding to COM1 and COM2 are off. 0V VLCD LCD driver output when only LCD segments corresponding to COM1 are on. 0V VLCD LCD driver output when only LCD segments corresponding to COM2 are on. 0V VLCD LCD driver output when LCD segments corresponding to COM1 and COM2 are on. 0V Control data Frame frequency fo [Hz] FC0 FC1 FC2 1 1 0 fosc/768, fCK/768 1 1 1 fosc/576, fCK/576 0 0 0 fosc/384, fCK/384 0 0 1 fosc/288, fCK/288 0 1 0 fosc/192, fCK/192 No.A0712-17/22 LC75832E, 75832W Display Control and the INH Pin Since the IC's internal data (the display data D1 to D54 and the control data when in static drive mode, and the display data D1 to D108 and the control data when in 1/2 duty drive mode) is undefined when power is first applied, applications should set the INH pin low at the same time as power is applied to turn off the display (setting S1/P1 to S4/P4 and S5 to S54, COM1, and COM2 to the VSS level) and during this period send serial data from the controller. The controller should then set the INH pin high after the data transfer has completed. This procedure prevents unnecessary display at power on (See Figures 4 to 7). Notes on the Power On/Off Sequences Applications should observe the following sequence when turning the LC75832E and LC75832W power on and off. (See Figures 4 to 7): • At power on: Logic block power supply (VDD) on → LCD driver block power supply (VLCD) on • At power off: LCD driver block power supply (VLCD) off → Logic block power supply (VDD) off However, if the logic and LCD driver block use a shared power supply, then power supplies can be turned on and off at the same time. • Static drive mode t2 t1 ≈ t3 ≈ VDD ≈ VLCD INH VIL1 VIL1 Display data and control data transferred D1 to D54,P0 to P2, Internal data DT, FC0 to FC2, OC, SC, BU Undefined ≈ ≈ ≈ tc CE Defined Undefined Notes: t1≥0 t2>0 t3≥0 (t2>t3) tc ⋅⋅⋅ 10μs min Figure 4 • Static drive mode (when in 822 mode data transfer) t2 ≈ t1 t3 ≈ VDD ≈ VLCD INH VIL1 D1 to D23, Internal data D25 to D54, DT VIL1 Display data and control data transferred Undefined Figure 5 ≈ ≈ ≈ tc CE Defined Undefined Notes: t1≥0 t2>0 t3≥0 (t2>t3) tc ⋅⋅⋅ 10μs min No.A0712-18/22 LC75832E, 75832W • 1/2 duty drive mode t2 t3 ≈ t1 ≈ VDD ≈ VLCD INH VIL1 CE D1 to D54, P0 to P2, Internal data DT, FC0 to FC2, OC, SC, BU VIL1 Display data and control data transferred Undefined Internal data (D55 to D108) Defined Undefined ≈ ≈ ≈ ≈ ≈ tc Undefined Defined Undefined Notes: t1≥0 t2>0 t3≥0 (t2>t3) tc ⋅⋅⋅ 10μs min Figure 6 1/2 duty drive mode (when in 822 mode data transfer) t2 ≈ t1 t3 ≈ VDD ≈ VLCD INH VIL1 tc CE Internal data (D55 to D106) Display data and control data transferred ≈ ≈ ≈ ≈ ≈ Internal data D1 to D46, D49 to D54, DT VIL1 Defined Undefined Undefined Figure 7 Defined Undefined Undefined Notes: t1≥0 t2>0 t3≥0 (t2>t3) tc ⋅⋅⋅ 10μs min No.A0712-19/22 LC75832E, 75832W Notes on Controller Transfer of Display Data Since the LC75832E/W transfer the display data (D1 to D108) in two separate transfer operations in 1/2 duty drive mode, we recommend that applications make a point of completing all of the display data transfer within a period of less than 30 ms to prevent observable degradation of display quality. OSC Pin Peripheral Circuit (1) RC oscillator operating mode (control data OC = 0) An external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and GND if RC oscillator operating mode is selected. OSC Rosc Cosc (2) External clock operating mode (control data OC = 1) When the external clock operating mode is selected, insert a current protection resistor Rg (4.7 to 47kΩ) between the OSC pin and external clock output pin (external oscillator). Determine the value of the resistance according to the allowable current value at the external clock output pin. Also make sure that the waveform of the external clock is not heavily distorted. External clock output pin OSC Rg External oscillator Note: Allowable current value at external clock output pin > VDD Rg No.A0712-20/22 LC75832E, 75832W Sample Application Circuit 1 (P1) Static drive mode (P2) (P3) *3 (P4) +3.3V VDD OSC *2 General-purpose Output ports Used for functions such as backlight control COM1 VSS LCD panel (up to 54 segments) P1/S1 P2/S2 +5V VLCD P3/S3 P4/S4 S5 INH From the controller S53 CE CL S54 DI COM2 OPEN *2: In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. If external clock operating mode is selected, a current protection resistor, Rg (4.7 to 47 kΩ), must be inserted between the external clock output pin (on the external oscillator) and the OSC pin. (See the “OSC Pin Peripheral Circuit” section.) *3: When a capacitor except the recommended external capacitance (Cosc = 1000pF) is connected to the OSC pin, it should be in the range 220 to 2200pF. (P1) Sample Application Circuit 2 (P2) 1/2 duty drive mode (P3) *3 (P4) +3.3V VDD OSC *2 General-purpose Output ports Used for functions such as backlight control COM1 COM2 P1/S1 +5V VLCD P2/S2 P3/S3 P4/S4 S5 INH From the controller CE S52 CL S53 DI S54 LCD panel (up to 108 segments) VSS *2: In RC oscillator operating mode, an external resistor, Rosc, and an external capacitor, Cosc, must be connected between the OSC pin and ground. If external clock operating mode is selected, a current protection resistor, Rg (4.7 to 47 kΩ), must be inserted between the external clock output pin (on the external oscillator) and the OSC pin. (See the “OSC Pin Peripheral Circuit” section.) *3: When a capacitor except the recommended external capacitance (Cosc = 1000pF) is connected to the OSC pin, it should be in the range 220 to 2200pF. No.A0712-21/22 LC75832E, 75832W ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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