Ordering number : ENA1909A
LC87F1M16A
CMOS IC
16K-byte FROM and 1024-byte RAM integrated
8-bit 1-chip Microcontroller
with Full-Speed USB
Overview
The LC87F1M16A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 16K-byte flash ROM (onboard programmable),
1024-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit
timer (may be divided into 8-bit timers or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a timeof-day clock, two channels of synchronous SIO interface (with automatic block transmission/reception capabilities), an
asynchronous/synchronous SIO interface, a UART interface (full duplex), a UART interface with Smartcard interface
function (full duplex), a full-speed USB interface (function), a 12-bit 20-channel AD converter (12- or 8-bit resolution
selectable), 2 channels of 12-bit PWM, a system clock frequency divider, an internal reset and a 35-source 10-vector
interrupt feature.
Features
Flash ROM
• Capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5V
• Block-erasable in 128 byte units
• Writes data in 2-byte units
• 16384 × 8 bits
RAM
• 1024 × 9 bits
Bus Cycle Time
• 83.3ns (When CF=12MHz)
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
Ver.2.01
42011HKIM 20110311-S00003 No.A1909-1/32
LC87F1M16A
Minimum Instruction Cycle Time (tCYC)
• 250ns (When CF=12MHz)
Ports
• I/O ports
Ports whose I/O direction can be designated in 1-bit units 35 (P00 to P07, P10 to P17, P20 to P27, P31 to P34,
P70 to P73, PWM0, PWM1, XT2)
• USB ports
2 (D+, D-)
• Dedicated oscillator ports
2 (CF1, CF2)
• Input-only port (also used for oscillation)
1 (XT1)
• Reset pins
1 (RES)
• Dedicated debugger port
1 (OWP0)
• Power supply pins
6 (VSS1 to 3, VDD1 to 3)
Timers
• Timer 0: 16-bit timer/counter with 2 capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(lower-order 8 bits may be used as a PWM output)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
(1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
(2) Interrupts programmable in 5 different time schemes
SIO
• SIO0: Synchronous serial interface
(1) LSB first/MSB first mode selectable
(2) Transfer clock cycle: 4/3 to 512/3 tCYC
(3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units)
(Suspension and resumption of data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO4: Synchronous serial interface
(1) LSB first/MSB first mode selectable
(2) Transfer clock cycle: 4/3 to 1020/3 tCYC
(3) Automatic continuous data transmission (1 to 1024 bytes, specifiable in 1 byte units, suspension and resumption
of data transmission possible in 1 byte or 2 bytes units)
(4) Clock polarity selectable
(5) CRC16 calculator circuit built in
No.A1909-2/32
LC87F1M16A
Full Duplex UART
• UART1
(1) Data length : 7/8/9 bits selectable
(2) Stop bits
: 1 bit (2 bits in continuous transmission mode)
(3) Baud rate
: 16/3 to 8192/3 tCYC
• SCUART
(1) Data length : 7/8 bits selectable
(2) Stop bits
: 1/2 bits selectable
(3) Parity bits : None/even parity/odd parity
(4) Baud rate
: 8/3 to 8192/3 tCYC
(5) LSB first/MSB first mode delectable
(6) Smartcard interface function
AD Converter: 12 bits × 20 channels
• 12-/8-bit resolution selectable AD converter
PWM: Multifrequency 12-bit PWM × 2 channels
USB Interface (function controller)
(1) Compliant with USB 2.0 Full-Speed
(2) Supports a maximum of 6 user-defined endpoints.
EP0
EP1
EP2
EP3
EP4
EP5
Control
{
-
-
-
-
-
-
Bulk
-
{
{
{
{
{
{
Endpoint
Transfer
Type
EP6
Interrupt
-
{
{
{
{
{
{
Isochronous
-
{
{
{
{
{
{
64
64
64
64
64
64
64
Max. payload
Watchdog Timer
• Internal counter watchdog timer
(1) Generates an internal reset on an overflow occurring in the timer running on the low-speed RC oscillator clock
(approx. 30kHz) or subclock.
(2) Operating mode at HALT/HOLD mode is selectable from 3 modes
(continue counting/suspend operation/suspend counting with the count value retained)
Clock Output Function
(1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected
as the system clock.
(2) Can output the source oscillation clock for the subclock.
No.A1909-3/32
LC87F1M16A
Interrupts
• 35 sources, 10 vector addresses
(1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
(2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/USB bus active
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
7
00033H
H or L
T1L/T1H/INT7
SIO0/USB bus reset/USB suspend/UART1 receive complete/
SCUART receive complete
SIO1/USB endpoint/USB-SOF/SIO4/
8
0003BH
H or L
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/PWM0/PWM1/T4/T5
UART1 buffer empty/UART1 transmit complete/
SCUART buffer empty/SCUART transmit complete
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 512 levels maximum (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
( 5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
( 8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
Oscillation and PLL Circuits
• RC oscillation circuit (internal)
• Low-speed RC oscillation circuit (internal)
• CF oscillation circuit
• Crystal oscillation circuit
• PLL circuit (internal)
: For system clock (approx. 1MHz)
: For watchdog timer (approx. 30kHz)
: For system clock
: For system clock, time-of-day clock
: For USB interface (see Fig.5)
Internal Reset Circuit
•Power-on reset (POR) function
(1) POR reset is generated only at power-on time.
(2) The POR release level can be selected from 4 levels (2.57V, 2.87V, 3.86V and 4.35V) through option
configuration.
•Low-voltage detection reset (LVD) function
(1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
(2) The use/disuse of the LVD function and the voltage threshold level can be selected from 3 levels (2.81V, 3.79V
and 4.28V) through option configuration.
No.A1909-4/32
LC87F1M16A
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
(1) Oscillation is not halted automatically.
(2) There are three ways of resetting the HOLD mode.
1) Setting the reset pin to the lower level
2) Having the watchdog timer or LVD function generate a reset
3) Having an interrupt generated
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
(1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation.
Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby
mode is also controlled by the watchdog timer.
(2) There are five ways of resetting the HOLD mode.
1) Setting the reset pin to the lower level
2) Having the watchdog timer or LVD function generate a reset
3) Having an interrupt source established at one of the INT0, INT1, INT2, INT4 or INT5 pins
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
4) Having an interrupt source established at port 0
5) Having an bus active interrupt source established in the USB interface circuit
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
(1) The PLL base clock generator, CF and RC oscillator automatically stop operation.
Note: The low-speed RC oscillator is controlled directly by the watchdog timer; its oscillation in the standby
mode is also controlled by the watchdog timer.
(2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
(3) There are six ways of resetting the X'tal HOLD mode.
1) Setting the reset pin to the low level
2) Having the watchdog timer or LVD function generate a reset
3) Having an interrupt source established at either INT0, INT1, INT2, INT4 or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
4) Having an interrupt source established at port 0
5) Having an interrupt source established in the base timer circuit
6) Having an bus active interrupt source established in the USB interface circuit
Package Form
• SQFP48 (7×7): Lead-/Halogen-free type
Development Tools
• On-chip debugger: TCB87 type-C (one wire communication cable) + LC87F1M16A
No.A1909-5/32
LC87F1M16A
Flash ROM Programming Boards
Package
Programming boards
SQFP48(7×7)
W87F55256SQ
Flash Programmer
Maker
Flash Support
Group, Inc.
(FSG)
Model
Single
Programmer
Flash Support
Group, Inc.
(FSG)
+
Sanyo
Supported version
Device
Rev 03.32 or later
87F016JU
(Note 2)
LC87F1M16A
AF9709/AF9709B/AF9709C
(Including Ando Electric Co., Ltd.
models)
AF9101/AF9103(Main unit)
Onboard
Single/Gang
Programmer
(FSG models)
SIB87(Inter Face Driver)
(Sanyo model)
(Note 1)
Sanyo
Single/Gang
SKK/SKK Type B
Programmer
(SanyoFWS)
Onboard
Single/Gang
Programmer
Application Version
1.06 or later
SKK-DBG Type C
Chip Data Version
(SanyoFWS)
2.31 or later
LC87F1M16
For information about AF-Series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: [email protected]
Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from SANYO (SIB87)
together can give a PC-less, standalone on-board-programming capabilities.
Note2: It needs a special programming devices and applications depending on the use of programming environment.
Please ask FSG or SANYO for the information.
No.A1909-6/32
LC87F1M16A
Package Dimensions
unit : mm (typ)
3163B
36
0.5
9.0
7.0
25
24
48
13
7.0
9.0
37
1
12
0.5
0.15
0.18
(1.5)
0.1
1.7max
(0.75)
SANYO : SQFP48(7X7)
36
35
34
33
32
31
30
29
28
27
26
25
P27/INT5/AN19/DPUP2
P26/INT5/AN18
P25/INT5/AN17
P24/INT5/INT7/AN16/SCK4
P23/INT4/AN15/SI4
P22/INT4/AN14/SO4
P21/INT4/AN13/URX1
P20/INT4/INT6/AN12/UTX1
P07/AN7/T7O
P06/AN6/T6O
P05/AN5/CKO
P04/AN4
Pin Assignment
LC87F1M16A
24
23
22
21
20
19
18
17
16
15
14
13
P03/AN3
P02/AN2/TDN2
P01/AN1/TDP1
P00/AN0/TDN1
VSS2
VDD2
PWM0/AN9/TDP0
PWM1/AN8/TDN0
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
1
2
3
4
5
6
7
8
9
10
11
12
37
38
39
40
41
42
43
44
45
46
47
48
P73/INT3/T0IN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
DD+
VDD3
VSS3
P34/UFILT
P33
P32/SCRX
P31/SCTX
OWP0
P70/INT0/T0LCP/DPUP
P71/INT1/T0HCP
P72/INT2/T0IN
Top view
SANYO: SQFP48(7×7)
“Lead-/Halogen-free Type”
No.A1909-7/32
LC87F1M16A
SQFP48
NAME
SQFP48
NAME
1
P73/INT3/T0IN
25
P04/AN4
2
RES
26
P05/AN5/CKO
3
XT1/AN10
27
P06/AN6/T6O
4
XT2/AN11
28
P07/AN7/T7O
5
VSS1
29
P20/INT4/INT6/AN12/UTX1
6
CF1
30
P21/INT4/AN13/URX1
P22/INT4/AN14/SO4
7
CF2
31
8
VDD1
32
P23/INT4/AN15/SI4
9
P10/SO0
33
P24/INT5/INT7/AN16/SCK4
10
P11/SI0/SB0
34
P25/INT5/AN17
11
P12/SCK0
35
P26/INT5/AN18
12
P13/SO1
36
P27/INT5/AN19/DPUP2
13
P14/SI1/SB1
37
D-
14
P15/SCK1
38
D+
15
P16/T1PWML
39
VDD3
16
P17/T1PWMH/BUZ
40
VSS3
17
PWM1/AN8/TDN0
41
P34/UFILT
18
PWM0/AN9/TDP0
42
P33
19
VDD2
43
P32/SCRX
20
VSS2
44
P31/SCTX
21
P00/AN0/TDN1
45
OWP0
22
P01/AN1/TDP1
46
P70/INT0/T0LCP/DPUP
23
P02/AN2/TDN2
47
P71/INT1/T0HCP
24
P03/AN3
48
P72/INT2/T0IN
No.A1909-8/32
LC87F1M16A
System Block Diagram
Interrupt control
Standby control
CF
USB PLL
RC
Clock
generator
X’tal
PLA
IR
FROM
PC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
SIO4
Port 1
C register
Timer 0
Port 2
ALU
Timer 1
Port 3
Timer 4
Port 7
Timer 5
INT0 to INT7
Noise filter
RAR
Timer 6
UART1
RAM
Timer 7
SCUART
Stack pointer
Base timer
ADC
Watchdog timer
PWM0
USB interface
PSW
On-chip debugger
PWM1
High current driver
No.A1909-9/32
LC87F1M16A
Pin Description
Pin Name
I/O
Description
Option
VSS1,VSS2,
VSS3
-
- Power supply
No
VDD1, VDD2
-
+ Power supply
No
VDD3
-
USB reference voltage
Yes
Port 0
I/O
• 8-bit I/O ports
Yes
• I/O specifiable in 1-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 1-bit units
• HOLD reset input
• Port 0 interrupt input
• Pin functions
AD converter input ports: AN0 to AN7(P00 to P07)
P00: High current Nch driver(TDN1)
P01: High current Pch driver(TDP1)
P02: High current Nch driver(TDN2)
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/beeper output
Port 2
I/O
• 8-bit I/O ports
Yes
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistors can be turned on and off in 1-bit units
• Pin functions
AD converter input ports: AN12 to AN19(P20 to P27)
P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P20: INT6 input/timer 0L capture 1 input/UART1 transmit
P21: UART1 receive
P22: SIO4 date I/O
P23: SIO4 date I/O
P24: INT7 input/timer 0H capture 1 input/SIO4 clock I/O
P27: D+ 1.5kΩ pull-up resistor connect pin
Interrupt acknowledge types
Port 3
P31 to P34
I/O
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising &
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 4-bit I/O ports
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units
• Pin functions
P31: SCUART transmit
P32: SCUART receive
P34: USB interface PLL filter pin (see Fig. 5.)
Continued on next page.
No.A1909-10/32
LC87F1M16A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units
• Pin functions
P70: INT0 input/HOLD reset input/timer 0L capture input/ D+ 1.5kΩ pull-up resistor connect pin
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (input with noise filter)/timer 0 event input/timer 0H capture input
Interrupt acknowledge types
INT0
PWM0
I/O
Rising &
Rising
Falling
enable
enable
disable
Falling
H level
L level
enable
enable
INT1
enable
enable
disable
enable
enable
INT2
enable
enable
enable
disable
disable
INT3
enable
enable
enable
disable
disable
• PWM0, PWM1 output port
No
• Pin functions
PWM1
General-purpose input ports
AD converter input ports: AN8(PWM1), AN9(PWM0)
PWM0: High current Pch driver(TDP0)
PWM1: High current Nch driver(TDN0)
D-
I/O
• USB data I/O pin D-
No
• General-purpose I/O port
D+
I/O
• USB data I/O pin D+
No
• General-purpose I/O port
RES
Input
External reset input/internal reset output pin
No
XT1
Input
• 32.768kHz crystal oscillator input
No
• Pin functions
General-purpose input port
AD converter input ports: AN10
XT2
I/O
• 32.768kHz crystal oscillator output
No
• Pin functions
General-purpose I/O
AD converter input port: AN11
CF1
Input
CF2
OWP0
Ceramic resonator input
No
Output
Ceramic resonator output
No
I/O
Dedicated debugger port
No
No.A1909-11/32
LC87F1M16A
On-chip Debugger Pin Connection Requirements
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled “Rd87 On-chip
Debugger Installation Manual”
Recommended Unused Pin Connections
Recommended Unused Pin Connections
Port Name
Board
Software
P00 to P07
Open
Output low
P10 to P17
Open
Output low
P20 to P27
Open
Output low
P31 to P34
Open
Output low
P70 to P73
Open
Output low
PWM0, PWM1
Open
Output low
D+, D-
Open
Output low
XT1
Pulled low with a 100kΩ resistor or less
-
XT2
Open
Output low
OWP0
Pulled low with a 100kΩ resistor
-
Note: P34 and UFILT share the same pin, so if USB function is used, the pin must be set to input mode.
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
Option selected in
units of
1 bit
Option type
Output type
Pull-up resistor
1
CMOS
Programmable
2
Nch-open drain
Programmable
P10 to P17
P20 to P27
P31 to P34
P70
-
No
Nch-open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
No
PWM0, PWM1
-
No
CMOS
D+, D-
-
No
CMOS
No
XT1
-
No
Input only
No
XT2
-
No
32.768kHz crystal resonator output (N channel open
No
drain when in general-purpose output mode)
No.A1909-12/32
LC87F1M16A
User Option Table
Option Name
Option Type
Flash Version
Option Selected in Units of
Port output form
Option Selection
CMOS
P00 to P07
enable
1 bit
P10 to P17
enable
1 bit
P20 to P27
enable
1 bit
P31 to P34
enable
1 bit
-
enable
-
Nch-open drain
CMOS
Nch-open drain
CMOS
Nch-open drain
CMOS
Program start
address
00000h
USB Regulator
USB Regulator
(at HOLD mode)
USB Regulator
(at HALT mode)
enable
-
enable
-
function
NONUSE
USE
enable
-
NONUSE
ENABLE
-
enable
-
Low-voltage detection
Power-on reset
NONUSE
USE
Main clock 8MHz
reset function
03E00h
USE
USB Regulator
selection
Nch-open drain
DISABLE
Enable: Use
Detect function
enable
-
Detect level
enable
-
3-level
Power-On reset level
enable
-
4-level
Disable: Not Used
No.A1909-13/32
LC87F1M16A
USB Reference Power Option
When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the
reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be
switched by option select. The procedure for marking the option selection is described below.
(1)
Option settings
Reference voltage circuit state
(2)
(3)
(4)
USE
USE
NONUSE
NONUSE
NONUSE
NONUSE
USE
NONUSE
active
active
inactive
inactive
inactive
inactive
active
inactive
USB regulator
USE
USB regulator at HOLD mode
USE
USB regulator at HALT mode
USE
NONUSE
Normal mode
active
HOLD mode
active
HALT mode
active
inactive
• When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is
equal to VDD1.
• Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
• When the reference voltage circuit is activated, the current drain increases by approximately 100μA compared with
when the reference voltage circuit is inactive.
Example 1: VDD1=VDD2=3.3V
• Inactivating the reference voltage circuit (selection (4)).
• Connecting VDD3 to VDD1 and VDD2.
LSI
P70/P27
1.5kΩ
Power supply
3.3V
VDD1
VDD2
VDD3
D+
To USB connector
27 to 33Ω
D-
UFILT
5pF
2.2μF
0Ω
VSS1 VSS2 VSS3
2.2μF
Example 2: VDD1=VDD2=5.0V
• Activating the reference voltage circuit (selection (1)).
• Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS.
LSI
P70/P27
1.5kΩ
Power supply
5V
VDD1
D+
To USB connector
27 to 33Ω
DVDD2
5pF
VDD3
2.2μF
UFILT
0Ω
0.1µF
VSS1 VSS2 VSS3
2.2μF
No.A1909-14/32
LC87F1M16A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Maximum supply
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
XT1, CF1, RES
Input/output
VIO(1)
Ports 0, 1, 2, 3, 7
VDD1= VDD2= VDD3
voltage
voltage
PWM0, PWM1
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
unit
V
XT2
Peak output
IOPH(1)
current
P00, P02 to P07
Ports 1, 2
• When CMOS output
type is selected
-10
• Per 1 applicable pin
IOPH(2)
PWM1
Per 1 applicable pin
IOPH(3)
PWM0(TDP0)
• When CMOS output
P01(TDP1)
type is selected
-20
-50
• Per 1 applicable pin
IOPH(4)
Port 3
P71 to P73
• When CMOS output
type is selected
-5
• Per 1 applicable pin
Average
IOMH(1)
High level output current
output current
P00, P02 to P07
Ports 1, 2
(Note 1-1)
• When CMOS output
type is selected
-7.5
• Per 1 applicable pin
IOMH(2)
PWM1
Per 1 applicable pin
IOMH(3)
PWM0(TDP0)
• When CMOS output
P01(TDP1)
type is selected
-15
-30
mA
• Per 1 applicable pin
IOMH(4)
Port 3
P71 to P73
• When CMOS output
type is selected
-3
• Per 1 applicable pin
Total output
ΣIOAH(1)
current
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
ΣIOAH(6)
P00, P02 to P07
Total current of all
Ports 2
applicable pins
Port 1
Total current of all
PWM1
applicable pins
PWM0(TDP0)
Total current of all
P01(TDP1)
applicable pins
Ports 0, 1, 2
Total current of all
PWM0, PWM1
applicable pins
Port 3
Total current of all
P71 to P73
applicable pins
D+, D-
Total current of all
applicable pins
-25
-25
-50
-100
-10
-25
Note 1-1: The average output current is an average of current values measured over 100ms intervals.
Continued on next page.
No.A1909-15/32
LC87F1M16A
Continued from preceding page.
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Peak output
IOPL(1)
current
P03 to P07
min
typ
max
unit
Per 1 applicable pin
Ports 1, 2
20
PWM0
IOPL(2)
P01
Per 1 applicable pin
IOPL(3)
PWM1(TDN0)
Per 1 applicable pin
30
P00(TDN1)
50
P02(TDN2)
IOPL(4)
Ports 3, 7
Per 1 applicable pin
10
XT2
Low level output current
Average
IOML(1)
P03 to P07
output current
Ports 1, 2
(Note 1-1)
PWM0
Per 1 applicable pin
15
IOML(2)
P01
Per 1 applicable pin
IOML(3)
PWM1(TDN0)
Per 1 applicable pin
20
P00(TDN1)
30
mA
P02(TDN2)
IOML(4)
Ports 3, 7
Per 1 applicable pin
7.5
XT2
Total output
ΣIOAL(1)
current
ΣIOAL(2)
ΣIOAL(3)
P01, P03 to P07
Total current of all
Ports 2
applicable pins
Port 1
Total current of all
PWM0
applicable pins
PWM1(TDN0)
Total current of all
P00(TDN1)
applicable pins
45
45
50
P02(TDN2)
ΣIOAL(4)
ΣIOAL(5)
ΣIOAL(6)
Ports 0, 1, 2
Total current of all
PWM0, PWM1
applicable pins
Ports 3, 7
Total current of all
XT2
applicable pins
D+, D-
Total current of all
140
15
25
applicable pins
Allowable power
Pd max
Dissipation
Operating ambient
Topr
Temperature
Storage ambient
temperature
Tstg
SQFP48(7×7)
Ta=-30 to +70°C
190
Ta=-40 to +85°C
140
-40
+85
-55
+125
mW
°C
Note 1-1: The average output current is an average of current values measured over 100ms intervals.
No.A1909-16/32
LC87F1M16A
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Operating
Symbol
VDD(1)
Pin/Remarks
VDD1=VDD2=VDD3
Conditions
Specification
VDD[V]
0.245μs ≤ tCYC ≤ 200μs
supply voltage
0.490μs ≤ tCYC ≤ 200μs Except
(Note 2-1)
in onboard programming mode
0.245μs ≤ CYC ≤ 0.383μs
USB circuit active
Memory
VHD
VDD1=VDD2=VDD3
sustaining
min
typ
unit
max
3.0
5.5
2.7
5.5
3.0
5.5
2.0
5.5
RAM and register contents
sustained in HOLD mode.
supply voltage
High level
VIH(1)
input voltage
Low level
Port 0, 1, 2, 3, 7
2.7 to 5.5
PWM0, PWM1
VIH(2)
XT1, XT2, CF1,RES
VIL(1)
Port 1, 2, 3, 7
input voltage
VIL(2)
VIL(3)
Port 0
PWM0, PWM1
VIL(4)
VIL(5)
Instruction
XT1, XT2, CF1,RES
tCYC
cycle time
Except for onboard programming
(Note 2-2)
mode
USB circuit active
External
FEXCF(1)
CF1
0.3VDD
VDD
+0.7
2.7 to 5.5
0.75VDD
4.0 to 5.5
VSS
2.7 to 4.0
VSS
4.0 to 5.5
VSS
2.7 to 4.0
VSS
0.2VDD
V
VDD
0.1VDD
+0.4
0.2VDD
0.15VDD
+0.4
2.7 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.245
200
2.7 to 5.5
0.490
200
3.0 to 5.5
0.245
0.383
3.0 to 5.5
0.1
12
μs
• CF2 pin open
• System clock frequency
system clock
frequency
division ratio=1/1
• External system clock duty
=50±5%
MHz
• CF2 pin open
• System clock frequency
division ratio=1/1
2.7 to 5.5
0.1
6
• External system clock duty
=50±5%
Oscillation
FmCF
CF1, CF2
frequency
range
(Note 2-3)
When 12MHz ceramic oscillation
See Fig. 1.
FmRC
FmSLRC
FsX’tal
XT1, XT2
3.0 to 5.5
12
MHz
Internal RC oscillation
2.7 to 5.5
0.5
1.0
2.0
Internal low-speed RC oscillation
2.7 to 5.5
15
30
60
32.768kHz crystal oscillation
See Fig. 2.
kHz
2.7 to 5.5
32.768
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A1909-17/32
LC87F1M16A
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 2, 3, 7
Output disabled
RES
Pull-up resistor off
PWM0, PWM1
VIN=VDD
(Including output Tr's off leakage
D+, D-
min
typ
max
2.7 to 5.5
1
2.7 to 5.5
1
2.7 to 5.5
15
unit
current)
IIH(2)
XT1, XT2
Input port configuration
VIN=VDD
Low level input
IIH(3)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3, 7
Output disabled
RES
PWM0, PWM1
Pull-up resistor off
current
D+, D-
VIN=VSS
(Including output Tr's off leakage
2.7 to 5.5
-1
2.7 to 5.5
-1
-15
μA
current)
IIL(2)
XT1, XT2
Input port configuration
VIN=VSS
IIL(3)
CF1
VIN=VSS
2.7 to 5.5
High level output
VOH(1)
Ports 0, 1, 2, 3
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
P71 to P73
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
VOH(3)
VOH(4)
VOH(5)
PWM0, WM1
P05(CKO when
using system clock
IOH=-0.2mA
2.7 to 5.5
VDD-0.4
IOH=-10mA
4.5 to 5.5
VDD-1.5
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
2.7 to 5.5
VDD-0.4
4.5 to 5.5
VDD-0.5
VOH(6)
output function)
IOH=-1mA
VOH(7)
PWM0, P01
IOH=-30mA
(when using high
VDD-0.15
current driver)
P00, P01
Low level output
VOL(1)
IOL=30mA
4.5 to 5.5
1.5
voltage
VOL(2)
IOL=5mA
3.0 to 5.5
0.4
VOL(3)
IOL=2.5mA
2.7 to 5.5
0.4
VOL(4)
Ports 0, 1, 2
IOL=10mA
4.5 to 5.5
1.5
VOL(5)
PWM0, PWM1
IOL=1.6mA
3.0 to 5.5
0.4
VOL(6)
VOL(7)
XT2
Ports 3, 7
VOL(8)
VOL(9)
PWM1, P00, P02
IOL=1mA
2.7 to 5.5
0.4
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
0.4
V
IOL=30mA
4.5 to 5.5
(when using high
0.15
0.5
current driver)
Pull-up resistance
Rpu(1)
Ports 0, 1, 2, 3, 7
VOH=0.9VDD
Rpu(2)
Hysteresis voltage
VHYS
RES
Port 1, 2, 3, 7
Pin capacitance
CP
All pins
4.5 to 5.5
15
35
80
2.7 to 5.5
18
50
150
kΩ
2.7 to 5.5
0.1VDD
V
2.7 to 5.5
10
pF
For pins other than that under
test:
VIN=VSS
f=1MHz
Ta=25°C
No.A1909-18/32
LC87F1M16A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Pin/
SCK0(P12)
Specification
Conditions
Remarks
VDD[V]
See Fig. 8.
typ
max
unit
2
1
pulse width
High level
min
tSCKH(1)
1
pulse width
• Continuous data transmission/
tSCKHA(1a)
reception mode
• USB nor SIO4 are not in use
4
simultaneous.
Input clock
• See Fig. 8.
• (Note 4-1-2)
• Continuous data transmission/
tSCKHA(1b)
2.7 to 5.5
tCYC
reception mode
• USB is in use simultaneous
7
• SIO4 is not in use simultaneous.
• See Fig. 8.
• (Note 4-1-2)
• Continuous data transmission/
tSCKHA(1c)
reception mode
• USB and SIO4 are in use
9
simultaneous.
Serial clock
• See Fig. 8.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 8.
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
pulse width
tSCKHA(2a)
• Continuous data transmission/
reception mode
• USB nor SIO4 are not in use
tSCKH(2)
+2tCYC
Output clock
simultaneous.
• CMOS output selected
• See Fig. 8.
tSCKHA(2b)
• Continuous data transmission/
• SIO4 is not in use simultaneous.
+(10/3)
tCYC
2.7 to 5.5
reception mode
• USB is in use simultaneous
tSCKH(2)
tSCKH(2)
+2tCYC
• CMOS output selected
tSCKH(2)
+(19/3)
tCYC
tCYC
• See Fig. 8.
tSCKHA(2c)
• Continuous data transmission/
reception mode
• USB and SIO4 are in use
simultaneous.
• CMOS output selected
tSCKH(2)
+2tCYC
tSCKH(2)
+(25/3)
tCYC
• See Fig. 8.
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Continued on next page.
No.A1909-19/32
LC87F1M16A
Continued from preceding page.
Parameter
Serial input
Data setup time
tsDI(1)
Pin/
SB0(P11),
VDD[V]
min
typ
max
unit
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 8.
Data hold time
Specification
Conditions
Remarks
SI0(P11)
thDI(1)
0.03
2.7 to 5.5
0.03
Input clock
Output delay
tdD0(1)
SO0(P10),
SB0(P11)
time
• Continuous data transmission/
(1/3)tCYC
reception mode
+0.05
• (Note 4-1-3)
• Synchronous 8-bit mode
tdD0(2)
μs
1tCYC
• (Note 4-1-3)
+0.05
2.7 to 5.5
(Note 4-1-3)
tdD0(3)
Output clock
Serial output
Symbol
(1/3)tCYC
+0.05
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 8.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Pin/
SCK1(P15)
VDD[V]
min
See Fig. 8.
Frequency
tCYC
SCK1(P15)
• When CMOS output type is
• See Fig. 8.
tSCKL(4)
pulse width
High level
2
2.7 to 5.5
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
Data hold time
(1/3)tCYC
to rising edge of SIOCLK.
• See Fig. 8.
thDI(2)
+0.01
2.7 to 5.5
0.01
Output delay time
Serial output
tsDI(2)
unit
1
selected
Low level
max
1
tSCKH(3)
tSCK(4)
typ
2
2.7 to 5.5
pulse width
High level
Specification
Conditions
Remarks
pulse width
Output clock
Serial clock
Parameter
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
2.7 to 5.5
change in open drain output
(1/2)tCYC
+0.05
mode.
• See Fig. 8.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A1909-20/32
LC87F1M16A
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Parameter
Symbol
Frequency
tSCK(5)
Low level
tSCKL(5)
Pin/
SCK4(P24)
Specification
Conditions
Remarks
VDD[V]
See Fig.8.
typ
max
unit
2
1
pulse width
High level
min
tSCKH(5)
1
pulse width
tSCKHA(5a)
• USB nor continuous data
transmission/reception mode
of SIO0 are not in use
4
simultaneous.
Input clock
• See Fig.8.
• (Note 4-3-2)
tSCKHA(5b)
• USB is in use simultaneous.
2.7 to 5.5
tCYC
• Do not use SIO0 continuous
data transmission mode at the
7
same time.
• See Fig.8.
• (Note 4-3-2)
tSCKHA(5c)
• USB and continuous
data transmission/ reception
mode of SIO0 are in use
10
simultaneous.
Serial clock
• See Fig.8.
• (Note 4-3-2)
Frequency
tSCK(6)
SCK4(P24)
• CMOS output selected
4/3
• See Fig.8
Low level
tSCKL(6)
1/2
pulse width
High level
tSCK
tSCKH(6)
1/2
pulse width
tSCKHA(6a)
• USB nor continuous data
transmission/reception mode
of SIO0 are not in use
Output clock
simultaneous.
• CMOS output selected
• See Fig.8.
tSCKHA(6b)
• USB is in use simultaneous.
tSCKH(6)
tSCKH(6)
+(5/3)
+(10/3)
tCYC
tCYC
tSCKH(6)
tSCKH(6)
+(5/3)
+(19/3)
tCYC
tCYC
tSCKH(6)
tSCKH(6)
+(5/3)
+(28/3)
tCYC
tCYC
2.7 to 5.5
• Do not use SIO0 continuous
data transmission mode at the
same time.
• CMOS output selected
tCYC
• See Fig8.
tSCKHA(6c)
• USB and continuous
data transmission/reception
mode of SIO0 are in use
simultaneous.
• CMOS output selected
• See Fig.8.
Serial input
Data setup time
tsDI(3)
SO4(P22),
SI4(P23)
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
• See Fig.8.
Data hold time
μs
thDI(3)
2.7 to 5.5
0.03
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input in continuous trans/rec mode, a time from SI4RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Continued on next page.
No.A1909-21/32
LC87F1M16A
Continued from preceding page.
Parameter
Symbol
Output delay time
tdD0(5)
Pin/
SO4(P22),
Serial output
SI4(P23)
Specification
Conditions
Remarks
VDD[V]
min
typ
max
unit
• Must be specified with
respect to rising edge of
SIOCLK.
• Must be specified as the time
to the beginning of output state
(1/3)tCYC
2.7 to 5.5
+0.05
μs
change in open drain output
mode.
• See Fig.8.
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High/low level
tP1H(1)
INT0(P70), INT1(P71),
• Interrupt source flag can be set.
pulse width
tP1L(1)
INT2(P72),
• Event inputs for timer 0 or 1 are
INT4(P20 to P23),
enabled.
INT5(P24 to P27),
min
typ
2.7 to 5.5
1
2.7 to 5.5
2
2.7 to 5.5
64
2.7 to 5.5
256
2.7 to 5.5
200
max
unit
INT6(P20),
INT7(P24)
tPIH(2)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(2)
filter time constant is
• Event inputs for timer 0 are
1/1
tPIH(3)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(3)
filter time constant is
• Event inputs for timer 0 are
1/32
nabled.
tPIH(4)
INT3(P73) when noise
• Interrupt source flag can be set.
tPIL(4)
filter time constant is
• Event inputs for timer 0 are
1/128
tPIL(5)
RES
tCYC
enabled.
enabled.
Resetting is enabled.
μs
No.A1909-22/32
LC87F1M16A
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
<12-bits AD Converter Mode>
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07),
min
typ
3.0 to 5.5
(Note 6-1)
max
unit
12
bit
±16
3.0 to 5.5
accuracy
AN8(PWM1),
Conversion time
AN9(PWM0),
See conversion time calculation
4.5 to 5.5
32
115
AN10(XT1),
formulas. (Note 6-2)
3.0 to 5.5
64
115
3.0 to 5.5
VSS
VDD
TCAD
AN11(XT2),
Analog input
VAIN
voltage range
AN12(P20) to
LSB
μs
V
AN19(P27)
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
1
-1
μA
<8-bits AD Converter Mode>
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07),
min
typ
3.0 to 5.5
(Note 6-1)
max
unit
8
bit
±1.5
3.0 to 5.5
accuracy
AN8(PWM1),
Conversion time
AN9(PWM0),
See conversion time calculation
4.5 to 5.5
20
90
AN10(XT1),
formulas. (Note 6-2)
3.0 to 5.5
40
90
3.0 to 5.5
VSS
VDD
TCAD
AN11(XT2),
Analog input
VAIN
voltage range
AN12(P20) to
LSB
μs
V
AN19(P27)
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
1
-1
μA
Conversion time calculation formulas :
12-bits AD Converter Mode : TCAD (Conversion time) = ((52/(AD division ratio))+2) × (1/3) × tCYC
8-bits AD Converter Mode : TCAD (Conversion time) = ((32/(AD division ratio))+2) × (1/3) × tCYC
<Recommended Operating Conditions>
External
Supply Voltage
System Clock
oscillator
Range
Division
FmCF[MHz]
VDD[V]
(SYSDIV)
4.0 to 5.5
1/1
3.0 to 5.5
1/1
Cycle Time
tCYC [ns]
AD Frequency
Conversion Time (TCAD)[μs]
Division Ratio
(ADDIV)
12-bit AD
8-bit AD
250
1/8
34.8
21.5
250
1/16
69.5
42.8
12
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A1909-23/32
LC87F1M16A
Power-on Reset (POR) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Conditions
Option selected
voltage
POR release voltage
Detection voltage
PORRL
POUKS
unknown state
Power supply rise time
min
typ
unit
Select from option
2.57V
2.45
2.57
2.69
(Note 7-1)
2.87V
2.75
2.87
2.99
3.86V
3.73
3.86
3.99
4.35V
4.21
4.35
4.49
0.7
0.95
See Fig.11
(Note 7-2)
PORIS
max
Power supply rise time from 0V
100
to 1.6V
V
ms
Note 7-1: The POR release level can be selected out of 4 levels only when the LVD reset function is disabled.
Note 7-2: POR is in unknown state before transistor start operation.
Low Voltage Detection Reset (LVD) Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Conditions
Option selected
voltage
LVD reset voltage
LVDET
(Note 8-2)
LVUKS
Low voltage detection
minimum width
2.71
2.81
2.91
3.79V
3.69
3.79
3.89
4.28V
4.18
4.28
4.38
2.81V
V
55
3.79V
60
4.28V
60
See Fig.12
0.7
(Note 8-4)
TLVDW
unit
2.81V
LVHYS
unknown state
max
See Fig.12
(Note 8-3)
Detection voltage
typ
Select from option
(Note 8-1)
LVD hysteresis width
min
mV
0.95
V
LVDET-0.5V
See Fig.13
0.2
ms
(Reply sensitivity).
Note 8-1: The LVD reset level can be selected out of 3 levels only when the LVD reset function is enabled.
Note 8-2: LVD reset voltage specification values do not include hysteresis voltage.
Note 8-3: LVD reset voltage may exceed its specification values when port output state changes and and/or when a
large current flows through port.
Note 8-4: LVD is in unknown state before transistor start operation.
No.A1909-24/32
LC87F1M16A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/
VDD[V]
• FmCF=12MHz ceramic oscillation mode
consumption
VDD1
=VDD2
current
=VDD3
• System clock set to 12MHz side
Normal mode
IDDOP(1)
(Note 9-1)
(Note 9-2)
IDDOP(2)
Specification
Conditions
Remarks
• FsX'tal=32.768kHz crystal oscillation mode
min
typ
max
4.5 to 5.5
8.8
16
3.0 to 3.6
5.1
9.2
4.5 to 5.5
13
23
3.0 to 3.6
7.0
13
4.5 to 5.5
5.6
9.5
3.0 to 3.6
3.6
6.0
unit
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• USB circuit stopped
• 1/1 frequency division ratio
IDDOP(3)
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
IDDOP(4)
• Internal PLL oscillation mode active
• Internal RC oscillation stopped
• USB circuit active
mA
• 1/1 frequency division ratio
IDDOP(5)
IDDOP(6)
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
IDDOP(7)
• Internal RC oscillation stopped
• 1/2 frequency division ratio
2.7 to 3.0
3.0
4.8
IDDOP(8)
• FmCF=0Hz(oscillation stopped)
4.5 to 5.5
0.76
2.8
IDDOP(9)
• FsX'tal=32.768kHz crystal oscillation mode
3.0 to 3.6
0.43
1.5
IDDOP(10)
• 1/2 frequency division ratio
2.7 to 3.0
0.36
1.2
IDDOP(11)
• FmCF=0Hz(oscillation stopped)
4.5 to 5.5
48
140
3.0 to 3.6
18
55
2.7 to 3.0
14
40
4.5 to 5.5
4.3
7.6
3.0 to 3.6
2.2
4.0
4.5 to 5.5
8.1
15
3.0 to 3.6
4.2
7.5
4.5 to 5.5
2.7
4.8
3.0 to 3.6
1.3
2.4
2.7 to 3.0
1.1
1.8
4.5 to 5.5
0.48
1.9
3.0 to 3.6
0.22
0.81
2.7 to 3.0
0.17
0.57
• System clock set to internal RC oscillation
• FsX'tal=32.768kHz crystal oscillation mode
IDDOP(12)
• System clock set to crystal oscillation.
(32.768kHz)
IDDOP(13)
• Internal RC oscillation stopped
• 1/2 frequency division ratio
HALT mode
IDDHALT(1)
• HALT mode
consumption
• FmCF=12MHz ceramic oscillation mode
current
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
(Note9-1)
(Note9-2)
μA
IDDHALT(2)
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• USB circuit stopped
• 1/1 frequency division ratio
IDDHALT(3)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
IDDHALT(4)
• Internal PLL oscillation mode active
• Internal RC oscillation stopped
• USB circuit active
mA
• 1/1 frequency division ratio
IDDHALT(5)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
IDDHALT(6)
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
IDDHALT(7)
• Internal RC oscillation stopped
• 1/2 frequency division ratio
IDDHALT(8)
• HALT mode
• FmCF=0Hz(oscillation stopped)
IDDHALT(9)
IDDHALT(10)
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation.
• 1/2 frequency division ratio
Note 9-1: The consumption current value includes none of the currents that flow into the output transistors and internal
pull-up resistors.
Note9-2: Unless otherwise specified, the consumption current for the LVD circuits is not included.
Continued on next page.
No.A1909-25/32
LC87F1M16A
Continued from preceding page.
Parameter
Symbol
HALT mode
IDDHALT(11)
consumption
current
IDDHALT(12)
Pin/
Specification
Conditions
Remarks
VDD[V]
VDD1
=VDD2
• HALT mode
=VDD3
• FsX'tal=32.768kHz crystal oscillation mode
max
unit
35
120
3.0 to 3.6
9.5
39
2.7 to 3.0
6.4
27
• HOLD mode
4.5 to 5.5
0.08
24
• CF1=VDD or open (External clock mode)
3.0 to 3.6
0.03
11
2.7 to 3.0
0.02
9.6
• System clock set to crystal oscillation.
(Note 9-2)
typ
4.5 to 5.5
• FmCF=0MHz (oscillation stopped)
(Note 9-1)
min
(32.768kHz)
IDDHALT(13)
• Internal RC oscillation stopped
• 1/2 frequency division ratio
HOLD mode
IDDHOLD(1)
consumption
IDDHOLD(2)
current
VDD1
IDDHOLD(3)
(Note 9-1)
(Note 9-2)
IDDHOLD(4)
• HOLD mode
4.5 to 5.5
2.9
29
IDDHOLD(5)
• LVD option selected
• CF1=VDD or open (External clock mode)
3.0 to 3.6
2.2
15
IDDHOLD(6)
2.7 to 3.0
2.1
12
IDDHOLD(7)
• HOLD mode
4.5 to 5.5
2.9
32
3.0 to 3.6
1.4
16
2.7 to 3.0
1.2
14
4.5 to 5.5
31
110
3.0 to 3.6
7.0
34
2.7 to 3.0
4.3
22
• Watchdog timer operation mode
IDDHOLD(8)
(internal low-speed RC oscillation circuit
operation)
IDDHOLD(9)
Timer HOLD
• CF1=VDD or open (External clock mode)
• Timer HOLD mode
IDDHOLD(10)
• CF1=VDD or open (External clock mode)
mode
consumption
• FsX’tal=32.768kHz crystal oscillation mode
IDDHOLD(11)
current
(Note 9-1)
μA
IDDHOLD(12)
(Note 9-2)
Note 9-1: The consumption current value includes none of the currents that flow into the output transistors and internal
pull-up resistors.
Note9-2: Unless otherwise specified, the consumption current for the LVD circuits is not included.
USB Characteristics and Timing at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Specification
Conditions
min
typ
max
unit
High level output
VOH(USB)
• 15kΩ±5% to GND
2.8
3.6
V
Low level output
VOL(USB)
• 1.5kΩ±5% to 3.6V
0.0
0.3
V
Output signal crossover voltage
VCRS
1.3
2.0
Differential input sensitivity
VDI
• ⏐(D+)-(D-)⏐
0.2
Differential input common mode range
VCM
0.8
High level input
VIH(USB)
2.0
Low level input
VIL(USB)
USB data rise time
tR
• RS=27 to 33Ω, CL=50pF
• VDD3=3.0 to 3.6V
USB data fall time
tF
• RS=27 to 33Ω, CL=50pF
• VDD3=3.0 to 3.6V
V
V
2.5
V
V
0.8
V
4
20
ns
4
20
ns
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = 0V
Parameter
Onboard programming
Symbol
IDDFW(1)
current
Programming time
Pin/
Remarks
VDD1
Specification
Conditions
VDD[V]
• Excluding power dissipation in the
microcontroller block
tFW(1)
• Erase operation
tFW(2)
• Write operation
3.0 to 5.5
3.0 to 5.5
min
typ
max
unit
10
mA
20
30
ms
40
60
μs
5
No.A1909-26/32
LC87F1M16A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
at Ta = -40°C to +85°C
Nominal
Vendor
Frequency
Name
12MHz
MURATA
Circuit Constant
Oscillator Name
CSTCE12M0GH5L**-R0
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[V]
[ms]
[ms]
(33)
(33)
470
3.0 to 5.5
0.1
0.5
Remarks
C1 and C2
integrated
SMD type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the
following cases (see Figure 4):
• Till the oscillation gets stabilized after VDD goes above the operating voltage lower limit.
• Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed.
• Till the oscillation gets stabilized after the HOLD mode is reset.
• Till the oscillation gets stabilized after the X'tal HOLD mode is reset with CFSTOP (OCR register, bit 0) set to 0.
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor
Frequency
Name
EPSON
32.768kHz
TOYOCOM
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
OPEN
680k
2.7 to 5.5
1.1
3.0
Remarks
Applicable
MC-306
CL value=12.5pF
SMD type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the
following cases (see Figure 4):
• Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed.
• Till the oscillation gets stabilized after the HOLD mode is reset with EXTOSC (OCR register, bit 6) set to 1.
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf
Rd1
C1
CF
Figure 1 CF Oscillator Circuit
C2
Rd2
C3
X’tal
C4
Figure 2 Crystal Oscillator Circuit
No.A1909-27/32
LC87F1M16A
0.5VDD
Figure 3 AC Timing Measurement Point
VDD
Operating VDD
lower limit
GND
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating
mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF1,CF2
tmsX’tal
XT1, XT2
Operating mode
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
No.A1909-28/32
LC87F1M16A
P34/UFILT
Rd
0kΩ
+
Cd
- 2.2μF
When using the internal PLL circuit to generate
the-48MHz clock for USB, it is necessary to
connect a filter circuit such as that shown to the
left to the P34/UFILT pin.
After PLL settings, 20ms or more is required to
stabilize.
Figure 5 External Filter Circuit for the Internal USB-dedicated PLL Circuit
VD3OEN/
VD3OE2
P70/
P27
1.5kΩ
Note:
It’s necessary to adjust the Circuit Constant of the
USB Port Peripheral Circuit each mounting board.
Make the D+ Pull-up resistors available to control
on/off according to the Vbus.
D+
27 to 33Ω
5pF
D27 to 33Ω
5pF
Figure 6 USB Port Peripheral Circuit
VDD
RRES
RES
Note:
The external circuit for reset may vary
depending on the usage of POR and LVD.
See “Reset Function” in the user’s manual.
CRES
Figure 7 Sample Reset Circuit
No.A1909-29/32
LC87F1M16A
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transfer
period (SIO0, 4 only)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transfer
period (SIO0, 4 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 8 Serial Input/Output Waveform
tPIL
tPIH
Figure 9 Pulse Input Timing Signal Waveform
Voh
tr
D+
tr
90%
90%
Vcrs
10%
Vol
10%
D-
Figure 10 USB Data Signal Timing and Voltage Level
No.A1909-30/32
LC87F1M16A
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
100μs or longer
Reset period
Reset unknown
area (POUKS)
RES
Figure 11 Example of POR Only (LVD Deselected) Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only)
• The POR function generates a reset only when the power voltage goes up from the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level
as shown in (a). If such a case is anticipated, use the LVD function together with the POR function as shown below or
implement an external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on
again after this condition continues for 100μs or longer.
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
LVD reset voltage
(LVDET)
Reset period
Reset period
Reset period
Reset unknown area
(LVUKS)
RES
Figure 12 Example of POR + LVD Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only)
• Reset are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection
level.
VDD
LVD release voltage
LVD detect voltage
LVDET-0.5V
TLVDW
VSS
Figure 13 Minimum Low Voltage Detection Width (Example of Voltage Sag/Fluctuation Waveform)
No.A1909-31/32
LC87F1M16A
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of March, 2011. Specifications and information herein are subject
to change without notice.
PS No.A1909-32/32