SANYO LC87F1364A

Ordering number : ENA0137
LC87F1364A
CMOS IC
FROM 64K byte, RAM 1K byte on-chip
8-bit 1-chip Microcontroller
with Low-speed USB
Overview
The SANYO LC87F1364A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time
of 166ns, integrates on a single chip a number of hardware features such as 64K-byte flash ROM (onboard
programmable), 1024-byte RAM, an on-chip debugger, a sophisticated 16-bit timers/counters (may be divided into 8-bit
timers), 16-bit timers (may be divided into 8-bit timers or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer
serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmit/
receive function), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a USB (Low-Speed)
interface, two 12-bit PWM channels, an 8-bit 9-channel AD converter, and a 29-source 10-vector address interrupt
feature.
Features
„Flash ROM
• Block-erasable in 128-byte units
• 65536 × 8 bits
„Minimum Bus Cycle Time
• 166ns (CF = 6MHz)
Note: The bus cycle time here refers to the ROM read speed.
„Minimum Instruction Cycle Time (tCYC)
• 500ns (CF = 6MHz)
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
Ver.1.07
80807HKIM 20060405-S00011 No.A0137-1/22
LC87F1364A
„Ports
• I/O ports
Ports whose I/O direction can be designated in 1 bit units
Ports whose I/O direction can be designated in 4 bit units
• USB ports
• Dedicated oscillator ports
• Reset pins
• Power pins
9 (P1n, P70)
8 (P0n)
2 (D+, D-)
2 (XT1, XT2)
1 (RES)
1 (VSS1, VDD1)
„Timers
• Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer that supports PWM/toggle output capabilities)
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) × 2 channels
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer with an 8-bit prescaler (with toggle output)
(The lower-order 8 bits can be used as a timer with toggle output.)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle output)
(The lower-order 8 bits can be used as PWM.)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler
• Timer 7: 8-bit timer with a 6-bit prescaler
„SIO
• SIO0: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3tCYC)
3) Automatic continuous data transmission (1 to 256 bits)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
„Full Duplex UART
• UART1
1) Data length: 7/8/9 bits selectable
2) Stop bits: 1 bit (2 bits in continuous transmission mode)
3) Baud rate: 16/3 to 8192/3 tCYC
„AD Converter: 8 bits × 9 channels
„PWM: Multifrequency 12-bit PWM × 2 channels
No.A0137-2/22
LC87F1364A
„USB Controller
• USB Specification rev. 1.1 (Low-Speed) compatible
• Supports a maximum of 2 user-defined endpoints.
Endpoint
EP0
EP1
Control
enable
enable
-
Interrupt
-
enable
enable
8
8
8
Transfer Type
Max. payload
EP2
„Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
„Interrupts
• 29 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/USB bus active
4
0001BH
H or L
INT3/base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/USB bus reset/USB suspend/UART1 receive
8
0003BH
H or L
SIO1/USBERR/USBPOV/USBENP/USBNAK/ USBSTL/UART1 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/PWM0/PWM1/T4/T5
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
„Subroutine Stack Levels: 512 levels (the stack is allocated in RAM.)
„High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
„Oscillation Circuits
• RC oscillation circuit (internal):
• CF oscillation circuit:
• Crystal oscillation circuit:
• PLL circuit (internal):
For system clock
For system clock, USB interface
For system clock, time-of-day clock
For system clock, USB interface
No.A0137-3/22
LC87F1364A
„Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an bus active interrupt source established in the USB interface circuit
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The PLL base clock generator, CF and RC oscillator automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an bus active interrupt source established in the USB interface circuit
„Package Form
• MFP24S(300mil): Lead-free type
„Development Tools
• On-chip debugger: TCB87 type-A or TCB87 type-B + LC87F1364A
„Flash ROM Programming Boards
Package
Programming boards
MFP24S(300mil)
W87F5300M
„Recommended EPROM Programmer
Maker
Model
Flash Support Group, Inc.
AF9708/AF9709/AF9709B
(Single)
(including product of Ando Electric Co.,Ltd)
SANYO
SKK(SANYO FWS)
Supported version
Device
After 02.40
LC87F1364A
Application Version: After 1.03
Chip Data Version: After 2.01
LC87F1364
No.A0137-4/22
LC87F1364A
Package Dimensions
unit : mm (typ)
3112B
12.5
0.63
7.6
13
5.4
24
1
12
1.0
0.15
0.35
1.7max
0.1
(1.5)
(0.75)
SANYO : MFP24S(300mil)
Pin Assignment
P05/AN5/CKO
1
24
P04/AN4/DBGP2
P06/AN6/T6O
2
23
P03/AN3/DBGP1
P07/AN7/T7O
3
22
P02/AN2/DBGP0
P70/INT0/T0LCP/AN8/DPUP
4
21
P01/AN1/URX1
D+
5
20
P00/AN0/UTX1
D-
6
19
P16/PWM1
RES
7
18
P15/SCK1/INT3/T0IN/PWM0
P17/FILT
8
17
P14/SI1/SB1/INT2/T0IN
VSS1
9
16
P13/SO1/INT1/T0HCP
XT1/CF1
10
15
P12/SCK0
XT2/CF2
11
14
P11/SI0/SB0
VDD1
12
13
P10/SO0
MFP24S
Top view
No.A0137-5/22
LC87F1364A
MFP
NAME
1
P05/AN5/CKO
2
P06/AN6/T6O
3
P07/AN7/T7O
4
P70/INT0/T0LCP/AN8/DPUP
5
D+
6
D-
7
RES
8
P17/FILT
9
VSS1
10
XT1/CF1
11
XT2/CF2
12
VDD1
13
P10/SO0
14
P11/SI0/SB0
15
P12/SCK0
16
P13/SO1/INT1/T0HCP
17
P14/SI1/SB1/INT2/T0IN
18
P15/SCK1/INT3/T0IN/PWM0
19
P16/PWM1
20
P00/AN0/UTX1
21
P01/AN1/URX1
22
P02/AN2/DBGP0
23
P03/AN3/DBGP1
24
P04/AN4/DBGP2
No.A0137-6/22
LC87F1364A
System Block Diagram
Interrupt control
IR
Standby control
PLA
Flash-ROM
RC
PLL
Clock
generator
PC
CF/X’tal
SIO0
Bus interface
ACC
SIO1
Port 0
B register
Timer 0
Port 1
C register
Timer 1
Port 7
Timer 4
INT0 to 3
Noise rejection filter
Timer 5
UART1
ALU
PSW
Timer 6
ADC
RAR
Timer 7
RAM
Base timer
Stack pointer
PWM0
Watchdog timer
PWM1
USB interface
On-Chip-Debugger
No.A0137-7/22
LC87F1364A
Pin Description
Pin Name
I/O
Description
Option
VSS1
-
- power supply pin
VDD1
-
+ power supply pin
No
No
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 4 bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4 bit units.
• HOLD reset input
• Port 0 interrupt input
• Pin functions
P00: AN0 (ADC input)/UART1 transmit
P01: AN1 (ADC input)/UART1 receive
P02: AN2 (ADC input)/For On-Chip-Debugger
P03: AN3 (ADC input)/For On-Chip-Debugger
P04: AN4 (ADC input)/For On-Chip-Debugger
P05: AN5 (ADC input)/System Clock Output
P06: AN6 (ADC input)/timer 6 toggle outputs
P07: AN7 (ADC input)/timer 7 toggle outputs
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1 bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1 bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output/INT1 input/HOLD reset input/timer OH capture input
P14: SIO1 data input/bus I/O/INT2 input/ HOLD reset input/timer 0 event input/timer OL capture
input
P15: SIO1 clock I/O/INT3 input (with noise filter)/timer 0 event input/timer OH capture input
/PWM 0 output
P16: Timer 1 PWML output/PWM 1 output
P17: Timer 1 PWMH output/beeper output/Internal PLL filter pin
Interrupt acknowledge type
Rising
Port 7
I/O
Falling
Rising &
Falling
H level
L level
INT1
enable
enable
disable
enable
enable
INT2
enable
enable
enable
disable
disable
INT3
enable
enable
enable
disable
disable
• 1-bit I/O port
No
• I/O specifiable in 1 bit units
P70
• Pull-up resistors can be turned on and off in 1 bit units.
• Shared pins
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/AN8 (ADC input) /
D- 1.5kΩ pull-up resistor connect pin
Interrupt acknowledge type
INT0
RES
I
Rising
Falling
enable
enable
Rising &
Falling
disable
Reset pin
H level
L level
enable
enable
No
XT1
I
Ceramic oscillator input pin/32.768kHz crystal oscillator input pin
No
XT2
I/O
Ceramic oscillator input pin/32.768kHz crystal oscillator output pin
No
D-
I/O
USB data I/O pin D-
No
D+
I/O
USB data I/O pin D+
No
No.A0137-8/22
LC87F1364A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option selected
in units of
P00 to P07
1 bit
P10 to P17
1 bit
Option type
1
Output type
Pull-up resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
P70
-
No
Nch-open drain
Programmable
XT1
-
No
Input only
No
XT2
-
No
32.768kHz crystal oscillator output
No
Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
USB Reference Power Option
When a voltage 4.5V to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the H
output level of the USB Port is 3.0V to 3.6V (the H output level of the ports except the USB Port is the VDD1 voltage
level, however). The active/inactive state of the reference voltage circuit can be determined by option settings.
According to the voltage to be supplied to VDD1, make option settings as shown below.
Option setting
VDD1 voltage (V)
USB Regulator
Reference voltage circuit state
4.5 to 5.5
3.0 to 3.6
USE
USE
USE
NONUSE
USB Regulator in HOLD mode
USE
NONUSE
NONUSE
NONUSE
USB Regulator in HALT mode
USE
NONUSE
USE
NONUSE
Normal state
active
active
active
inactive
HOLD mode
active
inactive
inactive
inactive
HALT mode
active
inactive
active
inactive
(1)
(2)
(3)
(4)
• When the USB reference voltage circuit is made inactive, the H output level of the USB Port becomes the VDD1
voltage level.
• Use the setting (2) or (3) to make the reference voltage circuit inactive in HOLD or HALT mode.
• When the reference voltage circuit is activated, the current drain increases by approximately 100µA compared with
when the reference voltage circuit is inactive.
No.A0137-9/22
LC87F1364A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Maximum supply
VDD max
VDD1
Input voltage
VI(1)
XT1, XT2
Input/output
VIO(1)
Ports 0, 1, 7
IOPH(1)
Ports 0, 1
VDD1
voltage
voltage
Peak output
High level output current
current
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
V
• When CMOS output
type is selected
-10
• Per 1 applicable pin
Average
IOPH(2)
PWM0, PWM1
Per 1 applicable pin
IOMH(1)
Ports 0, 1
• When CMOS output
output current
type is selected
(Note 2)
Total output
-20
-7.5
• Per 1 applicable pin
IOMH(2)
PWM0, PWM1
Per 1 applicable pin
ΣIOAH(1)
Ports 0, 1
Total of all applicable pins
current
PWM0, PWM1
-15
-50
mA
D+, DPeak output
Low level output current
unit
IOPL(1)
current
P00 to P05
Per 1 applicable pin
20
Ports 1, P70
PWM0, PWM1
Average
IOPL(2)
P06, 07
Per 1 applicable pin
IOML(1)
P00 to P05
Per 1 applicable pin
output current
Ports 1, P70
(Note 2)
PWM0, PWM1
Total output
Allowable power
15
IOML(2)
P06, 07
Per 1 applicable pin
ΣIOAL(1)
Ports 0, 1, P70
Total of all applicable pins
current
30
20
75
PWM0, PWM1 D+, DPd max
MFP24S
Ta=-20 to +70°C
mW
Dissipation
Operating ambient
Topr
Temperature
Storage ambient
Tstg
temperature
-20
+70
-55
+125
°C
Note 2: The mean output current is a mean value measured over 100ms.
No.A0137-10/22
LC87F1364A
Allowable Operating Conditions at Ta = -20°C to +70°C, VSS1 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Operating
VDD(1)
VDD1
supply voltage
0.490µs ≤ tCYC ≤ 200µs Except
for onboard programming (Note 3)
0.490µs ≤ tCYC ≤ 200µs
VDD(2)
internal PLL oscillation
Memory
VHD
VDD1
sustaining
min
typ
max
unit
2.5
5.5
4.5
5.5
2.0
5.5
0.3VDD
VDD
RAM and register contents
sustained in HOLD mode.
supply voltage
High level
VIH(1)
input voltage
Port 1
P70 port input
2.5 to 5.5
/interrupt side
VIH(2)
Port 70 watchdog
timer side
Low level
VIH(3)
XT1, XT2, RES
VIL(1)
Port 1
input voltage
/interrupt side
VIL(3)
Port 0
Port 70 watchdog
timer side
VIL(4)
Instruction
2.5 to 5.5
0.9VDD
VDD
2.5 to 5.5
0.75VDD
4.0 to 5.5
VSS
VDD
0.1VDD
2.5 to 4.0
VSS
4.0 to 5.5
VSS
2.5 to 4.0
VSS
2.5 to 5.5
VSS
2.5 to 5.5
VSS
0.25VDD
2.5 to 5.5
0.490
200
2.5 to 5.5
0.1
6
V
P70 port input
VIL(2)
+0.7
XT1, XT2, RES
+0.4
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
tCYC
cycle time
µs
(Note 4)
External
FEXCF(1)
XT1
system clock
• XT2 pin open
• System clock frequency
frequency
division ratio=1/1
• External system clock duty
MHz
=50±5%
• XT2 pin open
• System clock frequency
2.5 to 5.5
0.1
12
division ratio=1/2
Oscillation
FmCF
XT1, XT2
frequency
6MHz ceramic oscillation
See Fig. 1.
range
FmRC
(Note 5)
FsX’tal
Internal RC oscillation
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
2.5 to 5.5
2.5 to 5.5
2.5 to 5.5
6
0.3
1.0
MHz
2.0
32.768
kHz
Note 3: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 4: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 5: See Tables 1 and 2 for the oscillation constants.
No.A0137-11/22
LC87F1364A
Electrical Characteristics at Ta = -20°C to +70°C, VSS1 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High level input
IIH(1)
Ports 0, 1
Output disabled Pull-up resistor off
Port 70
RES
VIN=VDD
(Including output Tr's off leakage
IIH(2)
XT1, XT2
VIN=VDD
IIL(1)
Ports 0, 1
Output disabled Pull-up resistor off
Port 70
VIN=VSS
(Including output Tr's off leakage
current
min
typ
max
unit
2.5 to 5.5
1
2.5 to 5.5
1
current)
Low level input
current
RES
2.5 to 5.5
µA
-1
current)
IIL(2)
XT1, XT2
VIN=VSS
2.5 to 5.5
-1
High level output
VOH(1)
Ports 0, 1
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
VOH(3)
IOH=-0.2mA
2.5 to 5.5
VDD-0.4
VOH(4)
PWM0, PWM1
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(5)
P05 (CK0 when
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
2.5 to 5.5
VDD-0.4
VOH(6)
using system
clock output
IOH=-1mA
V
function)
Low level output
VOL(1)
Ports 0, 1
IOL=10mA
4.5 to 5.5
1.5
voltage
VOL(2)
Port 70
IOL=1.6mA
3.0 to 5.5
0.4
2.5 to 5.5
0.4
IOL=30mA
4.5 to 5.5
1.5
VOL(5)
IOL=5mA
3.0 to 5.5
0.4
VOL(6)
IOL=2.5mA
2.5 to 5.5
VOH=0.9VDD
4.5 to 5.5
15
35
80
18
50
150
VOL(4)
Pull-up resistance
Hysteresis voltage
PWM0, PWM1
IOL=1mA
VOL(3)
P06, P07
0.4
Rpu(1)
Ports 0, 1
Rpu(2)
Port 70
2.5 to 5.5
VHYS
RES
Port 1
2.5 to 5.5
0.1VDD
V
2.5 to 5.5
10
pF
kΩ
Port 70
Pin capacitance
CP
All pins
For pins other than that under test:
VIN=VSS
F=1MHz
Ta=25°C
No.A0137-12/22
LC87F1364A
Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Pin
SCK0(P12)
Specification
Conditions
/Remarks
VDD[V]
See Fig. 6.
max
unit
1
tSCKH(1)
1
pulse width
tSCKHA(1a)
Input clock
typ
2
pulse width
High level
min
• Continuous data
transmission/reception mode
• USB is not in use simultaneous.
2.7 to 5.5
4
tCYC
• See Fig. 6.
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data
transmission /reception mode
• USB is in use simultaneous.
7
Serial clock
• See Fig.6.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig.6.
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
pulse width
Output clock
tSCKHA(2a)
• Continuous data
transmission /reception mode
• USB is not in use
2.7 to 5.5
tSCKH(2)
+2tCYC
simultaneous.
• CMOS output selected
tSCKH(2)
+(10/3)
tCYC
• See Fig.6.
tSCKHA(2b)
tCYC
• Continuous data
transmission /reception mode
tSCKH(2)
• USB is in use simultaneous.
+2tCYC
• CMOS output selected
tSCKH(2)
+(19/3)
tCYC
• See Fig.6.
Serial input
Data setup time
SB0(P11),
SI0(P11)
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
2.7 to 5.5
0.03
• See Fig.6.
Data hold time
Input clock
Output delay
thDI(1)
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
transmission /reception mode
2.7 to 5.5
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
Output clock
Serial output
tsDI(1)
tdD0(3)
2.7 to 5.5
(1/3)tCYC
+0.05
µs
1tCYC
+0.05
(Note 4-1-3)
2.7 to 5.5
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock
is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig.6.
No.A0137-13/22
LC87F1364A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Pin
/Remarks
SCK1(P15)
VDD[V]
min
See Fig.6.
Frequency
SCK1(P15)
• CMOS output selected
1
2
tSCKL(4)
1/2
2.7 to 5.5
pulse width
High level
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
2.7 to 5.5
0.03
• See Fig.6.
Data hold time
Output delay time
Serial output
unit
1
• See Fig.6.
Low level
max
tCYC
tSCKH(3)
tSCK(4)
typ
2
2.7 to 5.5
pulse width
High level
Specification
CondiPtions
pulse width
Output clock
Serial clock
Input clock
Parameter
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
µs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the
time to the beginning of output
2.7 to 5.5
state change in open drain
(1/3)tCYC
+0.05
output mode.
• See Fig.6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0137-14/22
LC87F1364A
Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High/low level
tP1H(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tP1L(1)
INT1(P13),
• Event inputs for timer 0 or 1
INT2(P14),
INT3(P15) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
INT3(P15) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
INT3(P15) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
tPIL(5)
RES
1
2.5 to 5.5
2
unit
tCYC
2.5 to 5.5
64
2.5 to 5.5
256
2.5 to 5.5
200
enabled.
tPIH(4)
constant is 1/128
2.5 to 5.5
max
enabled.
tPIH(3)
constant is 1/32
typ
are enabled.
tPIH(2)
constant is 1/1
min
enabled.
Resetting is enabled.
µs
AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07),
Conversion
TCAD
time
AD conversion time = 32×tCYC
(when ADCR2=0) (Note 7)
4.5 to 5.5
AD conversion time = 64×tCYC
(when ADCR2=1) (Note 7)
4.5 to 5.5
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
max
unit
8
bit
±1.5
3.0 to 5.5
3.0 to 5.5
Analog input
typ
3.0 to 5.5
(Note 6)
AN8(P70)
accuracy
min
15.68
97.92
(tCYC=
(tCYC=
0.49µs)
3.06µs)
31.36
97.92
(tCYC=
(tCYC=
0.98µs)
3.06µs)
31.36
97.92
(tCYC=
(tCYC=
0. 49µs)
1.53µs)
31.36
97.92
(tCYC=
(tCYC=
0. 49µs)
1.53µs)
VSS
VDD
1
-1
LSB
µs
V
µA
Note 6: The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 7: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0137-15/22
LC87F1364A
Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
VDD1
IDDOP(2)
VDD[V]
• FmCF=6MHz ceramic oscillation mode
• Internal RC oscillation stopped
• 1/1 frequency division ration
(Note 8)
IDDOP(3)
Specification
Conditions
• System clock set to 6MHz side
consumption
current
Pin
/Remarks
min
typ
Max
4.5 to 5.5
5.3
13
2.5 to 4.5
3.5
9.6
4.5 to 5.5
6.7
17
4.5 to 5.5
0.67
3.1
2.5 to 4.5
0.43
2.3
4.5 to 5.5
120
380
unit
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to PLL clock side
• Internal RC oscillation stopped
mA
• 1/1 frequency division ration
IDDOP(4)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
IDDOP(5)
• Internal PLL oscillation stopped
• 1/2 frequency division ration
IDDOP(6)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
IDDOP(7)
µA
• Internal RC oscillation stopped
• Internal PLL oscillation stopped
2.5 to 4.5
79
290
4.5 to 5.5
2.0
5.4
2.5 to 4.5
1.2
3.6
4.5 to 5.5
3.6
9.6
4.5 to 5.5
0.33
1.6
2.5 to 4.5
0.19
1.1
4.5 to 5.5
30
130
2.5 to 4.5
12
73
4.5 to 5.5
0.04
13
2.5 to 4.5
0.02
9.8
4.5 to 5.5
27
120
2.5 to 4.5
9.6
66
• 1/2 frequency division ration
HALT mode
IDDHALT(1)
• HALT mode
consumption
• FmCF=6MHz ceramic scillation mode
current
• System clock set to 6MHz side
(Note 8)
IDDHALT(2)
• Internal RC oscillation stopped
• 1/1 frequency division ration
IDDHALT(3)
• HALT mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to PLL clock side
mA
• Internal RC oscillation stopped
• 1/1 frequency division ration
IDDHALT(4)
• HALT mode
• FsX'tal=32.768kHz crystal oscillation mode
IDDHALT(5)
• System clock set to internal RC oscillation
• Internal PLL oscillation stopped
• 1/2 frequency division ration
IDDHALT(6)
• HALT mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
IDDHALT(7)
• Internal RC oscillation stopped
• Internal PLL oscillation stopped
• 1/2 frequency division ration
HOLD mode
IDDHOLD(1)
consumption
current
Timer HOLD
IDDHOLD(2)
IDDHOLD(3)
mode
consumption
current
HOLD mode
Timer HOLD mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDHOLD(4)
µA
• XT1=VDD or open (External clock mode)
Note 8: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.A0137-16/22
LC87F1364A
USB Characteristics and Timing at Ta = -20°C to +70°C, VSS1 = 0V
Parameter
Symbol
Specification
Conditions
min
High level output
VOH(USB)
• 15kΩ±5% to GND
Low level output
VOL
• 1.5kΩ±5% to 3.6V
Output signal crossover voltage
VCRS
Differential input sensitivity
VDI
Differential input common mode range
VCM
0.8
High level input
VIH(USB)
2.0
Low level input
VIL(USB)
USB data rise time
tR
USB data fall time
tF
Rise/fall time
tRFM
• ⏐(D+)-(D-)⏐
typ
max
3.6
0.3
V
1.3
2.0
V
0.2
• tR/tF
unit
2.8
V
V
2.5
V
V
0.8
V
75
300
ns
75
300
ns
80
125
%
F-ROM Write Characteristics at Ta = +10°C to +55°C, VSS1 = 0V
Parameter
Symbol
Pin
Specification
Conditions
VDD[V]
Onboard
IDDFW(1)
programming
VDD1
min
typ
max
unit
• 128-byte programming
• Erasing current included
3.0 to 5.5
25
40
mA
3.0 to 5.5
22.5
45
mS
current
Programming
time
tFW(1)
• 128-byte programming
• Erasing current included
• Time for setting up 128-byte data
excluded.
No.A0137-17/22
LC87F1364A
Characteristics of a Sample External Clock Oscillation Circuit
Given below are the characteristics of a sample external clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample External Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor
Frequency
Name
32.768kHz
EPSON
TOYOCOM
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rf1
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
22
22
Open
820k
2.5 to 5.5
1.3
3
MC-306
Remarks
Applicable
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
XT1
XT2
Rf1
Rd1
C1
C2
X’tal
Figure 1 Crystal Oscillation Circuit
Table 2 Characteristics of a Sample External Clock Oscillator Circuit with a CF Oscillator
Nominal
Vendor
Frequency
Name
6MHz
MURATA
Circuit Constant
Oscillator Name
CSTCR6M00G15***-R0
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf2
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
(39)
(39)
Open
1k
2.5 to 5.5
0.1
0.5
Remarks
Built in C3, C4
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
XT1
XT2
Rf2
Rd2
C3
CF
C4
Figure 2 CF Oscillation Circuit
No.A0137-18/22
LC87F1364A
0.5VDD
Figure 3 AC Timing Measurement Point
VDD
Operating VDD
lower limit
GND
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF oscillation
(XT1, XT2)
tmsX’tal
Crystal oscillation
(XT1, XT2)
State
Unpredictable
Reset
Instruction execut
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absen
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF oscillation
(XT1, XT2)
tmsX’tal
Crystal
Oscillation
(XT1, XT2)
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0137-19/22
LC87F1364A
P17/FILT
0Ω
+
-
When using the internal PLL circuit to generate the
6MHz clock for USB or system clock, it is necessary
to connect a filter circuit such as that shown to the left
to the P17/FILT pin..
2.2µF
Figure 5 Filter Circuit for the Internal PLL Circuit
VDD
RRES
RES
CRES
Note:
Determine the value of CRES and RRES so
that the reset signal is present for a period of
200µs after the supply voltage goes beyond the
lower limit of the IC's operating voltage.
Figure 6 Reset Circuit
No.A0137-20/22
LC87F1364A
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transfer
period (SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transfer
period (SIO0 only)
tSCKHA
tSCKLA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 7 Serial Input/Output Waveforms
tPIL
tPIH
Figure 8 Pulse Input Timing Signal Waveform
Voh
tr
D+
tr
90%
90%
Vcrs
10%
Vol
10%
D-
Figure 9 USB Data Signal Timing and Voltage Level
No.A0137-21/22
LC87F1364A
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of July, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0137-22/22