SANYO LC87F14C8SA

Ordering number : ENA0590
LC87F14C8SA
CMOS IC
FROM 128K byte, RAM 10K byte on-chip
8-bit 1-chip Microcontroller
with USB-host controller
Overview
The SANYO LC87F14C8SA is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle
time of 83.3ns, integrates on a single chip a number of hardware features such as 128K-byte flash ROM (onboard
programmable), 10240-byte RAM, an on-chip debugger, a sophisticated 16-bit timers/counters (may be divided into 8-bit
timers), 16-bit timers/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with
a prescaler, a base timer serving as a time-of-day clock, three synchronous SIO interface (with automatic block transmit/
receive function), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a Full-Speed USB
interface (host controller), an 8-bit 12-channel AD converter, two 12-bit PWM channels, a system clock frequency
divider, ROM correction function, and a 36-source 10-vector address interrupt feature.
Features
„Flash ROM
• Capable of on-board-programming with wide range, 3.0V to 5.5V, of voltage source.
• Block-erasable in 128-byte units
• 131072 × 8 bits
„RAM
• 10240 × 9 bits
„Minimum Bus Cycle Time
• 83.3ns (CF=12MHz)
Note: The bus cycle time here refers to the ROM read speed.
„Minimum Instruction Cycle Time (tCYC)
• 250ns (CF=12MHz)
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
Ver.1.00
20707HKIM 20061106-S00003 No.A0590-1/26
LC87F14C8SA
„Ports
• I/O ports
Ports whose I/O direction can be designated in 1-bit units 28 (P10 to P17, P20 to P27, P30 to P34,
P70 to P73, PWM0, PWM1, XT2)
Ports whose I/O direction can be designated in 4-bit units 8 (P00 to P07)
• USB ports
2 (UHD+, UHD-)
• Dedicated oscillator ports
2 (CF1, CF2)
• Input-only port (also used for oscillation)
1 (XT1)
• Reset pins
1 (RES)
• Power pins
6 (VSS1 to 3, VDD1 to 3)
„Timers
• Timer 0: 16-bit timer/counter with two capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/
counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an-8bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
„SIO
• SIO0: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 512/3 tCYC
3) Automatic continuous data transmission
(1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
• SIO4: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units, suspension and resumption
of data transmission possible in 1 byte or 2 bytes units)
4) Auto-start-on-falling-edge function
5) Clock polarity selectable
6) CRC16 calculator circuit built in
Continued on next page.
No.A0590-2/26
LC87F14C8SA
Continued from preceding page.
• SIO9: Synchronous serial interface
1) LSB first/MSB first mode selectable
2) Transfer clock cycle: 4/3 to 1020/3 tCYC
3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units, suspension and resumption
of data transmission possible in 1 byte or 2 bytes units)
4) Auto-start-on-falling-edge function
5) Clock polarity selectable
6) CRC16 calculator circuit built in
„Full Duplex UART
• UART1
1) Data length: 7/8/9 bits selectable
2) Stop bits: 1 bit (2 bits in continuous transmission mode)
3) Baud rate: 16/3 to 8192/3 tCYC
„AD Converter: 8 bits × 12 channels
„PWM: Multifrequency 12-bit PWM × 2 channels
„USB Interface (host controller)
• Full-Speed is supported
• Transfer type: Control, Bulk, Interrupt, or Isochronous transfer possible
„Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
„Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
„Interrupts
• 36 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/UHC bus active
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H/INT6/UHC device attach/UHC device detach/UHC resume
6
0002BH
H or L
T1L/T1H/INT7/SIO9
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/SIO4/UART1 transmit
9
00043H
H or L
ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC STALL
10
0004BH
H or L
Port 0/PWM0/PWM1/T4/T5/UHC-SOF
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
„Subroutine Stack Levels: 5120 levels (the stack is allocated in RAM.)
No.A0590-3/26
LC87F14C8SA
„High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
„Oscillation Circuits
• RC oscillation circuit (internal):
• CF oscillation circuit:
• Crystal oscillation circuit:
• PLL circuit (internal):
For system clock
For system clock, USB interface
For system clock, time-of-day clock
For USB interface (see Fig.5)
„Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an bus active interrupt source established in the USB host controller circuit
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The PLL base clock generator, CF and RC oscillator automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an bus active interrupt source established in the USB host controller circuit
„ROM correction function
• Executes the correction program on detection of a match with the program counter value.
• Correction program area size: 128 bytes
„Package Form
• ΤQFP48J(7×7): Lead-free type
„Development Tools
• On-chip debugger: TCB87 type-A or TCB87 type-B + LC87F14C8A
„Flash ROM Programming Boards
Package
Programming boards
TQFP48J(7 × 7)
W87F55256SQ
No.A0590-4/26
LC87F14C8SA
„Recommended EPROM Programmer
Maker
Model
Flash Support Group, Inc.
AF9708/AF9709/AF9709B
(Single)
(including product of Ando Electric Co.,Ltd)
Flash Support Group, Inc.
(including product of Ando Electric Co.,Ltd)
(Gang)
AF9833(Unit)
AF9723(Main body)
(including product of Ando Electric Co.,Ltd)
SANYO
SKK(Sanyo FWS)
Supported version
Device
After 02.35
LC87F5JC8A FAST
After 02.04
LC87F5JC8A FAST
After 01.83
Application Version :After 1.03
Chip Data Version :After 2.01
LC87F14C8
Package Dimensions
unit : mm (typ)
3288
9.0
0.5
7.0
25
24
48
13
7.0
37
1
12
0.5
9.0
36
0.125
0.2
0.1
1.2max
(1.0)
(0.75)
SANYO : TQFP48J(7X7)
No.A0590-5/26
LC87F14C8SA
36
35
34
33
32
31
30
29
28
27
26
25
P27/INT5/SCK9
P26/INT5/SI9/WR9
P25/INT5/SO9/RD9
P24/INT5/INT7/SCK4
P23/INT4/SI4/WR
P22/INT4/SO4/RD
P21/INT4
P20/INT4/INT6
P07/AN7/T7O
P06/AN6/T6O
P05/AN5/CKO
P04/AN4/DBGP2
Pin Assignment
37
38
39
40
41
42
43
44
45
46
47
48
LC87F14C8SA
24
23
22
21
20
19
18
17
16
15
14
13
P03/AN3/DBGP1
P02/AN2/DBGP0
P01/AN1
P00/AN0
VSS2
VDD2
PWM0
PWM1
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
P73/INT3/T0IN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
1
2
3
4
5
6
7
8
9
10
11
12
UHDUHD+
VDD3
VSS3
P34/UFILT
P33
P32
P31/URX1
P30/UTX1
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
Top view
SANYO : TQFP48J(7×7)
TQFP48J
NAME
TQFP48J
NAME
1
P73/INT3/T0IN
25
P04/AN4/DBGP2
2
RES
26
P05/AN5/CKO
3
XT1/AN10
27
P06/AN6/T6O
4
XT2/AN11
28
P07/AN7/T7O
5
VSS1
29
P20/INT4/INT6
6
CF1
30
P21/INT4
7
CF2
31
P22/INT4/SO4/RD
8
VDD1
32
P23/INT4/SI4/WR
9
P10/SO0
33
P24/INT5/INT7/SCK4
10
P11/SI0/SB0
34
P25/INT5/SO9/RD9
11
P12/SCK0
35
P26/INT5/SI9/WR9
12
P13/SO1
36
P27/INT5/SCK9
13
P14/SI1/SB1
37
UHD-
14
P15/SCK1
38
UHD+
15
P16/T1PWML
39
VDD3
16
P17/T1PWMH/BUZ
40
VSS3
17
PWM1
41
P34/UFILT
18
PWM0
42
P33
19
VDD2
43
P32
P31/URX1
“Lead-free Type”
20
VSS2
44
21
P00/AN0
45
P30/UTX1
22
P01/AN1
46
P70/INT0/T0LCP/AN8
23
P02/AN2/DBGP0
47
P71/INT1/T0HCP/AN9
24
P03/AN3/DBGP1
48
P72/INT2/T0IN
No.A0590-6/26
LC87F14C8SA
System Block Diagram
Interrupt control
Standby control
CF
USB PLL
RC
Clock
generator
X’tal
PLA
IR
FROM
PC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
SIO4
Port 1
C register
SIO9
Port 2
ALU
Timer 0
Port 3
Timer 1
Port 7
Timer 4
INT0 to 7
Noise filter
Timer 5
UART1
Timer 6
ADC
Timer 7
PSW
RAR
RAM
Stack pointer
Watchdog timer
Base timer
On-chip debugger
PWM0
PWM1
USB host
No.A0590-7/26
LC87F14C8SA
Pin Description
Pin Name
VSS1,
VSS2,
VSS3
VDD1,
I/O
Description
Option
-
- power supply pin
No
No
-
+ power supply pin
VDD2
VDD3
-
USB reference voltage pin
Yes
Port 0
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pins functions
AD converter input port: AN0 to AN7 (P00 to P07)
On-chip debugger pins: DBGP0 to DBGP2 (P02 to P04)
P05: System Clock Output
P06: Timer 6 toggle outputs
P07: Timer 7 toggle outputs
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/beeper output
Port 2
P20 to P27
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20 to P23: INT4 input / HOLD reset input / timer 1 event input/
timer 0L capture input / timer 0H capture input
P24 to P27: INT5 input / HOLD reset input / timer 1 event input/
timer 0L capture input / timer 0H capture input
P20: INT6 input/timer 0L capture 1 input
P22: SIO4 date I/O/parallel interface RD output
P23: SIO4 date I/O/parallel interface WR output
P24: SIO4 clock I/O/INT7 input / timer 0H capture 1 input
P25: SIO9 date I/O/parallel interface RD9 output
P26: SIO9 date I/O/parallel interface WR9 output
P27: SIO9 clock I/O
Interrupt acknowledge type
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising &
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
Continued on next page.
No.A0590-8/26
LC87F14C8SA
Continued from preceding page.
Pin Name
Port 3
I/O
I/O
Description
Option
• 5-bit I/O port
Yes
• I/O specifiable in 1-bit units
P30 to P34
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P30: UART1 transmit
P31: UART1 receive
P34: USB interface PLL filter pin (see Fig.5)
Port 7
I/O
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/
timer 0L capture input / High speed clock counter input
P73: INT3 input (with noise filter) /timer 0 event input/timer 0H capture input
AD converter input port: AN8(P70), AN9(P71)
Interrupt acknowledge type
INT0
PWM0
I/O
Falling
enable
enable
disable
Falling
H level
L level
enable
enable
INT1
enable
enable
disable
enable
enable
INT2
enable
enable
enable
disable
disable
INT3
enable
enable
enable
disable
disable
• PWM0 and PWM1 output port
No
• General-purpose input port
PWM1
UHD-
Rising &
Rising
I/O
• USB data I/O pin UHD-
No
• General-purpose I/O port
UHD+
I/O
• USB data I/O pin UHD+
No
• General-purpose I/O port
RES
Input
Reset pin
No
XT1
Input
• 32.768kHz crystal oscillator input pin
No
• Pin functions
General-purpose input port
AD converter input port: AN10
XT2
I/O
Must be connected to VDD1 if not to be used.
32.768kHz crystal oscillator output pin
No
• Pin functions
General-purpose I/O port
AD converter input port: AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.A0590-9/26
LC87F14C8SA
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option selected
Option type
in units of
P00 to P07
1 bit
P10 to P17
1 bit
1
P20 to P27
Output type
Pull-up resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
Programmable
P30 to P34
P70
-
No
Nch-open drain
P71 to P73
-
No
CMOS
Programmable
PWM0, PWM1
-
No
CMOS
No
UHD+, UHD-
-
No
CMOS
No
XT1
-
No
Input only
No
XT2
-
No
32.768kHz crystal oscillator output
No
Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
Power Pin Treatment
Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of
output ports is supplied by their backup capacitors.
LSI
For backup
Power
supply
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode.
LSI
For backup
Power
supply
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.A0590-10/26
LC87F14C8SA
USB Reference Power Option
When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the
reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be
switched by option selection. The procedure for marking the option selection is described below.
(1)
Option selection
Reference voltage circuit state
(2)
(3)
(4)
USE
USE
NONUSE
NONUSE
NONUSE
NONUSE
USE
NONUSE
active
active
inactive
inactive
inactive
inactive
active
inactive
USB Regulator
USE
USB Regulator in HOLD mode
USE
USB Regulator in HALT mode
USE
NONUSE
Normal state
active
HOLD mode
active
HALT mode
active
inactive
• When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is
equal to VDD1.
• Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
• When the reference voltage circuit is activated, the current drain increases by approximately 100µA compared with
when the reference voltage circuit is inactive.
Example 1: VDD1=VDD2=3.3V
• Inactivating the reference voltage circuit (selection (4)).
• Connecting VDD3 to VDD1 and VDD2.
LSI
For backup
Power Supply
3.3V
VDD1
UHD+
33Ω
UHD-
To USB connector
VDD2
15kΩ
5pF
VDD3
UFILT
0Ω
VSS1 VSS2 VSS3
2.2µF
Example 2: VDD1=VDD2=5.0V
• Activating the reference voltage circuit (selection (1)).
• Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS.
LSI
For backup
VDD1
Power Supply
5V
UHD+
UHD-
33Ω
To USB connector
VDD2
VDD3
2.2µF
UFILT
15kΩ
5pF
0Ω
0.1µF
VSS1 VSS2 VSS3
2.2µF
No.A0590-11/26
LC87F14C8SA
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Maximum supply
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
XT1, CF1
Input/output
VIO(1)
Ports 0, 1, 2, 3, 7
VDD1= VDD2= VDD3
voltage
voltage
PWM0, PWM1
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
unit
V
XT2
Peak output
IOPH(1)
Ports 0, 1, 2
current
• When CMOS output
type is selected
-10
• Per 1 applicable pin
IOPH(2)
PWM0, PWM1
Per 1 applicable pin
IOPH(3)
Ports 3
• When CMOS output
P71 to P73
type is selected
-20
-5
High level output current
• Per 1 applicable pin
Average
IOMH(1)
Ports 0, 1, 2
output current
• When CMOS output
type is selected
(Note 1-1)
-7.5
• Per 1 applicable pin
IOMH(2)
PWM0, PWM1
Per 1 applicable pin
IOMH(3)
Port 3
• When CMOS output
P71 to P73
type is selected
-15
-3
• Per 1 applicable pin
Total output
ΣIOAH(1)
Ports 0, 2
Total of all applicable pins
current
ΣIOAH(2)
Port 1
Total of all applicable pins
PWM0, PWM1
ΣIOAH(3)
Ports 0, 1, 2
Total of all applicable pins
PWM0, PWM1
ΣIOAH(4)
Port 3
Total of all applicable pins
P71 to P73
Peak output
ΣIOAH(5)
UHD+, UHD-
Total of all applicable pins
IOPL(1)
P02 to P07
Per 1 applicable pin
current
-25
-25
-45
-10
mA
-25
20
Ports 1, 2
PWM0, PWM1
IOPL(2)
P00, P01
Per 1 applicable pin
IOPL(3)
Ports 3, 7
Per 1 applicable pin
30
10
Low level output current
XT2
Average
IOML(1)
P02 to P07
output current
Ports 1, 2
(Note 1-1)
PWM0, PWM1
Per 1 applicable pin
15
IOML(2)
P00, P01
Per 1 applicable pin
IOML(3)
Ports 3, 7
Per 1 applicable pin
20
7.5
XT2
Total output
ΣIOAL(1)
Ports 0, 2
Total of all applicable pins
current
ΣIOAL(2)
Port 1
Total of all applicable pins
45
45
PWM0, PWM1
ΣIOAL(3)
Ports 0, 1, 2
Total of all applicable pins
80
PWM0, PWM1
ΣIOAL(4)
Ports 3, 7
Total of all applicable pins
15
XT2
Allowable power
ΣIOAL(5)
UHD+, UHD-
Total of all applicable pins
Pd max
TQFP48J(7×7)
Ta=-40 to +85°C
25
140
dissipation
Operating ambient
Topr
temperature
Storage ambient
Tstg
temperature
-40
+85
-55
+125
mW
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A0590-12/26
LC87F14C8SA
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Operating
Symbol
VDD(1)
Pin/Remarks
VDD1=VDD2=VDD3
Conditions
0.245µs≤tCYC≤200µs
supply voltage
0.490µs≤tCYC≤200µs Except for
(Note 2-1)
onboard programming
Memory
VHD
VDD1=VDD2=VDD3
sustaining
Specification
VDD[V]
min
typ
unit
max
3.0
5.5
2.7
5.5
2.0
5.5
RAM and register contents
sustained in HOLD mode.
supply voltage
High level
VIH(1)
input voltage
Ports 0, 1, 2, 3
P71 to P73
P70 port input/
2.7 to 5.5
0.3VDD
+0.7
VDD
2.7 to 5.5
0.9VDD
VDD
2.7 to 5.5
0.75VDD
4.0 to 5.5
VSS
VDD
0.1VDD
2.7 to 4.0
VSS
4.0 to 5.5
VSS
2.7 to 4.0
VSS
2.7 to 5.5
VSS
2.7 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.245
200
2.7 to 5.5
0.490
200
3.0 to 5.5
0.1
12
interrupt side
PWM0, PWM1
VIH(2)
Port 70 watchdog
timer side
Low level
VIH(3)
XT1, XT2, CF1, RES
VIL(1)
Ports 1, 2, 3
input voltage
V
P71 to P73
VIL(2)
P70 port input/
interrupt side
VIL(3)
Port 0
PWM0, PWM1
VIL(4)
VIL(5)
Port 70 watchdog
timer side
VIL(6)
Instruction
XT1, XT2, CF1, RES
tCYC
cycle time
Except for onboard programming
(Note 2-2)
External
FEXCF(1)
CF1
+0.4
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
µs
• CF2 pin open
• System clock frequency
system clock
frequency
division ratio=1/1
• External system clock duty
=50±5%
MHz
• CF2 pin open
• System clock frequency
division ratio=1/1
2.7 to 5.5
0.1
6
• External system clock duty
=50±5%
Oscillation
FmCF(1)
CF1, CF2
frequency
range
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
(Note 2-3)
6MHz ceramic oscillation
See Fig. 1.
FmRC
FsX’tal
Internal RC oscillation
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
3.0 to 5.5
12
2.7 to 5.5
6
2.7 to 5.5
2.7 to 5.5
0.3
1.0
MHz
2.0
32.768
kHz
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0590-13/26
LC87F14C8SA
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High level input
IIH(1)
current
IIH(2)
Ports 0, 1, 2, 3
Output disabled
Port 7
Pull-up resistor off
RES
PWM0, PWM1
VIN=VDD
(Including output Tr's off leakage
UHD+, UHD-
current)
XT1, XT2
For input port specification
VIN=VDD
Low level input
IIH(3)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3
Output disabled
Port 7
Pull-up resistor off
RES
PWM0, PWM1
VIN=VSS
(Including output Tr's off leakage
UHD+, UHD-
current)
current
IIL(2)
XT1, XT2
For input port specification
VIN=VSS
min
typ
1
2.7 to 5.5
1
2.7 to 5.5
15
2.7 to 5.5
-1
2.7 to 5.5
-1
CF1
VIN=VSS
2.7 to 5.5
-15
High level output
VOH(1)
Ports 0, 1, 2, 3
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
VOH(3)
IOH=-0.2mA
2.7 to 5.5
VDD-0.4
VDD-0.4
P71 to P73
VOH(5)
IOH=-1.6mA
3.0 to 5.5
IOH=-1mA
2.7 to 5.5
VDD-0.4
VOH(6)
PWM0, PWM1
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(7)
P05 (CK0 when
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
2.7 to 5.5
VDD-0.4
VOH(8)
using system
clock output
unit
2.7 to 5.5
IIL(3)
VOH(4)
max
µA
IOH=-1mA
function)
Low level output
VOL(1)
IOL=30mA
4.5 to 5.5
1.5
voltage
VOL(2)
IOL=5mA
3.0 to 5.5
0.4
VOL(3)
IOL=2.5mA
2.7 to 5.5
0.4
P00, P01
VOL(4)
Ports 0, 1, 2
IOL=10mA
4.5 to 5.5
1.5
VOL(5)
PWM0, PWM1
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.7 to 5.5
0.4
VOL(6)
XT2
VOL(7)
Port 3
IOL=1.6mA
3.0 to 5.5
0.4
VOL(8)
P70
IOL=1mA
2.7 to 5.5
0.4
VOL(9)
P71 to P73
0.4
VOL(10)
Pull-up resistance
IOL=5mA
3.0 to 5.5
IOL=2.5mA
2.7 to 5.5
VOH=0.9VDD
4.5 to 5.5
15
35
80
18
50
150
V
0.4
Rpu(1)
Ports 0, 1, 2, 3
Rpu(2)
Port 70
2.7 to 5.5
Hysteresis voltage
VHYS
RES
Ports 1, 2, 3, 7
2.7 to 5.5
0.1VDD
V
Pin capacitance
CP
All pins
2.7 to 5.5
10
pF
kΩ
For pins other than that under test:
VIN=VSS
f=1MHz
Ta=25°C
No.A0590-14/26
LC87F14C8SA
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Pin/
SCK0(P12)
Specification
Conditions
Remarks
VDD[V]
See Fig. 8.
typ
max
unit
2
1
pulse width
High level
min
tSCKH(1)
1
pulse width
• Continuous data
tSCKHA(1a)
transmission/reception mode
• USB, SIO4 nor SIO9 are
4
not in use simultaneous.
Input clock
• See Fig. 8.
• (Note 4-1-2)
• Continuous data
tSCKHA(1b)
2.7 to 5.5
tCYC
transmission/reception mode
• USB is in use simultaneous.
• SIO4 nor SIO9 are not in
7
use simultaneous.
• See Fig. 8.
• (Note 4-1-2)
• Continuous data
tSCKHA(1c)
transmission/reception mode
• USB, SIO4 and SIO9
9
are in use simultaneous.
Serial clock
• See Fig. 8.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 8.
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
pulse width
tSCKHA(2a)
• Continuous data
Output clock
transmission/reception mode
• USB, SIO4 nor SIO9 are
tSCKH(2)
not in use simultaneous.
+2tCYC
• CMOS output selected
tSCKH(2)
+(10/3)
tCYC
• See Fig. 8.
tSCKHA(2b)
• Continuous data
2.7 to 5.5
transmission/reception mode
• USB is in use simultaneous.
• SIO4 nor SIO9 are not in
use simultaneous.
tSCKH(2)
+2tCYC
tSCKH(2)
+(19/3)
tCYC
tCYC
• CMOS output selected
• See Fig. 8.
tSCKHA(2c)
• Continuous data
transmission/reception mode
• USB, SIO4 and SIO9
are in use simultaneous.
• CMOS output selected
tSCKH(2)
+2tCYC
tSCKH(2)
+(25/3)
tCYC
• See Fig. 8.
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock
is “H” to the first negative edge of the serial clock must be longer than tSCKHA.
Continued on next page.
No.A0590-15/26
LC87F14C8SA
Continued from preceding page.
Parameter
Serial input
Data setup time
Symbol
tsDI(1)
SB0(P11),
SI0(P11)
Specification
Conditions
VDD[V]
min
typ
max
unit
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
2.7 to 5.5
0.03
• See Fig. 8.
Data hold time
Output delay
thDI(1)
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data transmission/
reception mode
(1/3)tCYC
2.7 to 5.5
+0.05
Input clock
• (Note 4-1-3)
• Synchronous 8-bit mode
tdD0(2)
• (Note 4-1-3)
tdD0(3)
µs
1tCYC
2.7 to 5.5
+0.05
(Note 4-1-3)
Output clock
Serial output
Pin/
Remarks
(1/3)tCYC
2.7 to 5.5
+0.05
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 8.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Pin/
SCK1(P15)
VDD[V]
See Fig. 8.
Frequency
SCK1(P15)
• CMOS output selected
2
1/2
2.7 to 5.5
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
tsDI(2)
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
2.7 to 5.5
0.03
• See Fig. 8.
Data hold time
Output delay time
Serial output
unit
1
tSCKL(4)
pulse width
High level
max
1
• See Fig. 8.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
2.7 to 5.5
pulse width
High level
Specification
Conditions
Remarks
pulse width
Output clock
Serial clock
Input clock
Parameter
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
µs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
2.7 to 5.5
change in open drain output
(1/3)tCYC
+0.05
mode.
• See Fig. 8.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0590-16/26
LC87F14C8SA
3. SIO4 Serial I/O Characteristics (Note 4-3-1)
Parameter
Symbol
Frequency
tSCK(5)
Low level
tSCKL(5)
Pin/
SCK4(P24)
Specification
Conditions
Remarks
VDD[V]
See Fig. 8.
tSCKH(5)
pulse width
tSCKHA(5a)
typ
max
unit
2
1
pulse width
High level
min
1
• USB, SIO9 nor continuous data
transmission/reception mode of
SIO0 are not in use simultaneous.
4
• See Fig. 8.
Input clock
• (Note 4-3-2)
• USB is in use simultaneous.
tSCKHA(5b)
2.7 to 5.5
• SIO9 nor continuous data
tCYC
transmission/reception mode of
7
SIO0 are not in use simultaneous.
• See Fig. 8.
• (Note 4-3-2)
• USB, SIO9 and continuous data
tSCKHA(5c)
transmission/reception mode of
SIO0 are in use simultaneous.
12
Serial clock
• See Fig. 8.
• (Note 4-3-2)
Frequency
tSCK(6)
Low level
tSCKL(6)
SCK4(P24)
• CMOS output selected
4/3
• See Fig. 8.
1/2
pulse width
High level
tSCK
tSCKH(6)
1/2
pulse width
• USB, SIO9 nor continuous data
tSCKHA(6a)
transmission/reception mode of
Output clock
SIO0 are not in use simultaneous.
• CMOS output selected
tSCKH(6)
tSCKH(6)
+(5/3)
+(10/3)
tCYC
tCYC
tSCKH(6)
tSCKH(6)
+(5/3)
+(19/3)
tCYC
tCYC
tSCKH(6)
tSCKH(6)
+(5/3)
+(34/3)
tCYC
tCYC
• See Fig. 8.
• USB is in use simultaneous.
tSCKHA(6b)
2.7 to 5.5
• SIO9 nor continuous data
transmission/reception mode of
SIO0 are not in use simultaneous.
• CMOS output selected
tCYC
• See Fig. 8.
• USB, SIO9 and continuous data
tSCKHA(6c)
transmission/reception mode of
SIO0 are in use simultaneous.
• CMOS output selected
• See Fig. 8.
Serial input
Data setup time
SO4(P22),
SI4(P23)
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
2.7 to 5.5
0.03
• See Fig. 8.
Data hold time
Output delay time
Serial output
tsDI(3)
thDI(3)
tdD0(5)
SO4(P22),
SI4(P23)
µs
• Must be specified with respect
to rising edge of SIOCLK.
• Must be specified as the time to
the beginning of output state
change in open drain output
2.7 to 5.5
(1/3)tCYC
+0.05
mode.
• See Fig. 8.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input in continuous trans/rec mode, a time from SI4RUN being set when serial clock
is “H” to the first negative edge of the serial clock must be longer than tSCKHA.
No.A0590-17/26
LC87F14C8SA
4. SIO9 Serial I/O Characteristics (Note 4-4-1)
Parameter
Symbol
Frequency
tSCK(7)
Low level
tSCKL(7)
Pin/
SCK9(P27)
Specification
Conditions
Remarks
VDD[V]
See Fig. 8.
tSCKH(7)
pulse width
tSCKHA(7a)
typ
max
unit
2
1
pulse width
High level
min
1
• USB, SIO4 nor continuous data
transmission/reception mode of
SIO0 are not in use simultaneous.
4
• See Fig. 8.
Input clock
• (Note 4-4-2)
• USB is in use simultaneous.
tSCKHA(7b)
2.7 to 5.5
• SIO4 nor continuous data
tCYC
transmission/reception mode of
7
SIO0 are not in use simultaneous.
• See Fig. 8.
• (Note 4-4-2)
• USB, SIO4 and continuous data
tSCKHA(7c)
transmission/reception mode of
SIO0 are in use simultaneous.
13
Serial clock
• See Fig. 8.
• (Note 4-4-2)
Frequency
tSCK(8)
Low level
tSCKL(8)
SCK9(P27)
• CMOS output selected
4/3
• See Fig. 8.
1/2
pulse width
High level
tSCK
tSCKH(8)
1/2
pulse width
• USB, SIO4 nor continuous data
tSCKHA(8a)
transmission/reception mode of
Output clock
SIO0 are not in use simultaneous.
• CMOS output selected
tSCKH(8)
tSCKH(8)
+(5/3)
+(10/3)
tCYC
tCYC
tSCKH(8)
tSCKH(8)
+(5/3)
+(19/3)
tCYC
tCYC
tSCKH(8)
tSCKH(8)
+(5/3)
+(37/3)
tCYC
tCYC
• See Fig. 8.
• USB is in use simultaneous.
tSCKHA(8b)
2.7 to 5.5
• SIO4 nor continuous data
transmission/reception mode of
SIO0 are not in use simultaneous.
• CMOS output selected
tCYC
• See Fig. 8.
• USB, SIO4 and continuous data
tSCKHA(8c)
transmission/reception mode of
SIO0 are in use simultaneous.
• CMOS output selected
• See Fig. 8.
Serial input
Data setup time
SO9(P25),
SI9(P26)
• Must be specified with respect
to rising edge of SIOCLK.
2.7 to 5.5
0.03
2.7 to 5.5
0.03
• See Fig. 8.
Data hold time
Output delay time
Serial output
tsDI(4)
thDI(4)
tdD0(6)
SO9(P25),
SI9(P26)
µs
• Must be specified with respect
to rising edge of SIOCLK.
• Must be specified as the time to
the beginning of output state
change in open drain output
2.7 to 5.5
(1/3)tCYC
+0.05
mode.
• See Fig. 8.
Note 4-4-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-4-2: To use serial-clock-input in continuous trans/rec mode, a time from SI9RUN being set when serial clock
is “H” to the first negative edge of the serial clock must be longer than tSCKHA.
No.A0590-18/26
LC87F14C8SA
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
High/low level
tP1H(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tP1L(1)
INT1(P71),
• Event inputs for timer 0 or 1
INT2(P72),
min
typ
max
unit
are enabled.
INT4(P20 to P23),
2.7 to 5.5
1
2.7 to 5.5
2
2.7 to 5.5
64
2.7 to 5.5
256
2.7 to 5.5
200
INT5(P24 to P27),
INT6(P20),
INT7(P24)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
constant is 1/1
enabled.
tPIH(3)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
constant is 1/32
enabled.
tPIH(4)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
constant is 1/128
tPIL(5)
RES
tCYC
enabled.
Resetting is enabled.
µs
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07),
(Note 6-1)
TCAD
AN9(P71),
AD conversion time = 32×tCYC
AN10(XT1),
(when ADCR2 = 0) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
AD conversion time = 64×tCYC
(when ADCR2 = 1) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN = VDD
3.0 to 5.5
input current
IAINL
VAIN = VSS
3.0 to 5.5
max
unit
8
3.0 to 5.5
AN11(XT2)
Analog input
typ
bit
±1.5
AN8(P70),
accuracy
Conversion time
min
3.0 to 5.5
15.68
97.92
(tCYC=
(tCYC=
0.49µs)
3.06µs)
23.52
97.92
(tCYC=
(tCYC=
0.735µs)
3.06µs)
18.82
97.92
(tCYC=
(tCYC=
0. 294µs)
1.53µs)
47.04
97.92
(tCYC=
(tCYC=
0.735µs)
1.53µs)
VSS
VDD
1
-1
LSB
µs
V
µA
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0590-19/26
LC87F14C8SA
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/
VDD[V]
• FmCF=12MHz ceramic oscillation mode
consumption
VDD1
=VDD2
current
=VDD3
• System clock set to 12MHz side
Normal mode
(Note 7-1)
IDDOP(1)
IDDOP(2)
Specification
Conditions
Remarks
• FsX’tal=32.768kHz crystal oscillation mode
min
typ
max
4.5 to 5.5
9.3
23
3.0 to 3.6
5.3
13
4.5 to 5.5
12
28
3.0 to 3.6
6.4
16
4.5 to 5.5
6.1
15
3.0 to 3.6
3.5
8.2
unit
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• 1/1 frequency division ration
IDDOP(3)
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
IDDOP(4)
• Internal PLL oscillation mode
• Internal RC oscillation stopped
mA
• 1/1 frequency division ration
IDDOP(5)
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(6)
• System clock set to 6MHz side
IDDOP(7)
• Internal RC oscillation stopped
• 1/2 frequency division ration
2.7 to 3.0
2.9
6.4
IDDOP(8)
• FmCF=0MHz (oscillation stopped)
4.5 to 5.5
0.68
3.3
IDDOP(9)
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(10)
IDDOP(11)
3.0 to 3.6
0.36
1.6
• 1/2 frequency division ration
2.7 to 3.0
0.30
1.23
• FmCF=0MHz (oscillation stopped)
4.5 to 5.5
42
160
3.0 to 3.6
17
64
2.7 to 3.0
13
46
4.5 to 5.5
4.6
11
3.0 to 3.6
2.5
6.2
4.5 to 5.5
6.4
16
• System clock set to internal RC oscillation
• FsX’tal=32.768kHz crystal oscillation mode
IDDOP(12)
IDDOP(13)
HALT mode
IDDHALT(1)
• System clock set to 32.768kHz side
• 1/2 frequency division ration
• HALT mode
consumption
• FmCF=12MHz ceramic oscillation mode
current
• FsX’tal=32.768kHz crystal oscillation mode
(Note 7-1)
IDDHALT(2)
µA
• Internal RC oscillation stopped
• System clock set to 12MHz side
• Internal PLL oscillation stopped
• Internal RC oscillation stopped
• 1/1 frequency division ration
IDDHALT(3)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
IDDHALT(4)
mA
• System clock set to 12MHz side
• Internal PLL oscillation mode
• Internal RC oscillation stopped
3.0 to 3.6
3.5
8.5
4.5 to 5.5
2.8
6.8
3.0 to 3.6
1.5
3.7
2.7 to 3.0
1.3
2.9
• 1/1 frequency division ration
IDDHALT(5)
• HALT mode
• FmCF=12MHz ceramic oscillation mode
IDDHALT(6)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 6MHz side
IDDHALT(7)
• Internal RC oscillation stopped
• 1/2 frequency division ration
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0590-20/26
LC87F14C8SA
Continued from preceding page.
Parameter
Symbol
HALT mode
IDDHALT(8)
consumption
IDDHALT(9)
current
(Note 7-1)
Pin/
Specification
Conditions
Remarks
VDD[V]
VDD1
=VDD2
• HALT mode
=VDD3
• FsX'tal=32.768kHz crystal oscillation mode
0.37
1.8
3.0 to 3.6
0.18
0.84
2.7 to 3.0
0.15
0.63
4.5 to 5.5
27
108
3.0 to 3.6
8.2
38
• 1/2 frequency division ration
2.7 to 3.0
5.9
26
HOLD mode
4.5 to 5.5
0.10
27
• CF1=VDD or open
3.0 to 3.6
0.04
18
2.7 to 3.0
0.04
16
• HALT mode
• FmCF=0MHz (oscillation stopped)
• FsX'tal=32.768kHz crystal oscillation mode
IDDHALT(12)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
IDDHALT(13)
IDDHOLD(1)
VDD1
IDDHOLD(2)
current
max
4.5 to 5.5
• FmCF=0MHz (oscillation stopped)
• 1/2 frequency division ration
IDDHALT(11)
consumption
typ
(External clock mode)
IDDHOLD(3)
Timer HOLD
IDDHOLD(4)
Timer HOLD mode
4.5 to 5.5
22
92
mode
IDDHOLD(5)
• CF1=VDD or open
3.0 to 3.6
5.4
29
2.7 to 3.0
3.5
18
consumption
mA
µA
(External clock mode)
IDDHOLD(6)
current
unit
• System clock set to internal RC oscillation
IDDHALT(10)
HOLD mode
min
• FsX’tal=32.768kHz crystal oscillation mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
USB Characteristics and Timing at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Specification
Conditions
min
typ
max
unit
High level output
VOH(USB)
• 15kΩ±5% to GND
Low level output
VOL(USB)
• 1.5kΩ±5% to 3.6V
Output signal crossover voltage
VCRS
Differential input sensitivity
VDI
Differential input common mode range
VCM
0.8
High level input
VIH(USB)
2.0
Low level input
VIL(USB)
0.8
V
USB data rise time
tR
• RS=33Ω, CL=50pF
4
20
ns
USB data fall time
tF
• RS=33Ω, CL=50pF
4
20
ns
• ⏐(UHD+)-(UHD-)⏐
2.8
3.6
0.3
V
1.3
2.0
V
0.2
V
V
2.5
V
V
F-ROM Write Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin
Specification
Conditions
VDD[V]
Onboard
IDDFW(1)
VDD1
typ
max
unit
• 128-byte programming
• Erasing current included
programming
min
3.0 to 5.5
25
40
mA
3.0 to 5.5
22.5
45
ms
current
Programming
time
tFW(1)
• 128-byte programming
• Erasing current included
• Time for setting up 128-byte data is excluded.
No.A0590-21/26
LC87F14C8SA
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rd1
Range
[pF]
[pF]
[Ω]
[V]
[ms]
[ms]
1k
2.7 to 5.5
0.10
0.50
6MHz
MURATA
CSTCR6M00G15***-R0
(39)
(39)
typ
max
8MHz
MURATA
CSTCE8M00G15***-R0
(33)
(33)
470
3.0 to 5.5
0.10
0.50
10MHz
MURATA
CSTCE10M0G15***-R0
(33)
(33)
330
3.0 to 5.5
0.10
0.50
12MHz
MURATA
CSTCE12M0G15***-R0
(33)
(33)
330
3.0 to 5.5
0.10
0.50
Remarks
Built in C1, C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a CF Oscillator
Nominal
Vendor
Frequency
Name
EPSON
32.768kHz
TOYOCOM
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
OPEN
510k
2.7 to 5.5
1.1
3.0
MC-306
Remarks
Applicable
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf
Rd1
C1
CF
C2
Figure 1 CF Oscillator Circuit
Rd2
C3
X’tal
C4
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0590-22/26
LC87F14C8SA
VDD
Operating VDD
lower limit
GND
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF oscillation
(XT1, XT2)
tmsX’tal
Crystal oscillation
(XT1, XT2)
State
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset
signal
HOLD reset signal
absen
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF oscillation
(XT1, XT2)
tmsX’tal
Crystal
Oscillation
(XT1, XT2)
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0590-23/26
LC87F14C8SA
P34/FILT
When using the internal PLL circuit to generate the
48MHz clock for USB , it is necessary to connect a filter
circuit such as that shown to the left to the P34/FILT pin.
0Ω
+
-
2.2µF
Figure 5 Filter Circuit for the Internal PLL Circuit
33Ω
UHD+
5pF
15kΩ
Note:
It’s necessary to adjust the Circuit Constant of
the USB Port Peripheral Circuit each mounting
board.
33Ω
UHD5pF
15kΩ
Figure 6 USB Port Peripheral Circuit
VDD
RRES
RES
CRES
Note:
Determine the value of CRES and RRES so
that the reset signal is present for a period of
200µs after the supply voltage goes beyond the
lower limit of the IC's operating voltage.
Figure 7 Reset Circuit
No.A0590-24/26
LC87F14C8SA
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transfer
period (SIO0, 4, 9 only)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transfer
period (SIO0, 4, 9 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 8 Serial Input/Output Waveforms
tPIL
tPIH
Figure 9 Pulse Input Timing Signal Waveform
Voh
tr
D+
tr
90%
90%
Vcrs
10%
Vol
10%
D-
Figure 10 USB Data Signal Timing and Voltage Level
No.A0590-25/26
LC87F14C8SA
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of February, 2007. Specifications and information herein are subject
to change without notice.
PS No.A0590-26/26