SANYO LV24230LS

Ordering number : ENA1989
LV24230LS
Bi-CMOS LSI
Compact Portable Equipment
1-Chip FM Tuner IC
Overview
The LV24230LS is an I2C-controlled single-chip FM tuner IC that integrates external components which are necessary for
tuning in a compact VQLP package with dimensions of only 3.5×3.5×0.85mm3. Equipped with a state machine, the
LV24230LS has the capability to perform automatic tuning/seek and dissipates less power than conventional
LV24000series tuner ICs.
Features
• FM FE
• FM IF
• MPX stereo decoder
• Tuning
• Standby
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Maximum input voltage
Symbol
Ratings
Unit
Analog block supply voltage
5.0
V
VDD max
Digital block supply voltage
4.0
V
VIN1 max
SCL, SDA, Int
VDD+0.3
V
External_clk_in
VDD+0.3
VIN2 max
Allowable power dissipation
Conditions
VCC max
Pd max
Ta ≤ 70°C
140
V
mW
Operating temperature
Topr
-20 to +70
°C
Storage temperature
Tstg
-40 to +125
°C
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,
safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives
in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any
guarantee thereof. If you should intend to use our products for new introduction or other application different
from current conditions on the usage of automotive device, communication device, office equipment, industrial
equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the
intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely
responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer ' s products or
equipment.
O1211 SY 20080801-S00007 No.A1989-1/17
LV24230LS
Operating Conditions at Ta = 25°C
Parameter
Recommended supply voltage
Operating supply voltage range
Symbol
Conditions
Ratings
Unit
VCC
Analog block supply voltage
3.0
V
VDD
Digital block supply voltage
3.0
V
2.6 to 4.0
V
2.5 to 4.0
V
1.62 to 4.0
V
VCC op
VDD op
VIO op
Interface voltage
Note : Supply voltage VIO equal VDD, or VIO < VDD & VIO > 0.65 VDD
Operating Characteristics at Ta = 25°C, VCC = 3.0V, VDD = 3.0V, Volume set at maximum,
Soft Mute = 1/Soft Stereo = off with the designated test circuit
Output level set with Radio Control 1 of control register map (0Dh Bit0, Bit1 set to ‘1’, ‘1’)
In addition, Set IF_OSC = 150kHz, IF_BW = 100% (Radio Control 1 : 0D Bit6, Bit7 set to ‘1’, ’1’)
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
Current drain
ICCA
Analog block at 60dBμV EMF input
12
17
mA
(in operation)
ICCD
Digital block at 60 dBμV EMF input
0.3
0.8
mA
Current drain
ICCA
Analog standby mode
3
30
μA
ICCD
Digital standby mode
(in standby)
FM receive band
F_range
30
μA
108
MHz
3
Refer to PCB mounting conditions to cover
76
the FM receive band of 76M to 108MHz
FM receive characteristics; MONO : fc = 80MHz, fm = 1kHz, 22.5kHzdev. Note that Soft_mute = 1, Soft_stereo function OFF, IHF-BPF used
3dB sensitivity
-3dB LS
60dBμV, 22.5kHzdev output standard,
5
17
dBμV
8
16
dBμV
-3dB input.
EMF
Practical sensitivity 1
QS1
Input at S/N = 30dB
Practical sensitivity 2 (Reference)
QS2
Input at S/N = 26dB
De-emphasis = 75μs, SG open display
EMF
μV
1.10
De-emphasis = 75μs, SG terminal display
Demodulation output
Vo
60dBμV EMF, pin 19 output
80
110
160
Channel balance
CB
60dBμV EMF, pin 18 output/pin 19 output
-2
0
2
Signal-to-noise ratio
S/N
60dBμV EMF, pin 19 output
48
58
Total harmonic distortion 1
mVrms
dB
dB
THD1
60dBμV EMF, pin 19 output, 22.5kHz dev.
0.4
1.5
%
THD2
60dBμV EMF, pin 19 output, 75.0kHz dev.
1.3
3
%
10
20
dBμV
(MONO)
Total harmonic distortion 2
(MONO)
Field intensity display level
FS
Reg1Dh_bit0 = OFF
3
Input level at which Reg02h_bit1-3 change
EMF
from 1 to 2.
Mute attenuation
Mute-Att.
60dBμV EMF, pin 19 output
60
70
dB
FM receive characteristics ; STEREO characteristics : fc = 80MHz, fm = 1kHz, VIN = 60dBμV EMF, Pilot = 10% (7.5kHzdev), MPX-Filter used
Separation
SEP
L-mod, pin 19 / pin 18 output
20
35
dB
L+R signals = 30% (22.5kHz dev.)
Total harmonic distortion (Main)
THD-ST1
Main-mod (for L + R input), 19 output
0.6
1.8
%
IHF_BPF L+R signals = 30% (22.5kHzdev.)
Interface block allowable operation range at Ta = -20 to +70°C, VSS = 0V
Ratings
Parameter
Symbol
Conditions
Unit
min
Supply voltage
VDD
Digital block input
VIH
High-level input voltage range
VIL
Low-level input voltage range
IOL
Output current at Low level
VOL
Output voltage at Low level IOL = 2mA
Digital block output
External clock operating frequency
fclk_ext
typ
2.5
Clock frequency for external input
max
4.0
V
0.7VDD
VDD
V
0
0.1VDD
2.0
32k
V
mA
32.768k
0.6
V
20M
Hz
Note : External clock input (pin 12) allows also input of the sine wave signal.
No.A1989-2/17
LV24230LS
Package Dimensions
unit : mm (typ)
3393
BOTTOM VIEW
(0.1)
0.35
0.4
24
3.5
(0.054)
3.5
0.35
SIDE VIEW
(0.75)
TOP VIEW
2 1
(0.75)
0.85 MAX
SIDE VIEW
0.0 NOM
0.2
SANYO : VQLP24J(3.5X3.5)
VCC
NC
Vstabi
NC
MPX
Line_out_R
Pin Assignment
18 17 16 15 14 13
12 Ext_CLK_IN
Line_out_L 19
Package-GND 20
11 Package-GND
Package-GND 21
10 Package-GND
Package-GND 22
9 Package-GND
Package-GND 23
8 Package-GND
1
2
3
4
5
6
FM_ANT2
VIO
VDD
INT
SDA
7 SCL
FM_ANT1
GND 24
No.A1989-3/17
LV24230LS
Line_out_R
MPX
NC
Vstabi
NC
V
CC
Block Diagram
18
17
16
15
14
13
Voltage
Stabilizer
Line_out_L 19
Package_GND 20
Package_GND 21
Demodulator
Package_GND 22
FM Selectivity
Filter
11 Package_GND
Mute
Stereo
Decorder
FM
Deemphasis
10 Package_GND
Tuning
System
FLL
RF and FM
Quadrature
Mixer
Package_GND 23
To
Each Block
Line SW
And
Buffer
AMP
12 Ext_CLK_IN
Tuning
Power
Manage
ment
Quadrature
Oscillator
Digital Interface
I2C Conversion
To
Each
Block
GND 24
1
2
3
4
5
6
FM_ANT1
FM_ANT2
VIO
DD
V
INT
SDA
To
Each Block
9
Package_GND
8
Package_GND
7
SCL
No.A1989-4/17
LV24230LS
Pin Function
Pin No.
Pin name
1
FM-ANT1
Antenna input
Description
Pin voltage
1V
2
FM-ANT2
Antenna GND
1V
Supplement
Antenna input pin
Antenna input pin. For pin 1 single input, pin 2 is set to AC_GND
via capacity
3
VI/O
Digital interface supply voltage
Power pin dedicated to the interface input/output elements
4
VDD
Digital supply voltage
Power pin for digital block
5
INT
Interrupt line
Output pin dedicated to interrupt
(hardware output: used for options)
Addition of pull-up or pull-down resistor recommended to cope
with initial instability
6
SDA
Digital interface DATA ine)
Bidirectional data line. Pull up to Vio line with 2.2k resistor
7
SCL
Digital interface Clock line)
Clock wire. Pull up to Vio line with 2.2k resistor
8
Package-GND
GND for package-shield
BND pin for package shield
BND pin for package shield
9
Package-GND
GND for package-shield
10
Package-GND
GND for package-shield
BND pin for package shield
11
Package-GND
GND for package-shield
BND pin for package shield
12
Ext_CLK_IN
13
VCC
14
NC
15
Vstabi.
16
NC
17
MPX
18
LINE-OUT-R
Reference clock-source input
External standard CLK input pin. Connect X’tal, if used, to GND.
for measurement
(CITIZEN CFS-206, CM31S recommended)
Analog supply voltage
Power pin for analog (tuner) block
Keep this open.
Stabilizer voltage
2.6V
Local oscillator reference bias pin. NC pin to be used
Keep this open.
MPX-signal output
2.3V
Stereo decoder input monitor pin. NC pin to be used
Radio Rch Line-output
1.2V
Audio R_ch output
Radio Lch Line-output
1.2V
19
LINE-OUT-L
20
Package-GND
GND for package-shield
GND pin for package shield
Audio L_ch output
21
Package-GND
GND for package-shield
GND pin for package shield
22
Package-GND
GND for package-shield
GND pin for package shield
23
Package-GND
GND for package-shield
GND pin for package shield
24
GND
GND (Analog and Digital GND)
GND pin for analog (FM tuner) block and digital (control) block
No.A1989-5/17
LV24230LS
Format of Bus Transfers
Bus transfers are primarily based on the I2C primitives
• Start condition
• Repeated start condition
• Stop condition
• Byte write
• Byte read
Start, restart, and stop conditions are specified as shown in Table 1 below.
Start
Repeated start
Stop
SCL
SCL
SCL
SDA
SDA
SDA
Fig. 1 the I2C start, repeated start and stop conditions.
For details, like timing, etc., refer to specifications of I2C.
8-bit write
8-bit data is sent from the master microcomputer to LV24230LS.
Data bit consists of MSB first and LSB last.
Data transmission is latched at the rising edge of SCL in synchronization with the SCL clock generated at the master IC.
Do not change data while SCL remains HIGH.
LV24230LS outputs the ACK bit between eighth and ninth falling edges of SCL
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Ack
Fig. 2 Signal pattern of the I2C byte write
Read is of the same form as write, only except that the data direction is opposite.
Eight data bits are sent from LV24230LS to the master while Ack is sent from the master to LV24230LS.
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
Ack
Fig. 3 Signal pattern of the I2C byte read
The serial clock SCL is supplied from the master side. It is essential that data bit is output from LV24230LS in
synchronization with the falling edge while the master side performs latching at the rising edge.
No.A1989-6/17
LV24230LS
LV24230LS latches ACK at the rising edge.
The sequence to write data D into the register A of LV24230LS is shown below.
• Start condition
• write the device address (C0h)
• write the register address, A
• write the target data, D
• stop condition
start
write device address
SCL
DA7
SDA
Ack
DA6...1
write register address
A7
A6...1
write data byte
Ack
D7
stop
Ack
D6...0
Fig. 4 Register write through I2C
When one or more data has been provided for writing, only the first data is allowed to be written.
Read sequence
• start condition
• write the device address (C0h)
• write the register address, A
• repeated start condition (or stop + start in a single master network)
• write the device address + 1 (C1h)
• read the register contents D, transmit NACK (no more data to be read)
• stop condition
start
write device address
write register address
rep.
SCL
DA7
SDA
start
DA6...1
Ack
write device address + 1
DA7
DA6...1
A7
A6...0
read data byte with NACK
Ack
D7
Ack
stop
D6...0
Fig. 5 Register read through I2C
Interrupt Pin INT
LV24230LS has the dedicated interrupt output pin. For the active level to the host, either LOW or HIGH can be selected.
The INT output pin is kept floating while the PWRAD bit is cleared during initialization.
Therefore, to avoid influence on the CPU side during initialization, it is recommended to secure the non-active state by
means of the pull-up or pull-down resistor.
This enables direct INT output connection to non-masking interruption of the host CPU.
No.A1989-7/17
LV24230LS
Digital interface specification (interface specification : reference)
(1). Characteristics of SDA and SCL bus line relative to the I2C bus interface
Repeated START
START Condition
Tf
TLOW
Tr
THIGH
SCL
Tf
Tr
SDA
THD;STA
THD;DAT
TSU;DAT
TSU;STA
Standard-mode
Parameter
Symbol
SCL clock frequency
min
FSCL
High_Speed-mode
max
min
100
0
400
Fall time of both SDA and SCL
Tf
300
20+0.1Cb
300
ns
Rise time of both SDA and SCL
Tr
1000
20+0.1Cb
300
ns
High time of SCL
0
unit
max
THIGH
4.0
kHz
μs
0.6
TLOW
4.7
1.3
μs
Hold time of STAT condition
THD ; STA
4.0
0.6
μs
Hold time of Data
THD ; DAT
0
Set-up time of STAT condition
TSU ; STA
4.7
0.6
μs
Set-up time of STOP condition
TSU ; STO
4.0
0.6
μs
Set-up time of Data
TSU ; DAT
250
100
ns
TBUF
4.7
1.3
μs
Low time of SCL
Bus free time between a STOP and
Capacitivie load for each bus line
3.45
Cb
0
400
0.9
400
μs
pF
*Cb = Total capacitance of one bus line
(2). Register map (On Register Map)
Following is Sub address map of LV24230LS. Each register becomes 8-bit constitution.
Address
00h
Register Name
CHIP_ID
02h
RADIO_STAT
0Bh
RFCAP
Mode
R/W
R
R/W
Remark
Chip ID
Status of Radio Station
RF Cap bank
0Dh
RADIO_CTRL1
R/W
Radio Control 1
0Eh
RADIO_CTRL2
R/W
Radio Control 2
0Fh
RADIO_CTRL3
R/W
Radio Control 3
10h
TNPL
R
Tune Position Low
11h
TNPH_STAT
R
Tune Position High and Status
19h
REF_CLK_PRS
R/W
Reference clock pre-scalar
1Ah
REF_CLK_DIV
R/W
Reference clock divider
1Bh
REF_CLK_OFF
R/W
Reference clock offset
1Dh
SCN_CTRL
R/W
Scan control
1Eh
TARGET_VAL_L
R/W
Target value Low
1Fh
TARGET_VAL_H
R/W
Target value High
R : Read only register
R/W : Read and Write register
No.A1989-8/17
LV24230LS
(3). Register description (ON Contents of each Register)
Register 00h – CHIP_ID – Chip identify register (Read/Write)
7
6
5
4
3
2
1
2
1
0
ID [7 : 0]
bit 7-0 :
ID [7 : 0] : 8-bit chip ID.
LV24230LS : 12h
Note : To abort the command, write any value in this register.
Register 02h – RADIO_STAT – Radio station status (Read-Only)
7
6
5
4
RAD_IF
N/A
N/A
MO_ST
bit 7 :
3
FS [2 : 0]
0
SF5DB
RAD_IF : Radio interrupt flag.
0 = no interrupt
1 = interrupt
Note :
When status (field strength, stereo/mono) changes, this bit is set.
If Interrupt of IRQ pin is enabled, Interrupt pin is set by following IPOL register condition.
This bit is cleared by register read. In stand-by mode (PW_RAD = 0), this bit is 1
bit 6-5 :
NA [1 : 0] : NA 0 fixed
bit 4 :
MO_ST : Mono/stereo indicator
0 = Forced monaural
1 = Normal (Receiving in stereo mode)
bit 3-1
FS [2 : 0] : Fieldstrength :
0 = Low field strength
…
7 = High field strength
bit 0 :
SF5DB : Fieldstrength +5dB :
0 = FS5dB no UP
1 = FS5dB UP
For details, refer to Application note.
Register 0Bh – RFCAP – RF Cap bank (Read/Write)
7
6
5
4
3
2
1
0
RFCAP [7 : 0]
bit 7-0 :
RFCAP [7 : 0] : RF Oscillator CAP bank
No.A1989-9/17
LV24230LS
Register 0Dh – RADIO_CTRL1 – Radio control 1 (Read/Write)
7
6
5
4
3
2
IF_SEL
IFBWSEL
AGC_SPD
DEEM
ST_M
nMUTE
bit 7 :
1
0
VOL [1 : 0]
IF_SEL : IF Frequency Setting
0 = 130kHz
1 = 150kHz
bit 6 :
IFBWSEL : IF band width setting
0 = 50%
1 = 100%
bit 5 :
AGC_SPD : AGC Speed setting
0 = Normal
1 = High
bit 4 :
DEEM : de-emphasis
0 = 50μs : Korea, China, Europe, Japan
1 = 75μs : USA
bit 3 :
ST_M : Stereo/mono setting
0 = Stereo enabled
1 = Stereo disabled (mono mode)
bit 2 :
nMUTE : Audio Mute
0 = Mute On
1 = Mute Off
bit 1-0 :
VOL [1 : 0] : Volume Setting
0 : Min
…
3 : Max
Register 0Eh – RADIO_CTRL2 – Radio control 2 (Read/Write)
7
6
5
4
SOFTST [2 : 0]
bit 7-5 :
3
SOFTMU [2 : 0]
2
1
0
N/A
STABI_BP
SOFTST [2 : 0] : Soft Stereo setting
000b = Soft stereo level 3
001b = Disable soft stereo
010b = Soft stereo level 1 (*)
100b = Soft stereo level 2
Note : do not use without these value.
(*) : recommended setting
bit 4-2 :
SOFTMU [2 : 0] : Soft audio mute setting
000b = Soft audio mute level 3
001b = Disable soft audio mute
010b = Soft audio mute level 1
100b = Soft audio mute level 2 (*)
Note : do not use without these value.
(*) : recommended setting
bit 1 :
Reserved : 0 (Fix)
bit 0 :
STABI_BP : Internal regulator by-pass bit
0 = Internal regulator operate (normal)
1 = Internal regulator by-pass
No.A1989-10/17
LV24230LS
Register 0Fh – RADIO_CTRL3 – Radio control 3 (Read/Write)
7
6
5
4
3
IPOL
SM_IE
RAD_IE
SD_PM
nIF_PM
bit 7 :
2
1
EXT_CLK_CFG [1 : 0]
0
PW_RAD
IPOL : Interrupt (IRQ) Polarity
0 = IRQ active high
1 = IRQ active low
bit 6 :
SM_IE : Command end interrupt
0 = Disable
1 = Enable
bit 5 :
RAD_IE : Radio Interrupt (field strength/stereo changes)
0 = Disable
1 = Enable
bit 4 :
SD_PM : Stereo decoder clock PLL mute
0 = SD PLL On (Normal Operation)
1 = SD PLL Off (Adjustment)
bit 3 :
nIF_PM : IF PLL mute
0 = IF PLL Off (Adjustment)
1 = IF PLL On (Normal Operation)
bit 2-1 :
EXT_CLK_CFG [1 : 0] : External Clock Setting
EXT_CLK_CFG [1 : 0]
Reference clock
00
Off
01
32768Hz crystal oscillator
10
Oscillator clock source / 32
(for high frequency source)
11
Oscillator clock source
(for low frequency source)
bit 0 :
PW_RAD : Radio Circuit Power
0 = Power Off (Stand-by).
1 = Power On
Note : At the time of start, PW_RAD becomes 0 (Stand-by)
Register 10h – TNPL – Tune position low (Read-Only)
7
6
5
4
3
2
1
0
TUNEPOS [7 : 0]
bit 7-0 :
TUNEPOS [7 : 0] : Current RF Frequency (Low 8bit)
No.A1989-11/17
LV24230LS
Register 11h – TNPH_STAT – Tune position high/status (Read-Only)
7
6
5
ERROR [2 : 0]
bit 7-5 :
bit 4 :
4
3
2
SM_IF
TUNED
NA
1
0
TUNEPOS [9 : 8]
ERROR [2 : 0] : Error Code
ERROR [2 : 0]
Remark
0
OK, Command end (No Error)
1
Default value after or during reset
2
Band Limit Error
3
DAC Limit Error
6
Command forced End
7
Command busy
SM_IF : Command End interrupt flag
0 = No Interrupt
1 = Interrupt
This bit is set when the command is over. When the IRQ pin interrupt is allowed, the pin status is changed, Reading this register causes clearing.
bit 3 :
TUNED : Radio tuning Flag
0 = No tune
1 = Tuned
Note : This flag is set when Tuned or a station search succeeded.
This flag is cleared under 3 conditions as below.
(1) PW_RAD = 0
(2) Tuning Frequency
(3) FM station searching
bit 2 :
NA : 0 (Fix)
bit 1 : 0 :
TUNEPOS [9 : 8] : Current RF frequency (High 2 bit)
Register 19h – REF_CLK_PRS – Reference clock prescaler (Read/Write)
7
6
5
4
3
REFPRE [2 : 0]
bit [7 : 5] :
2
1
0
2
1
0
2
1
0
REFMOD [4 : 0]
REFPRE [2 : 0] : Reference Clock pre- scaler
0=1:1
1=1:2
…
7 = 1:128
bit [4 : 0] :
REFMOD [4 : 0] : 5-bit slope correction
Register 1Ah – REF_CLK_DIV – Reference clock divider (Read/Write)
7
6
5
4
3
REFDIV [7 : 0]
Bit 7-0 :
REFDIV [7 : 0] : Reference Clock Divider
0 : Divider Value = 1
1 : Divider Value = 2
…
255 : Divider Value = 256
Register 1Bh –REF_CLK_OFF – Reference clock offset (Read/Write)
7
6
5
4
3
REFOFFS [7 : 0]
Bit 7-0 :
REFOFFS [7 : 0] : Offset register for the spread of reference clock
No.A1989-12/17
LV24230LS
Register 1Dh – SCN_CTRL – Scan control (Read/Write)
7
6
GRID [1 : 0]
bit 7-6 :
5
4
FLL_ON
FLL_MODE
3
2
1
FS [2 : 0]
0
SHF5DB
GRID [1 : 0] : FM station search frequency interval :
0 = IFSD set
1 = 50kHz grid
2 = 100kHz grid
3 = 200kHz grid
bit 5 :
FLL_ON : FLL Control
0 = FLL OFF
1 = FLL ON
During setting of the FM frequency and during seek, keep this OFF. Turn it ON after tuning.
bit 4 :
Reserved : 0 (Fix)
bit 3-1 :
FS [2 : 0] : Field strength setting at the time of FM station search and a frequency adjustment bit
Set 1 for setting of IFSD.
bit 0 :
SHF5DB : Scan stop level +5dB
Register1Eh – TARGET_VAL_L – Target Value Low Register (Read/Write)
7
6
5
4
3
2
1
0
1
0
TARGET [7 : 0]
bit 7-0 :
TARGET [7 : 0] : Target frequency low 8 bit :
Tuning frequency or Limit Frequency for FM Station Search
Register 1Fh – TARGET_VAL_H – Target Value High Register (Read/Write)
7
6
5
4
3
2
TARGET [15 : 8]
bit 7-0 :
TARGET [15 : 8] : Target frequency High 8 bit :
Target value of oscillator calibration, Tuning frequency value or limit frequency value for station search
Note : GRID [1 : 0] is not 0 TARGET [15 : 14] has different definition
With radio power ON, lower eight bits of the target frequency are set. Then, set higher eight bits of the target frequency to this register. The command is
executed.
No.A1989-13/17
LV24230LS
Test Circuit
22μF 0.1μF
Line_out_R 1.0μF
VCC
+
19
VCC
External_CLK_IN Voltage
12
Source
20
11
18
Line_out_L
1.0μF
17
16
15
14
13
21
SW
10
Top View
9
23
8
24
7
3
VIO
2
4
5
Package
GND
Pull-up
R:2.2kΩ
SCL
6
SDA
1
FM_ANT
INT
GND
22
VDD
Package
GND
1000pF
R:50Ω
0.1μF
SW
SW
VDD
Voltage
Source
Extenal
CLK_IN
SCL
(CLOCK)
VIO
Voltage
Source
SDA
(DATA)
INT
1000pF
I2C_Bus
MPU
No.A1989-14/17
LV24230LS
Application Circuit
Not necessary
when the CD cut capacity
is on the receive side
Line_out_R 1μF
22μF 0.1μF
+
Changeover of resistor
possible depending on the
state of power supply
VCC
13
External_CLK_IN Voltage
12
Source
VCC
18
17
16
15
14
19
Line_out_L
1μF
4.7μH
or
R:4.7Ω
20
SW
11
21
10
Top View
8
24
7
2.2μH
or
R:12Ω
SW
Changeover of resistor
possible depending on the
state of power supply
6
R1 R2
27pF
47pF
120nH
Winding type
VDD
Voltage
Source
5
R3
SCL
(CLOCK)
100 to
1000pF
4
SCL
SDA
VIO
3
SDA
(DATA)
1μH
2
INT
1
FM_ANT
Package
GND
200Ω to 1kΩ
23
R4
Extenal
CLK_IN
9
INT
GND
22
VDD
Package
GND
0.1μF
R6
R5
Voltage for I2C
interface pull-up
I2C_Bus
MPU
Cautions for mounting of IC
Note1 : For external part constant, the recommended value is described. Since the constant may differ during actual use
with the set mounted, be sure to consider optimization.
Note2 : The differential input antenna application is described. Single input with pin 1 only is also possible.
Note3 : If the spike noise between MPU and IC is large during communication, it is recommended to add limiting
resistors R1, R2, and R3 between MPU and IC. 0Ω at 1.8V.
Note4 : To reduce noise from power supply, add a capacitor between VCC - GND and between VDD - GND.
Note5 : The I2C bus communication line requires pull-up resistors R5 and R6. The commonly-employed resistance value
is 2.2k. Set the pull-up voltage to the same one of VIO of LV24230LS. (Supply from the same source as VIO and
VDD is recommended.
Note6 : Please use the INT pin arbitrarily. Recommended to open when unused.
The INT pin becomes unstable at IC startup. To protect MPU from any effects during startup, it is recommended
to add either the pull-up or pull-down resistor to set the non-active mode. (This is not necessary when the MPU
can be set to non-active by a software during initialization.
No.A1989-15/17
LV24230LS
PCB Mounting Conditions to cover the FM Receiving Area of 76M to 108MHz
LV24230LS's PCB mounting conditions
LV24230LS
Printed Circuit Board
X = 0mm
LAYER
• LV24230LS has an inductor for local oscillator on the package bottom side.
In order to cover the receiving frequency range of 76MHz to 108MHz, provide the GND layer to the first layer of
Side A of PCB that is directly below the package bottom side, as shown in the figure.
Recommended layout of PCB substrate
IC backside_LV24230LS
IC directly-below_PCB recommended
GND patten diagram
• With this SPL, the receiving frequency is measured under the following conditions :
• The X-value can be set freely between Min = 2.00mm and Max = 2.60mm with reference to IC.
(The X-value for Sanyo Demo Board is 2.4mm.)
• The Y-value can be set freely between Min = 1.00mm and Max = 2.40mm with reference to IC.
(The Y-value for Sanyo Demo Board is 2.3mm.)
• Avoid providing another wiring within 0.4mm of bottom layer of PCB_GND as much as possible.
No.A1989-16/17
LV24230LS
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of October, 2011. Specifications and information herein are subject
to change without notice.
PS No.A1989-17/17