Ordering number : ENA1527 Bi-CMOS IC LV8094CT Piezo Actuator Driver IC Overview The LV8094CT is a piezoelectric actuator driver IC. It internally generates drive waveforms and this makes it possible to control piezoelectric actuators with simple instructions. Features • Actuators using piezoelectric elements can be driven and controlled simply by I2C communication. • The piezoelectric drive waveforms are set externally by serial input signals using the I2C interface. The rising and falling timings are determined with clock count. • ENIN input that controls the startup/stop of the IC. • The time for which the actuator is driven is determined with the drive frequency setting based on I2C communication. • Provides a busy signal output during periods when the actuator is being driven by OUT pin output so that applications can be aware of the actuator operating/stopped state. • Built-in undervoltage protection circuits, and register power-on reset function. Specifications Absolute Maximum Ratings at Ta = 25°C, GND = 0V Parameter Symbol Supply voltage VCC max Output current IO max Peak output current Conditions t ≤ 1ms IO peak2 t ≤ 10μs VIN max Allowable power dissipation Pd max Unit -0.5 to 5.0 IO peak1 Input signal voltage Ratings mA 750 mA 1200 mA -0.5 to VCC+0.5 *Mounted on a specified board. V 300 350 V mW Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +125 °C * Specified board : 40mm×40mm×1.6mm, glass epoxy board. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 80509 SY 20090710-S00001 No.A1527-1/15 LV8094CT Allowable Operating Conditions at Ta = 25°C, GND = 0V Parameter Symbol Conditions Ratings Unit Supply voltage VCC 2.2 to 3.3 V Input signal voltage VIN -0.3 to VCC V Corresponding CLK input frequency Fclk to 60 Maximum operating frequency MHz Set STP count × 512 Ct max Times Electrical Characteristics at Ta = 25°C, VCC = 2.8V, GND = 0V, unless otherwise specified. Parameter Symbol Ratings Conditions min Standby mode current drain ICC0 No CLK input, When CLK/SDA=L Operating mode current drain ICC1 CLK = 10MHz, When SCL/SDA=L High-level input voltage Low-level input voltage VIH 2.2V ≤ VCC ≤ 3.3V SCL, SDA VIL 2.2V ≤ VCC ≤ 3.3V SCL, SDA Unit typ max 0.5 1.5 1.0 μA 1.0 mA VCC+0.3 V -0.3 0.3 V CLK pin high-level input voltage VIH2 CLK 0.5×VCC VCC+0.3 V CLK pin low-level input voltage VIL2 CLK -0.3 0.2×VCC V Low voltage detection voltage Vres VCC voltage Output block upper-side on RonP 1.8 2.0 2.2 V 0.8 1.5 Ω resistance Output block lower-side on resistance RonN 1.2 Ω Turn on time TPLH With no load *1 0.15 μS Turn off time TPHL With no load *1 0.1 μS 0.6 *1 : Rising time from 10 to 90% and falling time from 90 to 10% are specified with regard to the OUT pin voltage. Package Dimensions unit : mm (typ) 3381 0.235 SANYO : WLP8(1.67X0.87) W A 0.4 B 0.4 1 0.11 (0.16) SIDE VIEW 0.22 3 2 0.33 MAX LASER MARKED INDEX 4 0.4 Allowable power dissipation, Pd max - Pd max BOTTOM VIEW 0.235 SIDE VIEW 0.87 TOP VIEW 1.67 0.35 Ta Specified board : 40×40×1.6mm3 glass epoxy 0.3 0.2 0.14 0.1 0 30 0 30 60 Ambient temperature, Ta - 90 120 C No.A1527-2/15 LV8094CT Pin Assignment Ball side view A Top view B B A SCL CLK CLK SCL 1 SDA GND GND SDA 2 OUT1 3 RFG 4 0.4 0.4 1 2 1.67 3 OUT1 VCC VCC 4 RFG OUT2 OUT2 0.87 A1:SCL A2:SDA A3:OUT1 A4:RFG B1:CLK B2:GND B3:VCC B4:OUT2 No.A1527-3/15 LV8094CT Block Diagram VCC OUT1 OUT2 RFG Startup control block Piezoelectric drive waveform generation register Output control I2C interface GND CLK SCL SDA Value of the resistor connected to the RFG pin Inrush current flowing to the piezoelectric elements can be controlled in the LV8094CT by inserting a resistor between the RFG pin and GND potential. Since the resistance affects the actuator operation, the constant must be determined in a range from 0 to 3.3Ω while monitoring the operation of the actuator. Capacitor on the VCC line Piezoelectric actuators are capacitive loads in electrical terms, and they operate units by charging and discharging the charges. Since the charge between the capacitor on the VCC line and piezoelectric elements is transferred, the capacitor must be mounted near the VCC pin. The capacitance of the capacitor required is determined by the capacitance of the piezoelectric element. A capacitance within a range that does not affect operation must be selected. No.A1527-4/15 LV8094CT Serial Bus Communication Specifications I2C serial transfer timing conditions twH SCL th1 twL th2 tbuf SDA th1 ts2 ts1 ts3 Resend start condition Start condition ton Stop condition tof Input waveform condition Standard mode Parameter symbol Conditions min typ SCL clock frequency Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 4.7 ts2 Setup time of SDA with respect to the rising edge of SCL 250 ns ts3 Setup time of SCL with respect to the rising edge of SDA 4.0 μs μs Pulse width Input waveform conditions Bus free time 100 unit fscl Data hold time 0 max SCL clock frequency kHz μs th1 Hold time of SCL with respect to the rising edge of SDA 4.0 th2 Hold time of SDA with respect to the falling edge of SCL 0.06 μs twL SCL low period pulse width 4.7 μs twH SCL high period pulse width 4.0 ton SCL/SDA (input) rising time 1000 ns tof SCL/ SDA (input) falling time 300 ns tbuf Interval between stop condition and start condition μs μs 4.7 High-speed mode Parameter Symbol Conditions min typ Clock frequency of SCL Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 0.6 ts2 Setup time of SDA with respect to the rising edge of SCL 100 ns ts3 Setup time of SCL with respect to the rising edge of SDA 0.6 μs μs Pulse width Input waveform conditions Bus free time 400 unit fscl Data hold time 0 max SCL clock frequency kHz μs th1 Hold time of SCL with respect to the rising edge of SDA 0.6 th2 Hold time of SDA with respect to the falling edge of SCL 0.06 μs twL SCL low period pulse width 1.3 μs twH SCL high period pulse width 0.6 ton SCL/SDA (input) rise time 300 ns tof SCL/SDA (input) fall time 300 ns tbuf Interval between the stop condition and the start condition 1.3 μs μs No.A1527-5/15 LV8094CT I2C bus transfer method Start and stop conditions The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a data transfer operation. SCL SDA ts2 th2 When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is started when SDA is changed from high to low while SCL and SDA are high. Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is high. Start condition Stop condition th1 th3 SCL SDA No.A1527-6/15 LV8094CT Data transfer and acknowledgement response After the start condition is generated, data is transferred one byte (8 bits) at a time. Any number of data bytes can be transferred consecutively. An ACK signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. The transmission of an ACK signal is performed by setting the receiving side SDA to low after SDA at the sending side is released immediately after the clock pulse of SCL bit 8 in the data transferred has fallen low. After the receiving side has sent the ACK signal, if the next byte transfer operation is to receive only the byte, the receiving side releases SDA on the falling edge of the 9th clock of SCL. There are no CE signals in the I2C bus ; instead, a 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave address and to the command (R/W) which specifies the direction of subsequent data transfer. The READ function of the LV8094CT provides only the functionality to test the BUSY state. 7-bit address data is transferred sequentially starting at the MSB and the second and subsequent bytes are written if the state of the 8th bit is low and read if the state is high. In the LV8094CT, the slave address is stipulated to be “1110010.”. WRITE mode timing Start M S B Slave address L S B W A C K M S B Register address L S B A C K M S B L S B Data A C K Stop SCL SDA X X X X X X X 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 READ mode timing Start M S B Slave address L S B R A C K M S B L S B Data A C K Stop SCL SDA X X X X X X X 1 1 0 0 0 0 0 0 0 0 No.A1527-7/15 LV8094CT Data transfer write format The slave address and Write command must be allocated to the first byte and the register address in the serial map must be designated in the second byte. For the third byte, data transfer is carried out to the address designated by the register address which is written in the second byte. Subsequently, if data continues, the register address value is automatically incremented for the fourth and subsequent bytes. Thus, continuous data transfer starting at the designated address is made possible. After the register address reaches 07h, the transfer address for the next byte is set to 00h. Data write example S 1 1 1 0 0 1 0 0 A Slave address 0 0 0 0 0 0 1 0 A Data 1 Register address set to 02h A Write data to address 02h R/W = 0 written Data 2 A Write data to address 03h S Start condition Data 3 A Data 4 Write data to address 04h P Stop condition Master side transmission A A P Write data to address 05h A ACK signal A P Slave side transmission Data read example S 1 1 1 0 0 1 0 1 A Slave address Data Read data R/W = 1 read S Start condition Master side transmission P Notify end of read by not sending out ACK Stop condition A A ACK signal Slave side transmission No.A1527-8/15 LV8094CT Serial Map Register Address Data A7 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 0 0 0 M/I 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 D6 D5 D4 0 0 0 0 GATE × ENIN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 3 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 6 7 READ mode only register 8 0 0 0 CKSEL [1 : 0] D0 0 RET [1 : 0] 0 INIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GTAS [7 : 0] 0 0 0 0 GTBR [7 : 0] 0 0 0 0 0 0 0 0 1 5 D1 RST [7 : 0] 0 4 D2 DRVPULSE [6 : 0] 0 2 D3 0 GTBS [7 : 0] 0 STP [7 : 0] 0 0 0 0 × × × × 0 0 0 0 0 0 0 0 0 BUSY × × × × × × × 0 0 0 0 0 0 0 0 INITMOV [7 : 4] Upper : Register name Lower : Default value Serial Mode Settings 0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 D0 to D6: DRVPULSE [6 : 0] Operation count setting register. Specify a number from 0 to 127. The number of cyclic operations determined by <DRVPLUSE setting> × <STP setting> are performed. Additional data can be input and data is added up to the equivalent of total of 512 pulses. However, if the EN pin is set low or the ENIN register is set to 0, the DRVPULSE input is not accepted because the DRVPULSE counter is in the reset state. Since the output operation is carried out at the time the DRVPULSE input is recognized, the generation of the OUT signal is started at the time an ACK signal is generated after the execution of the instruction at address 00H according to the value of the waveform setup register established at that time. D7 M/I 0 ∞ 1 macro Operation direction switching *Default Infinity distance direction Macro direction Operation direction switching register The operation count setting register is reset when the register is switched. To stop the operation of the unit, switch the M/I register and set DRVPULSE to 0 for input. This register is also used to set the direction of operation when the initialization sequence is to be performed. No.A1527-9/15 LV8094CT 1 0 0 0 0 0 0 0 1 D7 0 D5 D4 D3 D2 D1 D0 D0: Register for selecting whether the initialization sequence is to be performed when EN is set high and ENIN is set to 1. D0 INIT Initialization to be performed/not to be performed setting 0 Initialization to be performed *Default 1 Initialization not to be performed D2 D1 0 0 2 times 0 1 1 time 1 0 3 times 1 1 4 times D4 D3 CKSEL 0 0 0 1 1/2 1 0 1 1 1 1 Number of initialization sequence swing back *Default RET Input clock division ratio switching *Default 1/4 1/2 1 (no frequency division) 1 (no frequency division) 1/4 D5 : ENIN ENIN register is used to start up IC and to give a trigger for initialization. Output operation of the IC is activated only when the EN pin is set high and EN pin is set to 1. A trigger for the initialization is also issued at the timing when the EN pin is set high and EN pin is set to 1. D7 2 0 GATE 0 MODE1 1 MODE2 0 0 Gate mode operation *Default Forward/reverse/braking Forward/reverse/standby 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 D2 D1 D0 RST7 to RST0 : Specifies the number of clocks per period (0 to 255). Default = 0 3 0 0 0 0 0 0 1 1 D7 D6 D5 D4 D3 GTAS7 to GTAS0 : Sets the GATE_A pulse set value (0 to 255). Default = 0 4 0 0 0 0 0 1 0 0 D7 D6 D5 D4 D3 GTBR7 to GTBR0 : Sets the GATE_B pulse reset value (0 to 255). Default = 0 No.A1527-10/15 LV8094CT 5 0 0 0 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 GTBS7 to GTBS0 : Sets the GATE_B pulse set value (0 to 255). Default = 0 RST7-0 GTAS7-0 GATEA GTBS7-0 GTBR7-0 GATEB 6 0 0 0 0 0 1 1 0 D7 D6 D5 D4 D3 STP7 to STP0 : Specifies the number of output pulse steps with regard to DRIVE input (1 to 256). Default = 1 The setting value range is handled as the data value plus 1. When data is input in 8-bit units (0 to 255), it is handled as an STP period of 1 to 256. 7 0 0 0 0 0 1 1 1 0 0 0 0 D3 D2 D1 D0 INITMOV7 to INITMOV4 : Sets the number of swing back of the initialization sequence to be performed (16 to 256). Default = 16 8 D3 D2 D1 D0 INIT7 to 4 16 to 256 0 0 0 0 0 16 0 0 0 1 1 32 0 0 1 0 2 48 0 0 1 1 3 64 0 1 0 0 4 80 0 1 0 1 5 96 0 1 1 0 6 112 0 1 1 1 7 128 1 0 0 0 8 144 1 0 0 1 9 160 1 0 1 0 10 176 1 0 1 1 11 192 1 1 0 0 12 208 1 1 0 1 13 224 1 1 1 0 14 240 1 1 1 1 15 256 No register address D7 0 0 0 0 0 0 0 READ only register line. D7 : BUSY register Set to 1 when the IC is performing the output operation. Set to 0 when the IC stops the output operation. No.A1527-11/15 LV8094CT Functional Description 1 period : One period of OUT waveform operation is equivalent to one output operation. Tf = 1 period Initialization sequence (on or off and direction can be set by I2C) : This is an internal sequence in which the actuator is moved to the initial position when the IC is started up. Switching the value of the ENIN register from 0 to 1 when the EN pin is set high starts the IC (conversely, the IC is also started by switching the state of the EN pin from low to high when the ENIN is set to 1). The presence or absence of the initialization operation can be set using the initialization mode select register (INIT). If the initialization operation is specified, the direction of the initialization sequence can be set using the M/I register. • M/I register = 0 : Initialization processing in infinity direction The IC performs the number of operations determined by STP setting period × INIT setting times in the infinite direction, then waits for the period equivalent to STP setting period × 4 times, and performs the number of swing back operations equal to STP setting period × RET setting times in the macro direction. • M/I register = 1 : Auto macro operation in macro direction The IC performs the number of operations determined by STP setting period × INIT setting times in the macro direction, then waits for the period equivalent to STP setting periods × 4, and performs the number of swing back operations equal to STP period setting period × RET setting times in the infinity direction. CLK input : The pin for the external CLK input that provides the reference time for generating drive waveforms. The frequency division ratio for I2C communication can be selected from 1/4, 1/2, and 1/1. Drive waveforms are generated by counting this frequency-divided clk pulses as the basic count unit. The LV8093CS supports frequency from 10MHz to 60MHz depending on the frequency division ratio and counter settings. Register setup sequence : (1) Apply VCC. (2) Set register addresses x01 to 0x07 (set the waveform and drive conditions). (3) Set the ENIN register to 1 (invoke initialization procedures if initialization is enabled or start up the IC). (4) Set up M/I and DRVPULSE to start the AF operation (actuator operation instruction). I2C communication during output operation : I2C communication with all the registers is possible even when the IC is in operation (OUT processing or BUSY is held high). No.A1527-12/15 LV8094CT Actuator drive waveform settings : Configuration of piezoelectric actuator drive waveform f = 1 period Ta off Tb Since the counter starts from zero, a value minus 1 is set. Drive parameter settings RST = Number of clock pulses in period minus 1 GTAS = Ta + 1 Ta - 1 + 2 = Ta + 1 since the waveforms start after two clock pulses. Rises here after two clock pulses from reference. GTBR = GTAS + off Waveform start reference point GTBS = GTBR + Tb The drive waveforms are set using four parameters: RST, GTAS, GTBR and GTBS. RST : Parameter determines the period, and sets the reference clock pulse count minus 1. GTAS : Parameter determines the time taken for the gate signal A to the falling edge from the reference point. Since the signal raises after two clock pulses from the reference, the Ta reference clock cycle count plus 1 is set. GTBR : Parameter determines the time taken for the gate signal B to the rising edge from the reference point. It sets the value obtained by adding the reference clock pulse count during the time from GTAS to “off.” GTBS : Parameter determines the time taken for the gate signal B to the falling ewdge from the reference point. It sets the value obtained by adding the reference clock pulse count during the time from GTBR to “Tb.” [Example of settings] When setting reference clock to 10MHz, period to 13μs, Ta to 2.0μs, off to 0.3μs, and Tb to 3.0μs Since the reference clock time is 0.1μs : The period is 130 clks. → Specify 129 (RST value of 130 -1). Ta is 20 clks. → Specify 21 (GTAS value of 20 + 1). off is 3 clks. → Specify 24 (GTBR value of 21 + 3). Tb is 30 clks. → Specify 54 (GTBS value of 24 + 30). No.A1527-13/15 LV8094CT Timing charts Enlarged view of the sequence of output signals (RST setting + 1) × number of clock pulses (GTAS setting - 1) × number of clock pulses Operation toward infinity (GTAS setting - 1) × number of clock pulses OUT1 (GTAS setting - 1) × number of clock pulses OUT2 (GTBR setting -1) × number of clock pulses (RST setting + 1) × number of clock pulses Operation toward macro (GTBR setting -1) × number of clock pulses OUT1 (GTBS setting - 1) × number of clock pulses OUT2 (GTAS setting - 1) × number of clock pulses (GTAS setting - 1) × number of clock pulses Sequence of initial setting operation (“on” or “off” can be set by the I2C settings.) When M/I register = 00 → Movement toward infinity position Startup when ENIN=1 , initial setting sequence starts ENIN resister 1 period OUT1 OUT2 Operation toward infinity STP period × INIT times Standby state STP period × 4 Operation toward macro STP period × RET setting times Initial setting operation time BUSY resister High during initial setting in wait state too BUSY output is high during initial setting operation. BUSY output is low after initial setting. When M/I register = 01 → Movement toward macro position Startup when ENIN=1 , initial setting sequence starts ENIN resister OUT1 1 period OUT2 Operation toward macro STP period × INIT times Standby state STP period × 4 Operation toward infinity STP period × RET setting times Initial setting operation time BUSY resister High during initial setting in wait state too BUSY output is high during initial setting operation. BUSY output is low after initial setting. No.A1527-14/15 LV8094CT Sequence of operations triggered by DRVPULSE input ENIN register Operation stops when ENIN input is low. Macro direction logic selection Infinity direction logic selection M/I register state Serial communication operation instruction completed 00000000_00000010 (operation 2 times toward infinity) DRVPULSE setting Equivalent to 2 pulses = STP setting period × operation for 2 times Serial communication operation instruction completed 00000000_10000010 (operation 2 times toward macro) 1 period OUT1 Operation toward infinity (STP setting period × 2 times) Operation toward macro OUT2 Serial communication Operation starts on completion of DRVPULSE input. Return to high when EN is set to low even before the completion of the operation. BUSY register BUSY output high, only during operation period Gate setting output logic 1 period GATE MODE1 : Forward, Braking, Reverse Forward Forward Output mode OUT1 Braking Braking OUT2 on OUT1 1 period Forward Forward OUT1 Wait Wait OUT2 off on OUT2 OUT1 off Reverse GATE MODE2 : Forward, Wait, Reverse off OUT2 on on off Forward Reverse off off off OUT1 off OUT2 OUT1 on on OUT2 off Braking off Wait Reverse SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2009. Specifications and information herein are subject to change without notice. PS No.A1527-15/15