Ordering number : ENA1938 LV76223A3F Monolithic Linear IC For PAL/NTSC/SECAM Color Television Sets VIF/SIF/Y/C/Deflection /CbCr IN Implemented in a Single Chip Overview The LV76223A3F is VIF/SIF/Y/C/D/Deflection /CbCr IN Implemented in a single chip for PAL/NTSC/SECAM color television sets. Functions • VIF / SIF / Y / C / Deflection / CbCr IN / Implemented in a Single Chip with CPU • I2C Bus Control Specifications BIP Chip Maximum Ratings at Ta=25°C Parameter Symbol Conditions Unit Allowable power dissipation Pd max 1.3 W Operating temperature Topr -10 to +65 °C Storage temperature Tstg Maximum supply voltage Maximum supply current Ta ≤65°C (*1) Ratings -55 to +150 °C V62 max 6.0 V V4 max 6.0 V I9 max 15 mA I20 max 20 mA I49 max 26.5 mA (*1) Provided with a glass epoxy board (230×150×1.6 mm) Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 33011 SY 20110228-S00005 No.A1938-1/47 LV76223A3F BIP Operating Conditions at Ta=25°C Parameter Recommended supply voltage Recommended supply current Operating supply voltage range Operating supply current range Symbol Conditions Ratings Unit V62 5.0 V4 5.0 V I9 11 mA I20 13 mA I49 22 mA V V62 4.7 to 5.3 V V4 4.7 to 5.3 V I9 9 to 13 mA I20 11 to 15 mA I49 20.5 to 26.5 mA (note) μ-Controller Chip:LC87F33C8A , F:FLASHROM=128Kbyte(Program_ROM:96Kbyte/character_ROM:32Kbyte) (This production is produced and sold by SANYO under license of the Silicon Storage Technology Inc.) Package Dimensions unit : mm (typ) 3300 33 1 32 0.2 13.8 64 15.24 57.2 (4.25) 0.51min 3.8 5.1max 0.95 1.78 (1.01) 0.5 SANYO : DIP64S(600mil) No.A1938-2/47 LV76223A3F μ-Controller Chip Absolute maximum ratings at Ta=25°C, VSS=0V Parameter Symbol Pins Conditions Limits VDD[V] max unit Maximum Supply voltage VDD max CpuVDD -0.3 to +6.0 V Input voltage VI XT1,RES# -0.3 to VDD+0.3 Output voltage VO1 XT2,FILT -0.3 to VDD+0.3 VO2 CpuVDD2 -0.3 to 3.3V+0.3 VIO Ports0,1 -0.3 to VDD+0.3 Peak output current Mean Output current IOPH Ports04 to 07,1 IOMH Ports04 to07,1 Total output current ΣIOAH Peak output current Mean output current Input/output voltage High level output current Low level output current Total output Current min typ CMOS output For each pin. CMOS output For each pin. -10 Ports04 to 07,1 The total of all pins. -25 IOPL Ports0,1 For each pin 20 IOML1 P02,P03,P06,P07 Ports1 For each pin 1 IOML2 P00,P01,P04,P05 For each pin 8 ΣIOAL1 P02,P03,P06,P07 Ports1 P00,P01,P04,P05 The total of all pins. 45 The total of all pins. 16 ΣIOAL2 mA -1 μ-Conttoller Chip Recommended operating range at Ta=-10°C to +65°C, VSS=0V Parameter Symbol Pins Conditions Limits VDD[V] max. unit Operating supply voltage range Hold voltage VDD CpuVDD 0.229µs≤tCYC≤200µs 4.5 5.5 V VHD CpuVDD RAMs and the registers data are kept in HOLD mode. 2.0 5.5 High level input Voltage VIH1 Ports0,1, P00 port input /interrupt Port00 Watch-dog timer RES# 4.5 to 5.5 0.3VDD +0.7 VDD 4.5 to 5.5 0.9VDD VDD 4.5 to 5.5 0.75VDD VDD Ports0,1, P00 port input /interrupt Port00 Watch-dog timer 4.5 to 5.5 VSS 0.1VDD +0.4 4.5 to 5.5 VSS 4.5 to 5.5 VSS 0.15VDD -0.4 0.25VDD VIH2 VIH3 Low level input Voltage VIL1 VIL2 VIL3 Operation cycle time (*3) Oscillation frequency range RES# tCYC1 All functions operating 4.5 to 5.5 tCYC2 OSD and Data slicer are not operating Built-in VCO1 Oscillation System clock Built-in VCO2 OCKSEL=0 oscillation OCKSEL=1 OSD clock 4.5 to 5.5 FmVCO1 FmVCO2 (*4) FmRC FsX’tal Oscillation stabilizing time tmsVCO XT1(P07), XT2(P06) min. typ. 0.231 0.231 µs 200 4.5 to 5.5 13.0 4.5 to 5.5 12.5 MHz 16.6 Built-in RC oscillation 4.5 to 5.5 At the 32.768KHz crystal Oscillating See the figure1 after the HOLD mode Power-On 4.5 to 5.5 0.3 4.5 to 5.5 1.0 2.0 32.768 KHz 300 ms (Note) FLASH-ROM erase/write temperature range :Ta=25±2°C(VDD=4.5 to 5.5V) (*3) Relational expression between Tcyc and oscillation frequency; 1/1 frequency dividing: 3/FmVCO1, 1/2 frequency dividing: 6/FVCO1. (*4) OCKSEL is the selectable register for OSD clock frequency. (See the LC873300 users manual for details.) No.A1938-3/47 LV76223A3F BIP Chip Electrical Characteristics at Ta=25°C, ICC=I9=11mA ICC=I20=13mA ICC=I49=22mA VCC=V62= V4=5.0V Parameter Symbol Conditions min typ max Unit [Circuit voltage, current] Horizontal supply voltage V20 I20=13mA 4.7 5.0 5.3 Logic supply voltage V9 I9=11mA 3.0 3.3 3.6 V RGB supply voltage V49 I49=22mA 7.8 8.15 8.5 V IF supply current I62 V62=5.0V 67 78 89 mA Video supply current I4 V4=5.0V 79 99 119 mA 4.3 4.7 5 Vdc 0 0.3 0.7 Vdc V [VIF block] Maximum RFAGC voltage VRFH CW=80 dBµ, DAC=0 Minimum RFAGC voltage VRFL CW=80 dBµ, DAC=63 RF AGC Delay Pt (@DAC=0) RFAGC0 DAC=0 90 − − dBµ RF AGC Delay Pt (@DAC=63) RFAGC63 DAC=63 − − 80 dBµ Input sensitivity Vi Output-3db − − 46 dBµ Sync signal tip level VOtip CW=80 dBµ 1.1 1.4 1.7 Vdc Video output amplitude VO 80dBu,AM=78%,fm=15kHz 1.90 2.00 2.10 Vp_p Video S/N S/N CW=80 dBµ 40 45 − dB dB C-S beat level IC-S V4.43MHz/V1.07MHz 35 − − Differential gain DG 80 dBµ, 87.5% Video MOD − 10 15 % Differential phase DP 80 dBµ, 87.5% Video MOD − 5.0 10.0 deg APC pull-in range(U) fPU 2.0 − − MHz APC pull-in range(L) fPL 2.0 − − MHz NTSC Trap1(4.5MHz) NTR1 − − -27 dB BG Trap1(5.5MHz) BTR1 − − -27 dB I Trap1(6.0MHz) ITR1 − − -27 dB DK Trap1(6.5MHz) DTR1 − − -27 dB [SIF block] FM detection output voltage SOADJ FM=±50kHz 450 630 850 mVrms FM limiting sensitivity SLS Output -3dB − − 60 dBµ -0.5 6.0 10.0 dB − − 3.0 % dB FM detection output f characteristics SF fm=100kHz FM detection output distortion STHD FM=±50kHz SSN DIN Audio 45.0 − − -3.0 0.0 +3.0 dB 0.8 1.0 1.2 Vrms kHz SIF S/N [AUDIO block] Volume gain AVGT 1kHz Maximum output voltage (Stereo mode) (Stereo mode) AVOT 1kHz THD=1% Frequency characteristic (Stereo mode) AFREQT − 20 30 Total harmonic distortion (Stereo mode) ATHDT DIN Audio − 0.05 0.25 % ANOT DIN Audio − -75 -70 dBV ACTT DIN Audio − -80 -70 dB AVGM 1kHz -3.0 0.0 +3.0 dB Maximum output voltage (Stereo mode) AVOM 1kHz THD=1% 0.8 1.0 1.2 Vrms Frequency characteristic (Mono mode) AFREQM − 20 30 kHz Total harmonic distortion (Mono mode) ATHDM DIN Audio − 0.05 0.20 % Output voltage noise ANOM DIN Audio − -75 -70 dBV AVOS 1kHz MODE-C, THD=1% 4 7 10 dB Total harmonic distortion (Surround mode) ATHDS DIN Audio − 0.2 0.5 % Output voltage noise (Surround mode) ANOS DIN Audio − -750 -700 dBV Bass band control range AGEQB 100Hz ±9 ±13 ±17 dB ±9 ±13 ±17 dB − -80 -70 dB -1.0 0 1.0 dB Output voltage noise Cross talk Volume gain (Stereo mode) (Stereo mode) (Mono mode) (Mono mode) Maximum output voltage (Surround mode) Treble band control range AGEQT 10kHz Mute AMUTE DIN Audio L/R Balance ABT 1kHz No.A1938-4/47 LV76223A3F Parameter Symbol Conditions min typ max Unit [Video block] Video overall gain (Contrast max) CONT127 11.0 13.5 16.0 dB Contrast adjustment Characteristics (Normal/max) CONT64 -7.0 -4.5 -2.0 dB Contrast adjustment characteristics (Min/max) CONT0 -17.0 -13.5 -10.0 dB -6.0 -3.0 0.0 dB Video frequency Characteristics 1 NTSC BW1 1.8MHz/100kHz , Y Filter.sys = 00 Video frequency characteristics 2 PAL BW2 2.2MHz/100kHz , Y Filter.sys = 01 -6.0 -3.0 0.0 dB Video frequency characteristics 3 WIDE BW3 2.3MHz/100kHz , Y Filter.sys = 10 -6.0 -3.0 0.0 dB Video frequency characteristics 4 APF BW4 3.4MHz/100kHz , Y Filter.sys = 00,Y APF=1 -6.0 -3.0 0.0 dB Chroma trap amount PAL CtrapP Y Filter.sys = 01 -26.0 -20.0 dB Chroma trap amount NTSC CtrapN Y Filter.sys = 00 -26.0 -20.0 dB DC restoration rate 1 ClampG1 DC.Rest=00 95.0 100.0 105.0 % DC restoration rate 2 ClampG2 DC.Rest=01 101.0 106.0 111.0 % DC restoration rate 3 ClampG3 DC.Rest=10 104.0 111.0 119.0 % DC restoration rate 4 ClampG4 DC.Rest=11 115.0 125.0 133.0 % Y-DL TIME1 TdY1 Y Filter.Sys=00 Y Delay Ajust=0100 680 ns Y-DL TIME2 TdY2 Y Filter.Sys=01 Y Delay Ajust=0100 660 ns Y-DL TIME3 TdY3 Y Filter.Sys=11,Delay Test=1 Y Delay Ajust=0100 800 ns Y-DL TIME4 TdY4 Y Filter.Sys=10 Y Delay Ajust=0100 450 ns Y-DL TIME Ajust1 TdYa1 Y Filter.Sys=00 Y Delay Ajust=0000 580 ns Y-DL TIME Ajust2 TdYa2 Y Filter.Sys=00 Y Delay Ajust=0111 700 ns Black stretch gain max BKSTmax Blk.Str.Gain=10 ,Blk.Str.Start=01 19.0 24.0 31.0 IRE Black stretch gain mid BKSTmid Blk.Str.Gain=01 ,Blk.Str.Start=01 12.0 17.0 24.0 IRE Black stretch gain min BKSTmin Blk.Str.Gain=00 ,Blk.Str.Start=01 5.0 10.0 16.0 IRE Black stretch start point max (60IRE ΔV) BKSTTHmax Blk.Str.Gain=01 ,Blk.Str.Start=10 -4.0 0.0 6.0 IRE Black stretch start point mid (50IRE ΔV) BKSTTHmid Blk.Str.Gain=01 ,Blk.Str.Start=01 -5.0 0.0 5.0 IRE Black stretch start point min (40IRE ΔV) BKSTTHmin Blk.Str.Gain=01 ,Blk.Str.Start=00 -5.0 0.0 5.0 IRE Sharp32T1 F=2.2MHz,Y Filter.Sys=00, Y Gamma Start=11,C_Kill.ON=1 2.0 5.0 8.0 dB F=2.2MHz,Y Filter.Sys=00, Y Gamma Start=11,C_Kill.ON=1 10.0 13.0 16.0 dB F=2.2MHz,Y Filter.Sys=00, Y Gamma Start=11,C_Kill.ON=1 -9.5 -6.5 -3.5 dB F=2.7MHz,Y Filter.Sys=01, Y Gamma Start=11,C_Kill.ON=1 2.0 5.0 8.0 dB F=2.7MHz,Y Filter.Sys=01, Y Gamma Start=11,C_Kill.ON=1 10.0 13.0 16.0 dB F=2.7MHz,Y Filter.Sys=01, Y Gamma Start=11,C_Kill.ON=1 -10.5 -7.5 -4.5 dB F=2.3MHz,Y Filter.Sys=11, Y Gamma Start=11,C_Kill.ON=1 2.0 5.0 8.0 dB F=2.3MHz,Y Filter.Sys=11, Y Gamma Start=11,C_Kill.ON=1 10.5 13.5 16.5 dB F=2.3MHz,Y Filter.Sys=11, Y Gamma Start=11,C_Kill.ON=1 -9.5 -6.5 -3.5 dB F=3.0MHz,Y Filter.Sys=10, Y Gamma Start=11,C_Kill.ON=1 2.0 5.0 8.0 dB F=3.0MHz,Y Filter.Sys=10, Y Gamma Start=11,C_Kill.ON=1 11.0 14.0 17.0 dB F=3.0MHz,Y Filter.Sys=10, Y Gamma Start=11,C_Kill.ON=1 -13.0 -8.0 -5.0 dB Sharpness variability range NTSC (trap 1 mid) Sharp63T1 (trap 1 max) (trap 1 min) Sharp0T1 Sharpness variability range PAL Sharp32T2 (trap 2 mid) Sharp63T2 (trap 2 max) (trap 2 min) Sharp0T2 Sharpness variability range PAL Sharp32T3 (trap 3 mid) Sharp63T3 (trap 3 max) (trap 3 min) Sharp0T3 Sharp32T4 Sharpness variability range 6MHz TRAP (trap 4 mid) Sharp63T4 (trap 4 max) (trap 4 min) Sharp0T4 No.A1938-5/47 LV76223A3F Parameter Symbol Conditions min typ max Unit White peak limiter effective point1 WPL1 APL=100% WPL=00 135 150 165 IRE White peak limiter effective point2 WPL2 APL=100% WPL=01 105 120 135 IRE 95 110 IRE 75 90 White peak limiter effective point3 WPL3 APL=100% WPL=10 80 White peak limiter effective point4 WPL4 APL=100% WPL=11 60 Y gamma Start effective point 1 YGST1 Y Gamma Start=00, Y Gamma GAIN=01 55 IRE Y gamma Start effective point 2 YGST2 Y Gamma Start=01, Y Gamma GAIN=01 65 IRE Y gamma Start effective point 3 YGST3 Y Gamma Start=10, Y Gamma GAIN=01 68 IRE Y gamma gain 1 YGGA1 Y Gamma Start=01, Y Gamma GAIN=00 220 IRE Y gamma gain 2 YGGA2 Y Gamma Start=01, Y Gamma GAIN=01 250 IRE Y gamma gain 3 YGGA3 Y Gamma Start=01, Y Gamma GAIN=10 260 IRE Gray Mode Level GRAY GLAY MODE=1, Cross B/W=10 Horizontal/vertical blanking output level RGBBLK Pre-shoot adjust1 PreShoot1 Pre-shoot adjust2 Over-shoot adjust IRE 12.5 16.0 19.5 − 0.3 0.5 IRE V Pre-shoot adj.=00 0.92 0.97 1.02 ratio PreShoot2 Pre-shoot adj.=11 1.08 1.13 1.18 ratio OverShoot Over-shoot adj.=11 1.08 1.13 1.18 ratio V [RGB output(cutoff drive)block] Brightness control (Normal) BRT64 1.9 2.3 2.7 Brightness control (Normal-H) BRT64H 3.5 3.9 4.3 V BRT127 20.0 27.5 35.0 IRE IRE Hi brightness (max) Low brightness (min) Cutoff control (Bias control) -35.0 -27.5 -20.0 Vbias0 1.7 2.3 2.9 Vbias255 2.7 3.3 3.9 Vbiassns − 3.5 − mV/Bit mV/Bit BRT0 (min) (max) Resolution Sub-bias control Resolution Vsbiassns RGB Drive adjustment Maximum output RGBout127 RGB Output attenuation RGBout0 V V − 7 − 1.9 2.3 2.7 Vpp 6 10 13 dB [Ext.RGB input block] ExFSTH 2.0 2.5 3.0 V Ext.Red output level Ext.RH 120 170 220 IRE Ext.Green output level Ext.GH 120 170 220 IRE Ext.Blue output level Ext.BH 120 170 220 IRE Ext.R 0.8 1.0 1.2 ratio 40 50 60 % 0.8 1.0 1.2 ratio Ext.RGB input Fast SW threshold Analog Ext.R output level gain match Linearity Ext.LR Analog Ext.G output level gain match Ext.G Linearity Ext.LG Analog Ext.B output level gain match Ext.B Linearity Ext.LB 40 50 60 % 0.8 1.0 1.2 ratio 45 50 60 % 1.9 2.2 2.5 [Video SW block] Video signal input 1DC voltage VIN1DC Video SW.=00 Video signal input 1AC voltage VIN1AC Video SW.=00 Video signal input 2DC voltage VIN2DC Video SW.=01 Video signal input 2AC voltage VIN2AC Video SW.=01 Video signal input 3DC voltage VIN3DC Video SW.=10 Video signal input 3AC voltage VIN3AC Video SW.=10 Video signal input 4DC voltage VIN4DC Video SW.=11 Video signal input 4AC voltage VIN4AC SVO pin DC voltage SVODC SVO pin AC voltage SVOAC SVO pin Ycmix AC Voltage SVOYC 1 1.9 YCMIX=0 Video SW.=01,SVO SW=1 YCMIX=0 Video SW.=01,SVO SW=1 YCMIX=1 2.5 1 1.9 2.2 1.9 2.2 V Vp-p 2.5 1 Video SW.=11 Video SW.=01,SVO SW=1 2.2 V Vp-p V Vp-p 2.5 1 V Vp-p 1.6 1.9 2.2 V 1.7 2 2.3 Vp-p 0.20 0.28 0.36 Vp-p No.A1938-6/47 LV76223A3F Parameter Symbol Conditions min typ max Unit [Chroma block]: PAL/NTSC common B-Y/Y amplitude ratio CLRBY 75 100 150 Color control characteristics 1 CLRMN Color MAX/CEN 4 6 8 ratio Color control characteristics 2 CLRMM Color MAX/MIN 30 45 65 dB 2 4 1 % Color control sensitivity CLRSE fsc output level FSC40 Residual higher harmonic level B E_CAR_B 300 mVp-p Residual higher harmonic level R E_CAR_R 300 mVp-p Residual higher harmonic level G E_CAR_G 300 mVp-p a reference value 350 %/bit mVp-p [Chroma block]: PAL ACC amplitude characteristics 1 ACCM1_P Input:+6dB/0dB 0dB=40IRE 0.7 1.0 1.2 ratio ACC amplitude characteristics 2 ACCM2_P Input:-20dB/0dB 0.7 1.0 1.1 ratio 0.50 0.56 0.67 ratio -0.24 -0.19 -0.17 ratio -0.56 -0.51 -0.46 ratio 85 90 Demodulation output ratio R-Y/B-Y:PAL RB_P Demodulation output ratio G-Y/B-Y :PAL GB_P Demodulation output ratio G-Y/R-Y :PAL GR_P Demodulation angle R-Y/B-Y :PAL ANGRB_P Killer operating point 0 (PAL) KILLP0 Killer operating point 3 (PAL) KILLP3 Difference between two Killer operating points DKILLP (PAL) APC pull-in range (+) PULIN+_P APC pull-in range (-) PULIN-_P R-Y/B-Y_GainBalance, R-Y/B-Y_Angle:Center R-Y/B-Y_GainBalance R-Y/B-Y_Angle:Center, R-Y= no-signal R-Y/B-Y_GainBalance R-Y/B-Y_Angle:Center, B-Y= no-signal R-Y/B-Y_GainBalance R-Y/B-Y_Angle:Center 95 °C 0dB=40IRE -44 -31 dB 0dB=40IRE -46 -33 dB KILLP0-KILLP3 0.5 6.0 dB 350 Hz -350 Hz 1.2 ratio [Chroma block]:NTSC ACC amplitude characteristics 1 ACCM1_N Input:+6dB/0dB 0dB=40IRE ACC amplitude characteristics 2 ACCM2_N Input:-20dB/0dB Demodulation output ratio R-Y/B-Y: NTSC Demodulation output ratio G-Y/B-Y: NTSC Demodulation angle B-Y/R-Y : NTSC Demodulation angle G-Y/B-Y : NTSC RB_N GB_N ANGBR_N ANGGB_N R-Y/B-Y_GainBalance R-Y/B-Y_Angle:Center R-Y/B-Y_GainBalance R-Y/B-Y_Angle:Center R-Y/B-Y_GainBalance R-Y/B-Y_Angle:Center R-Y/B-Y_GainBalance R-Y/B-Y_Angle:Center 0.7 1.0 0.7 1.0 1.1 ratio 0.80 0.90 1.00 ratio 0.22 0.27 0.38 ratio 95 105 111 °C 230 240 250 °C Killer operating point 0 (NTSC) KILLN0 0dB=40IRE -44 -33 dB Killer operating point 3 (NTSC) KILLN3 0dB=40IRE -46 -34 dB KILLN0-KILLN3 0.5 6.0 dB Difference between two Killer operating points DKILLN (NTSC) APC pull-in range (+) PULIN+_N APC pull-in range (-) PULIN-_N Tint center TINCEN Tint variable range (+) TINT+ Tint variable range (-) TINT- Cr Output amplitude CBCR-R CbCr_IN=1 ,Cross B/W=01 Cb Output amplitude CBCR-B CbCr_IN=1 ,Cross B/W=01 Hz 350 -10 0 -350 Hz 10 deg deg 35 -35 deg 2.1 4.3 Vp-p 1.8 3.7 Vp-p [Chroma block]:SECAM B-Y output amplitude MVBY 1.90 2.75 3.60 Vp-p R-Y output amplitude MVRY 1.30 2.15 3.00 Vp-p B-Y/R-Y output ratio MRATRB 1.05 1.28 1.45 ratio B-Y linearity MLINBY 75 100 130 % R-Y linearity MLINRY 75 100 130 % SECAM killer operating point MKILL -45 -35 -25 dB White balance B-Y MWBBY -350 0 350 mV White balance R-Y MWBRY -350 0 350 mV De-emphasis frequency response B-Y MFDEBY -8.3 -5.3 -2.3 dB De-emphasis frequency response R-Y MFDERY -6.5 -3.5 -0.5 dB No.A1938-7/47 LV76223A3F Parameter Symbol Conditions min typ max Unit [Filter block]: Chroma BPF Characteristic C-BPF1A (3.93MHz) CBPF1A C-BPF1B (4.73/4.13MHz) CBPF1B C-BPF1C (4.93/3.93MHz) CBPF1C C-BPF2A (3.93MHz) CBPF2A C-BPF2B (4.73/4.13MHz) CBPF2B C-BPF2C (4.93/3.93MHz) CBPF2C Reference: 4.43MHz C.Filter.Sys:10 Reference: 4.13MHz C.Filter.Sys:10 Reference: 3.93MHz C.Filter.Sys:10 Reference: 4.43MHz C.Filter.Sys:11 Reference: 4.13MHz C.Filter.Sys:11 Reference: 3.93MHz C.Filter.Sys:11 -6.0 -3.0 -1.0 dB -2.5 1.5 5.5 dB -3.5 2.0 7.5 dB -6.0 -3.0 -1.0 dB -4.0 0.0 4.0 dB -5.5 0.0 5.5 dB 15470 15670 15870 Hz [Deflection block] Horizontal free-running frequency FH Horizontal pull-in range FH PULL Horizontal output pulse width H duty 36.1 37.6 39.1 µs Horizontal output pulse saturation voltage V Hsat 0 0.2 0.4 V Vertical free-running cycle 50 VFR50 312.0 312.5 313.0 H Vertical free-running cycle 60 VFR60 262.0 262.5 263.0 H Horizontal output pulse phase HPHCENpal 3.8 5.8 7.8 µs Horizontal output pulse phase HPHCENnt 3.8 5.8 7.8 µs Horizontal position adjustment range HPH range Horizontal position adjustment maximum variability width HPH step Horizontal blanking left @0 BLKL0 ±400 Hz ±1.8 5bit µs 180.0 ns H.BLK.L:000 8000 9000 10000 ns Horizontal blanking left @7 BLKL7 H.BLK.L:111 11500 12500 13500 ns Horizontal blanking right @0 BLKR0 H.BLK.R:000 -1600 -600 400 ns Horizontal blanking right @7 BLKR7 H.BLK.R:111 1800 2800 3800 ns Sand castle pulse crest value H SANDH 5.3 5.6 5.9 V Sand castle pulse crest value M1 SANDM1 3.7 4.0 4.3 V Sand castle pulse crest value L SANDL 0.0 0.4 5.0 V Burst gate pulse width BGPWD 3 4 5 µs Burst gate pulse phase BGPPH 4.7 5.2 5.9 µs Horizontal output stop voltage H stop 3.30 3.60 3.90 V Horizontal phase bow correction @16 HBOW16 -0.5 0 0.5 µs Horizontal phase bow correction @0 HBOW0 0.7 1.2 1.7 µs Horizontal phase bow correction @31 HBOW31 -1.5 -1.0 -0.5 µs Horizontal phase angle correction @16 HANG16 -0.5 0 0.5 µs Horizontal phase angle correction @0 HANG0 0.4 0.9 1.4 µs Horizontal phase angle correction @31 HANG31 -1.3 -0.8 -0.3 µs 0.75 1.05 1.35 Vp-p <Vertical screen size adjustment> Vertical ramp output amplitude PAL @64 Vspal64 V.SIZE:1000000 Vertical ramp output amplitude NTSC @64 Vsnt64 V.SIZE:1000000 0.75 1.05 1.35 Vp-p Vertical ramp output amplitude PAL @0 Vspal0 V.SIZE:0000000 0.30 0.60 0.9 Vp-p Vertical ramp output amplitude NTSC @0 Vsnt0 V.SIZE:0000000 0.30 0.60 0.9 Vp-p Vertical ramp output amplitude PAL @127 Vspal127 V.SIZE:1111111 1.25 1.55 1.85 Vp-p Vertical ramp output amplitude NTSC @127 Vsnt127 V.SIZE:1111111 1.25 1.55 1.85 Vp-p Vertical ramp DC voltage @32 Vdc32 V.DC:10000 2.10 2.40 2.70 Vdc Vertical ramp DC voltage @0 Vdc0 V.DC:00000 1.80 2.10 2.40 Vdc Vertical ramp DC voltage @63 Vdc63 V.DC:11111 2.55 2.85 3.15 Vdc Vertical position @8 Vshift8 V.SHIFT:1000 500 550 600 µs Vertical position @0 Vshift0 V.SHIFT:0000 0 50 100 µs Vertical position @15 Vshift15 V.SHIFT:1111 950 1000 1050 µs Vpsizecomp V.COMP:000 0.89 0.93 0.97 ratio <Vertical screen position adjustment> <High-voltage dependent vertical size correction> Vertical size Correction @0 No.A1938-8/47 LV76223A3F Parameter Symbol Conditions min typ max Unit <Vertical screen linearity adjustment> Vertical linearity @16 Vlin16 V.LIN:10000 0.7 1.00 1.30 ratio Vertical linearity @0 Vlin0 V.LIN:00000 1.30 1.60 1.90 ratio ratio Vertical linearity @31 Vlin31 V.LIN:11111 0.35 0.65 0.95 Vertical S-shaped correction @16 Vscor16 V.SC:10000 0.70 1.00 1.30 ratio Vertical S-shaped correction @0 Vscor0 V.SC:00000 1.10 1.40 1.70 ratio Vertical S-shaped correction @31 Vscor31 V.SC:11111 0.30 0.60 0.90 ratio H size comp H.COMP:000 0.18 0.28 0.38 V 2.80 Vdc <High-voltage dependent horizontal size correction> Horizontal size correction @0 <Horizontal screen size adjustment> East/West DC Voltage@64 EWdc64 EWDC:1000000 1.80 2.30 East/West DC Voltage@0 Ewdc0 EWDC:0000000 0.80 1.30 1.80 Vdc East/West DC Voltage@127 Ewdc127 EWDC:1111111 2.80 3.30 3.80 Vdc 1.60 2.10 2.60 Vp-p -0.5 0.00 0.50 Vp-p 2.10 2.60 3.10 Vp-p -0.20 0.30 0.80 V -1.10 -0.60 -0.10 V 0.80 1.30 1.80 V 0.35 0.90 1.45 V 0.80 1.35 1.90 V <Pincushion correction> East/West amplitude@64 EWamp64 East/West amplitude@0 EWamp0 East/West amplitude@127 EWamp127 EWDC:1111111 EWAMP:1000000 EWDC:1111111 EWAMP:0000000 EWDC:1111111 EWAMP:1111111 <Trapezoidal distortion compensation> East/West tilt@64 Ewtilt64 East/West tilt@0 EWtilt0 East/West tilt@127 Ewtilt127 EWDC:1111111,EWCORSW:1 EWTILT:1000000 EWDC:1111111,EWCORSW:1 EWTILT:0000000 EWDC:1111111,EWCORSW:1 EWTILT:1111111 <Corner distortion compensation> East/West corner top EWcorTOP East/West corner bottom EWcorBOT EWDC:1111111,EWCORSW:1 EWCORTOP:00000-11111 EWDC:1111111,EWCORSW:1 EWCORBOTTOM: 00000-11111 No.A1938-9/47 LV76223A3F Test Conditions at Ta=25°C, ICC=I9=10mA, ICC=I20=11mA, ICC=I49=22mA, VCC=V62= V4=5.0V Parameter Symbol Test point Input signal Test method Bus conditions [Circuit voltage,current] Horizontal supply voltage (pin 20) V20 Logic supply voltage (pin 9) V9 RGB supply voltage(pin 49) I49 IF supply current(pin 62) I62 Video / vertical supply current (pin 4) I4 20 9 49 62 4 No signal Apply a current of 13mA to pin 20 and measure the voltage at pin 20. No signal Apply a current of 11mA to pin 9 and measure Initial the voltage at pin 9. No signal Apply a current of 22mA to pin 49 and measure the voltage (V) at pin49. No signal Apply a voltage of 5.0V to pin 62 and measure Initial the incoming DC current (mA). (IF AGC 2.5V applied) Apply a voltage of 5.0V to pin 4 and measure Initial the incoming DC current (mA). No signal Initial Initial • VIF Block Input Signals and Test Conditions 1. Input signals must be input to the PIF IN (pin 56) in the Test Circuit. 2. Input signal voltage values are the levels at the VIF IN (pin 56) in the Test Circuit. 3. Signal contents and signal levels 4. Bus control condition: VIF SYS:”001”, S.TRAP.SW:"1", OVER.MOD.SW:"0", SVO.SW:”0” Input signal Waveform Conditions SG1 38.9MHz CW SG2 34.47MHz CW SG3 33.4MHz CW SG4 Frequency variable CW SG5 38.9MHz 87.5% Video Mod. 10-stairstep wave (Subcarrier: 4.43MHz) SG6 38.9MHz fm=15kHz,AM=78% SG7 38.9MHz, 90dBu 87.5% Video Mod. 50IRE Luma (Carrier: variable) 50IRE 50IRE Luma No.A1938-10/47 LV76223A3F Parameter Symbol Test point Input signal Test method Bus conditions [VIF block ] Maximum RF AGC voltage VRFH Minimum RF AGC voltage VRFL RF AGC Delay Pt (@DAC=0) RFAGC0 RF AGC Delay Pt (@DAC=63) RFAGC63 Input sensitivity Vi Sync tip level VOtip Video output amplitude VO Video S/N S/N C-S beat level IC-S Differential gain DG Differential phase DP APC pull-in range (U),(L) fPU, fPL NT Trap1 (4.5MHz) NTR1 BG Trap 1 (5.5MHz) BTR1 I Trap1 (6.0MHz) ITR1 DK Trap1 (6.5MHz) DTR1 58 SG1 80dBμ Measure the DC voltage at pin 58. RF.AGC=”000000” 58 SG1 80dBμ Measure the DC voltage at pin 58. RF.AGC=”111111” SG1 Obtain the input level at which the DC voltage at pin 58 becomes 2.5V. RF.AGC=”000000” SG1 Obtain the input level at which the DC voltage at pin 58 becomes 2.5V. RF.AGC=”111111” SG6 Using an oscilloscope, observe the level at pin 61 and obtain the input level at which the waveform's amplitude becomes 1.4Vp-p. 61 SG1 80dBμ Measure the DC voltage at pin 61. 61 SG6 80dBμ Using an oscilloscope, observe the level at pin 61 and measure the waveform’s p-p value. 61 SG1 80dBμ 61 SG1 SG2 SG3 61 SG5 80dBμ Measure the noise voltage (Vsn) at pin 61 with an RMS voltmeter through a 10kHz to 5.0MHz band-pass filter and calculate 20log(1.43/Vsn). Input a 80dBμ SG1 signal and measure the DC voltage (V60) at pin 60. Mix SG1=74dBμ, SG2=64dBμ, and SG3=64dBμ to enter the mixture in the VIF IN. Apply V60 to pin 60 from an external DC power supply. Using a spectrum analyzer, measure the difference between pin 61’s 4.43MHz component and 1.07MHz component. Using a vector scope, measure the level at Pin 61. 61 SG5 80dBμ Using a vector scope, measure the level at Pin 61. 61 SG4 80dBμ Connect an oscilloscope to pin 61 and adjust the SG4 frequency to a frequency higher than 38.9MHz to bring the PLL into unlocked mode. (A beat signal appears.) Lower the SG4 frequency and measure the frequency at which the PLL locks again. In the same manner, adjust the SG4 frequency to a lower frequency to bring the PLL into unlocked mode. Higher the SG4 frequency and measure the frequency at which the PLL locks again. Determine the output level difference between carrier frequencies SIF.SYS=”00” of 1MHz and 4.5MHz.(Reference:1MHz) 58 58 61 61 61 61 61 SG7 SG7 Determine the output level difference between carrier frequencies of 1MHz and 5.5MHz.(Reference:1MHz) SIF.SYS=”01” SG7 Determine the output level difference between carrier frequencies of 1MHz and 6.0MHz.(Reference:1MHz) SIF.SYS=”10” SG7 Determine the output level difference between carrier frequencies of 1MHz and 6.5MHz.(Reference:1MHz) SIF.SYS=”11” •SIF Block (FM block) Input Signals and Test Conditions Unless otherwise specified, the following conditions apply when each measurement is made. 1. Bus control condition: IF.AGC.SW=“1”, SIF.SYS=”01”,DEEM-TC=”0”,FM.GAIN=”0” 2. SW: IF1=“ON”, pin 19=5V 3. Input signals are input to pin 52 and the carrier frequency is 5.5MHz. Parameter Symbol FM detection output voltage SOADJ FM limiting sensitivity SLS FM detection output f characteristics (fm=100kHz) FM detection output distortion SF SIF.S/N SSN STHD Test point 64 64 64 64 64 Input signal Test method 90dBμ, fm=400Hz, FM=±50kHz fm=400Hz, FM=±50kHz Measure the 400 Hz component (SV1:mVrms) of the FM detection output at pin 64. 90dBμ, fm=100kHz FM=±50kHz 90dBμ, fm=400Hz, FM=±50kHz 90dBμ, CW Set SW: IF1="OFF". Measure (SV2: mVrms) the FM detection output of pin 64. Calculate as follows: SF=20log(SV1/SV2) [dB] Measure the distortion factor of the 400Hz component of the FM detection output at pin 64. Bus conditions Measure the input level (dBμ) at which the 400Hz component of the FM detection output at pin 64 becomes -3dB relative to SV1. Measure the noise level (DIN AUDIO, SV4:mVrms) at pin 64. Calculate as follows: SSN=20log(SV1/SV4) [dB] No.A1938-11/47 LV76223A3F •Audio Block Input Signals and Test Conditions Unless otherwise specified, the following conditions apply when each measurement is made. 1. Bus control condition: Audio Mute :"0", A.MONI.SW:"1", FM MUTE:"1", Audio SW :"00", Surr cont: "0", VOL FIL: "0", Tone VOL FIL: "1", IF.AGC:"1", MONO Mode:"0", Volume (L/MONO):"0000000", Volume(R): "0000000", Tone ATT: "0", T Boost/Cut: "0", Treble gain: "1111111", B Boost/Cut: "0", Bass Gain:"1111111" 2. Enter an input signal EXT-LIN from pin 2. 3. Enter an input signal EXT-RIN from pin 1. 4. Output signal LOUT is output to pin 50. 5. Output signal ROUT is output to pin 51. Parameter Symbol Test point Input signal Test method Bus conditions [AUDIO block] Volume gain (Stereo mode) Maximum output voltage (Stereo mode) Frequency characteristic (Stereo mode) Total harmonic distortion (Stereo mode) Output voltage noise (Stereo mode) Cross talk (Stereo mode) Volume gain (Mono mode) Maximum output voltage (Mono mode) Frequency characteristic (Mono mode) Total harmonic distortion (Mono mode) Output voltage noise (Mono mode) Maximum output voltage (Surround mode) Total harmonic distortion (Surround mode) Output voltage noise (Surround mode) Bass band control range Treble band control range EXT-LIN(2PIN) =1kHz,300mVrms Measure the 1kHz component (V1:mVrms) at the LOUT(50PIN) and calculate as follows: AVGT=20log(V1/300) [dB] 2 EXT-LIN(2PIN) =1kHz When the distortion (DIN.AUDIO) of the LOUT(pin50) is 1%, Measure the voltage level at the EXT-LIN (pin 2). 2 EXT-LIN(2PIN) =300mVrms ATHDT 50 EXT-LIN(2PIN) =1kHz,300mVrms Measure the voltage level (V2:mVrms) at the LOUT(pin50) and calculate as follows: AFT=20log(V2/300) [dB] When the AFT is –3dB, Measure the frequency at the EXT-LIN (pin 2). Measure the distortion (DIN.AUDIO) of the 1kHz component at the LOUT (50PIN). ANOT 50 No signal Measure the noise level (DIN AUDIO) at the LOUT (pin50). ACTT 51 EXT-LIN(2PIN) =1kHz,300mVrms Measure the 1kHz component (V3:mVrms) at the ROUT (pin51) AVGM 50 EXT-LIN(2PIN) =1kHz,300mVrms Measure the 1kHz component (V4:mVrms) at the LOUT (pin50) Audio SW=10 Mono Mode=1 and calculate as follows: AVGM=20log(V4/300) [dB] AVOM 2 EXT-LIN(2PIN) =1kHz When the distortion (DIN.AUDIO) of the LOUT(pin50) is 1%, AFREQM 2 EXT-LIN(2PIN) =300mVrms Audio SW=10 Mono Mode=1 EXT-LIN(2PIN) =1kHz,300mVrms Measure the voltage level (V5:mVrms) at the LOUT (pin50) and calculate as follows: AFM=20log(V5/300) [dB] When the AFM is –3dB, Measure the frequency at the EXT-LIN (PIN 2). Measure the distortion (DIN.AUDIO) of the 1kHz component at the LOUT (pin50). No signal Measure the noise level (DIN AUDIO) at the LOUT (50PIN). Mono Mode=1 EXT-LIN(2PIN) =1kHz (phase 180 deg) EXT-LIN(2PIN) EXT-RIN(PIN1) =1kHz (phase 180 deg) 300mVrms No signal When the distortion (DIN.AUDIO) of the LOUT (PIN 50) is 1%. Surr cint:11 (MODE-C) Measure the voltage level at the LIN (PIN 2). EXT-LIN(2PIN) =100Hz, 100mVrms EXT-LIN(2PIN) =10kHz, 100mVrms EXT1-LIN(2PIN) EXT2-LIN(8PIN) =1kHz,300mVrms EXT1-LIN(2PIN) EXT1-RIN(1PIN) EXT2-LIN(8PIN) EXT2-RIN(7PIN) =1KHz,300mVrms Measure the 100Hz component (V6:mVrms) at the LOUT(PIN 50) and calculate as follows: AGEQB=20log(V6/300)[dB] AVGT 50 AVOT AFREQT ATHDM 50 ANOM 50 AVOS 2 50 ATHDS ANOS 50 AGEQB 50 AGEQT 50 AMUTE 50 Mute L/R Balance 51 ABT and calculate as follows: ACTT=20log(V3/300) [dB] Measure the voltage level at the EXT-LIN (PIN 2). Audio SW=10 Mono Mode=1 Audio SW=10 Mono Mode=1 Measure the distortion (DIN.AUDIO) of the 1kHz component at Surr cint:11 (MODE-C) the LOUT (pin50). Measure the noise (DIN.AUDIO) at the LOUT (pin50). Surr cint:11 (MODE-C) B Boost/Cut:1,0 Bass Gain :000000(12dB) Measure the 10kHz component (V7:mVrms) at the LOUT(PIN T Boost/Cut:1,0 50) and calculate as follows: AGEQT=20log(V7/300)[dB] Treble Gain :000000(12dB) Measure the 1kHz component (V8:mVrms) at the LOUT (PIN50) Audio.mute =1 and calculate as follows: AMUTE =20log(V8/300) [dB] Measure the 1KHz component(V9:mVrms) at the ROUT (PIN51) and calculate as follows: ABT=20Log(V1/V9) [dB] No.A1938-12/47 LV76223A3F • Video Block Input Signals and Test Conditions 1. C IN Input*chroma burst signal: 40 IRE 2. Y IN input signal 3. Bus control bit conditions: Initial test state 100IRE:714mV ·l0IRE signal (L-0): NTSC standard sync signal PEDESTAL LEVEL H SYNC 4.7μs (H/V SYNC: 40IRE: 286mV) · XIRE signal (L-X) XIRE (X= 0 to 100) 0 IRE · CW signal (L-CW) 20 IRE CW signal 50 IRE · BLACK STRETCH A point (0IRE to 99IRE) signal (L-BK) 60μs 100IRE …100IRE white signal as other H … 5 μs Point A · R/G/B IN Input signal · RGB Input signal 1 (0-1) to each 20μs 0.7V 0.35V 0.0VDC A B · RGB Input signal 2 (0-2) 20μs 30μs 5.0V 0.0VDC No.A1938-13/47 LV76223A3F Parameter Symbol Test point Input Test method signal Bus conditions [Video block] Video overall gain CONT127 46 L-50 Measure the output signal’s 50IRE amplitude (CNTHB Vp-p) CONTRAST:1111111 and calculate CONT127= 20log (CNTHB/0.357). Y Gamma Start=11 CONT64 46 L-50 Measure the output signal’s 50IRE amplitude (CNTCB Vp-p) CONTRAST:1000000 46 L-50 (Contrast max) Contrast adjustment characteristics and calculate CONT63= 20log (CNTCB/CNTHB). Y Gamma Start=11 (normal/max) Contrast adjustment CONT0 characteristics (min/max) Video frequency Measure the output signal’s 50IRE amplitude (CNTLB Vp-p) CONTRAST:0000000 and calculate CONT0=20log (CNTLB/CNTHB). BW1 Characteristics 1 46 L-CW Y Gamma Start=11 With the input signal’s continuous wave=100kHz, measure the Y Filter.sys:00 output signal’s continuous wave amplitude (PEAKDC Vp-p). SHARPNESS: 000000 (NTSC) With the input signal’s continuous wave=1.8MHz, measure the Y Gamma Start=11 output signal’s continuous wave amplitude (CW1.8 Vp-p). Calculate BW1=20Log (CW1.8/PEAKDC). Video frequency BW2 Characteristics 2 46 L-CW (PAL) Video frequency BW3 Characteristics 3 46 L-CW (6MHz TRAP) Video frequency BW4 Characteristics 4 46 L-CW (APF) With the input signal’s continuous wave=2.2MHz, measure the Y Filter.sys:01 output signal’s continuous wave amplitude (CW2.2 Vp-p). SHARPNESS: 000000 Calculate BW2=20Log (CW2.2/PEAKDC). Y Gamma Start=11 With the input signal’s continuous wave=2.3MHz, measure the Y Filter.sys:10 output signal’s continuous wave amplitude (CW2.3 Vp-p). SHARPNESS: 000000 Calculate BW3=20Log (CW2.3/PEAKDC). Y Gamma Start=11 With the input signal’s continuous wave=3.4MHz, measure the Y Filter.sys:00 output signal’s continuous wave amplitude (CW3.4 Vp-p). SHARPNESS: 000000 Calculate BW3=20Log (CW3.4/PEAKDC). Y APF:1 Y Gamma Start=11 Chroma trap amount CtraPP PAL Chroma trap amount CtraPN NTSC DC restoration rate 1 ClampG1 46 46 46 L-CW L-CW L-0 L-100 With the input signal’s continuous wave=4.43MHz, measure Y Filter.sys:01 the output signal’s continuous wave amplitude (F0P Vp-p). Sharpness: 000000 Calculate CtraP=20Log (F0P/PEAKDC). Y Gamma Start=11 With the input signal’s continuous wave=3.58MHz, measure Y Filter.sys:00 the output signal’s continuous wave amplitude (F0N Vp-p). Sharpness: 000000 Calculate CtraN=20Log (F0N/PEAKDC). Y Gamma Start=11 Measure the output signal’s 0IRE DC level Sub.Bais:1111111 (BRTPL V). CONTRAST:0111111 Measure the output signal’s 0IRE DC level(DRVPH V) and Sub.Bais:1111111 100IRE amplitude (DRVH Vp-p) and calculate Contrast:0111111 ClampG=100×(1+(DRVPH-BRTPL)/DRVH). DCREST=00 BLK.STR.START=11 WPL=0 DC restoration rate 2 ClampG2 46 L-100 With DCREST = 01, carry out measurement similarly to the case of DCREST =01 the DC restoration rate 1. DC restoration rate 3 ClampG3 46 L-100 With DCREST = 10, carry out measurement similarly to the case of DCREST =10 the DC restoration rate 1. DC restoration rate 4 ClampG4 46 L-100 With DCREST = 11, carry out measurement similarly to the case of DCREST =11 the DC restoration rate 1. Y-DL TIME1 TdY1 (NTSC) 46 L-50 Obtain the time difference (the delay time) from when the rise Y Filter.sys:00 of the input signal's 50IRE amplitude to the output signal's YDELAY Ajust:100 50IRE amplitude. Y-DL TIME2 TdY2 (PAL) 46 L-50 Obtain the time difference (the delay time) from when the rise Y Filter.sys:01 of the input signal's 50IRE amplitude to the output signal's YDELAY Ajust:100 50IRE amplitude. Y-DL TIME3 TdY3 46 L-50 (SECAM) Y-DL TIME4 TdY4 46 L-50 (6MHz TRAP) Obtain the time difference (the delay time) from when the rise Y Filter.sys:11 of the input signal's 50IRE amplitude to the output signal's YDELAY Ajust:100 50IRE amplitude. Delay Test:1 Obtain the time difference (the delay time) from when the rise Y Filter.sys:10 of the input signal's 50IRE amplitude to the output signal's YDELAY Ajust:100 50IRE amplitude. Y-DL TIME Ajust1 TdYa1 46 L-50 Obtain the time difference (the delay time) from when the rise Y Filter.sys:00 of the input signal's 50IRE amplitude to the output signal's Y Delay Ajust:000 50IRE amplitude. No.A1938-14/47 LV76223A3F Parameter Symbol Y-DL TIME Ajust2 TdYa2 Test point 46 Input signal L-50 Test method Bus conditions Obtain the time difference (the delay time) from when the rise Y Filter.sys:00 of the input signal's 50IRE amplitude to the output signal's Y Delay Ajust:111 50IRE amplitude. Black stretch gain BKST max (MAX) Black stretch gain BKST mid (MID) 46 L-BK Measure the 0IRE DC level(BKST1 V) at point A of the output Blk.str.start=11 (A=0IRE) signal in the Black Stretch Defeat (Black Stretch OFF) mode Y Filter.sys:10 Measure the 0IRE DC level(BKST2 V) at point A of the output Blk.str.gain=10 signal in the Black Stretch ON mode. Blk.str.start=01 Calculate BKST max=50 (BKST1-BKST2)/CNTHB. Y Filter.sys:10 46 L-BK With Blk.str.gain = 01, carry out the same measurement as for Blk.str.gain=01 (A=0IRE) the case of black stretch gain (MAX). Blk.str.start=01 46 L-BK With Blk.str.gain = 00, carry out the same measurement as for Blk.str.gain=00 (A=0IRE) the case of black stretch gain (max). Blk.str.start=01 L-BK Measure the 60IRE DC level (BKST3 V) at point A of the output Blk.str.gain=01 (A=60IRE) signal in the Black Stretch ON mode. Blk.str.start=10 Y Filter.sys:10 Black stretch gain BKST min (MIN) Y Filter.sys:10 Black stretch start max (60IRE ΔBlack) BKSTTH max 46 Y Filter.sys:10 Black stretch start mid (50IRE ΔBlack) BKSTTH mid 46 Measure the 60IRE DC level (BKST4 V) at point A of the output Blk.str.gain=00 signal in the Black Stretch Defeat (Black Stretch OFF) mode. Blk.str.start=11 Calculate BKSTTHmax=50 (BKST4-BKST3)/CNTHB. Y Filter.sys:10 L-BK Measure the 50IRE DC level (BKST5 V) at point A of the output signal Blk.str.gain=01 (A=50IRE) in the Black Stretch Defeat ON mode. Blk.str.start=01 Y Filter.sys:10 Calculate Blk.str.gain=00 BKSTTHmid=50 BKST6-BKST5)/CNTHB. Blk.str.start=11 Y Filter.sys:10 Black stretch start min (40IRE ΔBlack) BKSTTH min 46 L-BK Measure the 40IRE DC level (BKST7 V) at pointAof the output signal in the Blk.str.gain=01 (A=40IRE) Black Stretch Defeat ON mode. Blk.str.start=00 Y Filter.sys:10 Sharpness variable range Sharp32T1 (NTSC) 46 L-CW Measure the 40IRE DC level (BKST8 V) at point A of the output Blk.str.gain=00 signal in the Black Stretch Defeat (Black Stretch OFF) mode. Blk.str.start=11 Calculate BKSTTHmin=50 (BKST8-BKST7)/CNTHB. Y Filter.sys:10 With the input signal’s continuous wave=2.2MHz, measure the Y Filter.sys:00 output signal’s continuous wave amplitude (F01S32 Vp-p). Sharpness: 100000 Calculate Sharp32T1=20Log (F01S32/PEAKDC). Y Gamma Start=11 With the input signal’s continuous wave=2.2MHz, measure the Y Filter.sys:00 output signal’s continuous wave amplitude (F01S63 Vp-p). Sharpness: 111111 Calculate Sharp63T1=20Log (F01S63/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 (max) Sharp63T1 46 L-CW C_Kill.ON=1 (min) Sharp0T1 46 L-CW With the input signal’s continuous wave=2.2MHz, measure the Y Filter.sys:00 output signal’s continuous wave amplitude (F01S0 Vp-p). Sharpness: 000000 Calculate Sharp0T1=20Log (F01S0/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 Sharpness variable range Sharp32T2 (PAL) 46 L-CW With the input signal’s continuous wave=2.7MHz, measure the Y Filter.sys:01 output signal’s continuous wave amplitude (F02S32 Vp-p). Sharpness: 100000 Calculate Sharp32T2=20Log (F02S32/PEAKDC). Y Gamma Start=11 With the input signal’s continuous wave=2.7MHz, measure the Y Filter.sys:01 output signal’s continuous wave amplitude (F02S63 Vp-p). Sharpness: 111111 Calculate harp 63T2=20Log (F02S63/PEAKDC). Y Gamma Start=11 With the input signal’s continuous wave=2.7MHz, measure the Y Filter.sys:01 output signal’s continuous wave amplitude (F02S0 Vp-p). Sharpness: 000000 Calculate Sharp0T2=20Log (F02S0/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 (max) Sharp63T2 46 L-CW C_Kill.ON=1 (min) Sharp0T2 46 L-CW C_Kill.ON=1 No.A1938-15/47 LV76223A3F Parameter Symbol Sharpness variable range Sharp32T3 (SECAM) Test point 46 Input signal L-CW Test method Bus conditions With the input signal’s continuous wave=2.3MHz, measure the Y Filter.sys:11 output signal’s continuous wave amplitude (F03S32 Vp-p). Sharpness: 100000 Calculate Sharp32T3=20Log (F03S32/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 (max) Sharp63T3 46 L-CW With the input signal’s continuous wave=2.3MHz, measure the Y Filter.sys:11 output signal’s continuous wave amplitude (F03S63 Vp-p). Sharpness: 111111 Calculate harp 63T3=20Log (F03S63/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 (min) Sharp0T3 46 L-CW With the input signal’s continuous wave=2.3MHz, measure the Y Filter.sys:11 output signal’s continuous wave amplitude (F03S0 Vp-p). Sharpness: 000000 Calculate Sharp0T3=20Log (F03S0/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 Sharpness variable range Sharp32T4 (6MHz TRAP) 46 L-CW With the input signal’s continuous wave=3.0MHz, measure the Y Filter.sys:10 output signal’s continuous wave amplitude (F04S32 Vp-p). Sharpness: 100000 Calculate Sharp32T4=20Log (F04S32/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 (max) Sharp63T4 46 L-CW With the input signal’s continuous wave=3.0MHz, measure the Y Filter.sys:10 output signal’s continuous wave amplitude (F04S63 Vp-p). Sharpness: 111111 Calculate Sharp63T4=20Log (F04S63/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 (min) Sharp0T4 46 L-CW With the input signal’s continuous wave=3.0MHz, measure the Y Filter.sys:10 output signal’s continuous wave amplitude (F04S0 Vp-p). Sharpness: 000000 Calculate Sharp0T4=20Log (F04S0/PEAKDC). Y Gamma Start=11 C_Kill.ON=1 White peak limiter WPL1 operating point 1 46 L-100 Measure the amplitude (from pedestal to white) of the output signal WPL=00 with WPL=00. (PIN 45: 5V) Bigger the input signal and measure Y Gamma Start=11 the amplitude (from pedestal to white) of the output signal at which the output signal is clipped. (WP1) WPL1=WP1/CNTCB1*100 White peak limiter WPL2 operating point 2 46 L-100 Bigger the input signal and measure the amplitude(from pedestal to WPL=01 white) of the output signal at which the output signal is clipped with WPL=01. (WP2) White peak limiter WPL3 operating point 3 46 L-100 Bigger the input signal and measure the amplitude(from pedestal to WPL=10 white) of the output signal at which the output signal is clipped with WPL=10. (WP3) White peak limiter WPL4 operating point 4 46 L-100 point1 46 white) of the output signal at which the output signal is clipped L-100 L-50 Y Gamma Start=11 WPL3=WP3/CNTCB1*100 Bigger the input signal and measure the amplitude(from pedestal to WPL=11 with WPL=11. (WP4) Y gamma start effective YGST1 Y Gamma Start=11 WPL2=WP2/CNTCB1*100 Y Gamma Start=11 WPL4=WP4/CNTCB1*100 Measure the amplitude of the output signal (0 to 100IRE) with Y Y Gamma GAIN=00 GAMMA START=3.Y GAMMA GAIN=0. (GAM0) Y Gamma Start=11 Next measure the amplitude the output signal (0 to 50IRE) with Y Y Gamma GAIN=01 GAMMA START=1. Y GAMMA GAIN=1(GAM1) and calculate Y Gamma Start=00 YGS1= GAM1/GAM0*100 Y gamma start effective YGST2 point12 46 L-50 Measure the amplitude of the output signal (0 to 50IRE) with Y Y Gamma GAIN=01 46 L-50 46 L-50 Measure the amplitude of the output signal (0 to 50IRE).(GGAM1) Y Gamma Start =01 L-100 Measure the amplitude of the output signal (0 to GAMMA START=1. Y GAMMA GAIN=1 (GAM2) and calculate Y Gamma Start=01 YGS2= GAM2/GAM0*100 Y gamma start effective YGST3 point1 Y gamma gain 1 YGGA1 Measure the amplitude of the output signal (0 to 50IRE) (GAM3) Y Gamma GAIN=01 and calculate YGS3= GAM3/GAM0*100 Y Gamma Start=10 Y Gamma GAIN=00 100IRE).(GGAM2) Calculate YGG1=100*GGAM1/(GGAM2-GGAM1) Y gamma gain 2 YGGA2 46 L-50 Measure the amplitude of the output signal (0 to 50IRE).(GGAM3) Y Gamma Start =01 L-100 Measure the amplitude of the output signal (0 to Y Gamma GAIN=01 100IRE).(GGAM4) Calculate YGG2=100*GGAM3/(GGAM4-GGAM3) Y gamma gain 3 YGGA3 46 L-50 L-100 Measure the amplitude of the output signal (0 to Y Gamma Start =01 50IRE) .(GGAM5) Y Gamma GAIN=10 Measure the amplitude of the output signal (0 to 100IRE).(GGAM6) Calculate YGG3=100*GGAM5/(GGAM6-GGAM5) No.A1938-16/47 LV76223A3F Parameter GRAY MODE LEVEL Horizontal/vertical Symbol GRAY RGBBLK Test point Input 46 46 Test method signal L-100 blanking output Bus conditions Measure the DC level(deviation from pedestal)of pin46, and CROSS B/W:10 transfer IRE. GRAY MODE:1 Measure the DC level (RGBBLK V) for the output signal’s blanking period. level Pre-shoot adjust1 Pre-shoot adjust2 PreShoot1 PreShoot2 46 L-100 46 L-100 46 L-100 Measure the pre-shoot width (Tpre) and over-shoot width (Tover) Pre-shoot adj.=00 at rise of 100IRE amplitude of the output signal, and calculate Y Filter.sys:00 PreShoot = Tpre / Tover. Sharpness=111111 With Pre-shoot adj. = 11, carry out the same measurement as for the Pre-shoot adj.=11 case of Pre-Shoot 1. Y Filter.sys:00 Sharpness=111111 Over-shoot adjust [RGB output block] (Cutoff, drive block) Brightness control (normal) OverShoot BRT64 48 L-0 47 With Over-shoot adj. = 11Measure the pre-shoot width (Tpre) and Over-shoot adj.=11 over-shoot width (Tover) at rise of 100IRE amplitude of the Y Filter.sys:00 output signal, and calculate OverShoot = Tover/Tpre Sharpness=111111 Bus control bit conditions: Contrast=127 Contrast:1111111 Measure the 0IRE DC levels of the respective output signals of R Bright: 1000000 output (48), G output (47), and B output (46). Assign the measured values to BRTPCR, BRTPCG, and BRTPCB V, respectively. Calculate BRT63=(BRTPCR+BRTPCG+BRTPCB)/3 46 Brightness control (normal-H) BRT64H 46 L-0 Brightness control (max) BRT127 46 L-0 Brightness control (min) BRT0 46 L-0 Bias (cutoff) control (min) Vbias0 48 L-50 47 Measure the 0IRE DC level of the output signal of B output (46) Bright: 1000000 and assign the measured value to BRTPCBH. B.BIAS: 11111111 Sub Bias: 1111111 Measure the 0IRE DC level of the output signal of B output (46) Bright: 1111111 and assign the measured value to BRTPHB. B.BIAS: 11111111 Sub Bias: 1111111 Calculate BRT127=50×(BRTPHBH-BRTPCB)/CNTHB. Measure the 0IRE DC level of the output signal of B output (46) Bright: 0000000 and assign the measured value to BRTPLB. B.BIAS: 11111111 Calculate BRT0=50 (BRTPLB-BRTPCBH)/CNTHB. Sub Bias: 1111111 Measure the 0IRE DC levels (Vbias0χV)of Sub.Bias: 1111111 the respective output signals of R output (48), G output (47), and B output (46). (χ: R, G, and B) 46 Bias (cutoff) control (max) Vbias255 48 L-50 47 Measure the 0IRE DC levels (Vbias255χV)of the respective output signals of R output (48), G output (47), and B output (46). (χ: R, G, and B) Sub.Bias: 1111111 R/G/B.BIAS:11111111 Measure the 0IRE DC levels (BAS80χV) of the respective output signals of R output (48), G output (47), and B output (46). (χ: R, G, and B) Measure the 0IRE DC levels (BAS48χV)of the respective output signals of R output (48), G output (47), and B output (46). Calculate Vbiassnsχ= (BAS80χ-BAS48χ)/32 R/G/B.BIAS:01010000 Sub.Bias: 1111111 R/G/B.BIAS:00110000 Sub.Bias: 1111111 Set Sub.Bias 64 and measure the 0IRE DC levels (SB64χV) of the respective output signals of R output (48),G output(47), and B output(46).and next,set Sub.Bias 42,then measure the same as before. Calculate Vsbiassnsχ-(SB64χ-SB42χ)/22 Sub.Bias: 1000000/0101010 Contrast: 0111111 R/G/B.BIAS:11111111 46 Bias (cutoff) control resolution Vbiassns 48 L-50 47 46 Sub-bias control resolution Vsbiassns 48 47 L-50 46 No.A1938-17/47 LV76223A3F Parameter Symbol Drive adjustment maximum output RGBout127 Test point 48 Input signal Test method Bus conditions L-100 Measure the 100IRE amplitudes (DRVHχVp-p)of the respective output signals of R output (48),G output(47) and B output (46). (χ: R, G and B) L-100 Measure the 100IRE amplitudes (DRVLχVp-p) of the Bright: 0000000 respective output signals of R output (48), G output (47), and B R/G/B DRIVE: 0000000 output (46). (χ: R, G and B) Contrast: 1000000 Calculate RGBout0χ=20log(DRVHχ/DRVLχ) 47 Bright: 0000000 R/G/B DRIVE: 1111111 Contrast: 1000000 46 Output attenuation RGBout0 48 47 46 [Ext.RGB Block] Bus control bit conditions: Contrast:64, Brightness:64 Contrast:1000000 Brightness:1000000 Ext.RGB FSTH Fast SW threshold Ext.Red output level REXDC 46 48 L-0 Apply voltage to pin 8 and measure the voltage at pin 8 at the Pin 8: O-5 Applied O-2 point where the output signal switches to the Ext.RGB signal. VIN/Ext.RGB IN:0 Digital OSD:1 L-50 Measure the output signal’s 50IRE amplitude (CNTCR Vp-p) L-0 Measure the Ext.RGB output amplitude (EXTHR Vp-p). Pin 8 : 5V O-2 Calculate REXDH=50×(EXTHR/CNTCR). Pin 11A: O-2 Applied VIN/Ext.RGB IN: 0 Digital OSD :1 EXT.RGB Contrast:1000 Ext.RBIAS:1000 Ext.RDRIVE:1000 Ext.Green output level GEXDC 47 L-50 Measure the output signal’s 50IRE amplitude (CNTCG Vp-p) L-0 Measure the Ext.RGB output amplitude (EXTHG Vp-p). Pin 8 : 5V O-2 Calculate GEXDH=50×(EXTHG/CNTCG). Pin 10A: O-2 Applied VIN/Ext.RGB IN: 0 Digital OSD :1 EXT.RGB Contrast:1000 Ext.RBIAS:1000 Ext.RDRIVE:1000 Ext.Blue output level BEXDC 48 L-50 Measure the output signal’s 50IRE amplitude (CNTCB Vp-p) L-0 Measure the Ext.RGB output amplitude (EXTHB Vp-p). Pin 8 : 5V O-1 Calculate BEXDH=50×(EXTHB/CNTCB). Pin 13A: O-1 Applied VIN/Ext.RGB IN: 0 Digital OSD :1 EXT.RGB Contrast:1000 Ext.RBIAS:1000 Ext.RDRIVE:1000 Analog Ext R output level 48 L-0 Measure the amplitudes at point A (0.35V portion of the input Pin 8 : 5V O-1 signal 0-1) and point B (0.7V portion of the input signal 0-1) of Pin 11A: O-1 Applied the output signal. Assign the measured values to RGBLR Vp-p VIN/Ext.RGB IN: 0 and RGBHR Vp-p, respectively. Digital OSD :0 EXT.RGB Contrast:1000 Gain match RRGB linearity LRRGB Analog Ext G output level 47 Calculate RRGB=RGBLR/CNTCR. Ext.RBIAS:1000 Calculate LRRGB=100×(RGBLR/RGBHR). Ext.RDRIVE:1000 L-0 Measure the amplitudes at point A (0.35V portion of the input Pin 8 : 5V O-1 signal 0-1) and point B (0.7V portion of the input signal 0-1) of Pin 10A: O-1 Applied the output signal. Assign the measured values to RGBLG Vp-p VIN/Ext.RGB IN: 0 Digital OSD :0 EXT.RGB and RGBHG Vp-p, respectively. Contrast:1000 Gain match GRGB linearity LGRGB Analog Ext B output level 46 Calculate GRGB=RGBLG/CNTCG. Ext.RBIAS:1000 Calculate LGRGB=100×(RGBLG/RGBHG) Ext.RDRIVE:1000 L-0 Measure the amplitudes at point A (0.35V portion of the input Pin 8 : 5V O-1 signal 0-1) and point B (0.7V portion of the input signal 0-1) of Pin 10A: O-1 Applied the output signal. Assign the measured values to RGBLB Vp-p VIN/Ext.RGB IN: 0 Digital OSD :0 EXT.RGB and RGBHB Vp-p, respectively. Contrast:1000 Gain match BRGB linearity LBRGB Calculate BRGB=RGBLB/CNTCB. Ext.RBIAS:1000 Calculate LBRGB=100×(RGBLB/RGBHB) Ext.RDRIVE:1000 No.A1938-18/47 LV76223A3F Parameter Symbol Test point Input Test method signal Bus conditions [VIDEO SW [Block] Video signal input VIN1DC 5 VIN1AC 5 VIN2DC 3 VIN2AC 3 VIN3DC 10 Input signals to pin 10 and measure the voltage of the pedestal. Video SW:10 VIN3AC 10 Pin 10 recommended input level VIN4DC 7 Input signals to pin 7 and measure the voltage of the pedestal. Video SW:11 VIN4AC 7 Pin 7 recommended input level SVODC 61 L-100 61 L-100 61 L-0 Y signal is input to 7PIN, and C signal of 8PIN is input, and the VIDE0 SW:11 L-CW amplitude of 61PIN (SVO) is measured. 1DC voltage Video signal input 1 AC voltage Video signal input 2DC voltage Video signal input 2 AC voltage Video signal input 3DC voltage Video signal input 3AC voltage Video signal input 4DC voltage Video signal input 4AC voltage SVO terminal DC voltage L-100 Input signals to pin 5 and measure the voltage of the pedestal. Video SW:01 Pin 5 recommended input level L-100 Video SW:01 Input signals to pin 3 and measure the voltage of the pedestal. Video SW:00 Pin 3 recommended input level Video SW:00 Video SW:10 Video SW:11 Input signals to pin 5 and measure the voltage of the pedestal at Video SW:01 pin 61. SVO SW:1 YCMIX:0 SVO terminal AC SVOAC voltage The signal is input to 5PIN, and the amplitude of the signal of VIDE0 SW:01 61PIN is measured. SVO SW:1 YCMIX:0 SVO terminal Ycmix AC Voltage SVOYC SVO SW:1 YCMIX:1 No.A1938-19/47 LV76223A3F •Chroma Block Input Signals and Test Conditions Unless otherwise specified, the following conditions apply when each measurement is made. 1. VIF, SIF blocks: No signal 2. Deflection Block: Horizontal/vertical composite sync signals are input and the deflection block must be locked into the sync signals (Refer to the Deflection Block Input Signals and the Test Conditions). 3. Bus control conditions: Set the following conditions unless otherwise specified. Y Input is 7 Pin (YC-Y), C Input is 8 Pin (YC-C) (Video SW=3, C. Ext=1) Other DAC except the above-mentioned conditions is all initial conditions. 4. Y Input condition: No signal unless otherwise specified. (Sync is necessary to obtain synchronization). 5. How to calculate the demodulation ratio and angle: B-Y axis angle=tan-1(B ( 0) / B (270))+270° R-Y axis angle=tan-1(R (180) / R ( 90))+90° G-Y axis angle=tan-1(G (270) / G (180))+180° B-Y axis amplitude Vb=SQRT(B(0)*B(0)+B(270)*B(270)) R-Y axis amplitude Vr=SQRT(R(180)*R(180)+R(90)*R(90)) G-Y axis amplitude Vg=SQRT(G(180)*G(180)+G(270)*G(270)) R-Y axis 90° R(90) R(180) 180° B(270) B(0) G(180) 0° B-Y axis G(270) G-Y axis 270° No.A1938-20/47 LV76223A3F 6. Chroma input signal As for the PAL signal, the burst swings such as 135° and 225° every horizontal period. Chroma describes the phase caused when the burst occurs at 135°. As for the NTSC signal, the burst occurs constantly at 180°. The figures below are based on the phase of NTSC. When a PAL signal is generated, adjust the phase and then enter signals. The item common to both PAL and NTSC is the PAL signal. For those other than this, the measurement must be performed for each individual signals. The condition of fsc: Set the following conditions unless otherwise specified. PAL =4.433619MHz NTSC =3.579545MHz C-1 40IRE Burst 0 º 90 º 180 º 270 º fsc X IRE signal (L-X) C-2 40IRE Burst 40IRE fsc 346 deg C-3 40IRE Burst fsc CW (Note: fsc±N*fh when the frequency is specified. N should be a natural number and the nearest value should be used.) C-4 Burst B-Y only C-5 Burst R-Y only C-6 0.35V 0.35V *There is no signal for H, V blanking period. No.A1938-21/47 LV76223A3F 7. SECAM input condition BUS control condition: It sets it as follows if there is no specification. Blank.Def:1, CROSS.B/W: 1, Color.Sys:7, Video.SW:1, MONI_CbCr:1 R.BIAS:255, B.BIAS:255, G.BIAS:255, Sub.Bias:127 It all keeps initial excluding the above-mentioned. Input PIN EXT_VIDEO PIN Input signal (The following corrugate is shape of waves at the BELL.OFF.) Input signal A B ID ID B A R B R ID B A C ID D C 200mVp-p D 64μs Input signal B R B ID ID R/W 200mVp-p R/W 64μs Input signal C (Pre-emphasis=OFF) ID E1:63kHz の FM modulation E2:250kHz の FM modulation ID F1:63kHz の FM modulation F2:250kHz の FM modulation 200mVp-p 64μs B[MHz] R[MHz] Signal width ID 4.250 4.406 4.9 B/W 4.250 4.406 52.0 A 4.480 4.126 26.0 B 4.020 4.686 26.0 C 4.328 4.361 26.0 D 4.172 4.451 26.0 No.A1938-22/47 LV76223A3F Parameter Symbol Test Input point signal Test method Bus conditions [Chroma block]: PAL/NTSC common B-Y/Y amplitude ratio CLRBY 46 Color control Characteristics 1 CLRMN 46 Color control Characteristics 2 CLRMM 46 Color control sensitivity CLRSE Residual higher harmonic level B E_CAR_B Residual higher harmonic level G E_CAR_G Residual higher harmonic level R YIN:L77 Measure the Y system’s output level. V1 CIN: No signal Input a signal to the CIN (only sync Signal to the YIN) and C-2 measure the output level to calculate as follows: CLRBY=100×(V2/V1) Measure the output amplitude V1 at color Control MAX mode and C-1 output amplitude V2 at color control CEN mode and, Calculate as follows: CLRMN=V1/V2 Measure the output amplitude V3 at color Control MIN mode to C-1 calculate as follows: CLRMM=20log (V1/V3) Color:1000000 Color:1111111 Color:1000000 Color:0000000 C-1 Measure the output amplitude V4 at color Control 90 mode and output amplitude V5 at color control 38 mode to calculate as follows: CLRSE=100×(V4− V5)/(V2×52) 46 C-1 Measure the 8.86MHz component output amplitude at pin 46. 47 C-1 E_CAR_R 48 Burst only Measure the 8.86MHz component output amplitude at pin 48. ACC amplitude characteristics 1 ACCM1_P 46 C-1 0dB +6dB ACC amplitude characteristics 2 ACCM2_P 46 C-1 -20dB Demodulation output ratio R-Y/B-Y:PAL RB_P 46 Measure the output amplitude when 0dB is applied to the chroma Color:1000000 inputand when +6dB is applied to the chroma input. And calculate the ratio between them. ACCM1_P=20log(+6dBdata/0dBdata) Measure the output amplitude when –20dB is applied to the Color:1000000 chroma input and calculate the ratio between them. ACCM2_P=20log(-20dBdata/0dBdata) Refer to 5. and measure Bout output amplitude Vb and ROUT output Color:1000000 amplitude Vr. And calculate RB_P=Vr/Vb. 46 Color:1011010 Color:0100110 Burst only Measure the 8.86MHz component output amplitude at pin 47. Burst only [Chroma block]: PAL C-1 48 Demodulation output ratio G-Y/B-Y:PAL GB_P 46 C-4 Measure Bout output amplitude Vbp and GOUT output amplitude Vgbp. And calculate GB_P=Vgbp/Vbp. Color:1000000 C-5 Measure ROUT output amplitude Vrp and GOUT output amplitude Vgbp. And calculate GR_P=Vgrp/Vrp. Color:1000000 C-1 Refer to 5. and measure the B-Y and R-Y demodulation angle and calculate. Color:1000000 47 Demodulation output ratio G-Y/R-Y:PAL GR_P 47 48 Demodulation angle R-Y/B-Y:PAL ANGRB_P 46 48 Killer operating point 0 (PAL) KILLP0 46 C-1 Reduce the input signal until the output Level becomes 75mVp-p Color Killer or less. Measure the input level at that moment. Ope.:00 Killer operating point 3 (PAL) KILLP3 46 C-1 Reduce the input signal until the output Level becomes 75mVp-p Color Killer or less. Measure the input level at that moment. Ope.:11 Difference between two Killer operating points (PAL) APC pull-in range(+) DKILLP PULIN+_P 46 C-1 Decrease the chroma fsc frequency from 4.433619MHz+1000Hz and measure the frequency at which the VCO locks. APC pull-in range(-) PULIN-_P 46 C-1 Increase the chroma fsc frequency from 4.433619MHz-1000Hz and measure the frequency at which the VCO locks. Calculate as follows, DKILLP=KILLP0-KILLP3 No.A1938-23/47 LV76223A3F Parameter Symbol Test point Input signal Test method Bus conditions [Chroma block]: NTSC ACC amplitude characteristics 1 ACCM1_N ACC amplitude characteristics 2 ACCM2_N Demodulation output ratio R-Y/B-Y:NTSC RB_N Demodulation output ratio G-Y/B-Y:NTSC Demodulation angle B-Y/R-Y: NTSC GB_N 46 C-1 0dB +6dB 46 C-1 -20dB 46 C-1 Measure the output amplitude when 0dB is applied to the chroma input and when +6dB is applied to the chroma input. And calculate the ratio between them. ACCM1_N=20log(+6dBdata/0dBdata) Measure the output amplitude when 20dB is applied to the chroma input and calculate the ratio between them. ACCM2_N=20log(-20dBdata/0dBdata) Refer to 5. And measure Bout output amplitude Vb and ROUT output amplitude Vr. And calculate RB_N=Vr/Vb. Color:1000000 48 ANGBR_N 47 46 C-1 Refer to 5. and measure GOUT output amplitude Vg. And calculate GB_N=Vg/Vb. Color:1000000 C-1 Refer to 5. and measure the B-Y and R-Y demodulation angle and calculate. Reference: B-Y angle Color:1000000 C-1 Refer to 5. and measure the B-Y and G-Y demodulation angle and calculate. Reference: B-Y angle Color:1000000 C-1 Reduce the input signal until the output Level becomes 75mVp-p or less. Measure the input level at that moment. Reduce the input signal until the output Level becomes 75mVp-p or less. Measure the input level at that moment. Calculate as follows, DKILLN=KILLN0-KILLN3 Decrease the chroma fsc frequency from 3.579545MHz+1000Hz and measure the frequency at which the VCO locks. Color Killer Ope.:00 48 Demodulation angle G-Y/B-Y: NTSC ANGGB_N 46 47 Killer operating point 0 (NTSC) KILLN0 Killer operating point 3 (NTSC) KILLN3 Difference between two Killer operating points (NTSC) APC pull-in range(+) DKILLN APC pull-in range(-) PULIN-_N Tint center TINCEN Tint variable range (+) TINT+ Tint variable range (-) TINT- Cr output Amplitude CBCR-R Cb output Amplitude CBCR-B PULIN+_N 46 46 46 46 46 46 46 48 46 C-1 C-1 Color Killer Ope.:11 C-1 Increase the chroma fsc frequency from 3.579545MHz-1000Hz and measure the frequency at which the VCO locks. C-1 Measure each part of the output level and calculate the B-Y axis angle. TINT:1000000 C-1 Measure each part of the output level and calculate the B-Y axis angle. TINT+ =B-Y axis angle –TINCEN Measure each part of the output level and calculate the B-Y axis angle. TINT- =B-Y axis angle –TINCEN Measure the output amplitude. (B-Y IN:no signal) TINT:1111111 C-1 R-Y IN:C-6 B-Y IN:C-6 Measure the output amplitude. (R-Y IN:no signal) TINT:0000000 CbCr IN: 1 Color Sys:101 Cross B/W: 01 CbCr IN: 1 Color Sys: 101 Cross B/W: 01 [Chroma block]: SECAM B-Y output amplitude MVBY 46 Input signal A A and B of the output amplitude are measured. MVBY=A Color..Sys:110 Y Filter.Sys:111 R-Y output amplitude MVRY 48 Input signal A C and D of the output amplitude are measured. MVRY=C Color..Sys:110 Y Filter.Sys:111 B-Y/R-Y output ratio MRATRB It calculates by the next expression. MRATRB=MVBY/MVRY B-Y linearity MLINBY It calculates by the next expression. MLINBY=(A/B)*(156/460)*100 R-Y linearity MLINRY SECAM killer operating point MKILL White balance B-Y MWBBY White balance R-Y MWBRY 46 46 46 Color..Sys:110 Y Filter.Sys:111 Input signal A It calculates by the next expression. MLINRY=(C/D)*(90/560)*100 Input signal A Amplitude (=A) of the input signal when the input signal is reduced, and Color..Sys:110 DA5 [SEC.KIL]=1 and output amplitude B become 75mVp-p or less is Y Filter.Sys:111 measured. Input signal B Output voltage A1 is measured, output voltage A2 at SEC.KIL.ON:1 Color..Sys:110 SEC.KIL,ON:1 o'clock is measured, and it requests it by the next expression. MWBBY=A1-A2 Input signal B Output voltage B1 is measured, output voltage B2 at SEC.KIL.ON:1 Color..Sys:110 o'clock is measured, and it requests it by the next expression. MWBRY=B1-B2 Y Filter.Sys:111 SEC.KIL.ON:1 No.A1938-24/47 LV76223A3F Parameter De-emphasis frequency response B-Y De-emphasis frequency response R-Y Symbol MFDEBY MFDERY Test point 46 48 Input Test method signal Input signal C Output amplitude A and B of E1 and E2 are measured, and it requests it by the next expression. MFDEBY=20*log(B/A) Input signal D Output amplitude C and D of F1 and F2 are measured, and it requests it by the next expression. MFDERY=20*log(D/C) Bus conditions Color..Sys:110 Color..Sys:110 [Filter Block]:Chroma BPF Characteristic C-BPF1A Peaker amplitude characteristic 3.93MHz CBPF1A C-BPF1B Peaker amplitude characteristic 4.73/4.13MHz C-BPF1C Peaker amplitude characteristic 4.93/3.93MHz C-BPF2A BandPass amplitude characteristic 3.93MHz CBPF1B C-BPF2B BandPass amplitude characteristic 4.73/4.13MHz C-BPF2C BandPass amplitude characteristic 4.93/3.93MHz CBPF2B CBPF1C CBPF2A CBPF2C 46 C-3 PAL signal Set the chroma frequency (CW) to 4.433619MHz-100kHz and measure C.Filter.Sys:10 V0 output amplitude. And then, set the chroma frequency (CW) to C.BYPASS:0 3.93MHz and measure V1 output amplitude to calculate as follows: CBPF1A=20log(V1/V0) 46 C-3 PAL signal Measure V2 output amplitude when the chroma frequency (CW) is 4.13MHz and V3 output amplitude when it (CW) is 4.73MHz to calculate as follows: CBPF1B =20log(V3/V2) C.Filter.Sys:10 C.BYPASS:0 46 C-3 PAL signal Set the chroma frequency (CW) to 4.93MHz and measure V4 output amplitude to calculate as follows: CBPF1C =20log(V4/V1) C.Filter.Sys:10 C.BYPASS:0 46 C-3 PAL signal Set the chroma frequency (CW) to 4.433619MHz-100MHz and measure V00 output amplitude. And then, set the chroma frequency (CW) to 3.93MHz and measure V10 output amplitude to calculate as follows: CBPF2A=20log(V10/V00) C.Filter.Sys:11 C.BYPASS:0 46 C-3 PAL signal Measure V20 output amplitude when the chroma frequency (CW) is 4.13MHz and V30 output amplitude when it (CW) is 4.73MHz to calculate as follows: CBPF2B =20log(V30/V20) C.Filter.Sys:11 C.BYPASS:0 46 C-3 PAL signal Set the chroma frequency (CW) to 4.93MHz and measure V40 output amplitude to calculate as follows: CBPF2C =20log(V40/V10) C.Filter.Sys:11 C.BYPASS:0 No.A1938-25/47 LV76223A3F •Deflection Block Input Signals and Test Conditions Unless otherwise specified,the following conditions apply when each measurement is made. 1. VIF, SIF blocks: No signal 2. C input: No. signal 3. Sync input: A horizontal/vertical composite sync signal PAL: 43IRE, horizontal sync signal (15.625kHz) and vertical sync signal (50kHz) NTSC: 40IRE, horizontal sync signal (15.734264kHz) and vertical sync signal (59.94kHz) Note: No burst signal, chroma signal shall exist below the pedestal level. Signal unsuitable for Y input Signal suitable for Y input Chroma signal Burst signal 4. Bus control conditions: Initial conditions unless otherwise specified. 5. The delay time from the rise of the horizontal output (pin 23 output) to the fall of the FBP IN (pin 23 input) is 7μs. 6. Pin 15 (vertical size correction circuit input terminal) is connected to VCC (5.0V). Parameter Symbol Test point Input signal Test method Bus conditions [Deflection block] Horizontal free-running frequency fH Horizontal pull-in range fH PULL 22 22 5 Horizontal output pulse length Hduty Horizontal output pulse saturation voltage V Hsat Vertical free-running period 50(PAL) Vertical free-running period 60(NTSC) VFR50 VFR60 22 22 17 YIN: No signal Connect a frequency counter to the output of pin 22 (H out) and measure the horizontal free-running frequency. YIN: Horizontal /vertical sync signal PAL Using an oscilloscope, monitor the horizontal sync signal which is input to the Y IN (pin 5) and the pin 22 output (H out) and vary the horizontal signal frequency to measure the pull-in range. YIN: Horizontal /vertical sync signal PAL YIN: Horizontal /vertical sync signal PAL YIN: No signal Measure the voltage for the pin 22 horizontal output pulse’s low-level period. Measure the voltage for the pin 22 horizontal output pulse’s low-level period. Measure the vertical output period T at pin 17. T × 15.625kHz (PAL) T × 15.734kHz (NTSC) Vertical ramp output CDMODE:001 (PAL) CDMODE:010 (NTSC) 2.5V T Horizontal output pulse (PAL)(NTSC) HPHCEN (PAL) (NTSC) 22 5 Y IN: Horizontal /vertical sync signal PAL NTSC Measure the delay time from to the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal. Measuring HPHCEN 20IRE 2.5V Horizontal output No.A1938-26/47 LV76223A3F Parameter Horizontal position adjustment range Symbol HPHrange Test point 22 5 Input signal Y IN: Horizontal /vertical sync signal PAL Test method Bus conditions With H.PHASE: 0 and 31, measure the delay time from the H.PHASE:00000 rise of the pin 22 horizontal output pulse to the fall of the Y to IN horizontal sync H.PHASE:11111 signal and calculate the difference from H PHCEN. Measuring HPHCEN 20IRE 2.5V Horizontal output Horizontal position adjustment maximum variable width HPHstep 22 5 Y IN: Horizontal /vertical sync signal PAL With H.PHASE: 0 to 31 varied, measure the delay time H.PHASE:00000 from to the rise of the pin 22 horizontal output pulse to the to fall of the Y IN horizontal sync signal and calculate the H.PHASE:11111 variation at each step. Retrieve data for maximum variation. Measuring HPHCEN 20IRE 2.5V Horizontal position adjustment maximum variable width HPHstep 22 5 Y IN: Horizontal /vertical sync signal PAL Horizontal output With H.PHASE: 0 to 31 varied, measure the delay time H.PHASE:00000 from to the rise of the pin 22 horizontal output pulse to the to fall of the Y IN horizontal sync signal and calculate the H.PHASE:11111 variation at each step. Retrieve data for maximum variation. Measuring HPH CEN 20IRE Horizontal blanking left variable range@0 BLKL0 46 5 Y IN: Horizontal /vertical sync signal PAL Horizontal output Measure the time T from the left end of Hsync at pin 5 Y IN to the right end of blanking period at pin 46 BlueOUT with H.BLK.L = 000. Y IN Hsync H.BLK.L:000 T Blue Horizontal blanking left variable range@7 BLKL7 46 5 Y IN: Horizontal /vertical sync signal PAL Measure the time T from the left end of Hsync at pin 5 Y IN H.BLK.L:111 to the right end of blanking period at pin 46 BlueOUT with H.BLK.L = 111. Y IN Hsync T Blue No.A1938-27/47 LV76223A3F Parameter Horizontal blanking right variable range@0 Symbol BLKR0 Test point 46 5 Input signal Test method Y IN: Horizontal /vertical sync signal PAL Measure the time T from the left end of Hsync at pin 5 Y IN to the left end of blanking period at pin 46 BlueOUT with H.BLK.R = 000. Y IN T Bus conditions H.BLK.R:000 Hsync Blue Horizontal blanking right variable range@7 BLKR7 46 5 Y IN: Horizontal /vertical sync signal PAL Measure the time T from the left end of Hsync at pin 5 Y IN to the left end of blanking period at pin 46 BlueOUT with H.BLK.R = 111. Y IN T H.BLK.R:111 Hsync Blue Sand castle pulse crest value H Sand castle pulse crest value M1 SANDH SANDM1 23 23 Y IN : Horizontal /vertical sync signal PAL Measure the supply voltage at point H of the pin 23 FBP IN wave form for Hsync period. Y IN : Horizontal /vertical sync signal PAL Measure the supply voltage at point M1 of the pin 23 FBP IN wave form for Hsync period. H M1 Sand castle pulse crest value L SANDL 23 Y IN : Measure the supply voltage at point L of the pin 23 FBP IN wave Horizontal form for Hsync period. /vertical sync signal PAL L Burst gate pulse length Burst gate pulse phase BGPWD BGPPH 23 23 5 Y IN : Horizontal /vertical sync signal PAL Measure the BGP width T of the pin 23 FBP IN wave form for Hsync period. T Y IN : Measure the time from the left end of Hsync at pin 5 Y IN to the Horizontal left end of the pin 23 FBP IN wave form for Hsync period. /vertical sync Hsync signal PAL Y IN T FBP IN Horizontal output stop voltage Hstop 20 22 Y IN: Horizontal /vertical sync signal Decrease the current from a source connected to pin 20 and measure the pin 20 voltage at which HOUT(PIN22) stops. No.A1938-28/47 LV76223A3F Parameter H Phase BOW@16 Symbol HBOW16 Test point 22 5 Input signal Y IN: Horizontal /vertical sync signal Test method Measure the delay time T from the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 167(NTSC:142). Caluculat as follow with each value of T is as T1 and T2. HBOW16=T2-T1 Bus conditions T 20IRE 2.5V Horizontal Out Horizontal output H Phase BOW@0 HBOW0 22 5 Y IN: Horizontal /vertical sync signal Measure the delay time T from the rise of the pin 22 horizontal output pulse H Phase Bow: to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 00000 167(NTSC:142). Caluculat as follow with each value of T is as T1 and T2. HBOW0=T2-T1 T 20IRE 2.5V Horizontal Out Horizontal output H Phase BOW@31 HBOW31 22 5 Y IN: Horizontal /vertical sync signal Measure the delay time T from the rise of the pin 22 horizontal output pulse H Phase Bow: 11111 to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 167(NTSC:142). Caluculat as follow with each value of T is as T1 and T2. HBOW31=T2-T1 T 20IRE 2.5V Horizontal Out Horizontal output H Phase ANGLE@16 HANG16 22 5 Y IN: Horizontal /vertical sync signal Measure the delay time T from the rise of the pin 22 horizontal output pulse to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 167(NTSC:142).Caluculat as follow with each value of T is as T1 and T2. HANG16=T2-T1 T 20IRE 2.5V Horizontal Out Horizontal output H Phase ANGLE@0 HANG0 22 5 Y IN: Horizontal /vertical sync signal Measure the delay time T from the rise of the pin 22 horizontal output pulse H Phase Angle: to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 00000 167(NTSC:142).Caluculat as follow with each value of T is as T1 and T2. HANG0=T2-T1 T 20IRE 2.5V Horizontal Out Horizontal output No.A1938-29/47 LV76223A3F Parameter H Phase ANGLE@31 Symbol HANG31 Test point 22 5 Input signal Y IN: Horizontal /vertical sync signal Test method Bus conditions Measure the delay time T from the rise of the pin 22 horizontal output pulse H Phase Angle: to the fall of the Y IN horizontal sync signal with line 24(NTSC:22) and 11111 167(NTSC:142). Caluculat as follow with each value of T is as T1 and T2. HANG31=T2-T1 T 20IRE 2.5V Horizontal Out Horizontal output <Vertical screen size correction> vertical ramp output amplitude Vsize64 @64 17 Y IN: Horizontal /vertical sync signal PAL NTSC Monitor the pin 17 vertical ramp output and measure the voltage at line 24 (22:NTSC) and line 310 (262:NTSC). Calculate as follows:Vsize64=Vline310(262:NTSC)-Vline24(22:NTSC) Positive vertical ramp output Line 310 Line 24 vertical ramp output amplitude @0 Vsize0 17 Y IN: Horizontal /vertical sync signal PAL NTSC Monitor the pin 17 vertical ramp output and measure the voltage at VSIZE: line 24 (22:NTSC) and line 310 (262:NTSC). Calculate as follows: 0000000 Vsize0=Vline310(262:NTSC)-Vline24(22:NTSC) Positive vertical ramp output Line 310 Line 24 vertical ramp output amplitude Vsize127 @127 17 Y IN: Horizontal /vertical sync signal PAL NTSC Monitor the pin 17 vertical ramp output and measure the voltage at VSIZE: line 24 (22: NTSC) and line 310 (262:NTSC). Calculate as follows: 1111111 Vsize127=Vline310(262:NTSC)-Vline24(22:NTSC) Positive vertical ramp output Line 310 Line 24 <High-voltage dependent vertical size correction> Vertical size correction @0 Vsizecomp 17 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the voltage at VCOMP:000 the line 24 and line 310 with VCOMP = 000. Calculate as follows: FSCorEHT=1 Va=Vline310-Vline24 Apply 4.0V to pin 15 and measure the voltage at the line 24 and line 310 again. Calculate as follows: Va=Vline310-Vline24 Calculate as follows: Vsizecomp=Vb/Va Positive vertical ramp output Line 310 Line 24 No.A1938-30/47 LV76223A3F Parameter Symbol Test point Input signal Test method Bus conditions <Vertical screen position adjustment> Vertical ramp DC voltage @32 Vdc32 17 Y IN: Monitor the pin 17 vertical ramp output and measure the Horizontal /vertical voltage at line 167(142: NTSC). sync signal PAL Positive vertical ramp output NTSC Line 167 Vertical ramp DC voltage @0 Vdc0 17 Monitor the pin 17 vertical ramp output and measure the Y IN: Horizontal /vertical voltage at line 167(142: NTSC). sync signal Positive vertical ramp output PAL NTSC VDC:000000 Line 167 Vertical ramp DC voltage @63 Vdc63 17 Y IN: Monitor the pin 17 vertical ramp output and measure the Horizontal /vertical voltage at line 167(142: NTSC). sync signal PAL Positive vertical ramp output NTSC VDC:111111 Line 167 Verticalposition @8 Vshift8 17 Y IN: Measure the time T from the beginning of Vsync at pin 5 Y V.SHIFT:1000 Horizontal /vertical IN to the fall of the pin 17. sync signal the beginning of Vsync 5 T V.out(+):17pin Vertical position @0 Vshift0 17 Y IN: Measure the time T from the beginning of Vsync at pin 5 Y V.SHIFT:0000 Horizontal /vertical IN to the fall of the pin 17. sync signal the beginning of Vsync 5 T V.out(+):17pin Vertical position @15 Vshift15 17 Y IN: Measure the time T from the beginning of Vsync at pin 5 Y V.SHIFT:1111 Horizontal /vertical IN to the Rise of the pin 17. sync signal the beginning of Vsync 5 T V.out(+):17pin Vertical linearity@16 Vlin16 17 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the voltage at line 24, line 167 and 310. Assign the respective measured values to Va, Vb and Vc. Calculate as follows: Vlin16=(Vb-Va)/(Vc-Vb) Positive vertical ramp output Line 310 Line 167 Line 24 No.A1938-31/47 LV76223A3F Parameter Vertical linearity@0 Symbol Test point Vlin0 17 Input signal Y IN: Horizontal /vertical sync signal PAL Test method Bus conditions Monitor the pin 17 vertical ramp output and measure the VLIN:00000 voltage at line 24, line 167 and 310. Assign the respective measured values to Va, Vb and Vc. Calculate as follows: Vlin0=(Vb-Va)/(Vc-Vb) Positive vertical ramp output Line 310 Line 167 Line 24 Vertical linearity@31 Vlin31 17 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the VLIN:11111 voltage at line 24, line 167 and 310. Assign the respective measured values to Va, Vb and Vc. Calculate as follows: Vlin31=(Vb-Va)/(Vc-Vb) Positive vertical ramp output Line 310 Line 167 Line 24 Vertical S-shaped correction @16 Vscor16 17 Y IN: Horizontal /vertical sync signal PA L Monitor the pin 17 vertical ramp output and measure the voltage at line 26, line 70, line 145, line 189, line 264 and 308. Assign the respective measured values to Va, Vb, Vc, Vd, Ve and Vf. Calculate as follows: Vscor16=0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc) Positive vertical ramp output Line 308 Line 189 Line 70 Line 264 Line 145 Line 26 Vertical S-shaped correction @0 Vscor0 17 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the VSC:10000 voltage at line 26, line 70, line 145, line 189, line 264 and 308. Assign the respective measured values to Va, Vb, Vc, Vd, Ve and Vf. Calculate as follows: Vscor0=0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc) Positive vertical ramp output Line 308 Line 189 Line 70 Line 264 Line 145 Line 26 Vertical S-shaped correction @31 Vscor31 17 Y IN: Horizontal /vertical sync signal PAL Monitor the pin 17 vertical ramp output and measure the VSC:11111 voltage at line 26, line 70, line 145, line 189, line 284 and 308. Assign the respective measured values to Va, Vb, Vc, Vd, Ve and Vf. Calculate as follows: Vscor31=0.5((Vb-Va)+(Vf-Ve))/ (Vd-Vc) Positive vertical ramp output Line 308 Line 189 Line 70 Line 264 Line 145 Line 26 No.A1938-32/47 LV76223A3F Parameter Symbol Test point Input signal Test method Bus conditions <Horizontal size adjustment> East/Wst DC oltage @64 East/West DC voltage @0 East/West DC voltage @127 EWdc64 16 EWdc0 16 EWdc127 16 Horizontal, vertical sync signal Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 167. East/West output Line 167 Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 167. East/West output Horizontal, vertical sync signal EWDC:000000 Line 167 Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 167. East/West output EWDC:111111 Line 167 <High-voltage dependent horizontal size compensation> Horizontal size compensation @0 Hsizecomp 16 Horizontal, vertical sync signal Monitor the West/East output of pin 16 and measure the voltage (Va) at line 167. Apply 4.0 V to pin 16 and measure again the voltage (Vb) at line 167. Calculate as follows: Hsizecomp=Va-Vb HCOMP:000 FSCorEHT=1 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 167 (Vb). Calculate as follows: EWamp64=Vb-Va EWDC :1111111 <Pincushion distortion compensation> East/West parabolic amplitude @64 EWamp64 16 East/West output Line 167 Line 24 East/West parabolic amplitude @0 EWamp0 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 167 (Vb). Calculate as follows: EWamp0=Vb-Va East/West output EWAMP:000000 EWDC : 1111111 Line 167 Line 24 East/West parabolic amplitude @127 EWamp127 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 167 (Vb). Calculate as follows: EWamp127=Vb-Va East/West output EWAMP:1111111 EWDC : 1111111 Line 167 Line 24 <Trapezoidal distortion compensation> East/West parabolic tilt @64 EWtilt64 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 310 (Vb). Calculate as follows: Ewtilt64=Va-Vb East/West output EWDC : 1111111 EWCORSW: 1 Line 310 Line 24 East/West parabolic tilt @0 EWtilt0 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 (Va) and line 310 (Vb). Calculate as follows: Ewtilt0=Va-Vb East/West output EWTILT:0000000 EWDC : 1111111 EWCORSW : 1 Line 310 Line 24 No.A1938-33/47 LV76223A3F Parameter Symbol East/West parabolic tilt @127 EWtilt127 Test point 16 Input signal Test method Horizontal, Monitor the East/West output (parabolic wave output) of pin 16 and vertical sync measure the voltage at line 24 (Va) and line 310 (Vb). Calculate as signal follows: Ewtilt127=Va-Vb East/West output Bus conditions EWTILT:1111111 EWDC : 1111111 EWCORSW : 1 Line 310 Line 24 <Corner distortion compensation> East/West parabolic corner TOP EWcortop 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 24 under conditions of CORTOP:11111 (Va) and CORTOP:00000 (Vb). Calculate as follows: Ewcortop=Va-Vb CORTOP: 11111-00000 EWDC : 1111111 EWCORSW : 1 East/West output Line 24 East/West parabolic corner BOTTOM EWcorbot 16 Horizontal, vertical sync signal Monitor the East/West output (parabolic wave output) of pin 16 and measure the voltage at line 310 under conditions of CORBOT:11111 (Va) and CORBOT:00000 (Vb). Calculate as follows: Ewcorbot=Va-Vb East/West output CORBOTTOM: 11111-00000 EWDC:1111111 EWCORSW : 1 Line 310 No.A1938-34/47 LV76223A3F μ-Controller Chip (LC87F33C8A) Internal 128K-byte FROM (ROM/CGROM), 2048-byte RAM And 352×9-bit CRT Display RAM 8-bit Single-chip Microcontroller. 1. Features ■Flash ROM 128K bytes ● 96K-byte to 112K-byte program ROM (Changeability) ● 16K-byte to 32k-byte character generator ROM (Changeability) ● Runs on a 5V single source and permits onboard programming. ● Block erasable in 128 byte units. ● Permits 100 programming operations. ■Internal RAM ● General-purpose RAM: 2k-bytes ● CRT display RAM: 352 × 9 bits ● ROM correction RAM: 128 bytes ■Minimum bus cycle time ● 77 ns (13.0 MHz) Note: The bus cycle time here refers to the ROM read speed. ■Minimum instruction cycle time ● 231 ns (13.0MHz) ■OSD ● Screen display: 36 characters × 8 lines ● Display RAM : 352 words (1 word=9 bits) Display area: 36 words × 8 lines Control area: 8 words × 8 lines ● Font types: 16×32 font, 256 types (including 5 fixed fonts) An arbitrary number of characters can be generated as 16×17 or 8×9 font characters. ● Display colors: 512 colors (Analog output) Character text, background, borders, and full background can be displayed. A maximum 16 colors displayable on a line. ● Display mode specifiable on a line basis. OSD mode1, OSD mode 2(Quarter size), OSD mode 3(Simplified graphic), caption/text mode ● Vertical display start line and horizontal display start position specifiable on a line basis. ● Shutter function (specifying the display start or stop line) and scroll functions specifiable on a line basis. ● Horizontal character spacing (9 to 16 dots) (*6) and vertical character spacing (1 to 32 dots) specifiable on a line basis. ● Character size selectable from 10 character sizes on a line basis. (*6) (Horizontal×Vertical) = (1×1), (1×2), (2×2), (2×4), (1.5×1), (1.5×2), (3×2), (3×4), (0.5×0.5), (0.75×0.5) ● Simplified graphic display (One character (16×16 font) can be painted in 4 or 8 colors.) ● The half tone control of the TV picture in the background of the character is possible. ● Built-in the oscillation circuit for display (*5)The supported range varies depending on the active display mode. Refer to the user's guide for details. ■Data slicer function(closed caption format) ● Extracts closed caption data and XDS data. ● NTSC/PAL selectable and line specifiable. ■Ports ● Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units: 10 (P1n, P3n) Ports whose I/O direction can be designated in 4 bit units: 8 (P0n) *If X’tal oscillator is to be used for time-of-day clock, the number of available Port 0 is 6. Note: Threee of the available ports are internally connected to the companion signal processing IC. ■Timers ● Timer 0: 16-bit timer/counter with a capture register. ● Timer 1: 16-bit timer/counter that supports PWM/toggle outputs ● Base timer ■SIO ● SIO0: 8-bit synchronous serial interface ● SIO1: 8-bit asynchronous/synchronous serial interface (bus mode 1 system) Input and output is possible from the terminal of two systems in bus mode. The two data lines and clock lines can be connected. ■AD converter: 6 bits ×5 channels Note: One channel is connected internally to the signal processing IC. ■PWM: 14-bit PWM×1 channel No.A1938-35/47 LV76223A3F ■Remote controller receiver circuit (sharing with P03 and INT3 pins) ● Noise rejection function (noise filter time constant selectable from 1 Tcyc,32 Tcyc,and 128Tcyc) ■Watchdog timer ● External RC watchdog timer ● Interrupt and reset signals selectable ■High-speed multiplication/division instructions ● 16 bits×8 bits (Execution time: 5 Tcyc) ● 24 bits×16 bits (Execution time: 12 Tcyc) ● 16 bits÷8 bits (Execution time: 8 Tcyc) ● 24 bits÷16 bits (Execution time: 12 Tcyc) ■Interrupts ● 15 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level 1 2 3 4 5 6 7 8 9 10 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L Interrupt Source INT0 INT1 INT2/T0L INT3/base timer T0H T1L/T1H SIO0 SIO1/data slicer vertical sync (VS#)/scan line Port 0 ● Priority levels X > H > L ● If interrupts of the same level, the one with the smallest vector address takes precedence. ■Subroutine stack levels: 1024 levels maximum (the stack is allocated in RAM.) ■Oscillation circuits ● RC oscillation circuit (internal): For system clock ● VCO oscillation circuit (internal): For system clock generation and CRT display ● Crystal oscillation circuit: For base timer Note:When the base timer count of clock accuracy is necessary , use the port terminal (two ports) as the crystal oscillation. (See the [12 μ-Controller Chip Crystal Oscillation Circuit and Sample Characteristics] for details.) ■Standby function ● HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of resetting HALT mode. (1) Setting the reset pin to lower level. (2) Generation of reset with the watchdog timer. (3) Setting at least one of the INT0 and INT1 pins to the specified level. ● HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The VCO and RC oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Generation of reset with the watchdog timer. (3) Setting at least one of the INT0 and INT1 pins to the specified level. (4) Having an interrupt source established at port 0. ■ROM correction function ● Executes the correction program on detection of a match with the program counter value. ● Correction program area size: 128 bytes (4 vector addresses) ■Development tools ● Emulater: TCB87 (Type B or Typ C) (onchip debugger interface board) + ECB873200A (evaluation chip board + LC873600EVA) + POD36-JCT (connecter between evaluation chip board and POD) + POD76200 (POD) No.A1938-36/47 LV76223A3F ■Flash Programming Board : W76200D When using the Flash Programming Board, all of the jumper SW must be set to the OFF position. If set to the ON position, read/write operations will not perform correctly. Pin 1 of the conversion board should be located as indicated below. When viewing from the edge closest to jumper SW, pin 1 is located on the lower right of both the chip and conversion board. Pin1 W76200D ■Flash ROM Programmer(*6) Support Version Maker Model Flash Support AF9708/AF9709/AF9709B Group,Inc. (including models manufactured by Ando (Single) Electric Co.,Ltd) (*7) (*8) Device LC87F33C8A AF9723(main unit) Flash Support Group,Inc. (Gang) (including models manufactured by Ando Rev02.29 Electric Co.,Ltd) LC87F33C8A AF9833(unit) (3B237) (including models manufactured by Ando Rev01.89 Electric Co.,Ltd) SANYO SKK/SKK TypeB Application Version 1.04 Chip Data Version 2.041 LC87F33C8 (*6) The LC87F33C8A does not support a silicon signature feature. (*7) Check for the latest version. (*8) We have a schedule to request the registration No.A1938-37/47 LV76223A3F 2. μ-Controller Chip System Block Diagram Interrupt control IR Standby control VCO ROM correct Clock generator RC PLA Flash ROM Reference Clock PLL PC SIO0 Bus interface SIO1 Port 0 ACC Port 1 B register C register Timer 0 Timer 1 Port 3 ALU Xtal PSW RAR Base timer ADC PWM INT0-INT3 noise filter RAM Stack pointer Data slicer OSD Contro l Circuit CGROM Control Watchdog timer VRAM No.A1938-38/47 LV76223A3F 3. μ-Controller Chip Pin Function Chart Pin Name CpuGND CpuVDD CpuVDD2 Port 0 I/O - Description - + power supply pin - + power supply pin I/O P00 to P07 No No • 8-bit I/O port •I/O specifiable in 4 bit units •Pull-up resistors can be turned on and off in 4 bit units. •HOLD reset input •Port 0 interrupt input •Pin functions P00: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/ SIO0 data output P01: INT1 input/HOLD reset input/timer 0H capture input/SIO0 data input/bus I/O P02: SIO0 clock I/O P03: INT3 input (with noise filter input)/timer 0 event input/ timer 0H capture input P04: AD conversion input terminal (AN4) P05: AD conversion input terminal (AN5) P06: AD conversion input terminal (AN6)/Output terminal for 32.768kHz crystal oscillation (XT2) P07: AD conversion input terminal (AN7)/Input terminal for 32.768kHz crystal oscillation (XT1) Interrupt acknowledge type Rising Port 1 I/O P11 to P17 Port 3 I/O P30 to P32 Option No - power supply pin Falling Rising & H Level Falling INT0 ○ ○ × ○ INT1 ○ ○ × ○ INT3 ○ ○ ○ × The two terminal of P00, P01, P04 and P05 can be used as LED driver. •7-bit I/O port •I/O specifiable in 1 bit units •Pull-up resistors can be turned on and off in 1 bit units. •Pin functions P13: TVPWMD output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: SIO1 data input / bus I/O / data output P17: SIO1 clock I/O /T1PWML output •3-bit I/O port (Internal connected terminal) •I/O specifiable in 1 bit units • Pin functions P32 : INT2 input / timer 0 event input/ timer 0L capture input Interrupt acknowledge type P00-P03: No P04-P07: Yes L Level ○ ○ × Yes No Rising Falling Rising & Falling H Level L Level ○ ○ ○ × × INT2 Internal communication interface terminal: P30, P31 RES# Input FILT Output Reset pin No Internal PLL filter pin for system clock No VDDi1 VDDi2 - + power supply pin (Internal connected terminal) No - + power supply pin (Internal connected terminal) No RESi# Input Reset pin (Internal connected terminal) No XTIN Input Reference clock input (Internal connected terminal) No XTSEL Input Reference clock frequency selection (Internal connected terminal) No Input No CVIN PEOUT AN3 Video input pin (Internal connected terminal) Output Pedestal level output (Internal connected terminal) No Input ADC input terminal (Internal connected terminal) No VS# Input Vertical sync input pin (Internal connected terminal) No HS# Input Horizontal sync input pin (Internal connected terminal) No (Internal connected terminal) R Output Red (R) RGB video output pin G Output Green (G) RGB video output pin B Output Blue (B) RGB video output pin BL1 Output Fast blanking 1 control output pin (Internal connected terminal) No BL2 Output Fast blanking 2 control output pin (Internal connected terminal) No (Internal connected terminal) (Internal connected terminal) No No No No.A1938-39/47 LV76223A3F 4. μ-Controller Chip Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port name Option selected in units of Option type Output type P00 to P03 - No P04 to P07 1 bit 1 CMOS Programmable (*9) 2 Nch-open drain No 1 CMOS Programmable 2 Nch-open drain Programmable P11 to P17 1 bit Nch-open drain Pull-up resistor No P30 to P31 - No Nch-open drain Yes P32 - No Nch-open drain No (*9) Programmable pull-up resistors for port 0 are controlled in 4 bit units (P04 to P07). *Connect the IC as shown below to minimize the noise input to the CpuVDD pin. LSI CpuVDD Power supply CpuVDD2 1μF CpuGND 5. μ-Controller Chip On-board writing system The LC87F33C8A has the On-board writing system. The program is renewable by using SANYO Flash On-board System after the LSI has been installed on the application board. This system has to connect the 6 pins (communication (CLK, DATA × 2), power supply (CpuVDD, CpuGND) and RES#, pins) with the interface board of SANYO Flash On-board System. It is necessary that the pins to be used for the rewriting system should be able to be separated from the application board properly. Please ask to our sales persons before using On-board writing system. No.A1938-40/47 LV76223A3F 6. μ-Controller Chip Electrical characteristics/Ta=-10deg to +65deg, VSS=0V Parameter Symbol Pins High level input current IIH(1) Ports0,1 IIH(2) RES# Low level input current IIL(1) Ports0,1 Conditions ・Output disable ・Pull-up MOS Tr.OFF ・VIN=VDD (including the off-leak current of the output Tr.) VIN=VDD ・Output disable ・Pull-up MOS Tr.OFF ・VIN=VSS (including the off-leak current of the output Tr.) VIN=VSS VDD[V] 4.5~5.5 min typ Limits max 1 4.5~5.5 1 4.5~5.5 -1 IIL(2) RES# 4.5~5.5 -1 High level output voltage VOH Ports04-07, Ports1 IOH=-1.0mA 4.5~5.5 VDD-1 Low level output voltage VOL(1) Ports02,03 Ports06,07 Ports1 Ports00,01, Ports04,05 Ports04-07,1 IOL=10mA IOL=1.6mA 4.5~5.5 1.5 4.5~5.5 0.4 IOL=8.0mA 4.5~5.5 0.4 VOH=0.9VDD 4.5~5.5 4.5~5.5 VOL(2) Pull-up MOS Tr. Resistance Rpu Bus terminal short circuit resistance RBS for internal communication Hysteresis voltage VHIS ・P14-P30 ・P15-P31 ・P14-P16 ・P15-P17 Ports00-03,1 ・RES# unit µA V 15 40 130 4.5~5.5 70 300 0.35 kΩ Ω V 7. μ-Controller Chip SIO0 Characteristics(*10) /Ta=-10deg to +65deg, VSS=0V Parameter Symbol Input Clock Cycle tSCK(1) Low level pulse-width High level Pulse-width tSCKL(1) Pins SCK0(P02) Conditions See the figure 4. Limits VDD[V] 4.5~5.5 Output Clock Serial Clock tSCK(2) tSCKL(2) SCK0(P02) Serial Input tsDI(1) unit tCYC ・Continuous data transmitting and receiving mode ・See the figure 4. (*11) ・At the CMOS output selection ・See the figure 4. 4 4.5~5.5 4/3 1/2 tSCK 1/2 tSCKH(2) tSCKHA(2a) Data setup time max 1 tSCKHA(1a) Low level pulse-width Low level pulse-width typ 1 tSCKH(1) Cycle min 2 SI0(P01) SB0(P01) ・At the CMOS output ・Continuous data transmitting and receiving mode ・See the figure 4. ・Define for rising of SIOCLK. ・See the figure 4. tSCKH(2) + 2tCYC 4.5~5.5 tSCKH(2)+ (10/3)tCYC tCYC μs 0.03 0.03 thDI(1) Data hold time tdDO(1) tdDO(2) tdDO(3) SO0(P00) SB0(P01) ・Continuous data transmitting and receiving mode (*12) ・Synchronous 8-bit mode (*12) 4.5~5.5 (*12) Output Clock Serial Outpu Input Clock Output delay time (1/3)tCYC +0.05 1tCYC +0.05 (1/3)tCYC +0.05 (*10) This limited value is theoretical figure. Be sure to ensure the margin in accordance with use situation. (*11) When using the serial clock input with continuous data transmitting and receiving mode, lengthen time from the set of the cereal clock of SI0RUN in the state of "H" to the falling of the first cereal clock when it begins to send and receive continuous data more than tSCKHA. (*12) This is defined for falling of SIOCLK and it is defined as time until output change start in open drain output. (See the figure 4) No.A1938-41/47 LV76223A3F 8. μ-Controller Chip SIO1 Characteristics (*13) / Ta=-10deg to +65deg, VSS=0V Parameter Symbol Pins Conditions VDD[V] 4.5-5.5 min 2 Input Clock Output Clock Serial Clock Cycle tSCK(3) Low level pulse-width tSCKL(3) 1 High level pulse-width tSCKH(3) 1 Cycle tSCK(4) Low level pulse-width High level pulse-width tSCKL(4) SCK1(P15) SCK1(P15) See the figure 4. ・At the CMOS output selection ・See the figure 4. 4.5~5.5 unit tCYC 2 tSCK 1/2 1/2 tSCKH(4) Serial Input tsDI(2) Data setup time Limits max typ SI1(P14) SB1(P14) ・Define for rising of SIOCLK. ・See the figure 4. 4.5~5.5 μs 0.03 0.03 thDI(2) Data hold time Serial Output Output delay time tdDO(4) SO1(P16) SB1(P14) ・Define for falling of SIOCLK. ・Define as time until output change start in open drain output. ・See the figure 4. 4.5~5.5 (1/3)tCYC +0.05 (*13) This limited value is theoretical figure. Be sure to ensure the margin in accordance with use situation. 9. μ-Controller Chip Pulse input conditions / Ta=-10deg to +65deg, VSS=0V Parameter High/low level pulse width Symbol Pins Conditions tPIH(1) tPIL(1) INT0,INT1,INT2 tPIH(2) tPIL(2) INT3/P03 (1/1 is selected for noise rejection clock.) tPIH(3) tPIL(3) INT3/P03 (1/32 is selected for noise rejection clock.) tPIH(4) tPIL(4) INT3/P03 (1/128 is selected for noise rejection clock.) tPIL(5) RES# ・Interrupt acceptable ・Timer0, 1 event input enabled ・Interrupt acceptable ・Timer0, 1 event input enabled ・Interrupt acceptable ・Timer0, 1 event input enabled ・Interrupt acceptable ・Timer0, 1 event input enabled Reset acceptable VDD[V] 4.5~5.5 min 1 4.5~5.5 2 4.5~5.5 64 4.5~5.5 256 4.5~5.5 200 VDD[V] 4.5~5.5 min typ Limits max unit tCYC µs 10. μ-Controller Chip AD converter characteristics / Ta=-10deg to +65deg, VSS=0V Parameter Symbol Resolution Absolute precision Conversion time N ET tCAD Analog input voltage range VAIN Analog port input current IAINH IAINL Pins AN3, AN4~AN7 (P04-P07) Conditions (*14) Until result of conversion is ensured after Vref selection 1 bit conversion time = 3 × Tcyc Limits max ±1 0.636 VSS VAIN=VDD VAIN=VSS typ 6 VDD 1 unit bit LSB µs V µA -1 (*14) Absolute precision does not include quantizing error (1/2LSB). No.A1938-42/47 LV76223A3F 11. μ-Controller Chip Sample current dissipation characteristics / Ta=-10deg to +65deg, VSS=0V The sample current dissipation characteristics is the measurement result of Sanyo provided evaluation board when the recommended circuit parameters shown in the sample oscillation circuit characteristics are used externally. The currents through the output transistors and the pull-up MOS transistors are ignored Parameter Current dissipation during basic operation (*15) (*16) Current dissipation in HALT mode (*15) (*16) Current dissipation in HOLD mode (*16) Symbol Pins Conditions VDD[V] 4.5~5.5 min Limits typ max 24 33 unit mA IDDOP(1) CpuVDD ·Reference clock=4.43MHz crystal oscillation System clock: VCO (13.0MHz) ·VCO for OSD operating ·Built-in RC oscillation stops ·At the 1/1 frequency dividing ·OSD, DSL enabled IDDOP(2) CpuVDD ·Reference clock=4.43MHz crystal oscillation ·System clock: reference clock frequency dividing (32kHz) ·VCO for the main clock and for OSD stops ·Built-in RC oscillation stops ·At the 1/2 frequency dividing 4.5~5.5 2.0 3.1 mA IDDHALT(1) CpuVDD ·HALT mode ·Reference clock=4.43MHz crystal oscillation ·System clock: VCO (13.0MHz) ·VCO for OSD stops ·Built-in RC oscillation stops ·OSD, DSL enabled 4.5~5.5 4.8 7.5 mA IDDHALT(2) CpuVDD 4.5~5.5 0.85 1.65 mA IDDHALT(3) CpuVDD 4.5~5.5 0.82 1.54 mA IDDHOLD CpuVDD ·HALT mode ·Reference clock=4.43MHz crystal oscillation ·System clock: Built-in RC oscillation ·VCO for the main clock and for OSD stops ·At the 1/1 frequency dividing ·HALT mode ·Reference clock=4.43MHz crystal oscillation ·System clock: reference clock frequency dividing (32kHz) ·VCO for the main clock and for OSD stops ·Built-in RC oscillation stops ·At the 1/2 frequency dividing ·HOLD mode ·All oscillation stop 4.5~5.5 0.8 1.5 mA (*15) The currents of the output transistors and the internal pull-up MOS transistors are ignored. (*16) 4.43MHz crystal oscillation current is contained. No.A1938-43/47 LV76223A3F 12. μ-Controller Chip Ccrystal Oscillation Circuit and Sample Characteristics/Ta=-10deg to +65deg, VSS=0V The example of the oscillation circuit characteristic is an example of the characteristic when recommended oscillation constant to which it was confirmed to oscillate with stability by the departure pendulum maker is put outside by using the substrate for the oscillation evaluation of characteristics of our specification. Frequency Manufacturer 32.768kHz Epson TOYOCOM MC-306 TmsXtal (*17) Oscillation stabilizing time Operating supply voltage range Recommended circuit parameters Oscillator C1 C2 Rf Rd 18pF 18pF OPEN 390kΩ 4.5~5.5V Typ max 1.0S 1.5S Notes Applicable CL value = 12.5pF SMD-type (*17) The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see the Figure 3). The sample oscillation circuit characteristics may differ applications. For further assistance, please contact with oscillator manufacturer with the following notes in your mind. ・Since the oscillation frequency precision is affected by wiring capacity of the application board, etc., adjust the oscillation frequency on the production board. ・The above oscillation frequency and the operating supply voltage range are based on the operating temperature of -10deg to +65deg. For the use with the temperature outside of the range herein, or in the applications requiring high reliability such as car products, please consult with oscillator manufacturer ・When using the oscillator which is not shown in the sample oscillation circuit characteristics, please consult with Sanyo sales personnel. Since the oscillation circuit characteristics are affected by the noise or wiring capacity because the circuit is designed with low gain in order to reduce the power dissipation, refer to the following notices. ・ The distance between the clock I/O terminal (P07/XT1 terminal P06/XT2 terminal) and external parts should be as short as possible. ・ The capacitors’ VSS should be allocated close to the microcontroller’s CpuGND terminal and be away from other GND. ・ The signal lines with rapid state changes or with large current should be allocated away from the oscillation circuit. XT1 (P07) XT2 (P06) Rf C1 Rd C2 X’tal Figure 1 Recommended oscillation circuit. 0.5VDD Figure 2 The Point of AC timing measure. No.A1938-44/47 LV76223A3F CpuVDD Power supply 0V Reset time TPIL(5) RES# Built-in RC oscillation tmsVCO VCO1 tmsXtal XT1,XT2 XTAL Oscillation enable signal Indifinite Reset Instruction execution Reset time and oscillation stable time Invalid the HOLD release signal Valid the HOLD release signal Built-in RC oscillation tmsVCO VCO1 tmsXtal XT1,XT2 XTAL oscillation enable signal Status H(Enable state) HOLD HALT HOLD release signal and oscillation stable time Figure 3 Oscillation stable time. No.A1938-45/47 LV76223A3F SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transmission time (SIO0 only) tSCK tSCKL tSCKH SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transmission time ( ) tSCKL tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 4 Serial I/O wave. tPIL tPIH Figure 5 Pulse input timing wave. 100Ω FILT 1MΩ + 2.2μF 33000pF - Figure 6 FILT recommended circuit. (Note) Place FILT parts on board as close to the microcontroller as possible. No.A1938-46/47 LV76223A3F CpuVDD2 + - Figure 7 1μF CpuVDD2 recommended circuit. (Note) Place CpuVDD2 parts on board as close to the microcontroller as possible. * Refer to the user’s manual of LC873300 series,when you know the details about μ-Controller (LC87F33C8A). SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2011. Specifications and information herein are subject to change without notice. PS No.A1938-47/47