SANYO LV8760T_11

Ordering number : ENA1157B
LV8760T
Bi-CMOS LSI
Forward/Reverse H-bridge Driver
Overview
The LV8760T is an H-bridge driver that can control four operation modes (forward, reverse, brake, and standby) of a
motor. The low on-resistance, zero standby current, highly efficnet IC is optimal for use in driving brushed DC motors for
office equipment.
Features
• Forward/reverse H-bridge motor driver: 1 channel
• Built-in current limiter circuit
• Built-in thermal protection circuit
• Built-in short-circuit protection function
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Supply voltage
Symbol
Conditions
VM max
VCC max
Output peak current
IO peak
Output continuous current
IO max
Logic input voltage
Allowable power dissipation
tw ≤ 20ms, duty 5%
VIN
Pd max
Mounted on a specified board. *
Ratings
Unit
38
V
6
V
4
A
3
A
-0.3 to VCC+0.3
V
3.3
W
Operating temperature
Topr
-20 to +85
°C
Storage temperature
Tstg
-55 to +150
°C
* Specified circuit board : 90mm×90mm×1.6mm, glass epoxy 2-layer board (2S0P), with backside mounting.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
82411 SY 20110808-S00001/22410 SY 20100222-S00002/42308 MS PC 20080319-S00001 No.A1157-1/11
LV8760T
Allowable Operating Ratings at Ta = 25°C
Parameter
Supply voltage range
Symbol
Conditions
Ratings
Unit
VM
9 to 35
VCC
3 to 5.5
V
V
VREF input voltage
VREF
0 to VCC-1.8
V
Logic input voltage
VIN
0 to VCC
V
Electrical Characteristics at Ta = 25°C, VM = 24V, VCC = 5V, VREF = 1.5V
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
max
General
Standby mode current drain 1
IMst
PS = “L”
1
μA
Standby mode current drain 2
ICCst
PS = “L”
1
μA
Operating mode current drain 1
IM
PS = “H”, IN1 = “H”, with no load
1
1.3
mA
Operating mode current drain 2
ICC
PS = “H”, IN1 = “H”, with no load
3
4
mA
5
5.25
VREG output voltage
VREG
IO = -1mA
4.75
V
VCC low-voltage cutoff voltage
VthVCC
2.5
2.7
2.9
V
Low-voltage hysteresis voltage
VthHIS
120
150
180
mV
Thermal shutdown temperature
TSD
Design guarantee *
155
170
185
°C
ΔTSD
Design guarantee *
Ron1
IO = 3A, sink side
Ron2
IO = -3A, source side
Thermal hysteresis width
°C
40
Output block
Output on resistance
Output leakage current
IOleak
0.2
0.25
Ω
0.32
0.40
Ω
50
μA
VO = 35V
Rising time
tr
10% to 90%
200
500
ns
Falling time
tf
90% to 10%
200
500
ns
tpLH
IN1 or IN2 to OUTA or OUTB (L → H)
550
700
ns
tpHL
IN1 or IN2 to OUTA or OUTB (H → L)
550
700
ns
Step-up voltage
VGH
VM = 24V
28.7
29.8
V
Rising time
tONG
VG = 0.1μF
250
500
μs
140
165
kHz
Input output delay time
Charge pump block
Oscillation frequency
Fcp
28.0
115
Control system input block
Logic pin input current 1
IINL
VIN = 0.8V adaptive pin : PS
5.6
8
10.4
μA
IINH
VIN = 5V adaptive pin : PS
56
80
104
μA
IINL
VIN = 0.8V adaptive pin : IN1, IN2
5.6
8
10.4
μA
IINH
VIN = 5V adaptive pin : IN1, IN2
35
50
65
μA
Logic pin input H-level voltage
VINH
adaptive pin : PS, IN1, IN2
2.0
Logic pin input L-level voltage
VINL
adaptive pin : PS, IN1, IN2
Logic pin input current 2
V
0.8
V
Current limiter block
VREF input current
IREF
Current limit comparator
Vthlim
μA
-0.5
VREF = 1.5V
0.285
0.3
0.315
V
1.6
2.0
2.4
μs
threshold voltage
Blanking time
Tblk
Short-circuit protection block
SCP pin charge current
Comparator threshold voltage
Iscp
Vthscp
SCP = 0V
3.5
5
6.5
μA
0.8
1
1.2
V
* Design guarantee value and no measurement is made.
No.A1157-2/11
LV8760T
Package Dimensions
unit : mm (typ)
3279
TOP VIEW
BOTTOM VIEW
6.5
20
0.5
6.4
4.4
11
10
1
0.65
Exposed Die-Pad
0.15
0.22
(1.0)
0.08
SIDE VIEW
1.2max
(0.33)
SANYO : TSSOP20J(225mil)
Pin Assignment
PGND 1
20 VCC
OUTB 2
19 SCP
OUTB 3
18 VREF
RNF 5
VM 6
VM 7
LV8760T
RNF 4
17 IN2
16 IN1
15 REG5
14 CP1
OUTA 8
13 CP2
OUTA 9
12 VG
PS 10
11 GND
No.A1157-3/11
LV8760T
Pd max – Ta
Allowable power dissipation, Pd max – W
4.0
3.30
*1 With Exposed Die-Pad substrate
*2 Without Exposed Die-Pad
*1
3.0
2.0
1.60
*2
1.72
1.0
0.83
0
– 20
0
20
40
60
80
100
Ambient temperature, Ta – °C
Substrate Specifications (Substrate recommended for operation of LV8760T)
Size
: 90mm × 90mm × 1.6mm (two-layer substrate [2S0P])
Material
: Glass epoxy
Copper wiring density : L1 = 95% / L2 = 95%
L1 : Copper wiring pattern diagram
L2 : Copper wiring pattern diagram
Cautions
1) The data for the case with the Exposed Die-Pad substrate mounted shows the values when 90% or more of the
Exposed Die-Pad is wet.
2) For the set design, employ the derating design with sufficient margin.
Stresses to be derated include the voltage, current, junction temperature, power loss, and mechanical stresses such as
vibration, impact, and tension.
Accordingly, the design must ensure these stresses to be as low or small as possible.
The guideline for ordinary derating is shown below :
(1)Maximum value 80% or less for the voltage rating
(2)Maximum value 80% or less for the current rating
(3)Maximum value 80% or less for the temperature rating
3) After the set design, be sure to verify the design with the actual product.
Confirm the solder joint state and verify also the reliability of solder joint for the Exposed Die-Pad, etc.
Any void or deterioration, if observed in the solder joint of these parts, causes deteriorated thermal conduction,
possibly resulting in thermal destruction of IC.
No.A1157-4/11
GND
VCC
PS
REG5
VG
SCP
Short-circuit
Protection Circuit
Oscillation
circuit
LVS
TSD
Reference
Voltage
Circuit
Charge pump
CP1 CP2
VM
OUTA
OUTB
IN1
IN2
Output control
logic
M
Current
Limiter
Circuit
RNF
+
+
VREF
PGND
LV8760T
Block Diagram
Output preamplifier stage
Output preamplifier stage
+ -
+ -
No.A1157-5/11
LV8760T
Pin Functions
Pin No.
Pin Name
Pin Functtion
16
IN1
Output control signal input pin 1.
17
IN2
Output control signal input pin 2.
Equivalent Circuit
VCC
10kΩ
100kΩ
GND
10
PS
Power save signal input pin.
VCC
50kΩ
10kΩ
10kΩ
50kΩ
GND
18
VREF
Reference voltage input pin for output
VCC
current limit setting.
500Ω
GND
19
SCP
Short-circiut protection circuit, detection
time setting capacitor connection pin.
VCC
500Ω
GND
20
VCC
Power supply connection pin for control
block.
Continued on next page.
No.A1157-6/11
LV8760T
Continued from preceding page.
Pin No.
Pin Name
Pin Functtion
6, 7
VM
Motor power-supply connection pin.
8, 9
OUTA
OUTA output pin.
4, 5
RNF
Current sense resistor connection pin.
2, 3
OUTB
OUTB output pin.
1
PGND
Power ground.
Equivalent Circuit
6 7
REG5
8
9
2
3
500Ω
500Ω
4 5
1
GND
14
CP1
Charge pump capacitor connection pin.
13
CP2
Charge pump capacitor connection pin.
12
VG
Charge pump capacitor connection pin.
14
REG5
6 7
13
12
100Ω
GND
15
REG5
Internal reference voltage output pin.
VM
74kΩ
2kΩ
25kΩ
GND
11
GND
Ground.
No.A1157-7/11
LV8760T
DC Motor Driver
1.DCM output control logic
Contol Input
PS
IN1
Output
IN2
OUTA
OUTB
Mode
L
*
*
OFF
OFF
Standby
H
L
L
OFF
OFF
Output OFF
H
H
L
H
L
CW (forward)
H
L
H
L
H
CCW (reverse)
H
H
H
L
L
Brake
2.Current limit control timing chart
Limit current
Output current
OUTA
OUTB
toff
CHARGE
SLOW
Braking operation time in current limit mode can be set by connecting a capacitor between SCP and GND pins. This
setting is the same as the time setting required to turn off the outputs when an output short-circuit occurs as explained in
the section entitled "Output Short-circuit Protection Function." See "Output Short-circuit Protection Function," for the
settinig procedure.
3.Setting the current limit value
The current limit value of the DCM driver is determined by the VREF voltage and the resistance (RNF) connected
across the RNF and GND pins using the following formula :
Ilimit [A] = (VREF [V] /5) /RNF [Ω])
Assuming VREF = 1.5V, RNF = 0.2Ω, the current limit is :
Ilimit = 1.5V/5/0.2Ω = 1.5A
No.A1157-8/11
LV8760T
Output short-circuit protection function
The LV8760T incorporates an output short-circuit protection circuit. It turns the ouputs off to prevent destruction of the
IC if a problem such as an output pin being shorted to the motor power supply or ground occurs.
1.Protection function operation (Latch method)
The short-circuit protection circuit is activated when it detects the output short-circuit state. If the short-circuit state
continues for the internally preset period (≈ 4μs), the protection circuit turns off the output from which the short-circuit
state has been detected. Then it turns the output on again after a lapse of the timer latch time described later. If the
short-circuit state is still detected, it changes all the outputs to the standby mode and retains the state. The latched state
is released by setting the PS to L.
Output ON
H-bridge
output state
Output ON
Output OFF
Standby state
Threshold voltage
4μs
SCP voltage
Short-circuit
detection state
Short- Release
circuit
Short-circuit
Internal counter
1st counter
start
1st counter 1st counter
stop
start
1st counter
end
2nd counter
start
2nd counter
end
2.How to set the SCP pin constant (timer latch-up setting)
The user can set the time at which the outputs are turned off when a short-circuit occurs by connecting a capacitor
across the SCP and GND pins. The value of the capacitor can be determined by the following formula :
Timer latch-up : Tocp
Tocp ≈ C × V/I [s]
V : Comparator threshold voltage (1V typical)
I : SCP charge current (5μA typical)
When a capacitor with a capacitance of 50pF is connected across the SCP and GND pins, for example, Tscp is
calculated as follows :
Tscp = 50pF × 1V/5μA = 10μs
No.A1157-9/11
LV8760T
Application Circuit Example
(When you use the current limit function)
35kΩ 15kΩ
0.1μF
1
PGND
VCC 20
2
OUTB
SCP 19
3
OUTB
VREF 18
4
RNF
10μF
5
RNF
- +
6
VM
7
VM
8
OUTA
CP2 13
9
OUTA
VG 12
+ -
100pF
0.22Ω
LV8760T
M
IN2 17
Control input
IN1 16
REG5 15
0.1μF
CP1 14
0.1μF
0.1μF
Control input
10 PS
GND 11
Setting the current limit value
When VCC = 5V,
Vref = 1.5V
Ilimit = Vref/5/RNF
= 1.5V/5/0.22Ω = 1.36A
Setting the current limit regeneration time and short-circuit detection time
Tscp ≈ C × V/I
= 100pF × 1V/5μA
= 20μs
PS No.A1157-10/11
LV8760T
(When you do not use the current limit function)
1
PGND
VCC 20
2
OUTB
SCP 19
3
OUTB
VREF 18
4
RNF
5
RNF
6
VM
7
VM
8
OUTA
CP2 13
9
OUTA
VG 12
+ -
100pF
- +
Control input
10 PS
LV8760T
M
IN2 17
Control input
IN1 16
REG5 15
CP1 14
GND 11
Setting at short-circuit state detection time
TSCP≒C·V/I
=100pF·1V/5µA
=20µs
*Do the following processing when you do not use the current limit function.
· It is short between RNF-GND.
· The terminal VREF is hung on suitable potential of VCC or less.
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products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
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semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
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limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
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product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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This catalog provides information as of August, 2011. Specifications and information herein are subject
to change without notice.
PS No.A1157-11/11