Ordering number : EN5228D
Thick-Film Hybrid IC
STK672-050-E
Unipolar Constant-current Chopper (external excitation
PWM) Circuit with Built-in Microstepping Controller
Stepping Motor Driver (sine wave drive)
Output Current 3.0A (no heat sink*)
Overview
The STK672-050-E is a stepping motor driver hybrid IC that uses power MOSFETs in the output stage. It includes a builtin microstepping controller and is based on a unipolar constant-current PWM system. The STK672-050-E supports
application simplification and standardization by providing a built-in 4 phase distribution stepping motor controller. It
supports five excitation methods: 2 phase, 1-2 phase, W1-2 phase, 2W1-2 phase, and 4W1-2 phase excitations, and can
provide control of the basic stepping angle of the stepping motor divided into 1/16 step units. It also allows the motor speed
to be controlled with only a clock signal.
The use of this hybrid IC allows designers to implement systems that provide high motor torques, low vibration levels, low
noise, fast response, and high-efficiency drive.
Applications
• Facsimile stepping motor drive (send and receive)
• Paper feed and optical system stepping motor drive in copiers
• Laser printer drum drive
• Printer carriage stepping motor drive
• X-Y plotter pen drive
• Other stepping motor applications
Note*: Conditions: VCC1 = 24V, IOH = 2.0A, 2W1-2 excitation mode.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
61108HKIM/52004TN(OT)/60200RM(OT)/N2997HA(ID)/11896HA(ID) No.5228-1/19
STK672-050-E
Features
• Can implement stepping motor drive systems simply by providing a DC power supply and a clock pulse generator.
<Control Block Features>
• One of five drive types can be selected with the drive mode settings (M1, M2, and M3)
1) 2 phase excitation drive
2) 1-2 phase excitation drive
3) W1-2 phase excitation drive
4) 2W1-2 phase excitation drive
5) 4W1-2 phase excitation drive
• Provides four freely selectable modes for the vector locus during microstepping drive: circular mode, one inside mode,
and two outside modes.
• Phase retention even if excitation is switched.
• The excitation phase state can be verified in real time using the MO1, MO2, and MOI signal output pins.
• The CLK input counter block can be selected to be one of the following by the high/low setting of the M3 input pin.
1) Rising edge only
2) Both rising and falling edges
• The CLK and RETURN input pins include built-in malfunction prevention circuits for external pulse noise.
• ENABLE and RESET pins provided. These are Schmitt trigger inputs with built-in 20kΩ (typical) pull-up resistors.
• No noise generation due to the difference between the A and B phase time constants during motor hold since external
excitation is used.
• Microstepping operation supported even for small motor currents, since the reference voltage Vref can be set to any
value between 0V and 1/2VCC2.
<Driver Block>
• External excitation PWM drive allows a wide operating supply voltage range (VCC1 = 10 to 45V) to be used.
• Current detection resistor (0.2Ω) built-in the hybrid IC itself.
• Power MOSFETs adopted for low drive loss.
• Provides a motor output drive current of IOH = 3.0A.
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage 1
VCC1 max
No signal
52
V
Maximum supply voltage 2
VCC2 max
No signal
-0.3 to +7.0
V
Logic input pins
-0.3 to +7.0
V
4.0
A
Input voltage
VIN max
Output current
IOH max
Repeated avalanche capacity
Ear max
Allowable power dissipation
Pd max
Operating substrate temperature
Junction temperature
Storage temperature
Tstg
0.5s, 1 pulse, when VCC1 applied.
Load: R = 5Ω, L = 10mH for each phase.
38
mJ
25
W
Tc max
105
°C
Tj max
150
°C
-40 to +125
°C
θc-a = 0
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage 1
VCC1
With signals applied
10 to 45
V
Supply voltage 2
VCC2
With signals applied
5 ± 5%
V
0 to VCC2
V
100 (min)
V
3.0
A
Input voltage
Phase driver withstand voltage
Output current
VIH
VDSS
IOH
Tr1, 2, 3, and 4 (the A, A, B, and B outputs)
Duty 50%
No.5228-2/19
STK672-050-E
Electrical Characteristics at Tc = 25°C, VCC1 = 24V, VCC2 = 5V
Parameters
Symbols
Rating
Conditions
min
Control supply current
ICC
Output saturation voltage
Vsat
Average output current
Ioave
FET diode forward voltage
Vdf
unit
typ
max
Pin 7, with ENABLE pin held low.
4.5
15
mA
RL = 7.5Ω (I ≈ 3A)
1.4
2.6
V
0.50
0.55
A
1.2
1.8
V
Load: R = 3.5Ω / L = 3.8mH
For each phase, Vref ≈ 0.6V
0.45
If = 1A
[Control Inputs]
Input voltage
Input current
VIH
Except for the Vref pin
VIL
Except for the Vref pin
1
V
IIH
Except for the Vref pin
0
1
10
μA
IIL
Except for the Vref pin
125
250
510
μA
4
V
[Vref Input Pin]
Input voltage
VI
Pin 8
Input current
II
Pin 8
0
2.5
V
μA
1
[Control Outputs]
VOH
I = –3mA, pins MOI, MO1, MO2
VOL
I = +3mA, pins MOI, MO1, MO2
2W1-2, W1-2, 1-2
Vref
θ = 1/8
100
%
2W1-2, W1-2
Vref
θ = 2/8
92
%
2W1-2
Vref
θ = 3/8
83
%
2W1-2, W1-2, 1-2
Vref
θ = 4/8
71
%
2W1-2
Vref
θ = 5/8
55
%
2W1-2, W1-2
Vref
θ = 6/8
40
%
2W1-2
Vref
θ = 7/8
2
Vref
Output voltage
2.4
V
0.4
V
[Current Distribution Ratio (A·B)]
PWM frequency
fc
37
20
%
100
%
47
57
kHz
Note: A constant-voltage power supply must be used.
The design target value is shown for the current distribution ratio.
Package Dimensions
unit:mm (typ)
4164
67.0
9.0
1
(9.0)
1.0
22
2.0
0.5
21 2 = 42
4.0
3.6
16.0
25.5
11.0
5.6
60.0
0.4
2.9
No.5228-3/19
9
SG 22
ENABLE 18
MO2 21
MO1 20
MOI 19
RESET 16
RETURN 17
M3 11
CLK 14
CWB 15
M2 10
M1
RC oscillator
Excitation state monitor
Rise detection
Rise/fall
detection and switching
Excitation mode
control
Reference clock
generation
Phase
advance
counter
13
PWM control
Phase excitation drive
signal generation
Pseudo-sine
wave
generator
Current
distribution
ratio switching
12
7
M5
SUB
–
+
–
+
–
+
–
+
M4
–
+
VCC2
A
6
Vref
8
5
A
2
B
1
B
4
3
PG
STK672-050-E
Internal Block Diagram
ITF02390
No.5228-4/19
STK672-050-E
Test Circuit Diagrams
Vsat
Vdf
VCC2
VCC1
7
14
6
5
9
2
10
1
15Ω
7
Start
A
6
A
5
B
2
B
1
A
A
B
B
STK672-050-E
STK672-050-E
8
Vref=2.5V
V
V
VCC2
4
4
16
+
3
3
A
22
22
ITF02392
ITF02391
IIH, IIL
Ioave, ICC, fc
VCC2
VCC2
VCC1
A
M1
M2
M3
M4
M5
IIH
A
CLK
CWB
IIL
RESET
RETURN
ENABLE
Vref
7
9
11
12
14
6
9
2
13
5
10
14 STK672-050-E
1
15
Vref=1V
5V
16
17
Low when
measuring ICC
18
8 STK672-050-E
0V
0V
VCC2
b a
a
7
Start
10
b
SW1
A
A
B
SW2
B
VCC1
18
8
22
+
16
22
A
ITF02393
ITF02394
When measuring Ioave: With SW1 set to ‘a’, Vref = 0.6V
When measuring fc: With SW1 set to ‘b’, Vref = 0V
When measuring ICC: Set ENABLE low
No.5228-5/19
STK672-050-E
Power-on Reset
The application must perform a power-on reset operation when VCC2 power is first applied to this hybrid IC.
Application circuit that used 2W1-2 phase excitation (microstepping operation) mode.
VCC2=5V
VCC1=10V to 45V
7
VCC2=5V
9
6
10
5
11
2
12
1
A
A
B
+
B
100μF or higher
Two-phase
stepping motor
13
14
15
14
CLK
+
18
ENABLE
1kΩ
RESET
SG
STK672-050-E
3
PG
4
16
RET
17
MOI
19
MO1
20
MO2
21
VCC2=5V
8
Vref
22
ITF02395
Setting the Motor Current
The motor current IOH is set by the Vref voltage on the hybrid IC pin 8. The following formula gives the relationship
between IOH and Vref.
IOH = 1 × Vref/Rs, Rs: The hybrid IC internal current detection resistor (0.2Ω ±3%)
3
Applications can use motor currents from the current (0.05 to 0.1A) set by the duty of the frequency set by the oscillator
up to the limit of the allowable operating range, IOH = 3.0A
IOL
IOH
Ioave
0A
Motor current waveform
A12408
Function Table
M2
M1
M3
0
0
1
1
0
1
0
1
Phase switching clock edge timing
1
2 phase excitation
1-2 phase excitation
W1-2 phase excitation
2W1-2 phase excitation
Rising edge only
0
1-2 phase excitation
W1-2 phase excitation
2W1-2 phase excitation
4W1-2 phase excitation
Rising and falling edges
Forward
Reverse
ENABLE
Motor current is cut off when low
0
1
RESET
Active low
CWB
A
A
B
B
MO1
1
0
0
1
MO2
0
0
1
1
No.5228-6/19
STK672-050-E
Printed Circuit Board Design Recommendations
This hybrid IC has two grounds, the PG pins (pins 3 and 4) and the SG pin (pin 22). These are connected internally in
the hybrid IC.
Two power supplies are required: a motor drive supply and a 5V supply for the hybrid IC itself. If the ground
connections for these supplies are not good, the motor current waveforms may become unstable, motor noise may
increase, and vibration levels may increase. Use appropriate wiring for these grounds. Here we present two methods for
implementing these ground connections.
If the grounds for the motor drive supply and the hybrid IC 5V supply are connected in the immediate vicinity of the
power supplies:
• If PG and SG are shorted at the power supply, connect only the PG line to pins 3 and 4 on the hybrid IC. Also, be sure
that no problems occur due to voltage drops due to common impedances. In the specifications, this must be VCC2
±5%.
• The current waveforms will be more stable if the Vref ground is connected to pin 22.
• For initial values, use 470μF or over for C1 and 10μF or over for C2.
Locate C1 as close to the hybrid IC as possible, and the capacitor ground line must be as short as possible.
Stepping motor
+
STK672-050-E
Motor
drive
power -supply PG
C1
+
470μF or over
3
PG
4
+
7 VCC2
-SG
Oscillator
circuit
(CLK)
C2
10μF
or over
5V
power
supply
+
8 Vref
14
CLK
22
SG
ITF02396
If the grounds for the motor drive supply and the hybrid IC 5V supply are separated:
• Insert a capacitor (C1) of 100μF or over as close as possible to the hybrid IC. The capacitor ground line must be as
short as possible.
The capacitor C2 may be included if necessary. Its ground line should also be as short as possible.
Stepping motor
+
STK672-050-E
Motor
drive
power -supply PG
C1
+
470μF or over
Separation
3
PG
4
+
7 VCC2
-SG
Oscillator
circuit
(CLK)
C2
10μF
or over
5V
power
supply
+
8 Vref
14
CLK
22
SG
ITF02397
No.5228-7/19
STK672-050-E
Functional Description
External Excitation Chopper Drive Block Description
VCC1
M4
IOFF
M5
Enable φA (control signal)
ION
Current
divider
L2
L1
φA
φA
Vref
A=1
CR
oscillator
Divider
800kHz
45kHz
S
Q Latch circuit
D1
MOSFET
R
–
Noise
filter
+
AND
Rs
ITF02398
Driver Block Basic Circuit Structure
Since this hybrid IC adopts an external excitation method, no external oscillator circuit is required.
When a high level is input to φA in the basic driver block circuit shown in the figure and the MOSFET is turned on, the
comparator + input will go low and the comparator output will go low. Since a set signal with the PWM period will be
input, the Q output will go high, and the MOSFET will be turned on as its initial value.
The current ION flowing in the MOSFET passes through L1 and generates a potential difference in Rs. Then, when the
Rs potential and the Vref potential become the same, the comparator output will invert, and the reset signal Q output
will invert to the low level. Then, the MOSFET will be turned off and the energy stored in L1 will be induced in L2 and
the current IOFF will be regenerated to the power supply. This state will be maintained until the time when an input to
the latch circuit set pin occurs.
In this manner, the Q output is turned off and on repeatedly by the reset and set signals, thus implementing constant
current control. The resistor and capacitor on the comparator input are spike removal circuit elements and synchronize
with the PWM frequency. Since this hybrid IC uses a fixed frequency due to the external excitation method and at the
same time also adopts a synchronized PWM technique, it can suppress the noise associated with holding a position
when the motor is locked.
Input Pin Functions
Pin No.
Symbol
14
CLK
Phase switching clock
Function
Built-in pull-up resistor CMOS Schmitt trigger input
Pin circuit type
15
CWB
Rotation direction setting (CW/CCW)
Built-in pull-up resistor CMOS Schmitt trigger input
17
RETURN
Forced phase origin return
Built-in pull-up resistor CMOS Schmitt trigger input
18
ENABLE
Output cutoff
Built-in pull-up resistor CMOS Schmitt trigger input
9, 10, 11
M1, M2, M3
Excitation mode setting
Built-in pull-up resistor CMOS Schmitt trigger input
12, 13
M4, M5
Vector locus setting
Built-in pull-up resistor CMOS Schmitt trigger input
16
RESET
System reset
Built-in pull-up resistor CMOS Schmitt trigger input
8
Vref
Current setting
Operational amplifier input
No.5228-8/19
STK672-050-E
Input Signal Functions and Timing
• CLK (phase switching clock)
1) Input frequency range: DC to 50kHz
2) Minimum pulse width: 10μs
3) Duty: 40 to 60% (However, the minimum pulse width takes precedence when M3 is high.)
4) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure
5) Built-in multi-stage noise rejection circuit
6) Function:
- When M3 is high or open: The phase excited (driven) is advanced one step on each CLK rising edge.
- When M3 is low: The phase is advanced one step by both rising and falling edges, for a total of two steps per cycle.
CLK Input Acquisition Timing (M3 = Low)
CLK input
System clock
Phase excitation counter clock
Excitation counter up/down
Control output timing
Control output switching timing
A06850
• CWB (Method for setting the rotation direction)
1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure
2) Function:
- When CWB is low: The motor turns in the clockwise direction.
- When CWB is high: The motor turns in the counterclockwise direction.
3) Notes: When M3 is low, the CWB input must not be changed for about 6.25μs before or after a rising or falling
edge on the CLK input.
• RETURN (Forcible return to the origin for the currently excited phase)
1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure
2) Built-in noise rejection circuit
3) Notes: The currently excited (driven) phase can be forcibly moved to the origin by switching this input from low to
high. Normally, if this input is unused, it must be left open or connected to VCC2.
• ENABLE (Controls the on/off state of the A, A, B, and B excitation drive outputs and selects either operating or hold
as the internal state of this hybrid IC.)
1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure
2) Function:
- When ENABLE is high or open: Normal operating state
- When ENABLE is low: This hybrid IC goes to the hold state and excitation drive output (motor current) is
forcibly turned off. In this mode, the hybrid IC system clock is stopped and no inputs
other than the reset input have any effect on the hybrid IC state.
No.5228-9/19
STK672-050-E
• M1, M2, and M3 (Excitation mode and CLK input edge timing selection)
1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure
2) Function:
M2
M1
M3
0
0
1
1
0
1
0
1
Phase switching clock edge timing
1
2 phase excitation
1-2 phase excitation
W1-2 phase excitation
2W1-2 phase excitation
Rising edge only
0
1-2 phase excitation
W1-2 phase excitation
2W1-2 phase excitation
4W1-2 phase excitation
Rising and falling edges
3) Valid mode setting timing: Applications must not change the mode in the period 5μs before or after a CLK signal
rising or falling edge.
Mode Setting Acquisition Timing
CLK input
System clock
Mode setting
M1 to M3
Mode switching clock
Mode switching timing
Hybrid IC internal setting state
Phase excitation clock
Excitation counter up/down
A06851
• M4 and M5 (Microstepping mode rotation vector locus setting)
M4
1
0
1
Phase B
M5
1
0
0
1
Mode
Circular
1
2
3
See page 10 for details on the current division ratio.
1
0
2
Circular
3
Phase A
ITF02399
• RESET (Resets all parts of the system.)
1) Pin circuit type: Built-in pull-up resistor (20kΩ, typical) CMOS Schmitt trigger structure
2) Function:
- All circuit states are set to their initial values by setting the RESET pin low. (Note that the pulse width must be
at least 10μs.)
At this time, the A and B phases are set to their origin, regardless of the excitation mode. The output current
goes to about 71% after the reset is released.
3) Notes: When power is first applied to this hybrid IC, Vref must be established by applying a reset. Applications
must apply a power on reset when the VCC2 power supply is first applied.
• Vref (Sets the current level used as the reference for constant-current detection.)
1) Pin circuit type: Analog input structure
2) Function:
- Constant-current control can be applied to the motor excitation current at 100% of the rated current by applying a
voltage less than the control system power supply voltage VCC2 minus 2.5V.
- Applications can apply constant-current control proportional to the Vref voltage, with this value of 2.5V as the
upper limit.
No.5228-10/19
STK672-050-E
Output Pin Functions
Pin No.
Symbol
Function
Pin circuit type
19
MOI
Phase excitation origin monitor
Standard CMOS structure
20, 21
MO1, MO2
Phase excitation state monitor
Standard CMOS structure
Output Signal Functions and Timing
• A, A, B, and B (Motor phase excitation outputs)
1) Function:
- In the 4 phase and 2 phase excitation modes, a 3.75μs (typical) interval is set up between the A and A and B and
B output signal transition times.
• MO1, MO2, and MOI (Phase excitation state monitors)
1) Pin circuit type: Standard CMOS structure
1) Function:
- Output of the current phase excitation output state.
Phase coordinate
Phase A
Phase B
Phase A
Phase B
MO1
1
0
0
1
MO2
0
1
0
1
MOI outputs a 0 when each phase is at the origin, and outputs a 1 otherwise.
• Current division ratios set by M3, M4, and M5 ········· Values provided for reference purposes.
Mode
Setting
M3 = 0
M3 = 1
2W1-2
2W1-2
ratio
1
2
3
M4 = 1
M4 = 0
M4 = 1
M4 = 1
M5 = 1
M5 = 0
M5 = 0
M5 = 1
14
15
15
13
20
25
23
19
31
34
33
28
40
44
42
39
48
51
49
45
2W1-2
55
62
57
54
65
69
65
62
2W1-2
71
77
71
69
77
82
77
74
Current
division
Circular
4W1-2
2W1-2
2W1-2
2W1-2
83
88
85
82
88
92
89
85
92
95
95
92
97
98
98
94
100
100
100
100
Units
Number of steps
1/16
1/8
2/16
3/16
2/8
4/16
3/8
6/16
4/8
8/16
5/16
7/16
%
9/16
5/8
10/16
6/8
12/16
11/16
13/16
7/8
14/16
[Load conditions]
VCC1 = 24V, VCC2 = 5V, R/L = 3.5/3.8mH
No.5228-11/19
STK672-050-E
Phase States During Excitation Switching
• Excitation phases before and after excitation mode switching <clockwise direction>
2W1-2 phase → 1-2 phase
2W1-2 phase → 2 phase
A
0
3
28
27
25
28
B 24
8 B
5
8 B
12
20
12
16
9
11
12
20
17
19
A
0
4
28
26
6
28
4
B 24
B 24
8 B
12
28 0 4
24
31
3
5
30 0 2
28
4
26
6
24
22
8
20
10
18
12
16 14
25
B
8 B
8
23
10
12
B
9
11
19
14
13
17
15
A
1-2 phase → W1-2 phase
A
0
7
21
A
1-2 phase → 2 phase
1
27
6
16
A
1-2 phase → 2W1-2 phase
A
A
30
2
1
29
4
28
B 24
29
4
18
14
18 16
2
20
12
W1-2 phase → 2W1-2 phase
A
20
12
16
22
10
20
A
0
30
26
A
W1-2 phase → 1-2 phase
2
28
22
A
30 31 0 1 2
3
29
4
28
5
27
30 0 2
26
6
28
4
25
26
7
6
B 24
24
8
8 B
22
10
23
20
9
1816 1412
22
10
11
21
20
12
13
19
18 17 161514
A
W1-2 phase → 2 phase
20
15
16
16
A
30
4
28 0 4
8
24
4
B 24
20
A
31
1
2W1-2 phase → W1-2 phase
28
4
20
12
5
0
26
28
B
8 B
20
22
6
4
25
B
12
16
B
B
8
20
12
16
10
9
21
12
20
28 0 4
24
18
16
13
14
17
A
A
A
2 phase → W1-2 phase
2 phase → 1-2 phase
A
0
2 phase → 2W1-2 phase
A
A
30
29
5
6
B 24
28
4
20
12
B
8 B
22
28
4
20
12
28
4
20
12
B
B
B
21
14
16
A
A
13
17
A
Excitation phase according to the first clock input pulse after changing the excitation mode setting (M1 and M2)
Excitation phase immediately before setting the excitation mode
A12412
No.5228-12/19
STK672-050-E
• Excitation phases before and after excitation mode switching <counterclockwise direction>
2W1-2 phase → 1-2 phase
2W1-2 phase → 2 phase
31
A
0
28
2W1-2 phase → W1-2 phase
A
0 1
29
4
5
28
4
7
B 24
25
B 24
8 B
20
23
28 0 4
8
24
16
21
20
15
16
12
13
1716
A
A
A
W1-2 phase → 1-2 phase
W1-2 phase → 2 phase
A
0
30
8 B
9
12
20
12
30
6
28
8 B
20
12
16
12
22
22
A
5
25
8 B
10
23
14
13
17
15
A
1-2 phase → 2W1-2 phase
A
30
30
2
3
4
26
4
28
B
20
8 B
12
22
B
9
11
19
A
28
7
21
1-2 phase → W1-2 phase
A
0
B 24
3
A
1-2 phase → 2 phase
1
30 0 2
28
4
26
6
24
22
8
20
10
18
12
16 14
B
8
31
27
12
18 16
14
29
6
20
16
A
4
28 0 4
24
26
B 24
4
B 24
W1-2 phase → 2W1-2 phase
A
0 2
28
20
A
30 31 0 1 2
3
29
4
28
5
27
30 0 2
26
6
28
4
25
26
7
6
B 24
24
8
8 B
22
10
23
20
9
1816 1412
22
10
11
21
20
12
13
19
18 17 161514
20
16
27
6
28 0 4
24
28 0 4
24
B
B
12
B
8
20
12
16
23
10
7
11
12
20
19
14
18
16
A
15
A
A
2 phase → W1-2 phase
2 phase →1-2 phase
A
0
2 phase → 2W1-2 phase
A
A
2
3
27
B 24
26
4
28
20
12
B
8 B
28
4
20
12
B
B
10
28
4
20
12
B
11
16
A
19
18
A
A
A12413
No.5228-13/19
STK672-050-E
Excitation Time and Timing Charts
• CLK rising edge operation
2 Phase Excitation Timing Chart (M3 = 1)
1-2 Phase Excitation Timing Chart (M3 = 1)
1
M1 0
M1 0
M2 0
M2 0
M3 0
RESET
CWB
CWB
CLK
CLK
A
A
B
B
A
A
B
B
MO1
MO1
MO2
MO2
MOI
MOI
100%
100%
71%
71%
Vref A
100%
71%
Comparator reference voltage
Comparator reference voltage
RESET
MOSFET gate signal
1
M3 0
MOSFET gate signal
1
Vref A
100%
71%
Vref B
Vref B
W1-2 Phase Excitation Timing Chart (M3 = 1)
2W1-2 Phase Excitation Timing Chart (M3 = 1)
1
M1 0
M1 0
1
1
M2 0
M2 0
RESET
RESET
CWB
CWB
CLK
CLK
MOSFET gate signal
1
M3 0
MOSFET gate signal
1
M3 0
A
A
B
B
A
B
B
MO1
MO1
MO2
MO2
MOI
MOI
100%
92%
100%
92%
83%
71%
40%
Vref A
100%
92%
71%
40%
Comparator reference voltage
71%
Comparator reference voltage
A
55%
40%
20%
Vref A
100%
92%
83%
71%
55%
40%
20%
Vref B
Vref B
ITF02400
No.5228-14/19
STK672-050-E
• CLK rising and falling edge operation
1-2 Phase Excitation Timing Chart (M3 = 0)
W1-2 Phase Excitation Timing Chart (M3 = 0)
1
M1 0
M2 0
M2 0
M3 0
M3 0
RESET
CWB
CWB
CLK
CLK
A
A
B
B
A
A
B
B
MO1
MO1
MO2
MO2
MOI
MOI
100%
100%
92%
71%
71%
Vref A
100%
71%
Comparator reference voltage
Comparator reference voltage
RESET
MOSFET gate signal
0
MOSFET gate signal
M1
Vref B
40%
Vref A
100%
92%
71%
40%
Vref B
2W1-2 Phase Excitation Timing Chart (M3 = 0)
4W1-2 Phase Excitation Timing Chart (M3 = 0)
1
M1 0
M1 0
1
1
M3 0
M3 0
RESET
RESET
CWB
CWB
CLK
CLK
MOSFET gate signal
M2 0
MOSFET gate signal
M2 0
A
A
B
B
A
B
B
MO1
MO1
MO2
MO2
MOI
MOI
55%
40%
20%
Vref A
100%
92%
83%
71%
55%
40%
20%
Vref B
Comparator reference voltage
100%
92%
83%
71%
Comparator reference voltage
A
100%
97%
92%
88%
83%
77%
71%
65%
55%
48%
40%
31%
20%
14%
Vref A
100%
97%
92%
88%
83%
77%
71%
65%
55%
48%
40%
31%
20%
14%
Vref B
ITF02401
No.5228-15/19
STK672-050-E
Thermal Design
<Hybrid IC Average Internal Power Loss Pd>
The main elements internal to this hybrid IC with large average power losses are the current control devices, the
regenerative current diodes, and the current detection resistor. Since sine wave drive is used, the average power loss
during microstepping drive can be approximated by applying a waveform factor of 0.64 to the square wave loss during
2 phase excitation.
The losses in the various excitation modes are as follows.
2 phase excitation
·fclock
I
Pd2EX = (Vsat+Vdf) · fclock · IOH · t2 + OH
· (Vsat · t1+Vdf · t3)
2
2
1-2 phase excitation
Pd1-2EX = 0.64 · {(Vsat+Vdf) ·
·fclock
I
fclock
· IOH · t2 + OH
· (Vsat · t1+Vdf · t3)}
4
4
·fclock
I
fclock
·IOH · t2 + OH
· (Vsat · t1+Vdf · t3)}
8
8
W1-2 phase excitation PdW1-2EX = 0.64 · {(Vsat+Vdf) ·
·fclock
I
2W1-2 phase excitation Pd2W1-2EX = 0.64 · {(Vsat+Vdf) · fclock ·IOH · t2 + OH
· (Vsat · t1+Vdf · t3)}
16
16
4W1-2 phase excitation Pd4W1-2EX = 0.64 · {(Vsat+Vdf) ·
I OH ·fclock
fclock
·IOH · t2 +
· (Vsat · t1+Vdf · t3)}
16
16
Here, t1 and t3 can be determined from the same formulas for all excitation methods.
t1 =
VCC 1 + 0.48
t3 = − L · n (
)
R
I OH ·R + VCC 1 + 0.48
−L
· n (1 – R + 0.48 · IOH)
R + 0.48
VCC 1
However, the formula for t2 differs with the excitation method.
2 phase excitation
t2 =
W1-2 phase excitation t2 =
2
fclock
– (t1+t3)
1-2 phase excitation
7
– t1
fclock
3
fclock
t2 =
2W1-2 phase excitation
4W1-2 phase excitation
t2 =
– t1
15
– t1
fclock
IOH
t3
t1
t2
A12414
Motor Phase Current Model Figure (2 Phase Excitation)
fclock
Vsat
Vdf
IOH
t1
t2
t3
: CLK input frequency (Hz)
: The voltage drop of the power MOSFET and the current detection resistor (V)
: The voltage drop of the body diode and the current detection resistor (V)
: Phase current peak value (A)
: Phase current rise time (s)
VCC1 : Supply voltage applied to the motor (V)
: Constant-current operating time (s)
L
: Motor inductance (H)
: Phase switching current regeneration time (s)
R
: Motor winding resistance (Ω)
No.5228-16/19
STK672-050-E
<Determining the Size of the Hybrid IC Heat Sink>
Determine θc-a for the heat sink from the average power loss determined in the previous item.
Tc max: Hybrid IC substrate temperature (°C)
Tc
max
Ta
θc-a =
[°C/W]
Ta: Application internal temperature (°C)
Pd EX
PdEX: Hybrid IC internal average loss (W)
Determine θc-a from the above formula and then size S (in cm2) of the heat sink from the graphs shown below.
The ambient temperature of the device will vary greatly according to the air flow conditions within the application.
Therefore, always verify that the size of the heat sink is adequate to assure that the Hybrid IC back surface (the
aluminum plate side) will never exceed a Tc max of 105°C, whatever the operating conditions are.
θc-a - Pd
16
12
t
ien
8
40°
C
60
°C
4
50°C
No. Fin 23.0 (°C/W)
0
0
2
4
6
2m
m
10
7
10
12
IC internal average power loss, Pd - W
14
16
Al
pla
te
(fl a
t bl
5
ack
(no
sur
fa
Vertical
standing type
Natural
convection
air cooling
sur
ce
3
fa c
e fi
nis
h)
fi n
ish
)
2
No. Fin 23.0 (°C/W)
1.0
8
θc-a - S
2
Heat sink thermal resistance, θc-a - °C/W
θc-a= Tc max -- Ta (°C/W)
Pd
Tc max=105°C
b
am
ed
nte ure
ara rat
Gu mpe
te
Heat sink thermal resistance, θc-a - °C/W
20
10
2
3
5
7
100
2
Heat sink surface area, S - cm2
ITF02402
3
5
ITF02403
Next we determine the usage conditions with no heat sink by determining the allowable hybrid IC internal average loss
from the thermal resistance of the hybrid IC substrate, namely 18.5°C/W.
For a Tc max of 105°C at an ambient temperature of 50°C
PdEX = 105 - 50 = 2.9W
18.5
For a Tc max of 105°C at an ambient temperature of 40°C
PdEX = 105 - 40 = 3.5W
18.5
This hybrid IC can be used with no heat sink as long as it is used at operating conditions below the losses listed above.
(See ΔTc – Pd curve in the graph on page 19.)
<Hybrid IC internal power element (MOSFET) junction temperature calculation>
The junction temperature, Tj, of each device can be determined from the loss Pds in each transistor and the thermal
resistance θj-c.
Tj = Tc + θj-c × Pds (°C)
Here, we determine Pds, the loss for each transistor, by determining PdEX in each excitation mode.
Pds = PdEX/4
The steady-state thermal resistance θj-c of a power MOSFET is 5°C/W.
No.5228-17/19
STK672-050-E
fc - VCC2
fc - Tc
58
Tc=25°C
VCC2=5V
56
56
54
54
PWM frequency, fc - kHz
PWM frequency, fc - kHz
58
52
50
48
46
44
52
50
48
46
44
42
42
40
40
0
0
0 4.5
5.0
5.5
6.0
Supply voltage, VCC2 - V
0
40
60
80
100
3
5°C
C
25°
Tc=
1
3
2
1
0
0
0
1
2
3
4
5
Phase output current, IOH - A
0
6
Phase output current, IOH - A
2.0A
2.0
1.5A
1.5
1.0A
1.0
0.5A
0.5
2
30
40
ΔTc - PPS
1.0A
1.0
70
60
30
20
10
100
E X .5 A
1-2 = 1
I OH
40
1k
40
ITF02410
80
100
120
ITF02409
IM - VCC1
Test motor: PK264-02B
Tc=25°C, VCC2=5V
Motor common pin current
With one phase held.
1.2
1.0
IO
H=2
0.8
.5 A
IOH =
2.0A
0.6
0.4
IOH=1.0A
0.2
50k
60
Substrate temperature, Tc - °C
1.4
2W
4W 1-2
IO 1-2 EX
H = EX ,
2.0
A
10k
Input PPS - Hz
20
1.6
W1-2EX,
IOH=2.0A
50
A
X 1.5
2E H=
IO
Substrate temperature increase, ΔTc - °C
80
V
2E M =45
V
IO X
H= 1
.5A
50
ITF02408
Test motor: PK264-02B
VCC1=24V
VCC2=5V
100
90
6
ITF02407
Vref=0V
Supply voltage, VCC1 - V
110
5
2.0A
2.0
0
10
Motor COM current, IM - A
20
4
Test motor: PK264-02B
VCC1=24V
VCC2=5V
Vref=0V
0
0
3
IOH - Tc
3.0
Tc=25°C
VCC2=5V
Test motor: PK264-01B
1
FET diode forward voltage, Vdf - V
ITF02406
IOH - VCC1
2.5
Motor output current, IOH - A
4
105
°C
Tc=
25°
C
4
5
Tc=
Phase output current, IOH - A
Output saturation voltage, Vsat - V
VCC2=5V
5
10
Tc=
140
ITF02405
IOH - Vdf
6
VCC2=5V
2
120
Substrate temperature, Tc - °C
Vsat - IOH
6
20
ITF02404
0
10
20
30
Supply voltage, VCC1 - V
40
ITF02411
No.5228-18/19
STK672-050-E
Vref - I
1.6
av
e
1.4
I OL H
IO
1.2
ΔTc - Pd(typ)
90
Substrate temperature increase, ΔTc - °C
Test motor: PK264-02B
Tc=25°C
VCC1=24V
VCC2=5V
In hold mode
lo
Motor current setting voltage, Vref - V
1.8
1.0
0.8
0.6
0.4
0.2
0
80
70
60
50
40
30
20
10
Free standing with no heat sink
0
0
0.5
1.0
1.5
2.0
2.5
Motor output current, IOH, IOL, Ioave - A
3.0
ITF02412
0
1
2
3
4
5
6
Power loss, Pd - W
7
ITF02413
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products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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This catalog provides information as of June, 2008. Specifications and information herein are subject
to change without notice.
PS No.5228-19/19