SC624 LED Light Management Unit Charge Pump, 4 LEDs, Dual LDOs, and SemWireTM Interface POWER MANAGEMENT Features Description The SC624 is a high efficiency charge pump LED driver using Semtech’s proprietary mAhXLifeTM technology. Performance is optimized for use in single-cell Li-ion battery applications. Input supply voltage range — 3.0V to 5.5V Charge pump modes — 1x, 1.5x and 2x Four programmable current sinks with 32 steps from 0.5mA to 25mA Two programmable 200mA low-noise LDO regulators Charge pump frequency — 250kHz SemWireTM single wire interface — up to 75kbit/s Backlight current accuracy ±1.5% typical Backlight current matching ±0.5% typical Programmable fade-in/fade-out for main backlight Automatic sleep mode (LEDs off ) — IQ = 100μA Low shutdown current — 0.1μA (typical) Ultra-thin package — 3mm x 3mm x 0.6mm Lead-free and halogen-free WEEE and RoHS compliant Applications Cellular phone backlighting PDA backlighting Camera I/O and core power The charge pump provides backlight current in conjunction with four matched current sinks. The load and supply conditions determine whether the charge pump operates in 1x, 1.5x, or 2x mode. An optional fading feature that gradually adjusts the backlight current is provided to simplify control software. The SC624 also provides two low-dropout, low-noise linear regulators for powering a camera module or other peripheral circuits. The SC624 uses the proprietary SemWireTM single wire interface. The interface controls all functions of the device, including backlight current and two LDO voltage outputs. The single wire implementation minimizes microcontroller and interface pin counts. In sleep mode, the device reduces quiescent current to 100μA while continuing to monitor the serial interface. The two LDOs can be enabled when the device is in sleep mode. Total current reduces to 0.1μA in shutdown. Typical Application Circuit MAIN BACKLIGHT VBAT CIN 1μF SemWire Interface VOUT VIN COUT 2.2μF SWIF SC624 BYP CBYP 22nF BL1 BL2 BL3 BL4 GREF AGND LDO1 PGND LDO2 C1+ C1C1 1μF C2+ C2- VLDO1 = 2.5V to 3.3V VLDO2 = 1.5V to 1.8V CLDO1 1μF CLDO2 1μF C2 1μF US Patents: 6,504,422; 6,794,926 October 20, 2009 © 2009 Semtech Corporation 1 SC624 C2- VIN C1+ C2+ VOUT Ordering Information C1- Pin Configuration 20 19 18 17 16 1 15 LDO1 TOP VIEW PGND 2 14 LDO2 NC 3 13 BYP BL1 4 12 NC BL2 5 11 SWIF 6 7 8 9 10 BL3 BL4 AGND GREF NC T Device Package SC624ULTRT(1)(2) MLPQ-UT-20 3×3 SC624EVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant, and halogen-free. MLPQ-UT-20; 3x3, 20 LEAD θJA = 35°C/W Marking Information 624 yyww xxxx yyww = Date Code xxxx = Semtech Lot No. 2 SC624 Absolute Maximum Ratings Recommended Operating Conditions VIN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 Ambient Temperature Range (°C) . . . . . . . . -40 < TA < +85 VOUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 VIN (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 < VIN < 5.5 C1+, C2+ (V) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VOUT + 0.3) VOUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 < VOUT < 5.25 Pin Voltage — All Other Pins (V) . . . . . . . . . -0.3 to (VIN + 0.3) Voltage Difference between any two LEDs (V) . . . . . . < 1.2 VOUT Short Circuit Duration . . . . . . . . . . . . . . . . Continuous VLDO1, VLDO2 Short Circuit Duration. . . . . . . Continuous ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal Information Thermal Resistance, Junction to Ambient(2) (°C/W) . . . . 35 Maximum Junction Temperature (°C) . . . . . . . . . . . . . . +150 Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150 Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . +260 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless otherwise noted, TA = +25°C for Typ, -40ºC to +85°C for Min and Max, TJ(MAX) = 125ºC, VIN = 3.0V to 4.2V, CIN= C1= C2= 2.2μF, COUT = 4.7μF (ESR = 0.03Ω), ΔVF ≤ 1.2V(1) Parameter Symbol Conditions IQ(OFF) Min Typ Max Units Shutdown, VIN = 4.2V 0.1 2 μA Sleep (LDOs off ), SWIF = VIN 100 160 Sleep (LDOs on), SWIF = VIN, VIN > (VLDO + 300mV), ILDO < 200mA 220 340 Charge pump in 1x mode, 4 backlights on 3.8 4.65 Charge pump in 1.5x mode, 4 backlights on 4.6 5.85 Charge pump in 2x mode, 4 backlights on 4.6 5.85 VOUT pin shorted to GND 300 mA 160 °C Supply Specifications Shutdown Current Total Quiescent Current IQ μA mA Fault Protection Output Short Circuit Current Limit Over-Temperature IOUT(SC) TOTP 3 SC624 Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units VOVP VOUT pin open circuit, VOUT = VOVP rising threshold 5.3 5.7 6.0 V VUVLO Decreasing VIN Fault Protection (continued) Charge Pump Over-Voltage Protection 2.4 V 300 mV Undervoltage Lockout VUVLO-HYS Charge Pump Electrical Specifications Maximum Total Output Current IOUT(MAX) VIN > 3.4V, sum of all active LED currents, VOUT(MAX) = 4.2V 100 IBL Nominal setting for BL1 thru BL4 0.5 Backlight Current Accuracy IBL_ACC VIN = 3.7V, IBL = 12mA, TA = 25°C -8 Backlight Current Matching IBL-BL VIN = 3.7V, IBL = 12mA(2) -3.5 1x Mode to 1.5x Mode Falling Transition Voltage V TRANS1x IOUT = 40mA, IBLn = 10mA, VOUT = 3.2V 3.27 V 1.5x Mode to 1x Mode Hysteresis VHYST1x IOUT = 40mA, IBLn = 10mA, VOUT = 3.2V 250 mV 1.5x Mode to 2x Mode Falling Transition Voltage V TRANS1.5x IOUT = 40mA, IBLn = 10mA, VOUT = 4.0V(3) 2.92 V 2x Mode to 1.5x Mode Hysteresis VHYST1.5x IOUT = 40mA, IBLn = 10mA, VOUT = 4.0V(3) 300 mV Current Sink Off-State Leakage Current IBLn VIN = VBLn = 4.2V 0.1 fPUMP VIN = 3.2V 250 LDO1 Voltage Setting VLDO1 Range of nominal settings in 100mV increments 2.5 3.3 V LDO2 Voltage Setting VLDO2 Range of nominal settings in 100mV increments 1.5 1.8 V LDO1, LDO2 Output Voltage Accuracy VLDO1, VLDO2 VIN = 3.7V, ILDO = 1mA -3.5 ±3 +3.5 % 2.1 7.2 Backlight Current Setting Pump Frequency mA 25 mA ±1.5 +8 % ±0.5 +3.5 % 1 μA kHz LDO Electrical Specifications LDO1, ILDO1 = 1mA, VOUT = 2.8V Line Regulation ΔVLINE mV LDO2, ILDO2 = 1mA, VOUT = 1.8V 1.3 4.8 4 SC624 Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max Units LDO Electrical Specifications (continued) Load Regulation ΔVLOAD Dropout Voltage(4) VD Current Limit ILIM Power Supply Rejection Ratio 25 VLDO2 = 1.8V, VIN = 3.7V, ILDO2 = 1mA to 100 mA 20 mV ILDO1 = 100mA 100 150 200 mV mA PSRRLDO1 2.5V < VLDO1 < 3V, f < 1kHz, CBYP = 22nF, ILDO1 = 50mA, VIN = 3.7V with 0.5VP-P ripple 50 PSRRLDO2 f < 1kHz, CBYP = 22nF, ILDO2 = 50mA, VIN = 3.7V with 0.5VP-P ripple 60 en-LDO1 LDO1, 10Hz < f < 100kHz, CBYP = 22nF, CLDO = 1μF, ILDO1 = 50 mA, VIN = 3.7V, 2.5V < VLDO1 < 3V 100 en-LDO2 LDO2, 10Hz < f < 100kHz, CBYP = 22nF, CLDO = 1μF, ILDO2 = 50 mA, VIN = 3.7V 50 Output Voltage Noise Minimum Output Capacitor VLDO1 = 3.3V, VIN = 3.7V, ILDO1 = 1mA to 100 mA dB μVRMS CLDO(MIN) 1 μF Digital I/O Electrical Specifications (SWIF) Input High Threshold VIH VIN = 5.5V Input Low Threshold VIL VIN = 3.0V Input High Current IIH VIN = 5.5V Input Low Current IIL VIN = 5.5V SemWire Bit Rate 1.6 V 0.4 V -1 +1 μA -1 +1 μA fSWIF 10 75 kbit/s SemWire Start-up Time(5) tEN 1 ms SemWire Disable Time(6) tDIS 10 ms SemWire Data Latch Delay(7) DDL 5 bit Notes: (1) ΔVF is the voltage difference between any two LEDs. (2) Current matching equals ± [IBL(MAX) - IBL(MIN] / [IBL(MAX) + IBL(MIN)]. (3) Test voltage is VOUT = 4.0V — a relatively extreme LED voltage — to force a transition during test. Typically VOUT = 3.2V for white LEDs. (4) Dropout is defined as (VIN - VLDO1) when VLDO1 drops 100mV from nominal. Dropout does not apply to LDO2 since it has a maximum output voltage of 1.8V. (5) The SemWire start-up time is the minimum period that the SWIF pin must be held high to enable the part before commencing communication. (6) The SemWire disable time is the minimum period that the SWIF pin must be pulled low to shut the part down. (7) The SemWire data latch delay is the maximum duration after communication has ended before the register is updated. 5 SC624 Typical Characteristics Battery Current (4 LEDs) — 25mA Each 160 Battery Current (4 LEDs) — 12mA Each VOUT=3.66V, IOUT=100mA, 25°C 80 73 Battery Current (mA) Battery Current (mA) 150 140 130 120 66 59 52 110 100 4.2 4.0 3.8 3.6 VIN (V) 3.4 3.2 45 4.2 3.0 Backlight Efficiency (4 LEDs) — 25mA Each 100 100 % Efficiency % Efficiency 3.8 3.6 VIN (V) 3.4 3.2 3.0 VOUT=3.50V, IOUT=48mA, 25°C 90 80 70 80 70 60 60 50 4.2 4.0 3.8 3.6 VIN (V) 3.4 3.2 50 4.2 3.0 3.8 3.6 3.4 3.2 3.0 Backlight Efficiency (4 LEDs) — 5.0mA Each VOUT=3.33V, IOUT=20mA, 25°C 100 35 VOUT=3.33V, IOUT=20mA, 25°C % Efficiency 90 30 25 80 70 60 20 15 4.2 4.0 VIN (V) Battery Current (4 LEDs) — 5.0mA Each Battery Current (mA) 4.0 Backlight Efficiency (4 LEDs) — 12mA Each VOUT=3.66V, IOUT=100mA, 25°C 90 40 VOUT=3.50V, IOUT=48mA, 25°C 4.0 3.8 3.6 VIN (V) 3.4 3.2 3.0 50 4.2 4.0 3.8 3.6 VIN (V) 3.4 3.2 3.0 6 SC624 Typical Characteristics (continued) PSRR vs. Frequency (LDO2) PSRR vs. Frequency (LDO1) VIN=3.7V at 25°C, ILDO1=50mA, VLDO1=2.8V 0 -10 -10 -20 -20 PSRR (dB) PSRR (dB) 0 -30 -40 -30 -40 -50 -50 -60 -60 -70 100 10 10000 1000 VIN=3.7V at 25°C, ILDO2=50mA, VLDO2=1.8V -70 10 100 Frequency (Hz) Load Regulation (LDO1) 24 10000 1000 Load Regulation (LDO2) VLDO1=3.3V, VIN=3.7V, 25°C 24 16 VLDO2=1.8V, VIN=3.7V, 25°C 16 Output Voltage Variation (mV) Output Voltage Variation (mV) Frequency (Hz) 8 0 -8 -16 8 0 -8 -16 -24 0 30 60 90 ILDO1(mA) 120 150 -24 0 30 60 90 120 150 ILDO2(mA) 7 SC624 Typical Characteristics (continued) Noise vs Load Current (LDO2) Noise vs Load Current (LDO1) VLDO1=2.8V, VIN=3.7V, 25°C 100 90 80 80 60 Noise (μV) Noise (μV) 100 70 60 50 40 20 0 20 40 60 80 0 100 20 40 60 80 ILDO2 (mA) Line Regulation (LDO1) Line Regulation (LDO2) VLDO1=2.8V, ILDO1=1mA, 25°C 2 1 0 -1 -2 -3 4.2 0 ILDO1 (mA) Output Voltage Variation (mV) Output Voltage Variation (mV) 2 VLDO2=1.8V, VIN=3.7V, 25°C 100 VLDO2=1.8V, ILDO2=1mA, 25°C 1 0 -1 -2 -3 4.0 3.8 3.6 VIN (V) 3.4 3.2 3.0 4.2 4.0 3.8 3.6 VIN (V) 3.4 3.2 3.0 8 SC624 Typical Characteristics (continued) Load Transient Response (LDO1) — Rising Edge Load Transient Response (LDO2) — Rising Edge VIN=3.7V, VLDO1=2.8V, ILDO1=1 to 100mA VIN=3.7V, VLDO2=1.8V, ILDO2=1 to 100mA VLDO1 (50mV/div) VLDO2 (50mV/div) ILDO1 (100mA/div) ILDO2 (100mA/div) Time (20μs/div) Load Transient Response (LDO1) — Falling Edge Time (20μs/div) Load Transient Response (LDO2) — Falling Edge VIN=3.7V, VLDO2=1.8V, ILDO2=100 to 1mA VIN=3.7V, VLDO1=2.8V, ILDO1=100 to 1mA VLDO1 (50mV/div) VLDO2 (50mV/div) ILDO1 (100mA/div) ILDO2 (100mA/div) Time (200μs/div) Time (200μs/div) Output Open Circuit Protection Output Short Circuit Current Limit VOUT=0V, VIN=4.2V, 25°C VIN=3.7V, 25°C VBL1 (500mV/div) VOUT (1V/div) VOUT (2V/div) IOUT (100mA/div) IBL1 (20mA/div) Time (1ms/div) Time (200μs/div) 9 SC624 Pin Descriptions Pin # Pin Name Pin Function 1 C2- 2 PGND 3 NC Unused pin — do not terminate 4 BL1 Current sink output for main backlight LED 1 — leave this pin open if unused 5 BL2 Current sink output for main backlight LED 2 — leave this pin open if unused 6 BL3 Current sink output for main backlight LED 3 — leave this pin open if unused 7 BL4 Current sink output for main backlight LED 4 — leave this pin open if unused 8 AGND Analog ground pin — connect to ground and separate from PGND current 9 GREF Ground reference — connect to ground 10 NC 11 SWIF 12 NC Unused pin — do not terminate 13 BYP Bypass pin for voltage reference — connect with a 22nF capacitor to AGND 14 LDO2 Output of LDO2 — connect with a 1μF capacitor to AGND 15 LDO1 Output of LDO1 — connect with a 1μF capacitor to AGND 16 VOUT Charge pump output — all LED anode pins should be connected to this pin — requires a 2.2μF capacitor to PGND 17 C2+ Positive connection to bucket capacitor 2 — requires a 1μF capacitor connected to C2- 18 C1+ Positive connection to bucket capacitor 1 — requires a 1μF capacitor connected to C1- 19 VIN Battery voltage input — connect with a 1μF capacitor to PGND 20 C1- Negative connection to bucket capacitor 1 — requires a 1μF capacitor connected to C1+ T THERMAL PAD Negative connection to bucket capacitor 2 — requires a 1μF capacitor connected to C2+ Ground pin for high current charge pump Unused pin — do not terminate SemWire single wire interface pin — used to enable/disable the device and to set up all internal registers (refer to Register Map and SemWire Interface sections) Thermal pad for heatsinking purposes — connect to ground plane using multiple vias — not connected internally 10 SC624 Block Diagram VIN SWIF GREF 19 VIN 11 SemWireTM Digital Interface and Logic Control C1+ C1- C2+ C2- 18 20 17 1 VOUT mAhXLifeTM Fractional Charge Pump (1x, 1.5x, 2x) 9 13 NC 10 NC 12 Bandgap Reference Voltage Setting DAC 2 PGND 4 BL1 5 BL2 6 BL3 7 BL4 3 NC 15 LDO1 14 LDO2 VIN LDO1 VIN LDO2 AGND VOUT Oscillator Current Setting DAC BYP 16 8 11 SC624 Applications Information General Description This design is optimized for handheld applications supplied from a single Li-Ion cell and includes the following key features: • • • • A high efficiency fractional charge pump that supplies power to all LEDs Four matched current sinks that control LED backlighting current, with 0.5mA to 25mA per LED Two adjustable LDOs with outputs ranging from 2.5V to 3.3V for LDO1 and 1.5V to 1.8V for LDO2, adjustable in 100mV increments A SemWire single wire interface that provides control of all device functions High Current Fractional Charge Pump The backlight outputs are supported by a high efficiency, high current fractional charge pump output at the VOUT pin. The charge pump multiplies the input voltage by 1, 1.5, or 2 times. The charge pump switches at a fixed frequency of 250kHz in 1.5x and 2x modes and is disabled in 1x mode to save power and improve efficiency. The mode selection circuit automatically selects the 1x, 1.5x or 2x mode based on circuit conditions. Circuit conditions such as low input voltage, high output current, or high LED voltage place a higher demand on the charge pump output. A higher numerical mode may be needed momentarily to maintain regulation at the VOUT pin during intervals of high demand, such as the droop at the VIN pin during a supply voltage transient. The charge pump responds to these momentary high demands, setting the charge pump to the optimum mode (1x, 1.5x or 2x), as needed to deliver the output voltage and load current while optimizing efficiency. Hysteresis is provided to prevent mode toggling. The charge pump requires two bucket capacitors for low ripple operation. One capacitor must be connected between the C1+ and C1- pins and the other must be connected between the C2+ and C2- pins as shown in the typical application circuit diagram. These capacitors should be equal in value, with a minimum capacitance of 1μF to support the charge pump current requirements. The device also requires a 1μF capacitor on the VIN pin and a 2.2μF capacitor on the VOUT pin to minimize noise and support the output drive requirements. Capacitors with X7R or X5R ceramic dielectric are strongly recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. LED Backlight Current Sinks The backlight current is set via the SemWire interface. The current is regulated to one of 32 values between 0.5mA and 25mA. The step size varies depending upon the current setting. Between 0.5mA and 12mA, the step size is 0.5mA. The step size increases to 1mA for settings between 12mA and 15mA and 2mA for settings greater than 15mA. This feature allows finer adjustment for dimming functions in the low current setting range and coarse adjustment at higher current settings where small current changes are not visibly noticeable in LED brightness. All backlight current sinks have matched currents, even when there is variation in the forward voltages (ΔVF ) of the LEDs. A ΔVF of 1.2V is supported when the input voltage is at 3.0V. Higher ΔVF LED mis-match is supported when VIN is higher than 3.0V. All current sink outputs are compared and the lowest output is used for setting the voltage regulation at the VOUT pin. This is done to ensure that sufficient bias exists for all LEDs. The backlight LEDs default to the off state upon powerup. For backlight applications using less than four LEDs, any unused output must be left open and the unused LED driver must remain disabled. When writing to the Backlight Enable Control register, a zero (0) must be written to the corresponding bit of any unused output. 12 SC624 Applications Information (continued) Backlight Quiescent Current The quiescent current required to operate all four backlights is reduced by 1.5mA when backlight current is set to 4.0mA or less. This feature results in higher efficiency under light-load conditions. Further reduction in quiescent current will result from using fewer than four LEDs. Fade-In and Fade-Out Backlight brightness can be set to automatically fade-in when current is set to increase and fade-out when current is set to decrease. When enabled with a new current setting, the current will step through each incremental setting between the old and new values. The result is a visually smooth change in brightness with a rate of fade that can be set to 8, 16, 24, or 32 ms per step. Programmable LDO Outputs Two low dropout (LDO) regulators are provided for camera module I/O and core power. Each LDO has at least 100mA of available load current with ±3.5% accuracy. The minimum current limit is 200mA, so outputs greater than 100mA are possible at somewhat reduced accuracy. A 1μF, low ESR capacitor should be used as a bypass capacitor on each LDO output to reduce noise and ensure stability. In addition, it is recommended that a minimum 22nF capacitor be connected from the BYP pin to ground to minimize noise and achieve optimum power supply rejection. A larger capacitor can be used for this function, but at the expense of increasing turnon time. Capacitors with X7R or X5R ceramic dielectric are strongly recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. Shutdown State The device is disabled when the SWIF pin is low. All registers are reset to default condition when SWIF is low. Sleep Mode consumption by turning off the clock and the charge pump while continuing to monitor the serial interface for commands. Both LDOs can be powered up while in sleep mode. SemWire Single Wire Interface Functions All device functions can be controlled via the SemWire single wire interface. The interface is described in detail in the SemWire Interface section of the datasheet. Protection Features The SC624 provides several protection features to safeguard the device from catastrophic failures. These features include: • • • • • Output Open Circuit Protection Over-Temperature Protection Charge Pump Output Current Limit LDO Current Limit LED Float Detection Output Open Circuit Protection Over-Voltage Protection (OVP) is provided at the VOUT pin to prevent the charge pump from producing an excessively high output voltage. In the event of an open circuit at VOUT, the charge pump runs in open loop and the voltage rises up to the OVP limit. OVP operation is hysteretic, meaning the charge pump will momentarily turn off until VOUT is sufficiently reduced. The maximum OVP threshold is 6.0V, allowing the use of a ceramic output capacitor rated at 6.3V with no fear of over-voltage damage. Over-Temperature Protection The Over-Temperature (OT) protection circuit helps prevent the device from overheating and experiencing a catastrophic failure. When the junction temperature exceeds 160°C, the device goes into thermal shutdown with all outputs disabled until the junction temperature is reduced. All register information is retained during thermal shutdown. When all LEDs are off, sleep mode is activated. This is a reduced current mode that helps minimize overall current 13 SC624 Applications Information (continued) Charge Pump Output Current Limit The device also limits the charge pump current at the VOUT pin (typically 300mA). LDO Current Limit The device limits the output currents of LDO1 and LDO2 to help prevent it from overheating and to protect the loads. The minimum limit is 200mA, so load current greater than the rated 100mA can be used with degraded accuracy and larger dropout without tripping the current limit. LED Float Detection Float detect is a fault detection feature of the LED current sink outputs. If an output is programmed to be enabled and an open circuit fault occurs at any current sink output, that output will be disabled to prevent a sustained output OVP condition from occurring due to the resulting open loop. Float detect ensures device protection but does not ensure optimum performance. Unused LED outputs must be disabled to prevent an open circuit fault from occurring. 14 SC624 Applications Information (continued) • PCB Layout Considerations The layout diagram in Figure 1 illustrates a proper two-layer PCB layout for the SC624 and supporting components. Following fundament al layout rules is critical for achieving the performance specified in the Electrical Characteristics table. The following guidelines are recommended when developing a PCB layout: GND C1+ CLDO1 C2- LDO1 PGND LDO2 SC624 NC Figure 2 — Layer 1 SWIF CBYP NC NC BL2 GREF CLDO2 BYP BL1 BL3 • COUT C2 C2+ C1- C1 VOUT CIN • VOUT VIN GND AGND • VIN • Place all bypass and decoupling capacitors — C1, C2, CIN, COUT, CLDO1, CLDO2, and CBYP as close to the device as possible. All charge pump current passes through VIN, VOUT, and the bucket capacitor connection pins. Ensure that all connections to these pins make use of wide traces so that the resistive drop on each connection is minimized. The thermal pad should be connected to the ground plane using multiple vias to ensure proper thermal connection for optimal heat transfer. BL4 • • Make all ground connections to a solid ground plane as shown in the example layout (Figure 3). If a ground layer is not feasible, the following groupings should be connected: PGND — CIN, COUT AGND — Ground Pad, CLDO1, CLDO2, CBYP If no ground plane is available, PGND and AGND should be routed back to the negative battery terminal as separate signals using thick traces. Joining the two ground returns at the terminal prevents large pulsed return currents from mixing with the low-noise return currents of the LDOs. Both LDO output traces should be made as wide as possible to minimize resistive losses. Figure 1 — Recommended PCB Layout Figure 3 — Layer 2 15 SC624 Register Map Address D7 D6 D5 D4 D3 D2 D1 D0 Reset Value Description 0x00 FADE_1 FADE_0 FADE_EN BL_4 BL_3 BL_2 BL_1 BL_0 0x00 Backlight Current Control 0x01 0(1) 0(1) 0(1) 0(1) BLEN_4 BLEN_3 BLEN_2 BLEN_1 0x00 Backlight Enable Control 0x03 0(1) LDO2_2 LDO2_1 LDO2_0 LDO1_3 LDO1_2 LDO1_1 LDO1_0 0x00 LDO Control Notes: (1) 0 = always write a 0 to these bits Register and Bit Definitions Backlight Current Control Register (0x00) This register is used to set the currents for the backlight current sinks, as well as to enable and set the fade step rate. These current sinks need to be enabled in the Backlight Enable Control register to be active. FADE[1:0] These bits are used to set the rise/fall rate between two backlight currents as follows: FADE_1 FADE_0 Fade Feature Rise/Fall Rate (ms/step) 0 0 32 0 1 24 1 0 16 1 1 8 value to a new value set by bits BL[4:0] at a rate of 8ms to 32ms per step. A new backlight level cannot be written during an ongoing fade operation, but an ongoing fade operation may be cancelled by resetting the fade bit. Clearing the fade bit during an ongoing fade operation changes the backlight current immediately to the value of BL[4:0]. The number of counts to complete a fade operation equals the difference between the old and new backlight values to increment or decrement the BL[4:0] bits. If the fade bit is cleared, the current level will change immediately without the fade delay. The rate of fade may be changed dynamically, even while a fade operation is active, by writing new values to the FADE_1 and FADE_0 bits. The total fade time is determined by the number of steps between old and new backlight values, multiplied by the rate of fade in ms/step. The longest elapsed time for a full scale fade-out of the backlight is nominally 1.024 seconds when the default interval of 32ms is used. The number of steps in changing the backlight current will be equal to the change in binary count of bits BL[4:0]. FADE_EN This bit is used to enable or disable the fade feature. When the fade function is enabled and a new backlight current is set, the backlight current will change from its current 16 SC624 Register and Bit Definitions (continued) BL[4:0] These bits are used to set the current for the backlight current sinks. All enabled backlight current sinks will sink the same current, as shown in Table 1. Table 1 — Backlight Current Control Bits BL_4 BL_3 BL_2 BL_1 BL_0 Backlight Current (mA) 0 0 0 0 0 0.5 0 0 0 0 1 1.0 0 0 0 1 0 1.5 0 0 0 1 1 2.0 0 0 1 0 0 2.5 0 0 1 0 1 3.0 0 0 1 1 0 3.5 0 0 1 1 1 4.0 0 1 0 0 0 4.5 0 1 0 0 1 5 0 1 0 1 0 5.5 0 1 0 1 1 6 0 1 1 0 0 6.5 0 1 1 0 1 7 0 1 1 1 0 7.5 0 1 1 1 1 8 1 0 0 0 0 8.5 1 0 0 0 1 9 1 0 0 1 0 9.5 1 0 0 1 1 10 1 0 1 0 0 10.5 1 0 1 0 1 11 1 0 1 1 0 11.5 1 0 1 1 1 12 1 1 0 0 0 13 1 1 0 0 1 14 1 1 0 1 0 15 1 1 0 1 1 17 1 1 1 0 0 19 1 1 1 0 1 21 1 1 1 1 0 23 1 1 1 1 1 25 BL Enable Control Register (0x01) This register is used to enable the backlight current sinks. BLEN[4:1] These bits are used to enable current sinks (active high, default low). BLEN_4 — Enable bit for backlight BL4 BLEN_3 — Enable bit for backlight BL3 BLEN_2 — Enable bit for backlight BL2 BLEN_1 — Enable bit for backlight BL1 When enabled, the current sinks will carry the current set by the backlight current control bits BL[4:0], as shown in Table 1. 17 SC624 Register and Bit Definitions (continued) LDO Control Register (0x03) This register is used to enable the LDOs and to set their output voltages. LDO2[2:0] These bits are used to set the output voltage of LDO2, as shown in Table 2. LDO1[3:0] These bits set the output voltage of LDO1, as shown in Table 3. Table 3 — LDO1 Control Bits LDO1_3 LDO1_2 LDO1_1 LDO1_0 LDO1 Output Voltage 0 0 0 0 OFF 0 0 0 1 3.3V 0 0 1 0 3.2V 0 0 1 1 3.1V 0 1 0 0 3.0V Table 2 — LDO2 Control Bits LDO2_2 LDO2_1 LDO2_0 LDO2 Output Voltage 0 0 0 OFF 0 0 1 1.8V 0 1 0 1.7V 0 1 1 1.6V 0 1 0 1 2.9V 1 0 0 1.5V 0 1 1 0 2.8V OFF 0 1 1 1 2.7V 1 0 0 0 2.6V 1 0 0 1 2.5V 101 through 111 are not used 1010 through 1111 are not used OFF 18 SC624 SemWire Interface Semwire Interface Functions SemWire Communication Protocol and Timing The SWIF pin is a write-only single wire interface. It provides the capability to address up to 32 registers to control device functionality. The protocol for using this interface is described in the following subsections. The following six step communication sequence controls all device functions when the device is enabled. Driving the SWIF Pin The SWIF pin should be driven by a GPIO from the system microcontroller. The output level can be configured as either a push-pull driver (TTL or CMOS levels) or as an open drain driver with an external pull-up resistor. Enabling the Device The SWIF pin must be pulled from low to high for a period of greater than 1ms (tEN) to enable the device into the sleep state. In the sleep state, the device bandgap is active, UVLO monitoring is active, and the serial interface is monitored for communication. Automatic Sleep State If the backlight current sinks are disabled, the device automatically enters the sleep state in order to minimize the current draw from the battery. When in sleep mode, the charge pump and oscillator are both disabled. The LDOs remain on if enabled. Disabling the Device The SWIF pin must be pulled from high to low for a period greater than 10ms (tDIS) in order to shut down the device. In this state the device remains disabled until the SWIF pin is pulled high for a period greater than 1ms. All registers return to the default state. 1. OSC On — The SWIF pin is toggled low for one bit duration and high for one bit duration in order to enable the oscillator. The oscillator is turned off in the sleep state to minimize quiescent current. 2. Sample — The SWIF pin is toggled low for one bit duration and high for one bit duration. During this time, the device samples the bit rate and determines the bit rate at which the register address and data values that follow will arrive. The sample rate is at least 20 times the bit rate ensuring robust communication synchronization. 3. Start — The SWIF pin is pulled low for one bit duration, which starts communication with the target register. 4. Address — The next 5 bits are the address of the target register — MSB first, LSB last. 5. Data — The next 8 bits are the data written to the target register — MSB first, LSB last. 6. Standby — After the last data bit is sent, the SWIF pin is pulled high for 5 bit durations to return the device to standby before another data write can take place. If all LEDs are disabled, the device will go back to sleep mode. NOTE: The bit rate must be set by the host controller to a rate that is between the minimum and maximum frequencies listed in the Electrical Characteristics section. 19 SC624 SemWire Interface (continued) Single Write Operation Device Disabled Device Enabled Into Sleep OSC On Sample Register Address Start A4 A3 A2 A1 5 Resume high Sleep if bits all LEDs Min. are off Data A0 D7 D6 D5 D4 D3 D2 D1 t > tEN Device Disabled when low for tDIS D0 t > DDL t > tDIS Concatenated Write Operation OSC On Sample Register Address Start A4 A3 A2 A1 Data A0 D7 D6 D5 D4 D3 OSC On (Repeated) D2 D1 D0 Sample Start t > DDL To concatenate write operations, repeat Osc On, Sample and Start after the DO bit of the previous sequence as shown. 20 SC624 Outline Drawing — MLPQ-UT-20 3x3 A D PIN 1 INDICATOR (LASER MARK) DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX B E A2 A SEATING PLANE aaa C A A1 A2 b D D1 E E1 e L N aaa bbb .020 .000 - .024 .002 (.006) .006 .008 .010 .114 .118 .122 .061 .067 .071 .114 .118 .122 .061 .067 .071 .016 BSC .012 .016 .020 20 .003 .004 0.50 0.00 - 0.60 0.05 (0.1524) 0.15 0.20 0.25 2.90 3.00 3.10 1.55 1.70 1.80 2.90 3.00 3.10 1.55 1.70 1.80 0.40 BSC 0.30 0.40 0.50 20 0.08 0.10 C A1 D1 e LxN E/2 E1 2 1 N D/2 bxN bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS . 3. DAP is 1.90 x 190mm. 21 SC624 Land Pattern — MLPQ-UT-20 3x3 H R (C) DIMENSIONS K G Y X P Z DIM INCHES MILLIMETERS C G H K P R X Y Z (.114) (2.90) .083 .067 .067 .016 .004 .008 .031 .146 2.10 1.70 1.70 0.40 0.10 0.20 0.80 3.70 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com 22