SEMTECH SC197EVB

SC197
3.5MHz, 500mA Synchronous
Dual Step-Down DC-DC Regulator
POWER MANAGEMENT
Features
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Description
Input Voltage — 2.9V to 5.5V
Output Voltage — 0.8V to 3.3V
Output current capability — 500mA per regulator
Efficiency up to 94%
Programmable output voltages — 15
High light-load efficiency via automatic PSAVE mode
Fast transient response
Oscillator frequency — 3.5MHz
100% duty cycle capability
Quiescent current — 38µA typical per regulator
Shutdown current — 0.1µA typical per regulator
Internal soft-start
Over-voltage protection
Current limit and short circuit protection
Over-temperature protection
Under-voltage lockout
Floating control pin protection
MLPQ-UT18 2.0 x 3.0 x 0.6 (mm) package
Lead-free, halogen-free, and RoHS/WEEE compliant
Applications
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Smart phones and cellular phones
MP3/Personal media players
Personal navigation devices
Digital cameras
Single Li-ion cell or 3 NiMH/NiCd cell devices
Devices with 3.3V or 5V internal power rails
The SC197 contains two identical high efficiency 500mA
step-down regulators designed for use in batterypowered applications. Each regulator includes 15
programmable output voltage settings that can be
selected using the four control pins, eliminating the need
for external feedback resistors. The output voltage can be
fixed to a single setting or dynamically switched between
different levels. Pulling all four control pins low disables
the output.
The SC197 operates at a fixed 3.5MHz switching frequency
in normal PWM (Pulse-Width Modulation) mode. A variable frequency PSAVE (Power Save) mode is used to
optimize efficiency at light loads for each output setting.
Built-in hysteresis prevents chattering between the two
modes.
The SC197 provides several protection features to safeguard the device under stressed conditions. These include
short circuit protection, over-temperature protection,
under-voltage lockout, and soft-start to control in-rush
current. These features, coupled with the small 2.0 x 3.0 x
0.6 (mm) package make the SC197 a versatile device ideal
for step-down regulation in products needing high efficiency and a small PCB footprint.
Typical Application Circuit
VIN
2.9V to 5.5V
INA
CINA
4.7µF
Control Logic
For Output B
January 17, 2011
LXA
LXA
1.0µH
VOUTA
0.8V to 3.3V
OUTA
CTL3A
CTL2A
CTL1A
CTL0A
Control Logic
For Output A
VIN
2.9V to 5.5V
SC197
INB
CINB
4.7µF
COUTA
10µF
GNDA
LXB
LXB
1.0µH
VOUTB
0.8V to 3.3V
OUTB
CTL3B
CTL2B
CTL1B
CTL0B
COUTB
10µF
GNDB
© 2011 Semtech Corporation
SC197
2
OUTB
3
GNDB
4
LXB
5
NC
6
CTL3A
INA
16
TOP VIEW
7
8
9
CTL2B
CTL0A
17
CTL3B
1
18
INB
CTL1A
Ordering Information
CTL2A
Pin Configuration
15
NC
14
LXA
13
GNDA
12
OUTA
11
CTL0B
10
CTL1B
Device
Package
SC197ULTRT(1)(2)
MLPQ-UT18 2 x 3
SC197EVB
Evaluation Board
Notes:
(1) Available in tape and reel only. A reel contains 3,000 devices.
(2) Lead-free packaging only. Device is WEEE and RoHS compliant
and halogen-free.
MLPQ-UT18; 2 x 3, 18 LEAD
θJA = 77°C/W
Table 1 – Output Voltage Settings
Marking Information
197
yw
xxx
197 = SC197
yw = Date code
xxx = lot number
CTL3A/B
CTL2A/B
CTL1A/B
CTL0A/B
VOUTA/B
0
0
0
0
Shutdown
0
0
0
1
0.80
0
0
1
0
1.00
0
0
1
1
1.20
0
1
0
0
1.40
0
1
0
1
1.50
0
1
1
0
1.60
0
1
1
1
1.80
1
0
0
0
1.85
1
0
0
1
1.90
1
0
1
0
2.00
1
0
1
1
2.20
1
1
0
0
2.50
1
1
0
1
2.80
1
1
1
0
3.00
1
1
1
1
3.30
SC197
Absolute Maximum Ratings
Recommended Operating Conditions
INA, INB (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
Ambient Temperature Range (°C). . . . . . . . . . . -40 ≤ TA ≤ +85
LXA, LXB Voltage (V) . . . . . . . . . . . . . . . . . . . . . -1.0 to (VIN +0.5)
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 ≤ VIN ≤ 5.5
Other Pins (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)
Thermal Information
Output Short Circuit to GND. . . . . . . . . . . . . . . . . Continuous
ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5
Thermal Resistance, Junction to Ambient(2) (°C/W) . . . . 7 7
Storage Temperature Range (°C). . . . . . . . . . . . . -65 to +150
Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . . +260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB per JESD51 standards.
Electrical Characteristics
Unless otherwise specified: VIN= 3.6V, CIN= 4.7µF, COUT=10µF, LX=1µH, VOUT =1.8V, TJ(MAX)=125°C, TA= -40 to +85 °C. Typical values are TA=+25 °C.
All specifications are identical for converters A and B.
Parameter
Output Voltage Range
Output Voltage Tolerance
Symbol(1)
Condition
VOUT
VOUT_TOL
IOUT = 200mA
Min
Typ
Max
Units
0.8
3.3 (2)
V
-2.0
2.0
%
PSAVE mode
1.5
Line Regulation
ΔVLINEREG
2.9 ≤ VIN ≤ 5.5V, IOUT = 200mA
0.3
%/V
Load Regulation
ΔVLOADREG
200mA ≤ IOUT ≤ 500mA
-0.4
%
Output Current Capability
IOUT
500
Current Limit Threshold
ILIMIT
800
Foldback Current Limit
IFB_LIM
Under-Voltage Lockout
VUVLO
ILOAD > ILIMIT
mA
1300
150
Rising VIN
mA
2.9
Hysteresis
200
mA
V
mV
Quiescent Current
IQ
No switching, IOUT = 0mA
38
60
µA
Shutdown Current
ISD
VCTL 0-3= 0V
0.1
1.0
µA
LX Leakage Current
ILX
Into LX pin
0.1
1.0
µA
High Side Switch Resistance(3)
RDSON_P
IOUT= 100mA
250
Low Side Switch Resistance(4)
RDSON_N
IOUT= 100mA
350
mΩ
SC197
Electrical Characteristics (continued)
Parameter
Symbol(1)
Condition
Min
Typ
Max
Units
2.8
3.5
4.2
MHz
500
µs
Switching Frequency
fSW
Soft-Start
tSS
VOUT = 90% of final value
100
Thermal Shutdown
TOT
Rising temperature
160
°C
20
°C
Thermal Shutdown Hysteresis
THYST
Logic Inputs - CTL0A, CTL1A, CTL2A, CTL3A, CTL0B, CTL1B, CTL2B, and CTL3B
Input High Voltage
VIH
1.2
Input Low Voltage
VIL
Input High Current
IIH
VCTL 0-3= VIN
Input Low Current
IIL
VCTL 0-3= GND
V
0.4
V
-2.0
5.0
µA
-2.0
2.0
µA
Notes
(1) All symbol references apply equally to A and B devices.
(2) Maximum output voltage is limited to VIN if the input is less than 3.3V.
(3) Measured from INA to LXA or from INB to LXB.
(4) Measured from LXA to GNDA or from LXB to GNDB.
SC197
Typical Characteristics
VIN = 4.0V for VOUT = 3.3V, VIN = 3.6V for all others. CIN = 4.7µF, COUT = 10µF, LX = 1µH, TA = 25°C unless otherwise noted.
Efficiency vs. VOUT (TA = -40°C)
Efficiency vs. IOUT (TA = -40°C)
90
80
3.3V
2.8V
1.8V
95
0.8V
90
3.6V
4.2V
5.0V
Efficiency (%)
70
Efficiency (%)
IOUT = 300mA
100
100
60
85
50
40
80
30
20
75
10
0
70
0.1
1
10
Load Current (mA)
100
0.5
1000
Efficiency (%)
2.5
3.0
3.5
0.8V
60
95
3.6V
4.2V
5.0V
90
Efficiency (%)
3.3V
2.8V
1.8V
70
2.0
VOUT (V)
IOUT = 300mA
100
100
80
1.5
Efficiency vs. VOUT (TA = 25°C)
Efficiency vs. IOUT (TA = 25°C)
90
1.0
85
50
40
80
30
20
75
10
0
0.1
1
10
Load Current (mA)
100
70
1000
0.5
100
3.3V
2.8V
1.8V
Efficiency (%)
70
0.8V
60
2.0
VOUT (V)
2.5
3.0
3.5
IOUT = 300mA
95
3.6V
4.2V
5.0V
90
Efficiency (%)
100
90
1.5
Efficiency vs. VOUT (TA = 85°C)
Efficiency vs. IOUT (TA = 85°C)
80
1.0
85
50
40
80
30
20
75
10
0
0.1
1
10
Load Current (mA)
100
1000
70
0.5
1.0
1.5
2.0
VOUT (V)
2.5
3.0
3.5
SC197
Typical Characteristics (continued)
VIN = 4.0V for VOUT = 3.3V, VIN = 3.6V for all others. CIN = 4.7µF, COUT = 10µF, LX = 1µH, TA = 25°C unless otherwise noted.
Efficiency vs. VIN (VOUT =1.8V)
Frequency vs. Temperature
4.0
IOUT = 300mA
90
IOUT = 200mA
-40°C
89
25°C
88
3.6
3.3V
2.8V
Efficiency (%)
Frequency (MHz)
3.8
1.8V
87
85°C
86
85
3.4
0.8V
84
83
3.2
82
3.0
-50
-30
-10
30
10
Temperature (°C)
50
81
2.5
90
70
VIN = 3.6V
1.86
4
VIN (V)
4.5
5
5.5
5
5.5
IOUT = 200mA
1.84
Output Voltage (V)
1.84
1.82
VOUT (V)
1.82
85°C
25°C
1.80
100
200
300
Load Current (mA)
400
-40°C
85°C
1.78
1.76
0
25°C
1.80
-40°C
1.78
1.76
3.5
Line Regulation (VOUT =1.8V)
Load Regulation (VOUT = 1.8V)
1.86
3
500
2.5
3
3.5
4
VIN (V)
4.5
SC197
Typical Characteristics (continued)
Light Load Switching — VOUT = 1.8V
Light Load Switching — VOUT = 1.0V
IOUT = 10mA
IOUT = 10mA
VOUT (50mV/div)
VOUT (50mV/div)
VLX (2V/div)
VLX (2V/div)
ILX (200mA/div)
0mA —
ILX (200mA/div)
0mA —
Time (400n������
s�����
/div)
Time (400n������
s�����
/div)
Light Load Switching — VOUT = 3.3V
Light Load Switching — VOUT = 2.8V
IOUT = 10mA
IOUT = 10mA
VOUT (50mV/div)
VOUT (50mV/div)
VLX (2V/div)
VLX (2V/div)
ILX (200mA/div)
0mA —
ILX (200mA/div)
0mA —
Time (400n������
s�����
/div)
Time (400n������
s�����
/div)
Heavy Load Switching — VOUT = 1.8V
Heavy Load Switching — VOUT = 1.0V
IOUT = 500mA
IOUT = 500mA
VOUT (50mV/div)
VOUT (50mV/div)
VLX (2.0V/div)
VLX (2V/div)
ILX (500mA/div)
ILX (500mA/div)
0mA —
0mA —
Time (200n������
s�����
/div)
Time (200n������
s�����
/div)
SC197
Typical Characteristics (continued)
Heavy Load Switching — VOUT = 2.8V
Heavy Load Switching — VOUT = 3.3V
IOUT = 500mA
IOUT = 500mA
VOUT (50mV/div)
VOUT (50mV/div)
VLX (2V/div)
VLX (2V/div)
ILX (200mA/div)
ILX (500mA/div)
0mA —
0mA —
Time (200n������
s�����
/div)
Time (200n������
s�����
/div)
Light Load Soft-start
Heavy Load Soft-start
IOUT = 500mA, VOUT = 1.8V
VOUT (1.0V/div)
IOUT = 10mA
Vout (1.0V/div)
IOUT (500mA/div)
IOUT (10mA/div)
VCTL2-0 (5V/div)
VCTL2-0 (5V/div)
ILX (500mA/div)
ILX (500mA/div)
0mA —
0mA —
Time (40�����
s�����
/div)
Load Transient Response — 10 to 100mA
VOUT (100mV/div)
Time (40�����
s�����
/div)
Load Transient Response — 10 to 500mA
VOUT (100mV/div)
ILX (500mA/div)
ILX (500mA/div)
ILOAD (50mA/div)
ILOAD (500mA/div)
0mA —
Time (20�����
s�����
/div)
Time (20�����
s�����
/div)
SC197
Typical Characteristics (continued)
Load Transient Response — 200 to 500mA
VID Transient Response — PWM
VOUT = 1.8V
VOUT = 1.2V to 1.8V transition, IOUT = 500mA
VOUT (100mV/div)
VOUT (500mV/div)
ILX (500mA/div)
ILX (200mA/div)
ILOAD (500mA/div)
VCTL2 (5.0V/div)
Time (20�����
s�����
/div)
Time (20�����
s�����
/div)
Shutdown Transient Response
VID Transient Response — PSAVE
VOUT = 1.2V to 1.8V transition, RLOAD = 120Ω
VOUT = 1.8V, IOUT = 500mA
VOUT (1V/div)
VOUT (500mV/div)
ILX (200mA/div)
ILX (200mA/div)
VCTL3-0 (5V/div)
VCTL2-0 (5.0V/div)
Time (20�����
s�����
/div)
Time (100�����
s�����
/div)
Line Transient Response — PSAVE
Line Transient Response — PWM
VIN = 3.5 to 4.0V, VOUT = 1.8V, IOUT = 10mA
VIN = 3.5 to 4.0V, VOUT = 1.8V, IOUT = 400mA
VOUT (100mV/div)
VOUT (100mV/div)
ILX (200mA/div)
ILX (200mA/div)
4.0V —
VIN (500mV/div)
3.5 —
VIN 500mV/div)
Time (40�����
s�����
/div)
Time (40�����
s�����
/div)
SC197
Pin Descriptions
Pin
Pin Name
Pin Function
1
ctl1A
Control bit 1A — see Table 1, page 2, for output voltage selection. This pin has a weak pull-down resistor
(> 1MΩ) in place at reset that is removed when CTL1 is pulled above the logic high threshold.
2
ctl0A
Control bit 0A — see Table 1, page 2, for output voltage selection. This pin has a weak pull-down resistor
(> 1MΩ) in place at reset that is removed when CTL0 is pulled above the logic high threshold.
3
outB
Output voltage sense B — output voltage regulation point (connection node of inductor and output
capacitor).
4
GNDB
Ground B — reference and power ground for the SC197.
5
lxB
Switching output B — connect an inductor between this pin and the load to filter the pulsed output current.
6
NC
No connection
7
inB
Input power supply B — connect a bypass capacitor from this pin to GND.
8
ctl3B
Control bit 3B — see Table 1, page 2, for output voltage selection. This pin has a weak pull-down resistor
(> 1MΩ) in place at reset that is removed when CTL3 is pulled above the logic high threshold.
9
ctl2B
Control bit 2B — see Table 1, page 2, for output voltage selection. This pin has a weak pull-down resistor
(> 1MΩ) in place at reset that is removed when CTL2 is pulled above the logic high threshold.
10
ctl1B
Control bit 1B — see Table 1, page 2, for output voltage selection. This pin has a weak pull-down resistor
(> 1MΩ) in place at reset that is removed when CTL1 is pulled above the logic high threshold.
11
ctl0B
Control bit 0B — see Table 1, page 2, for output voltage selection. This pin has a weak pull-down resistor
(> 1MΩ) in place at reset that is removed when CTL0 is pulled above the logic high threshold.
12
outA
Output voltage sense A — output voltage regulation point (connection node of inductor and output
capacitor).
13
GNDA
Ground A — reference and power ground for the SC197.
14
lxA
Switching output A — connect an inductor between this pin and the load to filter the pulsed output current.
15
NC
No connection
16
inA
Input power supply A — connect a bypass capacitor from this pin to GND.
17
ctl3A
Control bit 3A— see Table 1, page 2, for output voltage selection. This pin has a weak pull-down resistor
(> 1MΩ) in place at reset that is removed when CTL3 is pulled above the logic high threshold.
18
ctl2A
Control bit 2A — see Table 1, page 2, for output voltage selection. This pin has a weak pull-down resistor
(> 1MΩ) in place at reset that is removed when CTL2 is pulled above the logic high threshold.
Notes
(1) Any of pins CTL3A, CTL2A, CTL1A, and CTL0A may be connected together to function as a single input for enable and disable.
(2) Any of pins CTL3B, CTL2B, CTL1B, and CTL0B may be connected together to function as a single input for enable and disable.
(3) A and B devices are electrically isolated and share no common connections internally. CTLxA and CTLxB pins may only be connected together
when A and B devices share the same power source, INA and INB are connected together, and GNDA and GNDB are connected together. Note
that connecting any CTLxA and CTLxB pins together will force both A and B devices to make output voltage changes simultaneously.
10
SC197
Block Diagram
PLIMIT Amp
Current Amp
Control
Logic
OSC & Slope
Generator
500mV
Ref
Error Amp
16 INA
14 LXA
PWM Comp
NLIMIT Amp
CTL3A
CTL2A 18
CTL1A
1
CTL0A
2
13 GNDA
PSAVE
Comp
17
Voltage
Select
12
OUTA
PLIMIT Amp
Current Amp
Control
Logic
OSC & Slope
Generator
500mV
Ref
Error Amp
7
INB
5
LXB
4
GNDB
3
OUTB
PWM Comp
NLIMIT Amp
CTL3B
8
CTL2B
9
CTL1B 10
CTL0B
11
PSAVE
Comp
Voltage
Select
11
SC197
Applications Information
General Description
The SC197 contains two identical synchronous step-down
PWM (Pulse Width Modulated) DC-DC regulators. Each
regulator utilizes a 3.5MHz fixed-frequency voltage mode
architecture. Each is designed to operate in fixed-frequency PWM mode and enter PSAVE (Power Save) mode
utilizing pulse frequency modulation under light load
conditions to maximize efficiency. Each regulator requires
only two capacitors and a single inductor to be implemented in most systems. The switching frequency has
been chosen to minimize the size of the inductor and
capacitors while maintaining high efficiency. Output
voltage is programmable, eliminating the need for external programming resistors. Loop compensation is also
internal, eliminating the need for external components to
control stability.
Programmable Output Voltage
The SC197 has 15 fixed output voltage levels which can be
individually selected by programming the CTLx(A/B)
control pins (see Table 1 on page 2 for settings). Control
pins with an “A” suffix refer to the A output, and the “B”
suffix refers to the B output. “A” and “B” devices are electrically isolated and share no connections internal to the
package. The “A” or “B” device is disabled whenever all four
CTLxA or all four CTLxB pins are pulled low. The “A” or “B”
device is enabled whenever at least one of the CTLxA or
CTLxB pins is pulled high. This configuration eliminates
the need for a dedicated enable pin. Each CTLx(A/B) pin is
internally pulled down via 1MΩ if VIN is below 1.5V or if the
voltage on the control pin is below the input high voltage.
This ensures that the output is disabled when power is
applied if there are no inputs to the CTLx(A/B) pins. Each
weak pull-down is disabled whenever its pin is pulled high
and remains disabled until all CTLx(A/B) pins are pulled
low.
The output voltage can be set using different methods. If
a static output voltage is required, the CTLx(A/B) pins can
be tied to either IN or GND to set the desired voltage
whenever power is applied at IN. If enable control is
required, each CTLx(A/B) pin can be tied to either GND or
to a microprocessor I/O line to create the desired control
code whenever the control signal is forced high. This
approach is equivalent to using the CTLx(A/B) pins collectively as a single enable pin. A third option is to connect
each of the four CTLx(A/B) pins to individual microprocessor I/O lines. Any of the 15 output voltages can be
programmed using this approach. If only two output
voltages are needed, the CTLx(A/B) pins can be combined
in a way that will reduce the number of I/O lines to 1, 2,
or 3, depending on the control code for each desired
voltage. Other CTLx(A/B) pins could be hard wired to
GND or IN. This option allows dynamic voltage adjustment for systems that reduce the supply voltage when
entering sleep states. Note that applying all zeros to the
CTLx(A/B) pins when changing the output voltages will
temporarily disable the device, so it is important to avoid
this combination when dynamically changing levels.
CTLxA and CTLxB pins may only be connected together
when A and B devices share the same power source; i.e.,
INA and INB pins are connected together, and GNDA and
GNDB are connected together. Note that connecting any
CTLxA and CTLxB pins together will force both A and B
devices to make output voltage changes
simultaneously.
Adjustable Output Voltage Selection
If an output voltage other than one of the 15 programmable settings is needed, an external resistor divider
network can be added to the SC197 to adjust the output
voltage setting. This network scales the output based on
the resistor ratio and the programmed output setting.
The resistor values can be determined using the equation. Note that VOUT may refer to either the A or B device.
VOUT
ª R RFB2 º
VSET u « FB1
» ILEAK u RFB1
¬ RFB2
¼
where VOUT is the desired output voltage, VSET is the
voltage setting selected by the CTLx(A/B) pins, RFB1 is the
resistor between the output capacitor and the OUT(A/B)
pin, RFB2 is the resistor between the OUT(A/B) pin and
ground, and ILEAK is the leakage current into the OUT(A/B)
pin during normal operation. The current into the
OUT(A/B) pin is typically 1µA, so the last term of the equation can be neglected if the current through RFB2 is much
larger than 1µA. Selecting a resistor value of 10kΩ or
12
SC197
Applications Information (continued)
lower will simplify the design. If ILEAK is neglected and RFB2
is fixed, RFB1 can be determined using the equation.
RFB1
RFB 2 u
VOUT VSET
VSET
Inserting resistance in the feedback loop will adversely
affect the system’s transient performance if feed-forward
capacitance is not included in the circuit. The circuit in
Figure 1 illustrates how the resistor divider and feedforward capacitor can be added to the SC197 schematic.
The value of feed-forward capacitance needed can be
determined using the equation.
CFF
VSET VOUT 0.5 RFB1 VOUT VSET VSET 0.5 2
4 u 10 6 u
SC197
VIN
INA
LXA
CIN
OUTA
CTL3A
CTL2A
Enable
CTL1A
LX
VOUT
CFF
RFB1
RFB2
COUT
GNDA
the CTL3-0 pins to 0010 (1.0V setting). The necessary
component values are as follows:
VOUT VSET
VSET
RFB1
RFB 2 u
CFF
8 u 10 6 u
3k:
VOUT 0.52
RFB1 VOUT 1
5.69nF
PWM Operation
Normal PWM operation occurs when the output load
current exceeds the PSAVE threshold. In this mode, the
PMOS high side switch is activated with the duty cycle
required to produce the output voltage programmed by
the CTLx(A/B) pins. An internal synchronous NMOS rectifier eliminates the need for an external Schottky diode on
the LX(A/B) pin. The duty cycle (percentage of time PMOS
is active) increases as VIN decreases to maintain output
voltage regulation. As the input voltage approaches the
programmed output voltage, the duty cycle approaches
100% (PMOS always on) and the device enters a passthrough mode. This mode remains active until the input
voltage increases or the load decreases enough to allow
PWM switching to resume.
CTL0A
Power Save Mode Operation
Figure 1 — Application Circuit with External Resistors
To simplify the design, it is recommended to program the
output setting to 1.0V, use resistor values smaller than
10kΩ, and include a feed-forward capacitance calculated
with the equation above. If the output voltage is set to
1.0V, the previous equation reduces to the following.
CFF
8 u 10 6 u
VOUT 0.52
RFB1 VOUT 1
Example:
An output voltage of 1.3V is desired, but this is not a programmable option. What external component values for
Figure 1 are needed?
Solution: To keep the circuit simple, set RFB2 to 10kΩ so
current into the OUT(A/B) pin can be neglected and set
When the load current decreases below the PSAVE
threshold, PWM switching stops and the device automatically enters PSAVE mode. This threshold varies
depending on the input voltage and output voltage
setting, optimizing efficiency for all possible load currents
in PWM or PSAVE mode. While in PSAVE mode, output
voltage regulation is controlled by a series of switching
bursts. During a burst, the inductor current is limited to a
peak value which controls the on-time of the PMOS
switch. After reaching this peak, the PMOS switch is disabled and the inductor current decreases to near 0mA.
Switching bursts continue until the output voltage climbs
to VOUT +2.5% or until the PSAVE current limit is reached.
Switching is then stopped to eliminate switching losses,
enhancing overall efficiency. Switching resumes when
the output voltage reaches the lower threshold of VOUT
and continues until the upper threshold again is reached.
Note that the output voltage is regulated hysteretically
while in PSAVE mode between VOUT and VOUT + 2.5%. The
13
SC197
Applications Information (continued)
period and duty cycle while in PSAVE mode are solely
determined by VIN and VOUT until PWM mode resumes. This
can result in the switching frequency being much lower
than the PWM mode frequency.
If the output load current increases enough to cause VOUT
to decrease below the PSAVE exit threshold (VOUT -2%), the
device automatically exits PSAVE and operates in continuous PWM mode. Note that the PSAVE high and low
threshold levels are both set at or above VOUT to minimize
undershoot when the SC197 exits PSAVE. Figure 2 illustrates the transitions from PWM mode to PSAVE mode and
back to PWM mode.
Load
Demand
(IOUT)
VOUT +2.5%
OFF
VOUT
VOUT -2%
BURST
VLX
PWM Mode at
Medium/High
Load
PSAVE
EXIT
PSAVE Mode at
Light Load
Time
PWM Mode at
Medium/High
Load
Figure 2 — Transitions Between PWM and PSAVE Modes
Protection Features
The SC197 provides the following protection features:
•
•
•
•
•
Soft-Start Operation
Over-Voltage Protection
Current Limit
Thermal Shutdown
Under-Voltage Lockout
Soft-Start
The soft-start sequence is activated after a transition from
an all zeros CTLx(A/B) code to a non-zero CTLx(A/B) code
enables the device. At start-up, the PMOS current limit is
stepped through four levels: 25%, 40%, 60%, and 100%.
Each step is maintained for 60μs following an internal reference start up of 20μs, resulting in a total nominal
start-up period of 260μs. If VOUT reaches 90% of the target
within the first 2 steps, the device continues in PSAVE
mode at the end of soft-start; otherwise, it goes into PWM
mode. Note the VOUT ripple in PSAVE mode can be larger
than the ripple in PWM mode.
Over-Voltage Protection
OVP (Over-Voltage Protection) ensures the output voltage
does not rise to a level that could damage its load. When
VOUT exceeds the regulation voltage by 15%, the PWM
drive is disabled. Switching does not resume until VOUT has
fallen below the regulation voltage by 2%.
Current Limit
The SC197 switching stage is protected by a current limit
function. If the output load exceeds the PMOS current
limit for 32 consecutive switching cycles, the device enters
fold-back current limit mode and the output current is
limited to approximately 150mA. Under these conditions,
the output voltage will be the product of IFB-LIM and the load
resistance. The load must fall below IFB-LIM for the device to
exit fold-back current limit mode. This function makes the
device capable of sustaining an indefinite short circuit on
its output under fault conditions.
Thermal Shutdown
The SC197 has a thermal shutdown feature to protect the
device if the junction temperature exceeds 160°C. During
thermal shutdown, the PMOS and NMOS switches are
both disabled, tri-stating the LX(A/B) output. When the
junction temperature drops by the hysteresis value (20°C),
the device goes through the soft-start process and
resumes normal operation.
Under-Voltage Lockout
UVLO (Under-Voltage Lockout) activates when the supply
voltage drops below the UVLO threshold. This prevents
the device from entering an ambiguous state in which
regulation cannot be maintained. Hysteresis of approximately 200mV is included to prevent chattering near the
threshold.
Inductor Selection
The SC197 is designed to operate with a 1µH inductor
between the LX(A/B) pin and the OUT(A/B) pin. Other
values may lead to instability, malfunction, or out-ofspecification performance. The specified current levels
14
SC197
Applications Information (continued)
for PSAVE entry, PSAVE exit, and current limit are dependent on the inductor value.
The SC197 converter has internal loop compensation. The
compensation is designed to work with a specific singlepole output filter corner frequency defined by the
equation.
I&
S / u &287
where L = 1μH and COUT = 10μF.
When selecting output filter components, the LC product
should not vary over a wide range. Selection of smaller
inductor and capacitor values will move the corner frequency, potentially impacting system stability.
It is also important to consider the change in inductance
with DC bias current when choosing an inductor. The
inductor saturation current is specified as the current at
which the inductance drops a specific percentage from
the nominal value (approximately 30%). Except for shortcircuit or other fault conditions, the peak current must
always be less than the saturation current specified by the
manufacturer. The peak current is the maximum load
current plus one half of the inductor ripple current at the
maximum input voltage. Load and/or line transients can
cause the peak current to exceed this level for short durations. Maintaining the peak current below the inductor
saturation specification keeps the inductor ripple current
and the output voltage ripple at acceptable levels.
Manufacturers often provide graphs of actual inductance
and saturation characteristics versus applied inductor
current. The saturation characteristics of the inductor can
vary significantly with core temperature. Core and
ambient temperatures should be considered when examining the core saturation characteristics.
When the inductor value has been determined, the DC
resistance (DCR) must be examined. Efficiency can be
optimized by lowering the inductor’s DCR as much as possible. Low DCR in an inductor requires either more surface
area for the increased wire diameter or fewer turns to
reduce the length of the copper winding. Fewer turns
requires an inductor core with a larger cross-sectional area
in order to maintain the same saturation characteristics.
The inductor size must always be considered when examining the inductor DCR to determine the best compromise
between DCR and component area on a PCB. Note that
the ripple component of the inductor is a small percentage of the DC load. AC losses in the inductor core and
winding do not contribute significantly to the total
losses.
Magnetic fields associated with the output inductor can
interfere with nearby circuitry. This can be minimized by
the use of low-noise shielded inductors which use the
minimum gap possible to limit the distance that magnetic
fields can radiate from the inductor. Shielded inductors,
however, typically have a higher DCR and are, therefore,
less efficient than a similar sized non-shielded inductor.
Final inductor selection depends on various design considerations such as efficiency, EMI, size, and cost. Table 2
lists the manufacturers of recommended inductor options.
The inductors with larger packages tend to provide better
overall efficiency, while the smaller package inductors
provide decent efficiency with reduced footprint or height.
The saturation current ratings and DC characteristics are
also shown.
Table 2 — Recommended Inductors
Manufacturer
Part Number
L
(μH)
DCR
(Ω)
Saturation
Current
(mA)
L at
400mA
(μH)
Dimensions
LxWxH
(mm)
Murata
LQM21PN1R0MC0
1.0±20%
0.19
800
0.75
2.0x1.25x0.55
Murata
LQM2HPN1R0MJ0
1.0±20%
0.09
1500
0.95
2.5x2.0x1.1
Murata
LQM31PN1R0M00
1.0±20%
0.12
1200
0.95
3.2x1.6x0.85
Taiyo Yuden
CKP25201R0M-T
1.0±20%
0.08
800
0.88
2.5x2.0x1.0
Toko
MDT2012-CR1R0N
1.0±30%
0.08
1350
1.00
2.0x1.25x1.0
FDK
MIPSZ2012D1R0
1.0±30%
0.09
1100
1.00
2.0x1.25x1.0
FDK
MIPSU2520D1R0
1.0±30%
0.08
1300
0.78
2.5x2.0x0.5
FDK
MIPSA2520D1R0
1.3±30%
0.09
1200
1.20
2.5x2.0x1.2
Taiyo Yuden
BRC1608T1R0M
1.0±20%
0.18
850
0.90
1.6x0.8x0.8
15
SC197
Applications Information (continued)
COUT Selection
The internal voltage loop compensation in the SC197
limits the minimum output capacitor value to 10μF. This
is due to its influence on the the loop crossover frequency,
phase margin, and gain margin. Increasing the output
capacitor above this minimum value will reduce the crossover frequency and provide greater phase margin.
The output capacitor determines the output voltage
ripple and contributes load current during large step load
transitions. A capacitor between 10μF and 22μF will
usually be adequate in stabilizing the output during large
load transitions.
Capacitors with X7R or X5R ceramic dielectric are recommended for their low ESR and superior temperature and
voltage characteristics. Y5V capacitors should not be used
as their temperature coefficients make them unsuitable
for this application.
In addition to ensuring stability, the output capacitor
serves other important functions. This capacitor determines the output voltage ripple — as capacitance
increases, ripple voltage decreases. It also supplies current
during a large load step for a few switching cycles until
the control loop responds (typically 3 switching cycles).
Once the loop responds, regulation is restored and the
desired output is reached. During the period prior to PWM
operation resuming, the relationship between output
voltage and output capacitance can be approximated
using the following equation.
COUT
3 u 'ILOAD
VDROOP u f
This equation can be used to approximate the minimum
output capacitance needed to ensure voltage does not
droop below an acceptable level. For example, a load step
from 50mA to 400mA requiring droop less than 50mV
would require the minimum output capacitance to be as
follows.
COUT
3 u 0 .4
0.05 u 4 u 10 6
6.0PF
In this example, using a standard 10µF capacitor would be
adequate to keep voltage droop less than the desired
limit. Note that if the voltage droop limit were decreased
from 50mV to 25mV, the output capacitance would need
to be increased to at least 12µF (twice as much capacitance for half the droop). Capacitance will decrease from
the nominal value when a ceramic capacitor is biased with
a DC current, so it is important to select a capacitor whose
value exceeds the necessary capacitance value at the programmed output voltage. Check the manufacturer’s
capacitance vs. DC voltage graphs when selecting an
output capacitor to ensure the capacitance will be
adequate.
Table 3 lists the manufacturers of recommended output
capacitor options.
Table 3 — Recommended Output Capacitors
Value
(μF)
Type
Rated
Voltage
(VDC)
Dimensions
LxWxH (mm)
Case Size
Murata
GRM188R60J106ME47D
10±20%
X5R
6.3
1.6x0.8x0.8
0603
Murata
GRM21BR60J106K
10±10%
X5R
6.3
2.0x1.25x1.25
0805
Taiyo Yuden
JMK107BJ106MA-T
10±20%
X5R
6.3
1.6x0.8x0.8
0603
TDK
C1608X5R0J106MT
10±20%
X5R
6.3
1.6x0.8x0.8
0603
Manufacturer
Part Nunber
CIN Selection
The SC197 input source current will appear as a DC supply
current with a triangular ripple imposed on it. To prevent
large input voltage ripple, a low ESR ceramic capacitor is
required. A minimum value of 4.7μF should be used. It is
important to consider the DC voltage coefficient characteristics when determining the actual required value. For
example, a 10μF, 6.3V, X5R ceramic capacitor with 5V DC
applied may exhibit a capacitance as low as 4.5μF. The
value of required input capacitance is estimated by determining the acceptable input ripple voltage and calculating
the minimum value required for CIN using the equation
CIN
VOUT § VOUT ·
¨1 ¸
VIN ¨©
VIN ¸¹
§ 'V
·
¨¨
ESR ¸¸f
© IOUT
¹
16
SC197
Applications Information (continued)
Type
Rated
Voltage
(VDC)
Dimensions
LxWxH (mm)
Case Size
Murata
GRM188R60J475K
4.7±10%
X5R
6.3
1.6x0.8x0.8
0603
Murata
GRM188R60J106K
10±10%
X5R
6.3
1.6x0.8x0.8
0603
Taiyo Yuden
JMK107BJ475KA
4.7±10%
X5R
6.3
1.6x0.8x0.8
0603
TDK
C1608X5R0J475KT
4.7±10%
X5R
6.3
1.6x0.8x0.8
0603
CINA
COUTB
PCB Layout Considerations
The following guidelines are recommended for designing
a PCB layout:
17
16
CTL1A 1
CTL0A 2
LXB
15
NC
14
LXA
13
GNDA
12
OUTA
11
CTL0B
10
CTL1B
OUTB 3
GNDB 4
LXB 5
NC 6
7
INB
The layout diagram in Figure 3 shows a recommended
PCB top-layer for the SC197 and supporting components.
Specified layout rules must be followed since the layout is
critical for achieving the performance specified in the
Electrical Characteristics table. Poor layout can degrade
the performance of the DC-DC converter and can contribute to EMI problems, ground bounce, and resistive voltage
losses. Poor regulation and instability can result.
18
8
LXA
9
CTL2B
Value
(μF)
CTL3A
Manufacturer
Part Nunber
INA
Table 4 — Recommended Input Capacitors
CTL3B
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the PMOS switch.
Low ESR/ESL X5R ceramic capacitors are recommended
for this function. To minimize stray inductance, the capacitor should be placed as closely as possible to the IN and
GND pins of the SC197. Table 4 lists the recommended
input capacitor options from different manufacturers.
2. Keep the LXA and LXB pin traces as short as possible
to minimize pickup of high frequency switching edges
to other parts of the circuit.
3. Route a trace from the OUTA pin and connect it directly
to the terminal of COUTA. Repeat by adding a trace
between the OUTB pin and the COUTB capactor. Provide
space between the OUTA trace and LXA to minimize
noise and magnetic interference. Also provide space
between OUTB and LXA.
4. COUTA and COUTB should have a direct return to ground
with minimized trace length.
5. Use a ground plane referenced to ground pins GNDA
and GNDB. Use multiple vias to connect to ground
to further reduce noise and interference on sensitive
circuit nodes.
6. Minimize the resistance from the output and ground
pins to the load. This will reduce errors in DC regulation
due to voltage drops in the traces.
CTL2A
The input voltage ripple is at maximum level when the
input voltage is twice the output voltage (50% duty cycle
scenario).
COUTA
CINB
Figure 3 — Recommended PCB Layout
1. CINA and CINB should be placed as close to the IN and
NC pins as possible. This capacitor provides a low
impedance loop for the pulsed currents present at
the buck converter’s input. Use short wide traces to
minimize trace impedance. This will also minimize
EMI and input voltage ripple by localizing the high
frequency current pulses.
17
SC197
Outline Drawing — MLPQ-UT18
D
A
B
DIMENSIONS
DIM
PIN 1
INDICATOR
(LASER MARK)
E
A2
A
SEATING
PLANE
aaa C
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
MILLIMETERS
MIN NOM MAX
0.50
0.60
0.00
0.05
(0.152)
0.15 0.20 0.25
1.90 2.00 2.10
0.85 1.00 1.10
2.90 3.00 3.10
1.85 2.00 2.10
0.40 BSC
0.25 0.30 0.35
18
0.08
0.10
C
A1
0.80
e
0.285
D1
LxN
1.20
2.00
e
0.310
0.310
2.00
E1
1.20
1
N
0.30 x 45° CHAMFER
e
bxN
0.285
bbb
C A B
e
0.80
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
18
SC197
Land Pattern — MLPQ-UT18
K
0.80
P
DIMENSIONS
0.285
Y
1.20
H
2.00
P
0.310
0.310 P
2.00
G
(C)
Z
1.20
X
0.80
0.285
DIM
C
C1
G
G1
H
K
P
X
Y
Z
Z1
MILLIMETERS
(3.05)
(2.05)
2.40
1.40
2.00
1.00
0.40
0.20
0.65
3.70
2.70
P
G1
(C1)
Z1
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3.
THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
19
SC197
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Contact Information
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Power Management Products Division
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www.semtech.com
20