February 2010 74LVX3245 8-Bit Dual Supply Translating Transceiver with 3-STATE Outputs General Description Features The LVX3245 is a dual-supply, 8-bit translating transceiver that is designed to interface between a 3V bus and a 5V bus in a mixed 3V/5V supply environment. The Transmit/ Receive (T/R) input determines the direction of data flow. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B Ports by placing them in a high impedance condition. The A Port interfaces with the 3V bus; the B Port interfaces with the 5V bus. ■ Bidirectional interface between 3V and 5V buses ■ Inputs compatible with TTL level ■ 3V data flow at A Port and 5V data flow at B Port ■ Outputs source/sink 24 mA ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Implements proprietary EMI reduction circuitry ■ Functionally compatible with the 74 series 245 The LVX3245 is suitable for mixed voltage applications such as notebook computers using 3.3V CPU and 5V peripheral components. Ordering Code: Order Number Package Number Package Description 74LVX3245WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVX3245QSC MQA24 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 74LVX3245MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol/s Connection Diagram/s Pin Descriptions Pin Names Description OE Output Enable Input T/R Transmit/Receive Input A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs © 1993 Fairchild Semiconductor Corporation www.fairchildsemi.com Truth Table/s Inputs OE Outputs T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram/s www.fairchildsemi.com 2 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCCA, VCCB) DC Input Voltage (VI) @ OE, T/R −0.5V to VCCA + 0.5V Supply Voltage DC Input/Output Voltage (VI/O) @ An −0.5V to VCCA + 0.5V @ Bn −0.5V to VCCB + 0.5V VCCA 2.7V to 3.6V VCCB 4.5V to 5.5V Input Voltage (VI) @ OE, T/R DC Input Diode Current (IIN) 0V to VCCA Input/Output Voltage (VI/O) @ OE, T/R DC Output Diode Current (IOK) ±20 mA @ An 0V to VCCA ±50 mA @ Bn 0V to VCCB DC Output Source or −40°C to +85°C Free Air Operating Temperature (TA) ±50 mA Sink Current (IO) Minimum Input Edge Rate (Δt/ΔV) DC VCC or Ground Current VCC @ 3.0V, 4.5V, 5.5V ±100 mA and Max Current @ ICCA Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ±200 mA @ ICCB Storage Temperature Range (TSTG) −65°C to +150°C DC Latch-Up Source or ±300 mA Sink Current Maximum Junction Temperature Under Bias (TJ) 8 ns/V VIN from 30% to 70% of VCC ±50 mA per Output Pin (ICC or IGND) Note 2: Unused Pins (inputs and I/Os) must be held HIGH or LOW. They may not float. +150°C DC Electrical Characteristics Symbol VIHA Parameter TA = −40°C to +85°C Guaranteed Limits 3.6 5.0 2.0 2.0 OE 2.7 5.0 2.0 2.0 Bn 3.3 4.5 2.0 2.0 3.3 5.5 2.0 2.0 Units V Maximum LOW Level An, T/R, 3.6 5.0 0.8 0.8 Input Voltage OE 2.7 5.0 0.8 0.8 Bn 3.3 4.5 0.8 0.8 3.3 5.5 0.8 0.8 Minimum HIGH Level 3.0 4.5 2.99 2.9 2.9 Output Voltage 3.0 4.5 2.65 2.35 2.25 2.7 4.5 2.5 2.3 2.2 2.7 4.5 2.3 2.1 2.0 3.0 4.5 4.5 4.4 4.4 3.0 4.5 4.25 3.86 3.76 Maximum LOW Level 3.0 4.5 0.002 0.1 0.1 Output Voltage 3.0 4.5 0.21 0.36 0.44 2.7 4.5 0.11 0.36 0.44 2.7 4.5 0.22 0.42 0.5 3.0 4.5 0.002 0.1 0.1 3.0 4.5 0.18 0.36 0.44 3.6 5.5 ±0.1 ±1.0 μA 3.6 5.5 ±0.5 ±5.0 μA VOLB IIN TA = +25°C Typ An, T/R, VOHB VOLA (V) Input Voltage VILB VOHA VCCB (V) Minimum HIGH Level VIHB VILA VCCA V Conditions VOUT ≤ 0.1V or ≥ VCC − 0.1V VOUT ≤ 0.1V or ≥ VCC −0.1V IOUT = −100 μA V IOH = −24 mA IOH = −12 mA IOH = −24 mA V IOUT = −100 μA IOH = −24 mA IOUT =100 μA V IOL = 24 mA IOL = 12 mA IOL = 24 mA V IOUT = 100 μA IOL = 24 mA Maximum Input Leakage Current VI = VCCB, GND @ OE, T/R IOZA VI = VIL, VIH Maximum 3-STATE Output Leakage IOZB VI = VIL, VIH Maximum 3-STATE Output Leakage OE = VCCA VO = VCCA, GND @ An 3.6 ±0.5 5.5 ±5.0 μA OE = VCCA VO = VCCB, GND @ Bn 3 www.fairchildsemi.com Symbol ΔICC Parameter Maximum Bn ICCT/Input @ An, T/R, OE ICCA TA = +25°C VCCA VCCB (V) (V) Typ 3.6 5.5 1.0 3.6 3.6 TA = −40°C to +85°C Guaranteed Limits Units 1.35 1.5 mA 5.5 0.35 0.5 mA 5.5 5 50 μA VI = VCCB − 2.1V VI = VCCA −0.6V An = VCCA or GND Quiescent VCCA Supply Current Conditions Bn = VCCB or GND, OE = GND, T/R = GND ICCB An = VCCA or GND Quiescent VCCB Supply Current 3.6 5.5 8 VOLPA Quiet Output Maximum 3.3 5.0 0.8 VOLPB Dynamic VOL 3.3 5.0 1.5 VOLVA Quiet Output Minimum 3.3 5.0 −0.8 VOLVB Dynamic VOL 3.3 5.0 −1.2 VIHDA Minimum HIGH Level 3.3 5.0 2.0 VIHDB Dynamic Input Voltage 3.3 5.0 2.0 VILDA Maximum LOW Level 3.3 5.0 0.8 VILDB Dynamic Input Voltage 3.3 5.0 0.8 80 μA Bn = VCCB or GND, OE = GND, T/R = VCCA V V V V (Note 3) (Note 4) (Note 3) (Note 4) (Note 3) (Note 5) (Note 3) (Note 5) Note 3: Worst case package. Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND. Note 5: Max number of Data Inputs (n) switching. (n−1) inputs switching 0V to VCC level. Input-under-test switching: VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1 MHz. AC Electrical Characteristics Symbol Parameters TA = +25°C TA = −40°C to +85°C CL = 50 pF CL = 50 pF TA = −40°C to +85°C CL = 50 pF VCCA = 3.3V (Note 6) VCCA = 3.3V (Note 6) VCCA = 2.7V VCCB = 5.0V (Note 7) VCCB = 5.0V (Note 7) VCCB = 5.0V (Note 7) Min Typ Max Min Max Min Max tPHL Propagation Delay 1.0 5.4 8.0 1.0 8.5 1.0 9.0 tPLH A to B 1.0 5.6 7.5 1.0 8.0 1.0 8.5 tPHL Propagation Delay 1.0 5.1 7.5 1.0 8.0 1.0 8.5 tPLH B to A 1.0 5.7 7.5 1.0 8.0 1.0 8.5 tPZL Output Enable 1.0 4.8 8.0 1.0 8.5 1.0 9.0 tPZH Time OE to B 1.0 6.3 8.5 1.0 9.0 1.0 9.5 tPZL Output Enable 1.0 6.3 8.5 1.0 9.0 1.0 9.5 tPZH Time OE to A 1.0 6.8 9.0 1.0 9.5 1.0 10.0 tPHZ Output Disable 1.0 5.3 7.5 1.0 8.0 1.0 8.5 tPLZ Time OE to B 1.0 4.2 7.0 1.0 7.5 1.0 8.0 tPHZ Output Disable 1.0 5.3 8.0 1.0 8.5 1.0 9.0 tPLZ Time OE to A 1.0 3.7 6.5 1.0 7.0 1.0 7.5 tOSHL Output to Output tOSLH Skew (Note 8) 1.0 1.5 1.5 1.5 Units ns ns ns ns ns ns ns Data to Output Note 6: Voltage Range 3.3V is 3.3V ± 0.3V. Note 7: Voltage Range 5.0V is 5.0V ± 0.5V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. www.fairchildsemi.com 4 Capacitance Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance CPD Typ Units 4.5 pF 15 pF Power Dissipation A→B 55 Capacitance (Note 9) B→A 40 pF Conditions VCC = Open VCCA = 3.3V VCCB = 5.0V VCCB = 5.0V VCCA = 3.3V Note 9: CPD is measured at 10 MHz 8-Bit Dual Supply Translating Transceiver The LVX3245 is a dual supply device capable of bidirectional signal translation. This level shifting ability provides an efficient interface between low voltage CPU local bus with memory and a standard bus defined by 5V I/O levels. The device control inputs can be controlled by either the low voltage CPU and core logic or a bus arbitrator with 5V I/O levels. Manufactured on a sub-micron CMOS process, the LVX3245 is ideal for mixed voltage applications such as notebook computers using 3.3V CPU's and 5V peripheral devices. Power Up Considerations To insure that the system does not experience unnecessary ICC current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to Table 1): figured as inputs. With VCCA receiving power first, the A I/O Port should be configured as inputs to help guard against bus contention and oscillations. • A side data inputs should be driven to a valid logic level. This will prevent excessive current draw. • Power up the control side of the device first. This is the VCCA. The above steps will ensure that no bus contention or oscillations, and therefore no excessive current draw occurs during the power up cycling of these devices. These steps will help prevent possible damage to the translator devices and potential damage to other system components. • OE should ramp with or ahead of VCCA. This will help guard against bus contention. • The Transmit/Receive control pin (T/R) should ramp with VCCA, this will ensure that the A Port data pins are con- TABLE 1. Low Voltage Translator Power Up Sequencing Table Device Type 74LVX3245 VCCA VCCB T/R OE A Side I/O 3V 5V ramp ramp logic (power up 1st) configurable with VCCA with VCCA 0V or VCCA B Side I/O Floatable Pin Allowed outputs No Please reference Application Note AN-5001 for more detailed information on using Fairchild’s LVX Low Voltage Dual Supply CMOS Translating Transceivers. 5 www.fairchildsemi.com Physical Dimensions 1 5 .40 ±0 .2 0 A 1 4 .52 1 3 .9 7 0 24 13 B 7 .5 0 ±0.10 1 0 .95 1 0 .3 2 5 9 .2 P IN O N E IN D IC A T O R 1 12 0 .5 1 0 .3 5 1 .2 7 0 .25 M 1 .7 5 T Y P C B A 0 .5 5 T Y P 1 .2 7 T Y P L A N D P A T T E R N R E C O M M E N D A T IO N S E E D E T A IL A 2 .6 5 M A X 0 .33 0 .20 C 0 .1 0 C 0 .20±0.10 0 .75 0 .25 S E A T IN G P LA N E X 45° N O T E S : U N L E S S O T H E R W IS E S P E C IF IE D (R 0.10) A ) T H IS P A C K A G E C O N F O R M S T O JE D E C M S -0 13, IS S U E E , D A T E D S E P T 2005. B ) A L L D IM E N S IO N S A R E IN M ILLIM E T E R S . C ) D IM E N S IO N S D O N O T IN C LU D E M O LD FLASH O R BURRS. D ) LA N D P A T E R N S T A N D A R D : S O IC 127P 1030X 265-24L G A G E P LA N E (R 0.10) 0 .25 8° 0° E ) D R A W IN G F IL E N A M E : M K T -M 24B R E V 2 S E A T IN G P LA N E 0 .4 0 ~ 1 .27 (1.40) D E T A IL A S C A L E : 2:1 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. www.fairchildsemi.com 6 8 .7 4 8 .5 9 0 .1 0 24 A -B 13 1.75 A 24 13 5 .6 0 3 .9 9 3 .8 4 0 .1 0 6 12 1 A -B 1 0 .2 0 12 .635 C 0 .4 2 X 1 2 T IP S 0 .6 3 5 B 2 4 X 0 .3 LAND PATTERN R E C O M M E N D A T IO N 0 .2 T O P V IE W (0.6 95) 0 .1 7 8 C A -B D 0 .7 1 0 .6 1 1 .4 9 1 .3 9 45° 0 .2 0 3 0 .1 0 1 1 .7 3 M A X 0 .1 6 1 0 .0 6 1 8° 2° E N D V IE W S ID E V IE W 0 .6 1 0.71 0 M IN NOTES : A . T H IS P A C K A G E C O N F O R M S T O JE D E C M 0 -1 3 7 V A R IA T IO N A E G A G E P LA N E R 0.008 B . A L L D IM E N S IO N S A R E IN M ILLIM E T E R S C . D R A W IN G C O N F O R M S T O A S M E Y 14.5M -1994 D . D IM E N S IO N S A R E E X C LU S IV E O F B U R R S , M O LD F LA S H , A N D T IE B A R E X T R U S IO N S E . LA N D P A T T E R N S T A N D A R D : S O P 63P 600X 175-24M 0 .2 5 4 S E A T IN G P LA N E D E T A IL A F . D R A W IN G F ILE N A M E : M K T -M Q A 24R E V 2 24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. 7 www.fairchildsemi.com A 7 .8 ±0 .1 0 .2 0 T Y P 13 24 13 1 12 B 12 1 (1 .4 5 ) 3 .2 6 .4 4 .4 ±0 .1 (4 .4 5 ) 5 .9 (7 .3 5 ) 24 0 .6 5 0 .2 0 C B A 0 .1 0 C 0 .6 5 T Y P 0 .1 0 C B Z 1 2° T O P & B O T T O M R 0 .0 9M IN 0 °- 8 ° 0 .7 5 0 .4 5 D A T E 10/97. (1 .0 0 ) D E T A IL A M TC24REV4 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. www.fairchildsemi.com 8 9 www.fairchildsemi.com