Revised November 2001 74ALVC163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs General Description Features The ALVC163245 is a dual supply, 16-bit translating transceiver that is designed for 2 way asynchronous communication between busses at different supply voltages by providing true signal translation. The supply rails consist of VCCA, which is a higher potential rail operating at 2.3V to 3.6V and VCCB, which is the lower potential rail operating at 1.65V to 2.7V. (VCCB must be less than or equal to VCCA for proper device operation). This dual supply design allows for translation from 1.8V to 2.5V busses to busses at a higher potential, up to 3.3V. ■ Bidirectional interface between busses ranging from 1.65V to 3.6V The Transmit/Receive (T/R) input determines the direction of data flow. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable (OE) input, when HIGH, disables both A and B Ports by placing them in a High-Z condition. The A Port interfaces with the higher voltage bus (2.7V to 3.3V); The B Port interfaces with the lower voltage bus (1.8V to 2.5V). Also the ALVC163245 is designed so that the control pins (T/Rn, OEn) are supplied by VCCB. The 74ALVC163245 is suitable for mixed voltage applications such as notebook computers using a 1.8V CPU and 3.3V peripheral components. It is fabricated with an Advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ Supports Live Insertion and Withdrawal (Note 1) ■ Uses patented Quiet Series noise/EMI reduction circuitry ■ Functionally compatible with 74 series 16245 ■ Latchup conforms to JEDEC JED78 ■ ESD performance: Human Body Model >2000V Machine model >200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high impedance state during power up or power down, OEn should be tied to VCCB through a pull up resistor. The minimum value of the resistor is determined by the current sourcing capability of the driver. Ordering Code: Order Number 74ALVC163245GX (Note 2) 74ALVC163245T (Note 3) Package Number BGA54A (Preliminary) MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: BGA package available in Tape and Reel only. Note 3: Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Quiet Series is a trademark of Fairchild Semiconductor Corporation. © 2001 Fairchild Semiconductor Corporation ds500695 www.fairchildsemi.com 74ALVC163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs November 2001 74ALVC163245 Logic Diagram Connection Diagrams Pin Descriptions Pin Names Pin Assignment for TSSOP Description OEn Output Enable Input (Active LOW) T/Rn Transmit/Receive Input A0–A15 Side A Inputs or 3-STATE Outputs B0–B15 Side B Inputs or 3-STATE Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A B0 NC T/R1 OE1 NC A0 B B2 B1 NC NC A1 A2 C B4 B3 VCCB VCCA A3 A4 D B6 B5 GND GND A5 A6 E B8 B7 GND GND A7 A8 F B10 B9 GND GND A9 A10 G B12 B11 VCCB VCCA A11 A12 H B14 B13 NC NC A13 A14 J B15 NC T/R2 OE2 NC A15 Truth Tables Inputs OE1 Pin Assignment for FBGA T/R1 Outputs L L L H Bus B0–B7 Data to Bus A0–A7 Bus A0–A7 Data to Bus B0–B7 H X HIGH Z State on A0–A7, B0–B7 Inputs OE2 Outputs L L L H Bus B8–B15 Data to Bus A8–A15 Bus A8–A15 Data to Bus B8–B15 H X HIGH-Z State on A8–A15, B8–B15 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance (Top Thru View) www.fairchildsemi.com T/R2 2 To guard against power up problems, some simple guidelines need to be adhered to. The 74ALVC163245 is designed so that the control pins (T/Rn, OEn) are supplied by VCCB. Therefore the first recommendation is to begin by powering up the control side of the device, VCCB. The OEn control pins should be ramped with or ahead of VCCB, this will guard against bus contentions and oscillations as all A Port and B Port outputs will be disabled. To ensure the high impedance state during power up or power down, OEn should be tied to VCCB through a pull up resistor. The minimum value of the resistor is determined by the current sourcing capability of the driver. Second, the T/Rn control pins should be placed at logic LOW (0V) level, this will ensure that the B-side bus pins are configured as inputs to help guard against bus contention and oscillations. B-side Data Inputs should be driven to a valid logic level (0V or VCCB), this will prevent excessive current draw and oscillations. VCCA can then be powered up after VCCB, however VCCA must be greater than or equal to VCCB to ensure proper device operation. Upon completion of these steps the device can then be configured for the users desired operation. Following these steps will help to prevent possible damage to the translator device as well as other system components. Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74ALVC163245 74ALVC163245 Translator Power Up Sequence Recommendations 74ALVC163245 Absolute Maximum Ratings(Note 4) Recommended Operating Conditions (Note 6) Supply Voltage VCCA −0.5V to +4.6V VCCB −0.5V to VCCA VCCA 2.3V to 3.6V −0.5V to +4.6V VCCB 1.65V to 2.7V DC Input Voltage (VI) Power Supply (Note 7) DC Output Voltage (VI/O) (Note 5) Input Voltage (VI) @ OE, T/R An −0.5V to VCCA + 0.5V Bn −0.5V to VCCB + 0.5V 0V to VCCB Input/Output Voltage (VI/O) An DC Input Diode Current (IIK) 0V to VCCA Bn VI < 0V −50 mA 0V to VCCB Free Air Operating Temperature (TA −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) DC Output Diode Current (IOK) VO < 0V −50 mA VIN = 0.8V to 2.0V, VCC = 3.0V DC Output Source/Sink Current ±50 mA (IOH/IOL) ±100 mA DC VCC or Ground Current Supply Pin (ICC or Ground) −65°C to +150°C Storage Temperature (TSTG) 10 ns/V Note 4: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs or I/O pins must be held HIGH or LOW. They may not float. Note 7: Operation requires: VCCB ≤ VCCA DC Electrical Characteristics Symbol VIHA Parameter Conditions HIGH Level Input Voltage An VCCB VCCA (V) (V) Min Max 1.65 - 1.95 2.3 - 2.7 1.7 1.65 - 2.7 3.0 - 3.6 2.0 Bn, T/R, OE 1.65 - 1.95 2.3 - 3.6 0.65 x VCCB 2.3 - 2.7 3.0 - 3.6 1.6 An 1.65 - 1.95 2.3 - 2.7 0.7 1.65 - 2.7 3.0 - 3.6 0.8 1.65 - 1.95 2.3 - 3.6 0.35 x VCCB Units V VIHB VILA LOW Level Input Voltage V Bn, T/R, OE VILB VOHA VOHB VOLA VOLB HIGH Level Output Voltage HIGH Level Output Voltage Low Level Output Voltage Low Level Output Voltage 2.3 - 2.7 3.0 - 3.6 1.65 - 2.7 2.3 - 3.6 VCCA–0.2 IOH = −12 mA 1.65 2.3 - 2.7 1.7 IOH = −24 mA 1.65 - 2.3 3.0 - 3.6 2 VCCB–0.2 IOH = −100 µA 0.7 IOH = −100 µA 1.65 - 2.7 2.3 - 3.6 IOH = −4 mA 1.65 - 1.95 2.3 - 3.0 1.2 IOH = −12 mA 2.3 - 2.7 3.0 1.7 V V IOL = 100 µA 1.65 - 2.7 2.3 - 3.6 IOL = 12 mA 1.65 2.3 - 2.7 0.7 IOL = 24 mA 1.65 - 2.3 3.0 - 3.6 0.55 0.2 V IOL = 100 µA 1.65 - 2.7 2.3 - 3.6 0.2 IOL = 4 mA 1.65 - 1.95 2.3 - 3.0 0.45 IOL = 12 mA 2.3 -2.7 3.0 0.7 1.65 - 2.7 2.3 - 3.6 ±5.0 µA 1.65 - 2.7 2.3 - 3.6 ±10 µA 0 0 10 µA 1.65 - 2.7 2.3 - 3.6 40 µA II Input Leakage Current @ OE, T/R 0V ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0V ≤ VO ≤ 3.6V OE = VCCB V VI = VIH or VIL IOFF Power Off Leakage Current 0≤ (VI, VO) ≤ 3.6V ICCA/ICCB Quiescent Supply Current, An = V CCA or GND per supply, VCCA / VCCB Bn, OE, & T/R = VCCB or GND Increase in ICC per Input, Bn, T/R, OE VI = VCCB – 0.6V 1.65 - 2.2 2.3 - 3.6 750 µA Increase in ICC per Input, An VI = VCCA – 0.6V 1.65 - 2.2 2.3 - 3.6 750 µA ∆ICC www.fairchildsemi.com 4 TA = −40°C to +85°C, RL = 500Ω Symbol tPHL, tPLH CL = 50 pF Parameter Propagation Delay VCCA = 3.3 ± 0.3 A to B VCCB = 2.5 ± 0.2 VCCA = 3.3 ± 0.3 VCCB = 1.8 ± 0.15 VCCA = 2.7 VCCB = 1.8 ± 0.15 Min Max 1.3 4.9 2.0 6.7 2.0 6.3 VCCB = 1.8 ± 0.15 Propagation Delay VCCA = 3.3 ± 0.3 B to A VCCB = 2.5 ± 0.2 VCCA = 3.3 ± 0.3 VCCB = 1.8 ± 0.15 VCCA = 2.7 VCCB = 1.8 ± 0.15 1.1 4.5 1.1 5.6 1.3 6.0 VCCB = 1.8 ± 0.15 Output Enable Time VCCA = 3.3 ± 0.3 OE to B VCCB = 2.5 ± 0.2 VCCA = 3.3 ± 0.3 VCCB = 1.8 ± 0.15 VCCA = 2.7 VCCB = 1.8 ± 0.15 1.3 5.1 2.0 8.7 2.0 8.8 VCCB = 1.8 ± 0.15 Output Enable Time VCCA = 3.3 ± 0.3 OE to A VCCB = 2.5 ± 0.2 VCCA = 3.3 ± 0.3 VCCB = 1.8 ± 0.15 VCCA = 2.7 VCCB = 1.8 ± 0.15 1.1 4.5 1.1 5.6 1.3 5.8 VCCB = 1.8 ± 0.15 Output Disable Time VCCA = 3.3 ± 0.3 OE to B VCCB = 2.5 ± 0.2 VCCA = 3.3 ± 0.3 VCCB = 1.8 ± 0.15 VCCA = 2.7 VCCB = 1.8 ± 0.15 1.3 4.9 1.3 5.0 1.3 5.1 VCCB = 1.8 ± 0.15 Output Disable Time VCCA = 3.3 ± 0.3 OE to A VCCB = 2.5 ± 0.2 VCCA = 3.3 ± 0.3 VCCB = 1.8 ± 0.15 VCCA = 2.7 VCCB = 1.8 ± 0.18 VCCA = 2.5 ± 0.2 VCCB = 1.8 ± 0.18 5 5.8 0.6 5.1 0.8 5.5 1.5 8.2 1.5 8.3 0.6 5.1 0.8 5.3 0.8 4.5 ns VCCA = 2.5 ± 0.2 tPLZ, tPHZ 1.5 ns VCCA = 2.5 ± 0.2 tPLZ, tPHZ 6.2 ns VCCA = 2.5 ± 0.2 tPZL, tPZH 1.5 Units ns VCCA = 2.5 ± 0.2 tPZL, tPZH Max ns VCCA = 2.5 ± 0.2 tPHL, tPLH CL = 30 pF Min 1.1 5.3 1.1 6.1 1.3 5.7 0.8 4.6 0.6 5.6 ns 0.8 5.2 www.fairchildsemi.com 74ALVC163245 AC Electrical Characteristics 74ALVC163245 Capacitance Symbol Parameter Conditions TA = +25°C VCC Typical Units CIN Input Capacitance VI = 0V or VCC 3.3 5 pF COUT Output Capacitance VI = 0V or VCC 3.3 6 pF CPD Power Dissipation Capacitance 3.3 20 2.5 20 www.fairchildsemi.com Outputs Enabled f = 10 MHz, CL = 50 pF 6 pF TABLE 1. Values for Figure 1 TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VL tPZH, tPHZ GND FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V 1.5V VCC/2 VCC/2 Vmo 1.5V 1.5V VCC/2 VCC/2 VX VOL + 0.3V VOL + 0.3V VOL + 0.15V VOL + 0.15V VY VOH − 0.3V VOH − 0.3V VOH − 0.15V VOH − 0.15V VL 6V 6V VCC*2 VCC*2 FIGURE 2. Waveform for Inverting and Non-inverting Functions tr = tf ≤ 2.0 ns, 10% to 90% FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0 ns, 10% to 90% FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0 ns, 10% to 90% 7 www.fairchildsemi.com 74ALVC163245 AC Loading and Waveforms 74ALVC163245 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary) 8 www.fairchildsemi.com 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com 74ALVC163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)