74AC373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED) ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74AC373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP 74AC373B 74AC373M T&R 74AC373MTR 74AC373TTR logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level); while OE is in high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS April 2001 1/11 74AC373 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 Q0 to Q7 3 State Output Enable Input (Active LOW) Data Inputs D0 to D7 3-State Outputs LE GND VCC NAME AND FUNCTION Latch Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OE LE D Q H L L L X L H H X X L H Z NO CHANGE L H X : Don’t Care Z : High Impedance NOTE: Outputs are latched at the time when the input is taken LOW logic level LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 OUTPUT 74AC373 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ± 400 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) V -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Value Unit 2 to 6 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C 8 ns/V dt/dv Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1) 1) VIN from 30% to 70% of V CC 3/11 74AC373 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II Ioz ICC IOLD IOHD Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current High Impedance Output Leakege Current Quiescent Supply Current Dynamic Output Current (note 1, 2) TA = 25°C VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 Value VO = 0.1 V or VCC-0.1V Min. Typ. 2.1 3.15 3.85 1.5 2.25 2.75 1.5 2.25 2.75 VO = 0.1 V or VCC-0.1V Max. -55 to 125°C Min. Min. Max. 2.1 3.15 3.85 0.9 1.35 1.65 Max. 2.1 3.15 3.85 0.9 1.35 1.65 Unit V 0.9 1.35 1.65 V 3.0 IO=-50 µA 2.9 2.99 2.9 2.9 4.5 IO=-50 µA 4.4 4.49 4.4 4.4 5.5 IO=-50 µA 5.4 5.49 5.4 5.4 3.0 IO=-12 mA 2.56 2.46 2.4 4.5 IO=-24 mA 3.86 3.76 3.7 5.5 IO=-24 mA 4.86 4.76 4.7 3.0 IO=50 µA 0.002 0.1 0.1 0.1 4.5 IO=50 µA 0.001 0.1 0.1 0.1 5.5 IO=50 µA 0.001 0.1 0.1 0.1 3.0 IO=12 mA 0.36 0.44 0.5 4.5 IO=24 mA 0.36 0.44 0.5 5.5 IO=24 mA 0.36 0.44 0.5 5.5 VI = VCC or GND ± 0.1 ±1 ±1 µA 5.5 VI = VIH or VIL VO = VCC or GND ± 0.5 ±5 ± 10 µA 5.5 VI = VCC or GND 4 40 80 µA VOLD = 1.65 V max 75 50 mA VOHD = 3.85 V min -75 -50 mA 5.5 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω 4/11 -40 to 85°C V V 74AC373 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time LE to Q tPLH tPHL Propagation Delay Time D to Q tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time tW ts th CLOCK Pulse Width HIGH or LOW Setup Time D to CLOCK, HIGH or LOW Hold Time D to CLOCK, HIGH or LOW Value TA = 25°C VCC (V) -55 to 125°C Min. Min. Typ. Max. (*) 6.5 12.0 14.0 14.0 5.0(**) 5.0 9.5 10.5 10.5 3.3(*) 6.5 12.0 14.0 14.0 (**) 5.0 5.0 9.5 10.5 10.5 3.3(*) 7.0 11.0 13.0 13.0 5.0(**) 5.0 8.5 9.5 9.5 3.3(*) 7.5 12.0 13.0 13.0 5.0(**) 6.5 9.0 10.0 10.0 3.3(*) 1.5 5.5 6.0 6.0 5.0(**) 1.5 4.0 4.5 4.5 3.3(*) 0.5 5.5 6.0 6.0 (**) 5.0 0.5 4.0 4.5 4.5 3.3(*) -0.5 1.0 5.0 5.0 5.0(**) -0.5 1.0 5.0 5.0 3.3 Min. -40 to 85°C Max. Unit Max. ns ns ns ns ns ns ns (*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5V CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter CIN Input Capacitance COUT Output Capacitance Power Dissipation Capacitance (note 1) CPD Value TA = 25°C VCC (V) Min. Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 5.0 4 pF 5.0 8 pF 20 pF 5.0 fIN = 10MHz 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit) 5/11 74AC373 TEST CIRCUIT TEST tPLH, tPHL SWITCH Open tPZL, tPLZ 2VCC tPZH, tPHZ Open CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUN PULSE WIDTH, Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11 74AC373 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 7/11 74AC373 Ceramic DIP-20 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 25 0.984 B 7.8 0.307 D E 3.3 0.5 e3 0.130 1.78 0.020 22.86 0.070 0.900 F 2.29 2.79 0.090 0.110 G 0.4 0.55 0.016 0.022 I 1.27 1.52 0.050 0.060 L 0.22 0.31 0.009 0.012 M 0.51 1.27 0.020 0.050 N1 P Q 4 (min.), 15 (max.) 7.9 8.13 5.71 0.311 0.320 0.225 P057H 8/11 74AC373 SO-20 MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 2.65 0.10 0.104 0.20 a2 MAX. 0.004 0.007 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.299 L 0.50 1.27 0.19 0.050 M S 0.75 0.029 8 (max.) P013L 9/11 74AC373 TSSOP20 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. A MIN. TYP. 1.1 0.433 A1 0.05 0.10 0.15 0.002 0.004 0.006 A2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.25 6.4 6.5 0.246 0.252 0.256 E1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 BSC 0.0256 BSC K 0o 4o 8o 0o 4o 8o L 0.50 0.60 0.70 0.020 0.024 0.028 A A2 A1 b K e E1 PIN 1 IDENTIFICATION 1 L E c D 10/11 MAX. 74AC373 Information furnished is believed to be accurate and reliable. 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