UNISONIC TECHNOLOGIES CO., LTD 8565 Preliminary LINEAR INTEGRATED CIRCUIT HIGH PERFORMANCE POWER FACTOR CORRECTION CONTROLLER IN CONTINUOUS CONDUCTION MODE DESCRIPTION The UTC 8565 is a wide input range controller integrated circuit for active power factor correction. The circuit is designed for boost PFC application, and requires reduced external component count. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC. The circuit operates in the continuous conduction mode under average current, and in discontinuous conduction mode only in light load condition. The switching frequency can be set with the external resistor at pin 4. Both current and voltage loop compensations are done externally to allow full user control. There are many kinds of protection features incorporated to make sure of safe system operation conditions, such as brown-out protection, output under voltage detection and peak current limitation. The inside reference is adjusted (5V±2%) to make sure control level and precise protection. There is a particular soft-start function to limit the start up current and thus reduces the stress on the boost diode. FEATURES * Supports wide input range * Average current control * Ease of use with few external components * External current and voltage loop compensation * Trimmed internal reference voltage (5V±2%) * Programmable operating/switching frequency * (50kHz ~ 250kHz) * Max duty cycle of 95% (typ) at 125kHz * Under voltage lockout * Cycle by cycle peak current limiting * Over-voltage protection * Open loop detection * Output under-voltage detection * Brown-out protection * Soft Over current Protection * Enhanced dynamic response ORDERING INFORMATION Ordering Number Lead Free 8565L-S08-R 8565L-S08-T 8565L-S08-R Halogen Free 8565G-S08-R 8565G-S08-T Package Packing SOP-8 SOP-8 Tape Reel Tube (1)Packing Type (1) R: Tape Reel, T: Tube (2)Package Type (2) S08: SOP-8 (3)Lead Free www.unisonic.com.tw Copyright © 2012 Unisonic Technologies Co., Ltd (3) G: Halogen Free, L: Lead Free 1 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT PIN CONFIGURATION GND 1 8 VCC ICOMP 2 7 GATE ISENSE 3 6 VSENSE FREQ 4 5 VCOMP PIN DESCRIPTION PIN NO. PIN NAME 1 VSENSE 2 VCOMP 3 ICOMP 4 FREQ 5 ISENSE 6 GND 7 GATE 8 VCC DESCRIPTION The output bus voltage of the boost converter is sensed at this pin via a resistive divider. The reference voltage for this pin is 5V. This VCOMP Pin provides the compensation of the output voltage loop with a compensation network to ground (see Fig. 2). This also gives the soft start function which controls an increasing AC input current during start-up. At this pin the compensation components of the current loop are connected. The capacitor which is connected at this pin integrates the output current of OTA2 and averages the current sense signal. A resistor connected to this pin sets the fixed switching frequency. The frequency range is from 50kHz to 250kHz. The pin senses the negative voltage drop at the external sense resistor (R1). This is the input signal for the average current regulation in the current loop. It is also fed to the peak current limitation block. During power up time, high inrush currents cause high voltage drop at R1, driving currents into pin 5 which could be beyond the absolute maximum ratings. Therefore a series resistor (R2) of around 220Ω is recommended in order to limit this current into the IC. This is the Ground pin. The GATE pin is the output of the internal driver stage, which has a capability of 1.5A source and sink current. Its gate drive voltage is clamped at 11.5V (typically). The VCC pin is the positive supply of the IC and should be connected to an external auxiliary supply. The operating range is between 10V and 21V. The turn-on threshold is at 11.2V and under voltage occurs at 10.2V. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT BLOCK DIAGRAM RFI Filter D2...D5 L1 Vin 85...265 VAC C1 D1 R3 VOUT C2 R7 R4 R1 R2 auxiliary supply GND GATE VCC UTC 8565 PWM Logic Variable Oscillator FREQ 2.5V + - OTA3 R5 OSC CLK 250ns Toff min Gate Driver R S R S Protection Block VCC Peak Current Limit Current Sense Opamp -1.43x OP1 Over-current Comp 300ns + 1.5V -C2 ISENSE Ramp Generator PWM Comp + C1 - Protection Logic Fault + C3 - Deglitcher S1 +/-30μA, 42μS - 0.73V 0 Current Loop Comp C3 -ve OTA2 S2 0.8V Fault Voltage Loop + 1.1mS +/-50μA linear range VSENSE OLP Current Loop ICOMP UV lockout + C4 2.5V OUP Nonlinear Gain 4.75V +ve 5.25V + 5V Soft Start 4.0V VCOMP 0 4.0V OTA1 Soft Over Current Control -ve Fault Window Detect R6 C4 C5 Representative Block diagram UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 3 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNIT VCC Supply Voltage VCC -0.3 ~ 22 V FREQ Voltage VFREQ -0.3 ~ 7 V ICOMP Voltage VICOMP -0.3 ~ 7 V ISENSE Voltage VISENSE -24 ~ 7 V ±1 ISENSE Current IISENSE mA VSENSE Voltage VVSENSE -0.3 ~ 7 V ±1 VSENSE Current IVSENSE mA VCOMP Voltage VVCOMP -0.3 ~ 7 V GATE Voltage VGATE -0.3 ~ 22 V ESD Protection (Note 2) VESD 2 kV Junction Temperature TJ -40 ~ 150 °C Storage Temperature TSTG -55 ~ 150 °C Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. 2. According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor) THERMAL DATA PARAMETER Junction to Ambient SYMBOL θJA RATINGS 90 UNIT K/W ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL OPERATING RANGE (Note 1) VCC Supply Voltage VCC Junction Temperature TJ(CON) SUPPLY SECTION (Note 2) VCC Turn-On Threshold VCCON VCC Turn-Off Threshold/ VCCUVLO Under Voltage Lock Out VCC Turn-On/Off Hysteresis VCCHY Start Up Current Before VCCON ICCSTART Operating Current With Active ICCHG GATE Operating Current During Standby ICCSTDBY VARIABLE FREQUENCY SECTION Switching Frequency (Typical) FSWNOM Switching Frequency (Min.) FSW(MIN) Switching Frequency (Max.) FSW(MAX) Voltage At FREQ Pin VFREQ PWM SECTION Max. Duty Cycle DMAX Min. Duty Cycle DMIN Min. Off Time TOFF(MIN) TEST CONDITIONS TYP VCCUVLO -40 MAX UNIT 21 125 V °C 10.5 11.2 11.9 V 9.4 10.2 10.8 V VVCC=VVCC(ON)-0.1V 0.8 50 1 100 1.3 200 V µA R5=33kΩ, CL=4.7nF 13.5 18 22.5 mA R5 = 33kΩ, VVSENSE=0.5V 2.0 2.6 3.2 mA R5=33kΩ R5=82kΩ R5=15kΩ 106 40 200 2.40 133 56 250 2.50 161 70 320 2.60 kHz kHz kHz V 92 95 150 250 98 0 350 % % ns FSW=FSWNOM (R5=33kΩ) VVCOMP=0V, VVSENSE=5V, VICOMP=6.4V VVCOMP=5V, VVSENSE=5V, VISENSE=0.1V UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN 4 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT ELECTRICAL CHARACTERISTICS(Cont.) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PROTECTION SECTION Open Loop Protection (OLP) VOLP 0.77 0.81 0.86 V VSENSE Threshold Peak Current Limitation (PCL) VPCL -1.15 -1.08 -1.00 V ISENSE Threshold Soft Over Current Control (SOC) ISENSE VSOC -0.79 -0.73 -0.66 V Threshold Output Under Voltage Detection (OUV) VOUV 2.45 2.55 2.65 V VSENSE Threshold Output Over-Voltage Protection (OVP) VOVP 5.12 5.25 5.38 V CURRENT LOOP SECTION OTA2 Transconductance Gain GmOTA2 At Temp=25°C 0.9 1.1 1.3 mS OTA2 Output Linear Range IOTA2 Guaranteed by design ±50 µA ICOMP Voltage during OLP VICOMPF VVSENSE=0.5V 3.6 4.0 V VOLTAGE LOOP SECTION OTA1 Reference Voltage VOTA1 4.90 5.00 5.10 V OTA1 Transconductance Gain GmOTA1 31.5 42 52.5 µS OTA1 Max. Source Current Under IOTA1SO VVSENSE=4.25V, VVCOMP=4V 21 30 38 µA Normal Operation OTA1 Max. Sink Current Under IOTA1SK VVSENSE=6V, VVCOMP=4V 21 30 38 µA Normal Operation Soft Start End VSOFT 3.80 4.00 4.20 V OTA1 Source Current Under Soft Start IOTA1SS VVSENSE=2V, VVCOMP=0V 8.0 10.8 13.4 µA VSENSE High VHi 5.12 5.25 5.38 V Enhanced Dynamic Response VSENSE Low VLo 4.63 4.75 4.87 V VSENSE Input Bias Current At 5V IVSEN5V VVSENSE=5V 0 1.5 µA VSENSE Input Bias Current at 1V IVSEN1V VVSENSE=1V 0 1 µA VCOMP Voltage during OLP VVCOMPF VVSENSE= 0.5V, IVCOMP=0.5mA 0 0.2 0.4 V DRIVER SECTION 1.2 V VCC=5V, IGATE=5mA VCC=5V, IGATE=20mA 1.5 V GATE Low Voltage VGATEL IGATE=0A 0.8 V IGATE=20mA 1.6 2.0 V IGATE=-20mA -0.2 0.2 V 11.5 V VCC=20V, CL=4.7nF GATE High Voltage VGATEH VCC=11V, CL =4.7nF 10.5 V VCC=VVCC(OFF)+0.2V, CL=4.7nF 7.5 V GATE Rise Time tR VGATE=2V...9V, CL=4.7nF 20 ns GATE Fall Time tF VGATE=9V...2V, CL=4.7nF 20 ns GATE Current, Peak, Rising Edge IGATE CL=4.7nF (Note 3) -1.5 A GATE Current, Peak, Falling Edge IGATE CL=4.7nF (Note 3) 1.5 A Notes: 1. Within the operating range the IC operates as described in the functional description. 2. The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from -40°C to 125°C. Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of VCC=15V is assumed for test condition. 3. Design characteristics (not meant for production testing) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT FUNCTIONAL DESCRIPTION 1. General The UTC 8565 is an active power factor correction controller for boost PFC application. The IC comes in DIP package and is suitable for wide input range applications from 85 to 265 VAC. The IC is usually realized with boost converters and it operates in continuous conduction mode with average current control. The UTC 8565 operates with a cascaded control; the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (DCM). In DCM, the average current waveform will be distorted but the resultant harmonics are still low enough to meet the Class D requirement of IEC 1000-3-2. The outer loop controls the output voltage. Depending on the load condition, OTA1 establishes an appropriate voltage at VCOMP pin which controls the amplitude of the average input current. The UTC 8565 provides several protection features to ensure safe operating condition for both the system and device. Important protection features are namely Brown-out protection, Current Limitation and Output Under-voltage Protection. 2. Power Supply The operating voltage range of the VCC is from 10V to 21V. An internal under voltage lockout (UVLO) block monitors the VCC power supply. As soon as it exceeds 11.2V and the voltage at pin 1 (VSENSE) is >0.8V, the IC begins operating its gate drive and performs its Soft-Start as shown in Fig. 3. If VCC drops below 10.2V, the IC is off. The IC will then be consuming typically 200µA, whereas consuming 18mA during normal operation. The IC can be turned off and forced into standby mode by pulling down the voltage at pin 1 (VSENSE) to lower than 0.8V. The current consumption is reduced to 3mA in this mode. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT FUNCTIONAL DESCRIPTION(Cont.) 3. Start-up (Soft-Start) The operation of OTA1 during startup is shown in Fig. 4 and 5. VSENSE ( R4 R3+R4 ×VOUT ) Soft Start 4.0V VOUT<80% rated 10.8μA during Soft Start + S1 R6 C5 VOUT>80% rated OTA1 VCOMP C4 Normal Operation Soft Start 5V Open-Loop Protect (OLP) C3 + 0.8V av(IIN) UTC 8565 t Fig. 4 Soft Start Circuit Fig. 5 Soft Start With Controlled Current It sources a constant 10.8µA into the compensation network at pin 2 (VCOMP). The voltage at this pin rises linearly and so does the amplitude of the input current. As soon as the output voltage VOUT reaches 80% of its rated level, the startup procedure is finished and the normal voltage control takes over. In normal operation, the IC operates with a higher maximum current at OTA1 and therefore with a higher voltage loop gain in order to improve the dynamic behavior of the device. The advantage of this technique is a soft-start function with lower stress for the boost diode but without the risk of audible noise. 4. System Protection The IC is equipped with various protection features to ensure the PFC system in safe operating range. Depending on the input line voltage (VIN) and output bus voltage (VOUT), When these protections are active the conditions are shown in Fig. 6 and 7. The following sections describe the functionality of these protection features. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT FUNCTIONAL DESCRIPTION(Cont.) 4.1 Brown-Out Protection (BOP) Input Brown-out occurs if the input voltage VIN falls below the minimum input voltage of the design (i.e. 85V for universal input voltage range) and the VCC has not entered into the VCC under voltage lockout level yet. For a system without BOP, the boost converter will increasingly draw a higher current from the mains at a given output power which may exceed the maximum design values of the input current. The UTC 8565 limits internally the current drawn from the mains and therefore also limits the input power. The difference of input and output power will result in decreasing output voltage. If the condition prolongs, the decreasing VOUT will terminate in output under voltage condition (OUV, 50% of rated), and the IC will be shut down (See section 4.5). Fig. 8 shows the occurrence of BOP in respect to the ISENSE voltage. The VIN threshold for BOP to occur is dependent on the voltage at ISENSE and thus the output power. The rated output power with a minimum VIN (VIN(MIN)) is POUT (rated) = VINMIN × R10.6 × 2 Due to the internal parameter tolerance, the maximum power with VIN(MIN) before BOP occurs is POUT (max) = VINMIN × R01×.732 And the BOP takes over the normal operation under rated output power latest at an input voltage of VBOPMAX = POUT (rated) × R1× 2 0.73 4.2 Soft Over Current Control (SOC) The UTC 8565 is designed not to support any output power that corresponds to a voltage lower than -0.73V at the ISENSE pin. A further increase in the inductor current, which results in a lower ISENSE voltage, will activate the Soft Over Current Control (SOC). This is a soft control as it does not directly switch off the gate drive like the PCL. It acts on the nonlinear gain block to result in a reduced PWM duty cycle. 4.3 Peak Current Limit (PCL) The UTC 8565 is equipped with a cycle by cycle peak current protection feature. It is active when the voltage at pin 5 (ISENSE) reaches -1.08V. This voltage is amplified by OP1 with a factor of -1.43 and connected to comparator C2 with a reference voltage of 1.5V as shown in Fig. 9. A deglitcher with 300ns after the comparator improves noise immunity to the activation of this protection. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 8 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT FUNCTIONAL DESCRIPTION(Cont.) 4.4 Open Loop Protection / Input Under Voltage Protect (OLP) Whenever VSENSE voltage falls below 0.8V, or equivalently VOUT falls below 16% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage VIN for normal operation. In this case, most of the blocks within the IC will be shutdown. The function is implemented using comparator C3 with a threshold of 0.8V as shown in the IC block diagram in Fig. 2. 4.5 Output Under Voltage Detection (OUV) In the event of main interrupt or brown-out condition, the PFC system is not able to deliver the rated output power. This will cause the output voltage VOUT to drop below its rated value. The IC provides an output under voltage detection that checks if VOUT is falling below 50% of its rated value. Comparator C4 as shown in the device block diagram (Fig. 2) senses the voltage at pin 1 (VSENSE) with a reference of 2.5V. If comparator C4 trips, the IC will be shut down as in OLP. The IC will be ready to restart if there is sufficient VIN to pull VOUT out of OLP. 4.6 Over-Voltage Protection (OVP) Whenever VOUT exceeds the rated value by 5%, the over-voltage protection OVP is active as shown in Fig. 7. This is implemented by sensing the voltage at pin VSENSE with respect to a reference voltage of 5.25V. A VSENSE voltage higher than 5.25V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This results in a lower input power to reduce the output voltage VOUT. 5. Frequency Setting The switching frequency of the PFC controller is fixed and can be set by an external resistor R5 at FREQ pin. The pin voltage VFREQ is typically 2.5V. The corresponding capacitor for the oscillator is integrated in the device and the R5/frequency relationship is given at the “Electrical Characteristic” section. The recommended operating frequency range is from 50kHz to 250kHz. As an example, a R5 of 33kΩ at pin FREQ will set a switching frequency FSW of 133kHz typically. 6. Average Current Control 6.1 Complete Current Loop Fig. 10 show the complete system current loop. It consists of the current loop block which averages the voltage at pin ISENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. From Full-wave Retifier R1 R2 L1 D1 R7 R3 VOUT C2 R4 GATE ISENSE ICOMP C3 voltage Current Loop proportional to averaged Gate Inductor current Driver Current Loop PWM Compensation Comparator RQ + + OTA2 S C1 PWM Logic 1.1mS +/-50μA (linear range) S2 4V Fault Input From Nonlinear Voltage Loop Gain UTC 8565 Fig. 10 Complete System Current Loop UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 9 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT FUNCTIONAL DESCRIPTION(Cont.) 6.2 Current Loop Compensation The compensation of the current loop is done at the ICOMP pin. This is the OTA2 output and a capacitor C3 has to be installed at this node to ground (see Fig. 10). Under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 5V in the event of IC shuts down when OLP and UVLO occur. 6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous conduction mode (CCM) to achieve the power factor correction. Assuming the voltage loop is working and output voltage is kept constant, the off duty cycle DOFF for a CCM PFC system is given as D OFF = VIN VOUT From the above equation, DOFF is proportional to VIN. The objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle DOFF, and thus to the input voltage VIN. Fig. 11 shows the scheme to achieve the objective. The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 3 (ICOMP). The PWM cycle starts with the Gate turn off for a duration of TOFF(MIN) (250ns typ.) and the ramp is kept discharged. The ramp is then allowed to rise after TOFF(MIN) expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle DOFF. Fig. 12 shows the timing diagrams of TOFF(MIN) and the PWM waveforms. 6.4 Nonlinear Gain Block The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the voltage at pin VCOMP. This block has been designed to support the wide input voltage range (85-265VAC). UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 10 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT FUNCTIONAL DESCRIPTION(Cont.) 7. PWM Logic The PWM logic block prioritizes the control input signals and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFF(MIN), are designed to meet a maximum duty cycle DMAX of 95% at the GATE output under 133kHz of operation. In case of high input currents which result in Peak Current Limitation, the GATE will be turned off immediately and maintained in off state for the current PWM cycle. The signal TOFFMIN resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Fig. 13. 8. Voltage Loop The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage VOUT. This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from VOUT. The pin VSENSE is the input of OTA1 which has an internal reference of 5V. Fig. 14 shows the important blocks of this voltage loop. 8.1 Voltage Loop Compensation The compensation of the voltage loop is installed at the VCOMP pin (see Fig. 14). This is the output of OTA1 and the compensation must be connected at this pin to ground. The compensation is also responsible for the soft start function which controls an increasing AC input current during start-up. L1 From Full-wave Retifier R7 D1 R3 C2 R4 Gate Driver Current Loop + PWM Generation GATE VIN Av(IIN) VOUT Nonlinear Gain - OTA1 + 5V VSENSE VCOMP UTC 8565 R6 C4 C5 Fig. 14 Voltage Loop UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 11 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT FUNCTIONAL DESCRIPTION(Cont.) 8.2 Enhanced Dynamic Response Due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about several 10ms. This may cause additional stress to the bus capacitor and the switching transistor of the PFC in the event of heavy load changes. The IC provides therefore a “window detector” for the feedback voltage VVSENSE at pin 1 (VSENSE). Whenever VVSENSE exceeds the reference value (5V) by ±5%, it will act on the nonlinear gain block which in turn affect the gate drive duty cycle directly. This change in duty cycle is bypassing the slow changing VCOMP voltage, thus results in a fast dynamic response of VOUT. 9. Output Gate Driver The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Fig. 15) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 7 (GATE) is typically clamped at 11.5V. The output is active HIGH and at VCC voltages below the under voltage lockout threshold VCCUVLO, the gate drive is internally pull low to maintain the off state. TYPICAL APPLICATION CIRCUIT VOUT Auxiliary Supply 85...265VAC EMI-Filter SWITCH VCC UTC 8565 PFC-Controller Protection Unit GATE FREQ ICOMP PWM Logic Driver Variable Oscillator Current Loop Compensation ISENSE UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw Voltage Loop Compensation Ramp Generator VSENSE VCOMP Nonlinear Gain GND 12 of 13 QW-R114-004.b 8565 Preliminary LINEAR INTEGRATED CIRCUIT UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 13 of 13 QW-R114-004.b