V er s i on 1 . 1 , M a r 2 0 1 0 CCM-PFC ICE 2P CS 06 ICE 2P CS 06 G St a n d a l o n e Po w e r F a c to r Co r re c t io n (P F C) C o n tr o lle r i n Co n tin u o u s C o n d u c t io n M o d e (C CM ) wit h I n p u t B ro w n -O u t Pr o te c t io n Powe r M anagem ent & S uppl y N e v e r s t o p t h i n k i n g . CCM-PFC Revision History: Datasheet Previous Version: V1.0 Page Subjects(major changes since last version) 18&19 Package outline change For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com Edition 2010-03-22 Published by Infineon Technologies AG 81726 München, Germany © 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. CCM-PFC ICE2PCS06 ICE2PCS06G Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM) with Input Brown-Out Protection ICE2PCS06 PG-DIP-8 Product Highlights • • • • • • • Leadfree DIP and DSO Package Wide Input Range Direct sensing, Input Brown-Out Detection Optimized for applications which require fast Startup Output Power Controllable by External Sense Resistor Fast Output Dynamic Response during Load Jumps Trimmed, internal fixed Switching Frequency (65kHz) Features • • • • • • • • • • • • • • • • Ease of Use with Few External Components Supports Wide Input Range Average Current Control External Current and Voltage Loop Compensation for Greater User Flexibility Trimmed internal fixed Switching Frequency (65kHz+5% at 25oC) Direct sensing, Input Brown-Out Detection with Hysteresis Short Startup(SoftStart) duration Max Duty Cycle of 95% (at 25oC) Trimmed Internal Reference Voltage (3V+2% at 25oC) VCC Under-Voltage Lockout Cycle by Cycle Peak Current Limiting Output Over-Voltage Protection Open Loop Detection Soft Overcurrent Protection Enhanced Dynamic Response ICE2PCS06G PG-DSO-8 Fulfills Class D Requirements of IEC 1000-3-2 Description The ICE2PCS06/G is a 8-pin wide input range controller IC for active power factor correction converters. It is designed for converters in boost topology, and requires few external components. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC. The IC operates in the CCM with average current control, and in DCM only under light load condition. The switching frequency is trimmed and fixed internally at 65kHz. Both current and voltage loop compensations are done externally to allow full user control. There are various protection features incorporated to ensure safe system operation conditions. The internal reference is trimmed (3V+2%) to ensure precise protection and output control level. IC E 2P C S 02 /G Typical A pplication VO U T A uxiliary S upply 85 ... 265 VA C VCC E M I-Filter C C M P FC VIN S B row n-out P rotection U nit GA TE d P W M Logic D river Fixed O scillator IC O M P C urrent Loop C om pensation ISE N S E Type Package ICE2PCS06 PG-DIP-8 ICE2PCS06G PG-DSO-8 Version 1.1 3 V oltage Loop C om pensation R am p G enerator VS EN SE VCOMP N onlinear G ain GND Mar 2010 CCM-PFC ICE2PCS06/G 1 1.1 1.2 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.7 3.8 3.8.1 3.8.2 3.9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Input Brown-Out Protection (IBOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Fixed Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Version 1.1 4 Mar 2010 CCM-PFC ICE2PCS06/G Pin Configuration and Functionality 1 Pin Configuration and Functionality 1.1 Pin Configuration Pin ICOMP (Current Loop Compensation) Low pass filter and compensation of the current control loop. The capacitor which is connected at this pin integrates the output current of OTA2 and averages the current sense signal. Symbol Function 1 GND IC Ground 2 ICOMP Current Loop Compensation 3 ISENSE Current Sense Input 4 VINS 5 VCOMP 6 VSENSE VOUT Sense (Feedback) Input ISENSE (Current Sense Input) The ISENSE Pin senses the voltage drop at the external sense resistor (R1). This is the input signal for the average current regulation in the current loop. It is also fed to the peak current limitation block. During power up time, high inrush currents cause high negative voltage drop at R1, driving currents out of pin 3 which could be beyond the absolute maximum ratings. Therefore a series resistor (R2) of around 220W is recommended in order to limit this current into the IC. Brown-out Sense Input Voltage Loop Compensation 7 VCC IC Supply Voltage 8 GATE Gate Drive Output VINS (Brown-out Sense Input) This VINS pin senses a filtered input voltage divider and detects for the input voltage Brown-out condition. A Brown-out condition of VINS<0.71V, shuts down the IC. The IC turns on at VINS>1.5V. Package PG-DIP-8 / PG-DSO-8 GND 1 8 GATE ICOMP 2 7 VCC ISENSE 3 6 VSENSE VINS 4 5 VCOMP Figure 1 1.2 VSENSE (Voltage Sense/Feedback) The output bus voltage is sensed at this pin via a resistive divider. The reference voltage for this pin is 3V. VCOMP (Voltage Loop Compensation) This pin provides the compensation of the output voltage loop with a compensation network to ground (see Figure 2). VCC (Power Supply) The VCC pin is the positive supply of the IC and should be connected to an external auxiliary supply. The operating range is between 11V and 26V. The turn-on threshold is at 11.8V and under voltage occurs at 11V. There is no internal clamp for a limitation of the power supply. Pin Configuration (top view) GATE The GATE pin is the output of the internal driver stage. Its gate drive voltage is internally clamped at 15.0V (typically). Pin Functionality GND (Ground) The ground potential of the IC. Version 1.1 5 Mar 2010 CCM-PFC ICE2PCS06/G Representative Block diagram 2 Figure 2 Representative Block diagram Representative Block diagram Version 1.1 6 Mar 2010 CCM-PFC ICE2PCS06/G Functional Description 3 Functional Description 3.1 General If VCC drops below 11V, the IC is off. The IC will then be consuming typically 300mA, whereas consuming 10mA during normal operation. The IC can be turned off and forced into standby mode by pulling down the voltage at pin 6 (VSENSE) to lower than 0.6V. In this standby mode, the current consumption is reduced to 300mA. Other condition that can result in the standby mode is when a Brown-out condition occurs, ie pin 4 (VINS) <0.71V. The ICE2PCS06/G is a 8 pin control IC for power factor correction converters. It comes in both DIP and DSO packages and is suitable for wide range line input applications from 85 to 265 VAC. The IC supports converters in boost topology and it operates in continuous conduction mode (CCM) with average current control. It is a design derivative from the ICE2PCS01/G with the differences in the supporting functions, namely the input brown-out detection and internal fixed switching frequency 65kHz. The IC operates with a cascaded control; the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (DCM) resulting in a higher harmonics but still meeting the Class D requirement of IEC 1000-3-2. The outer voltage loop controls the output bus voltage. Depending on the load condition, OTA1 establishes an appropriate voltage at VCOMP pin which controls the amplitude of the average input current. The IC is equipped with various protection features to ensure safe operating condition for both the system and device. 3.3 Start-up Figure 4 shows the operation of voltage loop’s OTA1 during startup. The VCOMP pin is pull internally to ground via switch S1 during UVLO and other fault conditions (see later section on “System Protection”). During power up when VOUT is less than 83% of the rated level, OTA1 sources an output current, maximum 30mA into the compensation network at pin 5 (VCOMP) causing the voltage at this pin to rise linearly. This results in a controlled linear increase of the input current from 0A thus reducing the stress on the external component. VSENSE ( R4 x VOUT ) R3 + R4 OTA1 3.2 Power Supply S1 (VVSENSE < 0.6 V) protect R6 An internal under voltage lockout (UVLO) block monitors the VCC power supply. As soon as it exceeds 11.8V and both voltages at pin 6 (VSENSE) >0.6V and pin 4 (VINS) >1.5V, the IC begins operating its gate drive and performs its Startup as shown in Figure 3. . (VVSENSE > 0.6 V) 3V VCOMP C4 Figure 4 C5 ICE2PCS06/G Startup Circuit As VOUT has not reached within 5% from the rated value, VCOMP voltage is level-shifted by the window detect block as shown in Figure 5, to ensure there is fast boost up output voltage. When VOUT approaches its rated value, OTA1’s sourcing current drops and so does the level shift of the window detect block is removed. The normal voltage loop then takes control. (VVSENSE > 0.6 V) AND (VVINS > 1.5 V) OR (VVINS < 0.8 V) AND (VVINS > 1.5 V) VCC 11.8 V 11.0 V t IC's Start Normal Open loop/ OFF Up Operation Standby State Figure 3 Normal Operation OFF State of Operation respect to VCC Version 1.1 7 Mar 2010 CCM-PFC ICE2PCS06/G Functional Description . Window Detect VOUT VOUT,Rated Normal Control 108% 100% Max Vcomp current VOUT =rated VOUT 20% 95%rated t 83%rated Supply related t Current related Output related OLP Level-shifted VCOMP av(IIN) UVLO / IBOP PCL / SOC OVP OLP VCOMP Figure 6 t Figure 5 3.4 Protection Features 3.4.1 Input Brown-Out Protection (IBOP) Brown-out occurs when the input voltage VIN falls below the minimum input voltage of the design (i.e. 85V for universal input voltage range) and the VCC has not entered into the VCCUVLO level yet. For a system without IBOP, the boost converter will increasingly draw a higher current from the mains at a given output power which may exceed the maximum design values of the input current. ICE2PCS06/G provides a new IBOP feature whereby it senses directly the input voltage for Input Brown-Out condition via an external resistor/capacitor/diode network as shown in Figure 7. This network provides a filtered value of VIN which turns the IC on when the voltage at pin 4 (VINS) is more than 1.5V. The IC enters into the standby mode when VINS goes below 0.71V. The hysteresis prevents the system to oscillate between normal and standby mode. Note also that VIN needs to at least 20% of the rated VOUT in order to overcome OLP and powerup the system. Startup with controlled maximum current System Protection The IC provides several protection features in order to ensure the PFC system in safe operating range: • VCC Undervoltage Lockout (UVLO) • Input Brown-out Detection (IBOP) • Soft Over Current Control (SOC) • Peak Current Limit (PCL) • Open-Loop Detection (OLP) • Output Over-Voltage Protection (OVP) After the system is supplied with the correct level of VCC and VIN, the system will enter into its normal mode of operation. Figure 6 shows situation when these protections features are active, as a function of the output voltage VOUT. An activation of the UVLO, IBOP and OLP results in the internal fault signal going high and brings the IC into the standby mode. As the function of UVLO has already described in the earlier “Power Supply” section, the following sections continue to describe the functionality of these protection features. D2 ... D5 Vin 85 ... 265 VAC C1 R8 Brown-Out Detection 0.71V C4 VINS D7 80k brown-out S R C5 1.5V C6 R9 3.5V ICE2PCS06/G Figure 7 Version 1.1 8 Input Brown-Out Protection (IBOP) Mar 2010 CCM-PFC ICE2PCS06/G Functional Description 3.4.2 Soft Over Current Control (SOC) The IC is designed not to support any output power that corresponds to a voltage lower than -0.75V at the ISENSE pin. A further increase in the inductor current, which results in a lower ISENSE voltage, will activate the Soft Over Current Control (SOC). This is a soft control as it does not directly switch off the gate drive. It acts on the nonlinear gain block to result in a reduced PWM duty cycle. Current Limit Full-wave Rectifier Deglitcher 1.5V 300ns C2 ISENSE Turn Off Driver R2 1.43x IINDUCTOR OP1 R1 POUT(rated) IC’s State POUT(max) ICE2PCS06/G Normal Operation Figure 9 SOC PCL 3.4.4 Open Loop Protection (OLP) Whenever VSENSE voltage falls below 0.6V, or equivalently VOUT falls below 20% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage VIN for normal operation. In this case, most of the blocks within the IC will be shutdown. It is implemented using comparator C3 with a threshold of 0.6V as shown in the IC block diagram in Figure 2. VISENSE -0.61V -0.75V 0 Figure 8 -1.04V SOC and PCL Protection as function of VISENSE The rated output power with a minimum VIN (VINMIN) is 0.61 P OUT ( rated ) = V INMIN ´ ------------------R1 × 2 3.4.5 Over-Voltage Protection (OVP) Whenever VOUT exceeds the rated value by 5%, the over-voltage protection OVP is active as shown in Figure 6. This is implemented by sensing the voltage at pin VSENSE with respect to a reference voltage of 3.15V. A VSENSE voltage higher than 3.15V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This results in a lower input power to reduce the output voltage VOUT. A VSENSE voltage higher than 3.25V will immediately turn off the gate, thereby preventing damage to bus capacitor. Due to the internal parameter tolerance, the maximum power with VINMIN is 0.75 P OUT ( max ) = V INMIN ´ ------------------R1 × 2 3.4.3 Peak Current Limit (PCL) The IC provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at pin 3 (ISENSE) reaches -1.04V. This voltage is amplified by OP1 by a factor of -1.43 and connected to comparator C2 with a reference voltage of 1.5V as shown in Figure 9. A deglitcher with 300ns after the comparator improves noise immunity to the activation of this protection. Version 1.1 Peak Current Limit (PCL) 3.5 Fixed Switching Frequency ICE2PCS06/G has an internally fixed switching frequency as opposed to the ICE2PCS01/G which can be externally set. This frequency is trimmed to 65kHz with an accuracy ±5% at 25oC. 9 Mar 2010 CCM-PFC ICE2PCS06/G Functional Description 3.6 Average Current Control From the above equation, DOFF is proportional to VIN. The objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle DOFF, and thus to the input voltage VIN. Figure 11 shows the scheme to achieve the objective. 3.6.1 Complete Current Loop The complete system current loop is shown in Figure 10. L1 From Full-wave Retifier D1 R3 Vout ave(IIN) at ICOMP ramp profile C2 R7 R4 R2 R1 GATE ISENSE Current Loop Current Loop Compensation ICOMP OTA2 voltage proportional to averaged Inductor current Gate Driver PWM Comparator C1 S2 4.2V GATE drive Q PWM Logic 1.0mS +/-50uA (linear range) C3 R S Nonlinear Gain t Input From Voltage Loop Figure 11 Fault The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 5 (ICOMP). The PWM cycle starts with the Gate turn off for a duration of TOFFMIN (400ns typ.) and the ramp is kept discharged. The ramp is then allowed to rise after TOFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle DOFF. Figure 12 shows the timing diagrams of T OFFMIN and the PWM waveforms. ICE2PCS06/G Figure 10 Complete System Current Loop It consists of the current loop block which averages the voltage at pin ISENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. TOFFMIN 400ns 3.6.2 Current Loop Compensation The compensation of the current loop is done at the ICOMP pin. This is the OTA2 output and a capacitor C3 has to be installed at this node to ground (see Figure 10). Under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 4.2V in the event of standby mode. PWM cycle VCREF(1) VRAMP ramp released PWM 3.6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous conduction mode (CCM) to achieve the power factor correction. Assuming the voltage loop is working and output voltage is kept constant, the off duty cycle D OFF for a CCM PFC system is given as V IN D OFF = -------------V OUT Version 1.1 Average Current Control in CCM t (1) VCREF is a function of VICOMP Figure 12 Ramp and PWM waveforms 3.6.4 Nonlinear Gain Block The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the 10 Mar 2010 CCM-PFC ICE2PCS06/G Functional Description voltage at pin VCOMP. This block has been designed to support the wide input voltage range (85-265VAC). 3.7 From Full-wave Retifier PWM Logic The PWM logic block prioritizes the control input signals and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFFMIN, are designed to meet a maximum duty cycle DMAX of 95% at the GATE output. In case of high input currents which result in Peak Current Limitation, the GATE will be turned off immediately and maintained in off state for the current PWM cycle. The signal Toffmin resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 13. Peak Current Limit Current Loop PWM on signal Current Limit Latch Q S L1 R 3.8 Gate Driver GATE VIN Nonlinear Gain Av(IIN) OTA1 3V VSENSE t HIGH = turn GATE on VCOMP R6 C4 C5 Q Figure 14 Voltage Loop 3.8.2 Enhanced Dynamic Response Due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about several 10ms. This may cause additional stress to the bus capacitor and the switching transistor of the PFC in the event of heavy load changes. The IC provides therefore a “window detector” for the feedback voltage VVSENSE at pin 6 (VSENSE). Whenever VVSENSE exceeds the reference value (3V) by +5%, it will act on the nonlinear gain block which in turn affect the gate drive duty cycle directly. This change in duty cycle is bypassing the slow changing VCOMP voltage, thus results in a fast dynamic response of VOUT. PWM Logic Voltage Loop The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage VOUT. This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from VOUT. The pin VSENSE is the input of OTA1 which has an accurate internal reference of 3V (±2%). Figure 14 shows the important blocks of this voltage loop. 3.9 3.8.1 Voltage Loop Compensation The compensation of the voltage loop is installed at the VCOMP pin (see Figure 14). This is the output of OTA1 and the compensation must be connected at this pin to ground. The compensation is also responsible for the soft start function which controls an increasing AC input current during start-up. Version 1.1 Vout C2 R7 ICE2PCS06/G G1 R3 Current Loop + PWM Generation Toffmin 385ns Figure 13 D1 R4 PWM on Latch S L2 R L1 Output Gate Driver The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Figure 15) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 8 (GATE) is typically clamped at 15V. 11 Mar 2010 CCM-PFC ICE2PCS06/G Functional Description VCC Gate Driver PWM Logic HIGH to turn on LV Z1 External MOS GATE * LV: Level Shift ICE2PCS06/G Figure 15 Gate Driver The output is active HIGH and at VCC voltages below the under voltage lockout threshold V CCUVLO, the gate drive is internally pull low to maintain the off state. Version 1.1 12 Mar 2010 CCM-PFC ICE2PCS06/G Electrical Characteristics 4 Electrical Characteristics 4.1 Note: Absolute Maximum Ratings Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. Parameter Symbol Limit Values min. max. Unit Remarks VCC Supply Voltage VCC -0.3 25 V VINS Voltage VVINS -0.3 9.5 V VINS Current IINS -1 35 uA ICOMP Voltage VICOMP -0.3 5 V ISENSE Voltage VISENSE -20 5 V 2) ISENSE Current IISENSE -1 1 mA Recommended R2=220W VSENSE Voltage VVSENSE -0.3 5 V VSENSE Current IVSENSE -1 1 mA VCOMP Voltage VVCOMP -0.3 5 V GATE Voltage VGATE -0.3 17 V Junction Temperature Tj -40 150 °C Storage Temperature TS -55 150 °C Thermal Resistance Junction-Ambient for PG-DSO-8 RthJA (DSO) - 185 K/W PG-DSO-8 Thermal Resistance Junction-Ambient for PG-DIP-8 RthJA(DIP) - 90 K/W PG-DIP-8 ESD Protection VESD - 2 kV Human Body Model1) 3) R3>400kW Clamped at 15V(typ) if driven internally. 1) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kW series resistor) 2) Absolute ISENSE current should not be exceeded 3) Absolute VINS current should not be exceeded 4.2 Note: Operating Range Within the operating range the IC operates as described in the functional description. Parameter Symbol Limit Values min. Unit max. VCC Supply Voltage VCC VCCUVLO 25 V Junction Temperature TJCon -40 °C Version 1.1 13 Remarks 125 Mar 2010 CCM-PFC ICE2PCS06/G Electrical Characteristics 4.3 Note: 4.3.1 Characteristics The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from – 40 °C to 125°C.Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of VCC =18V is assumed for test condition. Supply Section Parameter Symbol Limit Values min. typ. Unit Test Condition max. VCC Turn-On Threshold VCCon 11.4 11.8 12.7 V VCC Turn-Off Threshold/ Under Voltage Lock Out VCCUVLO 10.4 11.0 11.7 V VCC Turn-On/Off Hysteresis VCChy 0.65 0.8 1.4 V Start Up Current Before VCCon ICCstart - 450 1100 mA VVCC=VVCCon -0.1V Operating Current with active GATE ICCHG - 10 13 mA CL= 2.2nF Operating Current during Standby ICCStdby - 700 1300 mA VVSENSE= 0.5V VICOMP= 4V 4.3.2 PWM Section Parameter Symbol Fixed Oscillator Frequency fSW Max. Duty Cycle DMAX Min. Duty Cycle DMIN Min. Off Time TOFFMIN Version 1.1 Limit Values min. typ. 58 65 92 270 14 95 400 Unit Test Condition max. 70 kHz 98.5 % 0 % VVCOMP= 0V, VVSENSE= 3V VICOMP= 4.3V 770 ns VVSENSE= 3V VISENSE= 0.1V Mar 2010 CCM-PFC ICE2PCS06/G Electrical Characteristics 4.3.3 System Protection Section Parameter Symbol Limit Values min. typ. Unit Test Condition max. Open Loop Protection (OLP) VSENSE Threshold VOLP 0.55 0.6 0.65 V Peak Current Limitation (PCL) ISENSE Threshold VPCL -1.16 -1.04 -0.95 V Soft Over Current Control (SOC) ISENSE Threshold VSOC -0.75 -0.68 -0.61 V Output Over-Voltage Protection (OVP) VOVP 3.1 3.25 3.4 V Input Brown-out Protection (IBOP) High to Low Threshold VVINSL 0.64 0.71 0.77 V Input Brown-out Protection (IBOP) Low to High Threshold VVINSH 1.46 1.50 1.57 V Input Brown-out Protection (IBOP) VINS Bias Current IVIN0V -1 -0.2 1 mA 4.3.4 Current Loop Section Parameter Symbol Limit Values min. OTA2 Transconductance Gain typ. Unit Test Condition max. GmOTA2 0.8 1.0 1.3 mS OTA2 Output Linear Range1) IOTA2 - ± 50 - mA ICOMP Voltage during OLP VICOMPF 3.9 4.2 - V 1) VVINS= 0V At Temp = 25°C VVSENSE= 0.5V The parameter is not subject to production test - verified by design/characterization Version 1.1 15 Mar 2010 CCM-PFC ICE2PCS06/G Electrical Characteristics 4.3.5 Voltage Loop Section Parameter Symbol Limit Values min. OTA1 Reference Voltage typ. Unit Test Condition max. VOTA1 2.92 3.00 3.08 V OTA1 Transconductance Gain GmOTA1 26 39 51 mS OTA1 Max. Source Current Under Normal Operation IOTA1SO 18 30 38 mA VVSENSE= 2V VVCOMP= 3V OTA1 Max. Sink Current Under Normal Operation IOTA1SK 21 30 41 mA VVSENSE= 4V VVCOMP= 3V VHi VLo 3.09 2.76 3.18 2.85 3.26 2.94 V V VSENSE Input Bias Current at 3V IVSEN5V 0 - 1.5 mA VVSENSE= 3V VSENSE Input Bias Current at 1V IVSEN1V 0 - 1 mA VVSENSE= 1V VVCOMPF 0 0.2 0.4 V VVSENSE= 0.5V IVCOMP= 0.5mA Enhanced Dynamic Response VSENSE High Threshold VSENSE Low Threshold VCOMP Voltage during OLP Version 1.1 16 measured at VSENSE Mar 2010 CCM-PFC ICE2PCS06/G Electrical Characteristics 4.3.6 Driver Section Parameter Symbol GATE Low Voltage VGATEL Limit Values min. typ. max. - - 1.2 V VCC =10V IGATE = 5 mA 1.5 V VCC =10V IGATE =20 mA - GATE High Voltage VGATEH Unit Test Condition - 0.4 - V IGATE = 0 A - - 1.0 V IGATE = 20 mA -0.2 0 - V IGATE = -20 mA - 14.8 - V VCC = 25V CL = 2.2nF - 14.8 - V VCC = 19V CL = 2.2nF 7.8 9.2 - V VCC = VVCCoff + 0.2V CL = 2.2nF GATE Rise Time tr - 50 - ns VGate = 2V ...12V CL = 2.2nF GATE Fall Time tf - 40 - ns VGate = 12V ...2V CL = 2.2nF Version 1.1 17 Mar 2010 CCM-PFC ICE2PCS06/G Outline Dimension 5 Outline Dimension PG-DIP-8 Outline Dimension Version 1.1 18 Mar 2010 CCM-PFC ICE2PCS06/G Outline Dimension PG-DSO-8 Outline Dimension Version 1.1 19 Mar 2010 Total Quality Management Qualität hat für uns eine umfassende Bedeutung. Wir wollen allen Ihren Ansprüchen in der bestmöglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualität – unsere Anstrengungen gelten gleichermaßen der Lieferqualität und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Dazu gehört eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenüber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit „Null Fehlern“ zu lösen – in offener Sichtweise auch über den eigenen Arbeitsplatz hinaus – und uns ständig zu verbessern. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is “do everything with zero defects”, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Unternehmensweit orientieren wir uns dabei auch an „top“ (Time Optimized Processes), um Ihnen durch größere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualität zu beweisen. Wir werden Sie überzeugen. http://www.infineon.com Published by Infineon Technologies AG Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality – you will be convinced.