ELPIDA HM5212805FTD-A60

HM5212165FTD-75/A60/B60
HM5212805FTD-75/A60/B60
EO
128M LVTTL interface SDRAM
133 MHz/100 MHz
2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank
PC/133, PC/100 SDRAM
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Description
E0179H10 (Ver. 1.0)
Jul. 16, 2001
Features
•
•
•
•
•
•
•
•
Pr
The HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The HM5212805F is
a 128-Mbit S DRA M orga nized as 4194304-w ord × 8-bit × 4-ba nk. All inputs and outputs ar e re fe rre d to the
rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
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3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
 Sequential (BL = 1/2/4/8/full page)
 Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Byte control by DQM : DQM (HM5212805F)
: DQMU/DQML (HM5212165F)
• Refresh cycles: 4096 refresh cycles/64 ms
This product became EOL in June, 2005.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
• 2 variations of refresh
 Auto refresh
 Self refresh
• Full page burst length capability
 Sequential burst
 Burst stop capability
Ordering Information
Type No.
1
HM5212805FTD-75*1
HM5212805FTD-A60
HM5212805FTD-B60*2
CAS latency
Package
133 MHz
100 MHz
100 MHz
3
2/3
3
400-mil 54-pin plastic TSOP II (TTP-54DA)
133 MHz
100 MHz
100 MHz
3
2/3
3
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HM5212165FTD-75*
HM5212165FTD-A60
HM5212165FTD-B60*2
Frequency
Notes: 1. 100 MHz operation at CAS latency = 2.
2. 66 MHz operation at CAS latency = 2.
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Data Sheet E0179H10
2
HM5212165FTD/HM5212805FTD-75/A60/B60
Pin Arrangement (HM5212165F)
EO
54-pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
L
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
DQML
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
VCC
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
VSS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
uc
od
Pr
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
(Top view)
Pin Description
Pin name
Function
A0 to A13
Address input
 Row address
A0 to A11
 Column address
A0 to A8
Pin name
Function
DQMU/DQML
Input/output mask
CLK
Clock input
CKE
Clock enable
 Bank select address A12/A13 (BS) VCC
DQ0 to DQ15
Data-input/output
CS
Chip select
RAS
Row address strobe command
CAS
Column address strobe command
WE
Write enable
Power for internal circuit
VSS
Ground for internal circuit
VCCQ
Power for DQ circuit
VSS Q
Ground for DQ circuit
NC
No connection
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Data Sheet E0179H10
3
HM5212165FTD/HM5212805FTD-75/A60/B60
Pin Arrangement (HM5212805F)
EO
54-pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
L
VCC
DQ0
VCCQ
NC
DQ1
VSSQ
NC
DQ2
VCCQ
NC
DQ3
VSSQ
NC
VCC
NC
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
VCC
VSS
DQ7
VSSQ
NC
DQ6
VCCQ
NC
DQ5
VSSQ
NC
DQ4
VCCQ
NC
VSS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
uc
od
Pr
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
(Top view)
Pin Description
Pin name
Function
A0 to A13
Address input
 Row address
A0 to A11
 Column address
A0 to A9
Pin name
Function
DQM
Input/output mask
CLK
Clock input
CKE
Clock enable
 Bank select address A12/A13 (BS) VCC
DQ0 to DQ7
Data-input/output
CS
Chip select
RAS
Row address strobe command
CAS
Column address strobe command
WE
Write enable
Power for internal circuit
VSS
Ground for internal circuit
VCCQ
Power for DQ circuit
VSS Q
Ground for DQ circuit
NC
No connection
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Data Sheet E0179H10
4
HM5212165FTD/HM5212805FTD-75/A60/B60
Block Diagram (HM5212165F)
Column address
buffer
Memory array
4096 row
× 512 column
× 8 bit
Bank1
4096 row
× 512 column
× 8 bit
Row decoder
Memory array
Bank2
4096 row
× 512 column
× 8 bit
Column decoder
Bank0
Row decoder
Column decoder
Column decoder
Sense amplifier & I/O bus
Column decoder
Memory array
Row decoder
L
Sense amplifier & I/O bus
Row decoder
Refresh
counter
Row address
buffer
Sense amplifier & I/O bus
Column address
counter
Upper pellet
A0 to A13
A0 to A8
Sense amplifier & I/O bus
EO
A0 to A13
Memory array
Bank3
4096 row
× 512 column
× 8 bit
Pr
Output buffer
DQ8 to DQ15
DQ0 to DQ7
Row decoder
Column address
counter
Row decoder
Column address
buffer
RAS
CAS
WE
DQMU
/DQML
Memory array
Bank2
4096 row
× 512 column
× 8 bit
Row decoder
Row address
buffer
Column decoder
4096 row
× 512 column
× 8 bit
CS
Sense amplifier & I/O bus
Bank1
Column decoder
Memory array
Sense amplifier & I/O bus
4096 row
× 512 column
× 8 bit
Column decoder
Bank0
Sense amplifier & I/O bus
Column decoder
Sense amplifier & I/O bus
Memory array
Output buffer
CKE
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Input buffer
CLK
Control logic &
timing generator
Input buffer
Memory array
Bank3
4096 row
× 512 column
× 8 bit
Row decoder
Refresh
counter
t
Lower pellet
Data Sheet E0179H10
5
HM5212165FTD/HM5212805FTD-75/A60/B60
Block Diagram (HM5212805F)
Column address
buffer
Memory array
4096 row
× 1024 column
× 4 bit
Bank1
4096 row
× 1024 column
× 4 bit
Row decoder
Memory array
Bank2
4096 row
× 1024 column
× 4 bit
Column decoder
Bank0
Row decoder
Column decoder
Column decoder
Sense amplifier & I/O bus
Column decoder
Memory array
Row decoder
L
Sense amplifier & I/O bus
Row decoder
Refresh
counter
Row address
buffer
Sense amplifier & I/O bus
Column address
counter
Upper pellet
A0 to A13
A0 to A9
Sense amplifier & I/O bus
EO
A0 to A13
Memory array
Bank3
4096 row
× 1024 column
× 4 bit
Pr
Output buffer
DQ4 to DQ7
DQ0 to DQ3
Row decoder
Column address
counter
Row decoder
Column address
buffer
RAS
CAS
WE
DQM
Memory array
Bank2
4096 row
× 1024 column
× 4 bit
Row decoder
Row address
buffer
Column decoder
4096 row
× 1024 column
× 4 bit
CS
Sense amplifier & I/O bus
Bank1
Column decoder
Memory array
Sense amplifier & I/O bus
4096 row
× 1024 column
× 4 bit
Column decoder
Bank0
Sense amplifier & I/O bus
Column decoder
Sense amplifier & I/O bus
Memory array
Output buffer
CKE
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Input buffer
CLK
Control logic &
timing generator
Input buffer
Memory array
Bank3
4096 row
× 1024 column
× 4 bit
Row decoder
Refresh
counter
Data Sheet E0179H10
6
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Lower pellet
HM5212165FTD/HM5212805FTD-75/A60/B60
Pin Functions
EO
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising
edge.
CS (in pu t p in ): Whe n C S is Low, the command input cyc le bec omes valid. Whe n C S is High, all inputs ar e
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS , CAS an d WE (in pu t p in s): Although these pin name s ar e the same as those of conve ntiona l DR AMs,
they func tion in a diffe re nt wa y. The se pins def ine oper ation commands (r ea d, wr ite , etc .) depe nding on the
combination of their voltage levels. For details, refer to the command operation section.
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A0 to A11 (in pu t p in s): R ow addr ess (A X0 to AX11) is dete rmined by A0 to A11 leve l at the bank ac tive
command cycle CLK rising edge. Column address (AY0 to AY8; HM5212165F, AY0 to AY9; HM5212805F)
is dete rmined by A0 to A8 or A9 (A 8; HM5212165F , A9; HM5212805F ) leve l at the re ad or wr ite command
cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge
mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at
the precharge command cycle, only the bank that is selected by A12/A13 (BS) is precharged. For details refer to
the command operation section.
Pr
A12/A13 (in pu t p in ): A12/A13 ar e bank sele ct signal (B S ). The memory ar ra y of the HM5212165F , the
HM5212805F is divided into bank 0, bank 1, bank 2 and bank 3. HM5212165F conta in 4096-r ow × 512column × 16-bit. HM5212805F contain 4096-row × 1024-column × 8-bit. If A12 is Low and A13 is Low, bank
0 is sele cted. If A12 is High and A13 is Low, bank 1 is sele cted. If A12 is Low and A13 is High, bank 2 is
selected. If A12 is High and A13 is High, bank 3 is selected.
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CKE (in pu t p in ): This pin dete rmines whe the r or not the next C LK is valid. If C KE is High, the next C LK
rising edge is valid. If C KE is Low, the next C LK rising edge is invalid. This pin is used for powe r-dow n
mode, clock suspend mode and self refresh mode.
DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers.
R ea d oper ation: If DQM, DQMU /D QML is High, the output buff er bec omes High-Z. If the DQM,
DQMU /D QML is Low, the output buff er bec omes Low- Z. (The latenc y of DQM, DQMU /D QML during
reading is 2 clocks.)
Wr ite oper ation: If DQM, DQMU /D QML is High, the pre vious data is held (the new data is not wr itten) . If
DQM, DQMU /D QML is Low, the data is wr itten. (The latenc y of DQM, DQMU /D QML during wr iting is 0
clock.)
DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5212165F, DQ0 to
DQ7; HM5212805F).
VCC and VCC Q (power supply pins): 3.3 V is applied. (V CC is for the internal circuit and VCCQ is for the output
buffer.)
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VSS an d VSS Q (p owe r sup p ly p in s): Gr ound is conne cte d. (V SS is for the interna l cir cuit and VSS Q is for the
output buffer.)
Data Sheet E0179H10
7
HM5212165FTD/HM5212805FTD-75/A60/B60
Command Operation
EO
Command Truth Table
The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins.
CKE
CS
A0
RAS CAS WE A12/A13 A10 to A11
×
H
×
×
×
×
×
×
H
×
L
H
H
H
×
×
×
H
×
L
H
H
L
×
×
×
Column address and read command READ
H
×
L
H
L
H
V
L
V
Read with auto-precharge
H
×
L
H
L
H
V
H
V
Column address and write command WRIT
H
×
L
H
L
L
V
L
V
Write with auto-precharge
H
×
L
H
L
L
V
H
V
H
×
L
L
H
H
V
V
V
Symbol
n-1 n
Ignore command
DESL
H
No operation
NOP
Burst stop in full page
BST
L
Command
READ A
WRIT A
Row address strobe and bank active ACTV
Pr
Precharge select bank
PRE
H
×
L
L
H
L
V
L
×
Precharge all bank
PALL
H
×
L
L
H
L
×
H
×
Refresh
REF/SELF H
V
L
L
L
H
×
×
×
Mode register set
MRS
×
L
L
L
L
V
V
V
H
Note: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input
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Ignore command [DESL]: When this command is set (CS is High), the SDRAM ignore command input at the
clock. However, the internal status is held.
No op erat ion [N OP] : This command is not an exe cution command. Howe ver , the interna l oper ations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (512;
HM5212165F , 1024; HM5212805F )), and is ille gal other wise . Whe n data input/output is vompleted for a full
page of data, it automatically returns to the start address and input/output is preformed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In addition, the
start addr ess of burst re ad is dete rmined by the column addr ess (A Y0 to AY8; HM5212165F , AY0 to AY9;
HM5212805F) and the bank select address (BS). After the read operation, the output buffer becomes High-Z.
Re ad with au to-p re ch arge [R EAD A] : This command automatica lly per forms a pre cha rge oper ation af ter a
burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
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Data Sheet E0179H10
8
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
Colu mn ad dr ess str obe an d wr it e com man d [WR IT ]: This command starts a wr ite oper ation. Whe n the
burst wr ite mode is sele cted, the column addr ess (A Y0 to AY8; HM5212165F , AY0 to AY9; HM5212805F )
and the bank sele ct addr ess (A 12/A 13) bec ome the burst wr ite start addr ess. Whe n the single wr ite mode is
selected, data is only written to the location specified by the column address (AY0 to AY8; HM5212165F, AY0
to AY9; HM5212805F) and the bank select address (A12/A13).
Writ e with au to-p re ch arge [WR IT A] : This command automatica lly per forms a pre cha rge oper ation af ter a
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this
command is illegal.
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Row ad dr ess str obe an d b ank act ivate [A CTV ]: This command ac tiva tes the bank that is sele cted by
A12/A13 (B S ) and dete rmines the row addr ess (A X0 to AX11) . Whe n A12 and A13 ar e Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2
is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13.
If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low
and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Pr
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the
one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register is
spec ified by the addr ess pins (A 0 to A13) at the mode re giste r set cyc le. F or deta ils, re fe r to the mode re giste r
conf iguration. Af te r powe r on, the conte nts of the mode re giste r ar e undef ined, exe cute the mode re giste r set
command to set up the mode register.
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Data Sheet E0179H10
9
HM5212165FTD/HM5212805FTD-75/A60/B60
DQM Truth Table (HM5212165F)
EO
CKE
Command
Symbol
n-1
n
DQMU
DQML
Upper byte (DQ8 to DQ15) write enable/output enable ENBU
H
×
L
×
Lower byte (DQ0 to DQ7) write enable/output enable
H
×
×
L
Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU
H
×
H
×
Lower byte (DQ0 to DQ7) write inhibit/output disable
H
×
×
H
ENBL
MASKL
Note: H: VIH. L: VIL. ×: VIH or VIL.
Write: I DID is needed.
Read: I DOD is needed.
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DQM Truth Table (HM5212805F)
Command
Write inhibit/output disable
Note: H: VIH. L: VIL. ×: VIH or VIL.
Write: I DID is needed.
Read: I DOD is needed.
Symbol
n-1
Pr
Write enable/output enable
CKE
n
DQM
ENB
H
×
L
MASK
H
×
H
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od
The S DRA M ca n mask input/output data by mea ns of DQM, DQMU /D QML. DQMU masks the upper byte
and DQML masks the lower byte (HM5212165F).
Dur ing re ading, the output buff er is set to Low- Z by setting DQM, DQMU /D QML to Low, ena bling data
output. On the other hand, whe n DQM, DQMU /D QML is set to High, the output buff er bec omes High-Z,
disabling data output.
During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set to
High, the pre vious data is held (the new data is not wr itten) . De sir ed data ca n be maske d during burst re ad or
burst write by setting DQM, DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of
the SDRAM operating instructions.
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Data Sheet E0179H10
10
HM5212165FTD/HM5212805FTD-75/A60/B60
CKE Truth Table
EO
CKE
Command
n-1
n
CS
RAS
CAS
WE Address
Active
Clock suspend mode entry
H
L
×
×
×
×
×
Any
Clock suspend
L
L
×
×
×
×
×
Clock suspend
Clock suspend mode exit
L
H
×
×
×
×
×
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
×
Idle
Power down entry
H
L
L
H
H
H
×
H
L
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Self refresh
Power down
L
Current state
Self refresh exit (SELFX)
Power down exit
Note: H: VIH. L: VIL. ×: VIH or VIL.
Pr
Clock susp en d mod e en tr y: The S DRA M ente rs cloc k suspend mode fr om ac tive mode by setting C KE to
Low. If command is input in the cloc k suspend mode entr y cyc le, the command is valid. The cloc k suspend
mode changes depending on the current status (1 clock before) as shown below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the
bank active status.
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RE AD susp en d an d RE AD with Au to-p re ch arge susp en d: The data being output is held (a nd continues to
be output).
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not accepted.
However, the internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspe nd mod e exit : The S DRA M exits fr om cloc k suspend mode by setting C KE to High during the
clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
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Au to-r ef re sh com man d [R EF] : Whe n this command is input fr om the ID LE state, the S DRA M starts autore fre sh oper ation. (The auto- ref resh is the same as the C BR re fre sh of conve ntiona l DR AMs.) Dur ing the
auto- ref resh oper ation, re fre sh addr ess and bank sele ct addr ess ar e gene ra te d inside the S DRA M. F or eve ry
auto-refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the
entire memory. B efor e exe cuting the auto- ref resh command, all the banks must be in the ID LE state. In
addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command
is required after auto-refresh.
Data Sheet E0179H10
11
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self-refresh
operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is
performed internally and automatically, external refresh operations are unnecessary.
Powe r d own mod e en tr y: Whe n this command is exe cute d during the ID LE state, the S DRA M ente rs powe r
down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit.
S elf-r ef re sh exit : Whe n this command is exe cute d during self- re fre sh mode, the S DRA M ca n exit fr om selfrefresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit: When this command is executed at the power down mode, the SDRAM can exit from power
down mode. After exiting from power down mode, the SDRAM enters the IDLE state.
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Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM. The following table assumes that CKE is high.
CS
RAS
CAS
WE
Address
Command
Operation
Precharge
H
×
×
×
×
DESL
Enter IDLE after t RP
L
H
H
H
×
NOP
Enter IDLE after t RP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
ILLEGAL*4
L
L
H
L
BA, A10
PRE, PALL
NOP*6
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
t
uc
od
Idle
Pr
Current state
Data Sheet E0179H10
12
HM5212165FTD/HM5212805FTD-75/A60/B60
Current state
Row active
CS
RAS
CAS
WE
Address
Command
Operation
H
×
×
×
×
DESL
NOP
EO
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
Begin read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Begin write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
×
×
×
×
DESL
Continue burst to end
H
H
H
×
NOP
Continue burst to end
H
H
L
×
BST
Burst stop to full page
L
H
L
H
BA, CA, A10 READ/READ A
L
H
L
L
L
H
L
L
H
L
L
L
L
L
L
H
×
L
H
L
L
Pr
Continue burst read to CAS
latency and New read
L
BA, CA, A10 WRIT/WRIT A
Term burst read/start write
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
BA, A10
PRE, PALL
Term burst read and
Precharge
H
×
REF, SELF
ILLEGAL
L
MODE
MRS
ILLEGAL
×
×
×
H
H
H
×
L
H
H
L
×
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*4
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
uc
od
Read with autoprecharge
L
Read
L
DESL
Continue burst to end and
precharge
NOP
Continue burst to end and
precharge
BST
ILLEGAL
t
Data Sheet E0179H10
13
HM5212165FTD/HM5212805FTD-75/A60/B60
Current state
CS
RAS
CAS
WE
Address
Command
Operation
Write
H
×
×
×
×
DESL
Continue burst to end
EO
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop on full page
L
H
L
H
BA, CA, A10 READ/READ A
Term burst and New read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Term burst and New write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst write and
Precharge*2
L
L
L
H
×
REF, SELF
ILLEGAL
Write with autoprecharge
L
L
MODE
MRS
ILLEGAL
×
×
×
×
DESL
Continue burst to end and
precharge
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
L
H
L
L
L
H
L
L
H
L
L
L
L
L
H
H
Pr
L
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
BA, A10
PRE, PALL
ILLEGAL*4
H
×
REF, SELF
ILLEGAL
L
L
MODE
×
×
×
×
L
H
H
H
×
L
H
H
L
×
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
L
H
H
BA, RA
ACTV
ILLEGAL*5
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*5
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
uc
od
Refresh
(auto-refresh)
L
L
MRS
ILLEGAL
DESL
Enter IDLE after t RC
NOP
Enter IDLE after t RC
BST
Enter IDLE after t RC
t
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL.
The other combinations are inhibit.
2. An interval of t DPL is required between the final valid data input and the precharge command.
3. If t RRD is not satisfied, this operation is illegal.
4. Illegal for same bank, except for another bank.
5. Illegal for all banks.
6. NOP for same bank, except for another bank.
Data Sheet E0179H10
14
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
From PRECHARGE state, command operation
To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM enters the IDLE state after tRP
has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
L
To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The SDRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
Pr
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
uc
od
T o [PR E] , [PA LL ]: The se commands set the S DRA M to pre cha rge mode. (H oweve r, an interva l of tRAS is
required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency,
the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
t
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.
Data Sheet E0179H10
15
HM5212165FTD/HM5212805FTD-75/A60/B60
From READ with AUTO-PRECHARGE state, command operation
EO
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the
SDRAM then enters precharge mode.
T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
L
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
Pr
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the SDRAM
enters precharge mode.
uc
od
T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. )
Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the SDRAM automatically enters the IDLE
state.
t
Data Sheet E0179H10
16
HM5212165FTD/HM5212805FTD-75/A60/B60
Simplified State Diagram
EO
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
L
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
CLOCK
SUSPEND
CKE_
CKE
Pr
ROW
ACTIVE
BST
(on full page)
BST
(on full page)
WRITE
Write
WRITE
SUSPEND
CKE_
WRITE
CKE
WRITE
WITH AP
Read
CKE_
READ
CKE
uc
od
WRITEA
CKE_
READA
CKE
CKE
PRECHARGE
POWER
ON
READ
SUSPEND
READ
WITH AP
PRECHARGE
CKE_
POWER
APPLIED
READ
WITH
AP
WRITE
READ
WITH AP
WRITE
WITH AP
WRITEA
SUSPEND
READ
WRITE
WITH
AP
READ
READA
SUSPEND
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
t
Data Sheet E0179H10
17
HM5212165FTD/HM5212805FTD-75/A60/B60
Mode Register Configuration
EO
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode
register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9, A8: (OPCODE ): The S DRA M has two types of wr ite modes. One is the burst
write mode, and the other is the single write mode. These bits specify write mode.
B ur st re ad an d b ur st wr it e: B urst wr ite is per forme d for the spec ified burst length starting fr om the column
address specified in the write cycle.
B ur st re ad an d single wr it e: Da ta is only wr itten to the column addr ess spec ified during the wr ite cyc le,
regardless of the burst length.
L
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CAS latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A13
A12
A11
A10
A9
A8
OPCODE
Pr
A2, A1, A0: (BL): These pins specify the burst length.
A7
A6
0
LMODE
0
0
0
0
0
0
0
R
0
0
1
R
0
1
0
2
0
1
1
3
1
X
X
R
A9
A8
0
0
X
X
X
X
0
1
X
X
X
X
1
0
X
X
X
X
1
1
Write mode
A2
BT
0 Sequential
1
Burst read and single write
R
A3
A1
A0
BL
A3 Burst type
Burst read and burst write
R
A4
Burst length
uc
od
A6 A5 A4 CAS latency
A13 A12 A11 A10
A5
Interleave
A2 A1 A0
BT=0
BT=1
0
0
0
1
1
0
0
1
2
2
4
8
0
1
0
4
0
1
1
8
1
0
0
R
R
1
0
1
R
R
1
1
0
R
R
1
1
1
F.P.
R
F.P. = Full Page (512: HM5212165)
(1024: HM5212805)
R is Reserved (inhibit)
X: 0 or 1
t
Data Sheet E0179H10
18
HM5212165FTD/HM5212805FTD-75/A60/B60
Burst Sequence
EO
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequential Interleave
Starting Ad. Addressing(decimal)
A1
A0
Sequential
Interleave
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Burst length = 8
Addressing(decimal)
Starting Ad.
A1
0
0
0
0
0
1
0
1
1
0
L
A2
A0 Sequential
Interleave
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
t
uc
od
Pr
1
1
Data Sheet E0179H10
19
HM5212165FTD/HM5212805FTD-75/A60/B60
Operation of the SDRAM
EO
Read/Write Operations
B ank act ive: B efor e exe cuting a re ad or wr ite oper ation, the cor re sponding bank and the row addr ess must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the
status of the A12/A13 pin, and the row addr ess (A X0 to AX11) is ac tiva ted by the A0 to A11 pins at the bank
active command cycle. An interval of tRCD is required between the bank active command input and the following
read/write command input.
L
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the
(C AS latenc y-1) cyc le af ter re ad command set. HM5212165F , HM5212805F ca n per form a burst re ad
operation.
CAS Latency
CLK
t RCD
Command
Address
Dout
ACTV
Row
CL = 2
CL = 3
READ
Column
out 0
uc
od
Pr
The burst length ca n be set to 1, 2, 4, 8 or full-pa ge (512; HM5212165F , 1024; HM5212805F ). The start
addr ess for a burst re ad is spec ified by the column addr ess (A Y0 to AY8; HM5212165F , AY0 to AY9;
HM5212805F) and the bank select address (A12/A13) at the read command set cycle. In a read operation, data
output starts af ter the number of cloc ks spec ified by the C AS latenc y. The C AS latenc y ca n be set to 2 or 3.
Whe n the burst length is 1, 2, 4, 8, the Dout buff er automatica lly bec omes High-Z at the next cloc k af ter the
successive burst-length data has been output. The CAS latency and burst length must be specified at the mode
register.
out 1
out 2
out 3
out 0
out 1
out 2
out 3
CL = CAS latency
Burst Length = 4
t
Data Sheet E0179H10
20
HM5212165FTD/HM5212805FTD-75/A60/B60
Burst Length
EO
CLK
t RCD
Command
ACTV
READ
Address
Row
Column
out 0
BL = 1
out 0 out 1
BL = 2
Dout
out 0 out 1 out 2 out 3
BL = 4
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
L
BL = 8
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
BL = full page
out 0-1
out 0
out 1
BL : Burst Length
CAS Latency = 2
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8)
of the mode register.
Pr
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts
in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to
1, 2, 4, 8, and full-pa ge, like burst re ad oper ations. The wr ite start addr ess is spec ified by the column addr ess
(AY0 to AY8; HM5212165F, AY0 to AY9; HM5212805F) and the bank select address (A12/A13) at the write
command set cycle.
t RCD
Command
ACTV
WRIT
Address
Row
Column
BL = 1
in 0
in 0
in 1
in 0
in 1
in 2
in 3
in 0
in 1
in 2
in 3
in 4
in 5
in 0
in 1
in 2
in 3
in 4
in 5
BL = 2
Din
BL = 4
BL = 8
BL = full page
uc
od
CLK
in 6
in 7
in 6
in 7
in 8
in 0-1
in 0
in 1
CAS Latency = 2, 3
t
Data Sheet E0179H10
21
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
2. S in gle wr it e: A single wr ite oper ation is ena bled by setting OP CO DE (A 9, A8) to (1, 0). In a single wr ite
oper ation, data is only wr itten to the column addr ess (A Y0 to AY8; HM5212165F , AY0 to AY9;
HM5212805F) and the bank select address (A12/A13) specified by the write command set cycle without regard
to the burst length setting. (The latency of data input is 0 clock).
CLK
Command
Row
Column
L
Auto Precharge
WRIT
ACTV
Address
Din
t RCD
in 0
Pr
Re ad with au to-p re ch arge : In this oper ation, since pre cha rge is automatica lly per forme d af ter completing a
re ad oper ation, a pre cha rge command nee d not be exe cute d af ter ea ch re ad oper ation. The command exe cute d
for the same bank after the execution of this command must be the bank active (ACTV) command. In addition,
an interval defined by lAPR is required before execution of the next command.
CAS latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
CLK
CL=2 Command
ACTV
READ A
lRAS
DQ (input)
uc
od
Burst Read (Burst Length = 4)
ACTV
out0
out1
out2
out3
lAPR
CL=3 Command
ACTV
READ A
lRAS
DQ (input)
ACTV
out0
out1
out2
out3
lAPR
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge "
".
t
Data Sheet E0179H10
22
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
Write with auto-precharge: In this operation, since precharge is automatically performed after completing a
burst write or single write operation, a precharge command need not be executed after each write operation. The
command exe cute d for the same bank af ter the exe cution of this command must be the bank ac tive (A CTV )
command. In addition, an interva l of lAP W is re quired betwe en the fina l valid data input and input of next
command.
Burst Write (Burst Length = 4)
CLK
ACTV
ACTV
WRIT A
L
Command
IRAS
DQ (input)
in0
in1
in2
in3
lAPW
Pr
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
Single Write
Command
ACTV
WRIT A
IRAS
DQ (input)
in
uc
od
CLK
ACTV
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
t
Data Sheet E0179H10
23
HM5212165FTD/HM5212805FTD-75/A60/B60
Full-page Burst Stop
EO
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a
full-pa ge burst. The B ST command sets the output buff er to High-Z and stops the full-pa ge burst re ad. The
timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST
command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8.
CAS latency
BST to valid data
BST to high impedance
2
1
2
3
2
3
L
CAS Latency = 2, Burst Length = full page
CLK
DQ (output)
out
out
Pr
BST
Command
out
out
out
out
l BSH = 2 clocks
l BSR = 1 clock
CLK
BST
Command
DQ (output)
uc
od
CAS Latency = 3, Burst Length = full page
out
out
out
out
out
out
l BSR = 2 clocks
out
l BSH = 3 clocks
t
Data Sheet E0179H10
24
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
B ur st stop com man d at b ur st wr it e: The burst stop command (B S T command) is used to stop data input
during a full-pa ge burst wr ite . No data is wr itten in the same cloc k as the B ST command, and in subseque nt
cloc ks. In addition, the B ST command is only valid during full-pa ge burst mode, and is ille gal with burst
lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command.
Burst Length = full page
CLK
Command
PRE/PALL
L
DQ (input)
BST
in
in
t DPL
I BSW = 0 clock
t
uc
od
Pr
Data Sheet E0179H10
25
HM5212165FTD/HM5212805FTD-75/A60/B60
Command Intervals
EO
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address of
the same bank as the preceding read command execution, the second read can be performed after an interval of
no less than 1 cloc k. Eve n whe n the first command is a burst re ad that is not yet finished, the data re ad by the
second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
Command
Address
ACTV
Row
BS
L
CLK
READ
READ
Column A Column B
Dout
out A0 out B0 out B1 out B2 out B3
Pr
Bank0
Active
Column =A Column =B Column =A Column =B
Dout
Read
Read
Dout
CAS Latency = 3
Burst Length = 4
Bank 0
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges on same bank, conse cutive re ad
commands ca nnot be exe cute d; it is nec essa ry to sepa ra te the two re ad commands with a pre cha rge command
and a bank-active command.
READ to READ Command Interval (different bank)
CLK
Command
ACTV
ACTV
READ READ
Address
Row 0
Row 1
Column A Column B
BS
Dout
uc
od
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than
1 cloc k, provide d that the other bank is in the bank- ac tive state. Eve n whe n the first command is a burst re ad
that is not yet finished, the data read by the second command will be valid.
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Bank3 Bank0 Bank3
Active Read Read
Bank0 Bank3
Dout
Dout
CAS Latency = 3
Burst Length = 4
t
Data Sheet E0179H10
26
HM5212165FTD/HM5212805FTD-75/A60/B60
Write command to Write command interval:
EO
1. Same bank, same ROW address: When another write command is executed at the same ROW address of
the same bank as the pre ce ding wr ite command, the sec ond wr ite ca n be per forme d af ter an interva l of no less
than 1 clock. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CLK
Command
Row
BS
Din
WRIT
Column A Column B
in A0
Bank0
Active
WRIT
L
Address
ACTV
in B0
in B1
in B2
in B3
Column =A Column =B
Write
Write
Pr
Burst Write Mode
Burst Length = 4
Bank 0
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands
ca nnot be exe cute d; it is nec essa ry to sepa ra te the two wr ite commands with a pre cha rge command and a
bank-active command.
WRITE to WRITE Command Interval (different bank)
CLK
Command
ACTV
Address
Row 0
ACTV WRIT
Row 1
WRIT
Column A Column B
BS
Din
in A0
Bank0
Active
in B0
Bank3 Bank0 Bank3
Active Write Write
in B1
in B2
uc
od
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than
1 cloc k, provide d that the other bank is in the bank- ac tive state. In the ca se of burst wr ite , the sec ond wr ite
command has priority.
in B3
Burst Write Mode
Burst Length = 4
t
Data Sheet E0179H10
27
HM5212165FTD/HM5212805FTD-75/A60/B60
Read command to Write command interval:
EO
1. S ame b ank , same ROW ad dr ess: Whe n the wr ite command is exe cute d at the same R OW addr ess of the
same bank as the preceding read command, the write command can be performed after an interval of no less than
1 cloc k. Howe ver , DQM, DQMU /D QML must be set High so that the output buff er bec omes High-Z bef ore
data input.
READ to WRITE Command Interval (1)
CLK
Command
CL=3
L
DQM, CL=2
DQMU
/DQML
READ WRIT
in B0
Din
in B1
in B2
in B3
High-Z
Pr
Dout
Burst Length = 4
Burst write
READ to WRITE Command Interval (2)
CLK
Command
CL=2
Dout
CL=3
Din
WRIT
uc
od
DQM,
DQMU/DQML
READ
2 clock
High-Z
High-Z
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active
command.
3. Diff er en t b ank : Whe n the bank cha nges, the wr ite command ca n be per forme d af ter an interva l of no less
than 1 cycle, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must be
set High so that the output buffer becomes High-Z before data input.
t
Data Sheet E0179H10
28
HM5212165FTD/HM5212805FTD-75/A60/B60
Write command to Read command interval:
EO
1. S ame b ank , same ROW ad dr ess: Whe n the re ad command is exe cute d at the same R OW addr ess of the
same bank as the preceding write command, the read command can be performed after an interval of no less than
1 cloc k. Howe ver , in the ca se of a burst wr ite , data will continue to be wr itten until one cloc k bef ore the re ad
command is executed.
WRITE to READ Command Interval (1)
CLK
Command
Din
READ
L
DQM,
DQMU/DQML
WRIT
in A0
Dout
out B1
out B0
out B3
Burst Write Mode
CAS Latency = 2
Burst Length = 4
Bank 0
CAS Latency
Column = B
Dout
Pr
Column = A
Write
Column = B
Read
out B2
WRITE to READ Command Interval (2)
CLK
WRIT
READ
DQM,
DQMU/DQML
Din
in A0
in A1
Dout
uc
od
Command
out B0
Column = A
Write
out B1
CAS Latency
Column = B
Read
Column = B
Dout
out B2
out B3
Burst Write Mode
CAS Latency = 2
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot
be exe cute d; it is nec essa ry to sepa ra te the two commands with a pre cha rge command and a bank- ac tive
command.
t
3. Diff er en t b ank : Whe n the bank cha nges, the re ad command ca n be per forme d af ter an interva l of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data
will continue to be written until one clock before the read command is executed (as in the case of the same bank
and the same address).
Data Sheet E0179H10
29
HM5212165FTD/HM5212805FTD-75/A60/B60
Read with auto precharge to Read command interval
EO
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is
exe cute d. Eve n whe n the first re ad with auto- prec har ge is a burst re ad that is not yet finished, the data re ad by
the sec ond command is valid. The interna l auto- prec har ge of one bank starts at the next cloc k of the sec ond
command.
Read with Auto Precharge to Read Command Interval (Different bank)
CLK
Command
Dout
READ
L
BS
READ A
bank0
Read A
out A0
out A1
out B0
bank3
Read
out B1
CAS Latency = 3
Burst Length = 4
".
Pr
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
uc
od
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is
executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one
bank starts at the next clock of the second command .
Write with Auto Precharge to Write Command Interval (Different bank)
CLK
Command
WRIT A
WRIT
BS
Din
in A0
bank0
Write A
in A1
in B0
bank3
Write
in B1
Note: Internal auto-precharge starts at the timing indicated by "
in B2
in B3
Burst Length = 4
".
2. Same bank: The consecutive write command (the same bank) is illegal.
t
Data Sheet E0179H10
30
HM5212165FTD/HM5212805FTD-75/A60/B60
Read with auto precharge to Write command interval
EO
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is
exe cute d. Howe ver , DQM, DQMU /D QML must be set High so that the output buff er bec omes High-Z bef ore
data input. The internal auto-precharge of one bank starts at the next clock of the second command.
Read with Auto Precharge to Write Command Interval (Different bank)
CLK
Command
READ A
WRIT
BS
L
DQM,
DQMU/DQML
CL = 2
CL = 3
Din
in B0
Dout
in B1
in B2
in B3
High-Z
Pr
bank0
Read A
Burst Length = 4
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
".
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
t
uc
od
Data Sheet E0179H10
31
HM5212165FTD/HM5212805FTD-75/A60/B60
Write with auto precharge to Read command interval
EO
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is
exe cute d. Howe ver ,in ca se of a burst wr ite , data will continue to be wr itten until one cloc k bef ore the re ad
command is executed. The internal auto-precharge of one bank starts at the next clock of the second command.
Write with Auto Precharge to Read Command Interval (Different bank)
CLK
Command
WRIT A
READ
BS
Din
Dout
L
DQM,
DQMU/DQML
in A0
out B1
bank3
Read
Pr
bank0
Write A
out B0
Note: Internal auto-precharge starts at the timing indicated by "
out B2
out B3
CAS Latency = 3
Burst Length = 4
".
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
t
uc
od
Data Sheet E0179H10
32
HM5212165FTD/HM5212805FTD-75/A60/B60
Read command to Precharge command interval (same bank):
EO
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after
the cloc ks def ined by lHZ P, ther e is a ca se of interr uption to burst re ad data output will be interr upte d, if the
precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be
assured as an interval from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CAS Latency = 2, Burst Length = 4
Command
Dout
L
CLK
READ
out A0
CAS Latency = 3, Burst Length = 4
CLK
Command
READ
out A1
out A2
out A3
l EP = -1 cycle
Pr
CL=2
PRE/PALL
PRE/PALL
out A0
CL=3
uc
od
Dout
out A1
out A2
out A3
l EP = -2 cycle
t
Data Sheet E0179H10
33
HM5212165FTD/HM5212805FTD-75/A60/B60
READ to PRECHARGE Command Interval (same bank): To stop output data
EO
CAS Latency = 2, Burst Length = 1, 2, 4, 8, full page burst
CLK
Command
READ
PRE/PALL
Dout
High-Z
out A0
l HZP =2
L
CAS Latency = 3, Burst Length = 1, 2, 4, 8, full page burst
CLK
Command
READ
PRE/PALL
Pr
High-Z
Dout
out A0
l HZP =3
t
uc
od
Data Sheet E0179H10
34
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
Writ e com man d to Pr ech arge com man d int er val (sam e b ank ): Whe n the pre cha rge command is exe cute d
for the same bank as the write command that preceded it, the minimum interval between the two commands is 1
cloc k. Howe ver , if the burst wr ite oper ation is unfinished, the input data must be maske d by mea ns of DQM,
DQMU/DQML for assurance of the clock defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank)
Burst Length = 4 (To stop write operation)
CLK
Command
Din
PRE/PALL
L
DQM,
DQMU/DQML
WRIT
tDPL
Pr
CLK
Command
PRE/PALL
WRIT
DQM,
DQMU/DQML
Din
in A0
in A1
Burst Length = 4 (To write all data)
CLK
Command
PRE/PALL
WRIT
DQM,
DQMU/DQML
Din
in A0
uc
od
tDPL
in A1
in A2
in A3
tDPL
t
Data Sheet E0179H10
35
HM5212165FTD/HM5212805FTD-75/A60/B60
Bank active command interval:
EO
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
2. In the case of different bank-active commands: The interval between the two bank-active commands must
be no less than tRRD.
Bank Active to Bank Active for Same Bank
CLK
ACTV
Address
ROW
BS
ACTV
L
Command
ROW
t RC
Pr
Bank 0
Active
Bank 0
Active
Bank Active to Bank Active for Different Bank
CLK
Address
ACTV
ACTV
ROW:0
ROW:1
BS
t RRD
Bank 0
Active
uc
od
Command
Bank 3
Active
t
Data Sheet E0179H10
36
HM5212165FTD/HM5212805FTD-75/A60/B60
Mod e re gister set to B ank -ac tive com man d int er val: The interva l betwe en setting the mode re giste r and
executing a bank-active command must be no less than lRSA .
EO
CLK
Command
Address
MRS
ACTV
CODE
BS & ROW
L
I RSA
Mode
Register Set
DQM Control
Bank
Active
Pr
The DQM mask the DQ data . The DQMU and DQML mask the upper and lower bytes of the DQ data ,
respectively. The timing of DQMU/DQML is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting DQM,
DQMU /D QML to Low, the output buff er bec omes Low- Z, ena bling data output. B y setting DQM,
DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However,
internal reading operations continue. The latency of DQM, DQMU/DQML during reading is 2 clocks.
t
uc
od
Writing: Input data can be masked by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low, data
ca n be wr itten. In addition, whe n DQM, DQMU /D QML is set to High, the cor re sponding data is not wr itten,
and the previous data is held. The latency of DQM, DQMU/DQML during writing is 0 clock.
Data Sheet E0179H10
37
HM5212165FTD/HM5212805FTD-75/A60/B60
Reading
EO
CLK
DQM,
DQMU/DQML
DQ (output)
High-Z
out 0
out 1
out 3
lDOD = 2 Latency
L
Writing
DQM,
DQMU/DQML
DQ (input)
Pr
;
;;
CLK
in 0
in 1
in 3
l DID = 0 Latency
t
uc
od
Data Sheet E0179H10
38
HM5212165FTD/HM5212805FTD-75/A60/B60
Refresh
EO
Au to-r ef re sh : All the banks must be pre cha rged bef ore exe cuting an auto- ref resh command. S inc e the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW
addr esses to be re fre shed, exte rnal addr ess spec ifica tion is not re quired. The re fre sh cyc le is 4096 cyc les/64
ms. (4096 cyc les ar e re quired to re fre sh all the R OW addr esses. ) The output buff er bec omes High-Z af ter
auto- ref resh start. In addition, since a pre cha rge has bee n complete d by an interna l oper ation af ter the autorefresh, an additional precharge operation by the precharge command is not required.
L
S elf-r ef re sh : Af te r exe cuting a self- re fre sh command, the self- re fre sh oper ation continues while C KE is held
Low. Dur ing self- re fre sh oper ation, all R OW addr esses ar e re fre shed by the interna l re fre sh time r. A selfre fre sh is ter minated by a self- re fre sh exit command. B efor e and af ter self- re fre sh mode, exe cute auto- ref resh
to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to all
refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 µs after exiting
from self-refresh mode.
Pr
Others
Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power
down mode, powe r consumption is suppre sse d by dea ctivating the input initia l cir cuit. P ower down mode
continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down
mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed.
uc
od
Clock susp en d mod e: B y driving C KE to Low during a bank- ac tive or re ad/wr ite oper ation, the S DRA M
ente rs cloc k suspend mode. Dur ing cloc k suspend mode, exte rnal input signals ar e ignore d and the interna l
state is maintained. Whe n C KE is drive n High, the S DRA M ter mina te s cloc k suspend mode, and command
input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence: The SDRAM should be gone on the following sequence with power up.
The CLK, CKE, CS, DQM, DQMU/DQML and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQM, DQMU/DQML is driven to high between power stabilizes and the initialization sequence.
This S DRA M has VCC cla mp diodes for C LK, C KE, C S, DQM, DQMU /D QML and DQ pins. If these pins go
high before power up, the large current flows from these pins to VCC through the diodes.
t
Initialization sequence: When 200 µs or more has past after the above power-up sequence, all banks must be
precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF).
S et the mode re giste r set command (MR S) to initia liz e the mode re giste r. We re commend that by kee ping
DQM, DQMU /D QML and C KE to High, the output buff er bec omes High-Z during Initializa tion seque nce , to
avoid DQ bus contention on memory system formed with a number of device.
Data Sheet E0179H10
39
HM5212165FTD/HM5212805FTD-75/A60/B60
Initialization sequence
Power up sequence
EO
VCC, VCCQ
100 µs
200 µs
0V
CKE, DQM,
DQMU/DQML
Low
CLK
Low
CS, DQ
Low
Power stabilize
L
Absolute Maximum Ratings
Symbol
Value
Unit
Note
Voltage on any pin relative to VSS
VT
–0.5 to VCC + 0.5
(≤ 4.6 (max))
V
1
VCC
–0.5 to +4.6
V
1
Iout
50
mA
PT
1.0
W
Topr
0 to +70
°C
Tstg
–55 to +125
°C
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Note:
1. Respect to VSS .
DC Operating Conditions (Ta = 0 to +70˚C)
uc
od
Pr
Parameter
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
VCC, VCCQ
3.0
3.6
V
1, 2
VSS , VSS Q
0
0
V
3
Input high voltage
VIH
2.0
VCC + 0.3
V
1, 4
Input low voltage
VIL
–0.3
0.8
V
1, 5
Notes: 1.
2.
3.
4.
5.
All voltage referred to VSS .
The supply voltage with all VCC and VCCQ pins must be on the same level.
The supply voltage with all VSS and VSS Q pins must be on the same level.
VIH (max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.
VIL (min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS .
t
Data Sheet E0179H10
40
HM5212165FTD/HM5212805FTD-75/A60/B60
VIL/VIH Clamp
EO
This SDRAM has VIL and VIH clamp for CLK, CKE, CS, DQM and DQ pins.
Minimum VIL Clamp Current
VIL (V)
I (mA)
–2
–32
–1.8
–25
–1.6
–19
–1.4
–13
L
–1.2
–1
–0.9
–0.8
–0.6
–8
–4
–2
–0.6
0
Pr
–0.4
0
–0.2
0
0
0
I (mA)
–10
–15
–20
–25
–30
–35
–1.5
–1
–0.5
0
uc
od
0
–2
–5
VIL (V)
t
Data Sheet E0179H10
41
HM5212165FTD/HM5212805FTD-75/A60/B60
Minimum VIH Clamp Current (referred to VCC)
I (mA)
VCC + 2
10
VCC + 1.8
8
VCC + 1.6
5.5
VCC + 1.4
3.5
VCC + 1.2
1.5
VCC + 1
0.3
VCC + 0.8
0
VCC + 0.6
0
L
EO
VIH (V)
VCC + 0.4
VCC + 0.2
VCC + 0
I (mA)
8
6
4
2
0
VCC + 0.5
VCC + 1
uc
od
0
VCC + 0
0
Pr
10
0
VCC + 1.5
VCC + 2
VIH (V)
t
Data Sheet E0179H10
42
HM5212165FTD/HM5212805FTD-75/A60/B60
IOL/IOH Characteristics
EO
Output Low Current (I OL)
I OL
Vout (V)
Min (mA)
Max (mA)
0
0
0
0.4
27
71
0.65
41
108
0.85
51
134
1
58
70
188
72
194
75
203
1.8
77
209
1.95
77
212
3
80
3.45
81
1.4
1.5
250
Pr
151
1.65
L
I OL
220
223
IOL (mA)
150
uc
od
200
min
max
100
50
0
0
0.5
1
1.5
2
Vout (V)
2.5
3
3.5
t
Data Sheet E0179H10
43
HM5212165FTD/HM5212805FTD-75/A60/B60
Output High Current (I OH ) (Ta = 0 to +70˚C, VCC, VCCQ = 3.0 V to 3.45 V, VSS , VSS Q = 0 V)
I OH
Vout (V)
Min (mA)
Max (mA)
3.45
—
–3
3.3
—
–28
3
0
–75
2.6
–21
–130
2.4
–34
–154
2
–59
–197
1.8
–67
–227
L
EO
I OH
1.65
1.5
1.4
1
0
0.5
–78
–270
–81
–285
–89
–345
–93
–503
1
1.5
2
–200
2.5
3
3.5
uc
od
IOH (mA)
–100
0
–248
Pr
0
–73
min
max
–300
–400
–500
–600
Vout (V)
t
Data Sheet E0179H10
44
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
DC Char acter istics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
(HM5212165F)
HM5212165F
-75
-A60
-B60
Parameter
Symbol
Min
Max Min
Max Min
Max Unit
Test conditions
Notes
Operating current
(CAS latency = 2)
—
120
—
120
—
120
mA
Burst length = 1
t RC = min
1, 2, 3
I CC1
(CAS latency = 3)
I CC1
—
120
—
120
—
120
mA
—
3
—
3
—
3
mA
CKE = VIL, t CK = 12 ns 6
Standby current in power I CC2P
down
L
—
2
—
2
—
2
mA
CKE = VIL, t CK = ∞
7
Standby current in non I CC2N
power down
—
15
—
15
—
15
mA
CKE, CS = VIH,
t CK = 12 ns
4
Standby current in non I CC2NS
power down
(input signal stable)
—
10
—
10
—
10
mA
CKE = VIH, t CK = ∞
9
Active standby current in I CC3P
power down
—
Active standby current in I CC3PS
power down
(input signal stable)
—
Active standby current in I CC3N
non power down
—
Active standby current in I CC3NS
non power down (input
signal stable)
Pr
Standby current in power I CC2PS
down
(input signal stable)
—
6
—
6
mA
CKE = VIL, t CK = 12 ns 1, 2, 6
5
—
5
—
5
mA
CKE = VIL, t CK = ∞
2, 7
35
—
35
—
35
mA
CKE, CS = VIH,
t CK = 12 ns
1, 2, 4
—
24
—
24
—
150
—
120
I CC4
—
150
—
120
Refresh current
I CC5
—
220
—
220
Self refresh current
I CC6
—
2
—
2
Input leakage current
I LI
–1
1
–1
1
Burst operating current
(CAS latency = 2)
I CC4
(CAS latency = 3)
Output leakage current I LO
–1.5 1.5
–1.5 1.5
Output high voltage
VOH
2.4
—
2.4
—
Output low voltage
VOL
—
0.4
—
0.4
uc
od
6
—
24
mA
CKE = VIH, t CK = ∞
2, 9
—
120
mA
t CK = min, BL = 4
1, 2, 5
—
120
mA
—
220
mA
t RC = min
3
—
2
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
–1
1
µA
0 ≤ Vin ≤ VCC
–1.5 1.5
µA
0 ≤ Vout ≤ VCC
DQ = disable
2.4
—
V
I OH = –4 mA
—
0.4
V
I OL = 4 mA
t
Data Sheet E0179H10
45
HM5212165FTD/HM5212805FTD-75/A60/B60
DC Char acter istics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
(HM5212805F)
EO
HM5212805F
-75
-A60
-B60
Symbol
Min
Max Min
Max Min
Max Unit
Test conditions
Notes
Operating current
(CAS latency = 2)
—
120
—
120
—
120
mA
Burst length = 1
t RC = min
1, 2, 3
I CC1
(CAS latency = 3)
I CC1
—
120
—
120
—
120
mA
Standby current in power I CC2P
down
—
3
—
3
—
3
mA
CKE = VIL, t CK = 12 ns 6
Standby current in power I CC2PS
down
(input signal stable)
—
2
—
2
—
2
mA
CKE = VIL, t CK = ∞
7
Standby current in non I CC2N
power down
—
15
—
15
—
15
mA
CKE, CS = VIH,
t CK = 12 ns
4
Standby current in non I CC2NS
power down
(input signal stable)
—
10
—
10
—
10
mA
CKE = VIH, t CK = ∞
9
Active standby current in I CC3P
power down
—
Active standby current in I CC3PS
power down
(input signal stable)
—
Active standby current in I CC3N
non power down
—
Active standby current in I CC3NS
non power down (input
signal stable)
L
Parameter
Pr
—
6
—
6
mA
CKE = VIL, t CK = 12 ns 1, 2, 6
5
—
5
—
5
mA
CKE = VIL, t CK = ∞
2, 7
35
—
35
—
35
mA
CKE, CS = VIH,
t CK = 12 ns
1, 2, 4
—
24
—
24
—
140
—
110
I CC4
—
140
—
110
Refresh current
I CC5
—
220
—
220
Self refresh current
I CC6
—
2
—
2
Input leakage current
I LI
–1
1
–1
1
Burst operating current
(CAS latency = 2)
I CC4
(CAS latency = 3)
Output leakage current I LO
–1.5 1.5
–1.5 1.5
Output high voltage
VOH
2.4
—
2.4
—
Output low voltage
VOL
—
0.4
—
0.4
uc
od
6
—
24
mA
CKE = VIH, t CK = ∞
2, 9
—
110
mA
t CK = min, BL = 4
1, 2, 5
—
110
mA
—
220
mA
t RC = min
3
—
2
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
–1
1
µA
0 ≤ Vin ≤ VCC
–1.5 1.5
µA
0 ≤ Vout ≤ VCC
DQ = disable
2.4
—
V
I OH = –4 mA
—
0.4
V
I OL = 4 mA
t
Data Sheet E0179H10
46
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
Notes: 1. I CC depends on output load condition when the device is selected. I CC (max) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
9. Input signals are VIH or VIL fixed.
Parameter
Input capacitance (CLK)
Input capacitance (Input)
Output capacitance (DQ)
Symbol
Min
Max
Unit
Notes
CI1
2.5
7
pF
1, 2, 4
CI2
2.5
7
pF
1, 2, 4
CO
4
8
pF
1, 2, 3, 4
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
DQM, DQMU/DQML = VIH to disable Dout.
This parameter is sampled and not 100% tested.
t
uc
od
Pr
Notes: 1.
2.
3.
4.
L
Capacitance (Ta = 25°C, VCC, VCCQ = 3.3 V ± 0.3 V)
Data Sheet E0179H10
47
HM5212165FTD/HM5212805FTD-75/A60/B60
AC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
EO
HM5212165F/
HM5212805F
-75
-A60
-B60
Symbol
PC/100
Symbol Min
Max
Min
Max
Min
Max
Unit Notes
System clock cycle time
(CAS latency = 2)
t CK
Tclk
10
—
10
—
15
—
ns
(CAS latency = 3)
t CK
Tclk
7.5
—
10
—
10
—
ns
CLK high pulse width
t CKH
Tch
2.5
—
3
—
3
—
ns
1
CLK low pulse width
t CKL
Tcl
2.5
—
3
—
3
—
ns
1
t AC
Tac
—
6
—
6
—
8
ns
1, 2
t AC
Tac
—
5.4
—
6
—
6
ns
t OH
Toh
2.7
—
3
—
3
—
ns
1, 2
2
—
2
—
2
—
ns
1, 2, 3
Access time from CLK
(CAS latency = 2)
(CAS latency = 3)
Data-out hold time
L
Parameter
t LZ
CLK to Data-out high
impedance
(CAS latency = 2, 3)
t HZ
Input setup time
Pr
CLK to Data-out low
impedance
1
5.4
—
6
—
6
ns
1, 4
t AS , t CS, t DS, Tsi
t CES
1.5
—
2
—
2
—
ns
1, 5, 6
CKE setup time for power
down exit
t CESP
1.5
—
2
—
2
—
ns
1
Input hold time
t AH, t CH, t DH, Thi
t CEH
0.8
Ref/Active to Ref/Active
command period
t RC
Trc
67.5 —
Active to Precharge
command period
t RAS
Tras
45
Active command to column
command (same bank)
t RCD
Trcd
20
Precharge to active
command period
t RP
Trp
20
Write recovery or data-in to
precharge lead time
t DPL
Tdpl
10
Active (a) to Active (b)
command period
t RRD
Trrd
15
Tpde
Transition time (rise and fall) t T
1
Refresh period
—
t REF
uc
od
—
—
1
—
1
—
ns
1, 5
70
—
70
—
ns
1
120000 50
120000 50
120000 ns
1
—
20
—
20
—
ns
1
—
20
—
20
—
ns
1
—
10
—
10
—
ns
1
—
20
—
20
—
ns
1
5
1
5
1
5
ns
64
—
64
—
64
ms
t
Data Sheet E0179H10
48
HM5212165FTD/HM5212805FTD-75/A60/B60
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V.
Access time is measured at 1.5 V. Load condition is CL = 50 pF.
t LZ (min) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES define CKE setup time to CLK rising edge except power down exit command.
t AS /tAH: Address t CS/tCH: CS, RAS, CAS, WE, DQM, DQMU/DQML
t DS/tDH: Data-in t CES/tCEH : CKE
EO
Notes: 1.
2.
3.
4.
5.
6.
Test Conditions
• Input and output timing reference levels: 1.5 V
L
• Input waveform and output load: See following figures
2.4 V
input
0.4 V
I/O
2.0 V
0.8 V
CL
T
Pr
t
tT
t
uc
od
Data Sheet E0179H10
49
HM5212165FTD/HM5212805FTD-75/A60/B60
Relationship Between Frequency and Minimum Latency
EO
HM5212165F/
HM5212805F
Parameter
-75
-A60/B60
Frequency (MHz)
133
100
7.5
10
Notes
PC/100
Symbol
tCK (ns)
Symbol
Active command to column command
(same bank)
lRCD
3
2
1
Active command to active command
(same bank)
lRC
9
7
= [lRAS+ lRP]
1
L
Active command to precharge command
(same bank)
lRAS
6
5
1
Precharge command to active command
(same bank)
lRP
3
2
1
Write recovery or data-in to precharge
command (same bank)
lDPL
2
1
1
1
2
1
Tdpl
Pr
Active command to active command
(different bank)
lRRD
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input
lSREX
Tsrx
1
1
2
lAPW
Tdal
5
3
= [lDPL + lRP]
9
7
= [lRC]
3
lSEC
(CAS latency = 3)
lHZP
lHZP
Last data out to active command
(auto precharge) (same bank)
lAPR
Last data out to precharge (early precharge)
(CAS latency = 2)
(CAS latency = 3)
lEP
lEP
Column command to column command
lCCD
Write command to data in latency
lWCD
DQM to data in
lDID
DQM to data out
lDOD
CKE to CLK disable
lCLE
Register set to active command
lRSA
uc
od
Precharge command to high impedance
(CAS latency = 2)
Troh
2
2
Troh
3
3
1
1
–1
–1
–2
–2
Tccd
1
1
Tdwd
0
0
Tdqm
0
0
Tdqz
2
2
Tcke
1
1
Tmrd
1
1
t
Data Sheet E0179H10
50
HM5212165FTD/HM5212805FTD-75/A60/B60
HM5212165F/
HM5212805F
-75
-A60/B60
Frequency (MHz)
133
100
7.5
10
EO
Parameter
PC/100
Symbol
tCK (ns)
Symbol
CS to command disable
lCDD
0
0
Power down exit to command input
lPEC
1
1
Burst stop to output valid data hold
(CAS latency = 2)
lBSR
1
1
lBSR
2
2
lBSH
2
2
lBSH
3
3
lBSW
0
0
(CAS latency = 3)
(CAS latency = 3)
L
Burst stop to output high impedance
(CAS latency = 2)
Burst stop to write data ignore
Notes
t
uc
od
Pr
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Data Sheet E0179H10
51
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
;;;
;;;;
Timing Waveforms
Read Cycle
t CK
t CKH t CKL
CLK
t RC
VIH
CKE
t RP
;
;
;
;;;;;
;
;
;
;;;;;;
; ;
t RAS
t RCD
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
CS
RAS
t CS t CH
CAS
t CS t CH
L
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
t CS t CH
WE
t AS t AH
A10
t AS t AH
Pr
BS
t AS t AH
Address
t CS
t AC
t AC
Bank 0
Active
Bank 0
Read
t AS t AH
t CH
DQ (input)
DQ (output)
t AS t AH
t LZ
t OH
uc
od
DQM,
DQMU/DQML
t AS t AH
t AC
t OH
t AC
t OH
Bank 0
Precharge
t HZ
t OH
CAS latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
t
Data Sheet E0179H10
52
;
;
;
;
;
;
;;;;
HM5212165FTD/HM5212805FTD-75/A60/B60
Write Cycle
EO
t CK
t CKH t CKL
CLK
t RC
VIH
CKE
t RAS
t RCD
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
;;;
;
;
t CS t CH
t RP
CS
t CS t CH
t CS t CH
RAS
t CS t CH
L
CAS
t CS t CH
WE
t CS t CH
t AS t AH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
t AS t AH
BS
t AS t AH
t AS t AH
t AS t AH
t AS t AH
Address
t CS
DQM,
DQMU/DQML
Pr
A10
t DS t DH tDS
DQ (input)
t AS t AH
t CH
t DH t DS t DH t DS
t DH
uc
od
t DPL
DQ (output)
Bank 0
Active
Bank 0
Write
Bank 0
Precharge
CAS latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
t
Data Sheet E0179H10
53
;
;
;
;
;;;;;;;;;
;
;
;
;;;;;;;;;;;;;;;;;
;; ; ;;;;;;;;;
;;;;;
HM5212165FTD/HM5212805FTD-75/A60/B60
Mode Register Set Cycle
EO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
VIH
CKE
CS
RAS
CAS
WE
BS
code R: b
valid
DQ (output)
DQ (input)
l RSA
l RP
Precharge
If needed
2
3
4
5
6
CLK
CKE
VIH
7
8
9
10
11
CAS
WE
BS
C:a
R:b
DQ (output)
DQ (input)
CKE
C:b
a
C:b'
a+1 a+2 a+3
b
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Read
Precharge
VIH
l RCD = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
14
15
16
17
18
19
20
Read cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
C:b"
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
Write cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
CS
CAS
WE
BS
R:a
C:a
R:b
C:b
C:b'
C:b"
High-Z
DQ (input)
a
Bank 0
Write
a+1 a+2 a+3
Bank 3
Active
b
Bank 3
Write
b+1 b+2 b+3 b'
Bank 0
Precharge
Data Sheet E0179H10
Bank 3
Write
b'+1 b"
Bank 3
Write
b"+1 b"+2 b"+3
Bank 3
Precharge
t
Bank 0
Active
54
13
b’+3
High-Z
RAS
Address
DQM,
DQMU/DQML
DQ (output)
12
b’+2
uc
od
RAS
R:a
b’+1
Output mask
CS
Address
DQM,
DQMU/DQML
b’
Bank 3
Read
Pr
1
b+3
b
High-Z
l RCD
Mode
Bank 3
register Active
Set
Read Cycle/Write Cycle
0
C: b’
C: b
L
DQM,
DQMU/DQML
;
Address
;;;;;;
;;; ;
HM5212165FTD/HM5212805FTD-75/A60/B60
Read/Single Write Cycle
EO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
;
;;;;
;
;
;
;
0
CLK
CKE
VIH
CS
RAS
CAS
WE
BS
R:a
DQ (output)
R:b
C:a' C:a
a
Bank 0
Active
CKE
C:a
VIH
CS
a
L
Address
DQM,
DQMU/DQML
DQ (input)
Bank 0
Read
a+1 a+2 a+3
Bank 3
Active
a
Bank 0 Bank 0
Write
Read
a+1 a+2 a+3
Bank 0
Precharge
Bank 3
Precharge
RAS
CAS
BS
Address
DQM,
DQMU/DQML
DQ (input)
R:a
C:a
DQ (output)
Pr
WE
R:b
a
Bank 0
Active
Bank 0
Read
a+1
C:a
C:b C:c
a
b
c
a+3
Bank 0
Write
Bank 3
Active
Bank 0 Bank 0
Write
Write
Bank 0
Precharge
t
uc
od
Read/Single write
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
Data Sheet E0179H10
55
;
;
;
;;;;;
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
;
;
;;
;
Read/Burst Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
CS
RAS
CAS
WE
BS
R:a
DQ (output)
R:b
C:a'
a
Bank 0
Active
CKE
C:a
L
Address
DQM,
DQMU/DQML
DQ (input)
VIH
Bank 0
Read
a
a+1 a+2 a+3
a+1 a+2 a+3
Bank 3
Active
Clock
suspend
Bank 0
Write
Bank 0
Precharge
Bank 3
Precharge
CS
RAS
WE
BS
Address
DQM,
DQMU/DQML
DQ (input)
R:a
C:a
Pr
CAS
R:b
C:a
a
DQ (output)
a
Bank 0
Read
Bank 3
Active
a+1
a+3
Bank 0
Write
Bank 0
Precharge
uc
od
Bank 0
Active
a+1 a+2 a+3
Read/Burst write
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
t
Data Sheet E0179H10
56
;;
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
;;;;
;;
Full Page Read/Write Cycle
CLK
CKE
VIH
Read cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = full page
= VIH or VIL
CS
RAS
CAS
WE
BS
Address
DQM,
DQMU/DQML
DQ (output)
DQ (input)
Bank 0
Active
C:a
R:b
Bank 0
Read
a
a+1
VIH
CS
RAS
CAS
WE
a+3
High-Z
Bank 3
Active
Burst stop
BS
Bank 3
Precharge
R:a
C:a
R:b
Write cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = full page
= VIH or VIL
Pr
Address
DQM,
DQMU/DQML
DQ (output)
a+2
L
CKE
R:a
High-Z
DQ (input)
a
Bank 0
Active
Bank 0
Write
a+1
a+2
Bank 3
Active
a+3
a+4
a+5
a+6
Burst stop
Bank 3
Precharge
t
uc
od
Data Sheet E0179H10
57
;
;;;;;;;
;;;;;
HM5212165FTD/HM5212805FTD-75/A60/B60
EO
;
;
;
;;;;;;;; ;;;;;;;;;
;
;
;
;
;
;
;
;
;
;;;;;;;;;;;;;;;;;;
;;; ;;
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
a
a+1
CLK
CKE
VIH
CS
RAS
CAS
WE
BS
DQ (input)
DQ (output)
Precharge
If needed
Auto Refresh
CLK
tRC
Active
Bank 0
Auto Refresh
Read
Bank 0
Pr
Self Refresh Cycle
Refresh cycle and
Read cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
= VIH or VIL
l SREX
CKE Low
CKE
RAS
CAS
WE
BS
A10=1
DQM,
DQMU/DQML
DQ (input)
uc
od
CS
Address
High-Z
t RC
t RP
C:a
R:a
A10=1
L
Address
DQM,
DQMU/DQML
High-Z
DQ (output)
tRP
Precharge command
If needed
tRC
tRC
Self refresh entry
command
Self refresh exit
ignore command
or No operation
Next
clock
enable
Self refresh entry
command
Auto
Next
clock refresh
enable
Self refresh cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
t
Data Sheet E0179H10
58
;
;;;;;
;
;;;
;
HM5212165FTD/HM5212805FTD-75/A60/B60
Clock Suspend Mode
;
;;;;;;;;;;;;
;
;
;
;
;
;
;;;;;;
EO
t CES
0
1
2
3
4
5
t CES
t CEH
6
7
8
9
10
11
12
13
14
15
16
CLK
CKE
RAS
CAS
WE
BS
R:a
C:a
R:b
a
C:b
a+1 a+2
L
DQ (input)
Bank0 Active clock
Active suspend start
CKE
CS
RAS
Active clock Bank0
suspend end Read
Bank3
Active
a+3
b
High-Z
Read suspend
start
Read suspend
end
Bank3
Read
Bank0
Precharge
WE
Pr
BS
C:a R:b
R:a
C:b
High-Z
DQ (input)
a
Bank0
Active
Active clock
suspend start
19
20
a+1 a+2
Active clock Bank0 Bank3
supend end Write Active
Write suspend
start
b+1 b+2 b+3
Earliest Bank3
Precharge
Write cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
= VIH or VIL
CAS
Address
DQM,
DQMU/DQML
DQ (output)
18
Read cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
= VIH or VIL
CS
Address
DQM,
DQMU/DQML
DQ (output)
17
a+3 b
Write suspend
end
b+1 b+2 b+3
Bank3 Bank0
Write Precharge
Earliest Bank3
Precharge
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Data Sheet E0179H10
59
HM5212165FTD/HM5212805FTD-75/A60/B60
Power Down Mode
EO
;
;
;
;
;
;;;;;;
;
;
;;;;;;
;
;
;
; ;;;
;
;
;;;;;
;
CLK
CKE Low
CKE
CS
RAS
CAS
WE
L
BS
Address
R: a
A10=1
DQM,
DQMU/DQML
Pr
DQ (input)
High-Z
DQ (output)
tRP
Power down entry
Precharge command
If needed
Power down
mode exit
Active Bank 0
;;;
;;;;;;;;
;;;;;;;;
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Initialization Sequence
Power down cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
0
1
2
3
4
5
6
CLK
CKE
VIH
CS
RAS
CAS
WE
DQM,
DQMU/DQML
8
9
10
48
49
50
51
52
code
valid
Address
7
VIH
53
54
55
Valid
High-Z
DQ
t RP
All banks
Precharge
t RC
Auto Refresh
t RSA
tRC
Auto Refresh
Mode register
Set
Bank active
If needed
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Data Sheet E0179H10
60
HM5212165FTD/HM5212805FTD-75/A60/B60
Package Dimensions
EO
HM5212165FTD/HM5212805FTD Series
Unit: mm
22.22
22.72 Max
L
1
28
27
0.80
0.10
*0.30 +– 0.05
0.28 ± 0.05
10.16
54
0.13 M
0.80
11.76 ± 0.20
0.91 Max
Pr
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
0.45
0.50 ± 0.10
TTP-54DA
—
—
0.58 g
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*Dimension including the plating thickness
Base material dimension
0.05 ± 0.05
0.10
*0.12 ± 0.05
0.10 ± 0.04
1.20 Max
0° – 5°
Data Sheet E0179H10
61
HM5212165FTD/HM5212805FTD-75/A60/B60
Cautions
EO
L
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third
party’s patent, copyright, trademark, or other intellectual property rights for information contained in this
document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information contained in this
document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, contact Elpida Memory, Inc. before using the product in an application that demands especially
high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc.
particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when
used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other
consequential damage due to operation of the Elpida Memory, Inc. product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Elpida Memory, Inc..
7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc.
semiconductor products.
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Data Sheet E0179H10
62