MICROCHIP PIC16HV785T-I/ML

PIC16F785/HV785
Data Sheet
20-Pin Flash-Based, 8-Bit
CMOS Microcontroller with
Two-Phase Asynchronous Feedback PWM
Dual High-Speed Comparators and
Dual Operational Amplifiers
© 2008 Microchip Technology Inc.
DS41249E
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•
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC and SmartShunt are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41249E-page ii
© 2008 Microchip Technology Inc.
PIC16F785/HV785
20-Pin Flash-Based 8-Bit CMOS Microcontroller
High-Performance RISC CPU:
Peripheral Features:
• Only 35 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Interrupt Capability
• 8-Level Seep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• High-Speed Comparator module with:
- Two independent analog comparators
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
- 1.2V band gap voltage reference
- Comparator inputs and outputs externally
accessible
- < 40 ns propagation delay
- 2 mv offset, typical
• Operational Amplifier module with 2 independent
Op Amps:
- 3 MHz GBWP, typical
- All I/O pins externally accessible
• Two-Phase Asynchronous Feedback PWM
module:
- Complementary output with programmable
dead band delay
- Infinite resolution analog duty cycle
- Sync Output/Input for multi-phase PWM
- FOSC/2 maximum PWM frequency
• A/D Converter:
- 10-bit resolution and 14 channels (2 internal)
• 17 I/O pins and 1 Input-only Pin:
- High-current source/sink for direct LED drive
- Interrupt-on-pin change
- Individually programmable weak pull-ups
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator, if INTOSC mode
selected
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Capture, Compare, PWM module:
- 16-bit Capture, max resolution 12.5 ns
- Compare, max resolution 200 ns
- 10-bit PWM with 1 output channel, max
frequency 20 kHz
• In-Circuit Serial ProgrammingTM (ICSPTM) via two
pins
• Shunt Voltage Regulator (PIC16HV785 only):
- 5 volt regulation
- 4 mA to 50 mA shunt range
Special Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%
- Software selectable frequency range of
8 MHz to 32 kHz
- Software tunable
- Two-Speed Start-up mode
- Crystal fail detect for critical applications
- Clock mode switching during operation for
power savings
• Power-Saving Sleep mode
• Wide Operating Voltage Range (2.0V-5.5V)
• Industrial and Extended Temperature Range
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset (BOR) with Software Control
Option
• Enhanced Low-Current Watchdog Timer (WDT)
with on-chip Oscillator (software selectable
nominal 268 seconds with full prescaler) with
Software Enable
• Multiplexed Master Clear with Pull-up/Input Pin
• Programmable Code Protection
• High-Endurance Flash/EEPROM cell:
- 100,000 write Flash endurance
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM retention: > 40 years
Low-Power Features:
• Standby Current:
- 30 nA @ 2.0V, typical
• Operating Current:
- 8.5 μA @ 32 kHz, 2.0V, typical
- 100 μA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current:
- 1 μA @ 2.0V, typical
• Timer1 Oscillator Current:
- 2 μA @ 32 kHz, 2.0V, typical
© 2008 Microchip Technology Inc.
DS41249E-page 1
PIC16F785/HV785
Program
Memory
Data Memory
Device
Two10-bit
Op
Timers Shunt
Comparators CCP Phase
A/D (ch) Amps
8/16-bit Reg.
PWM
I/O
Flash
SRAM EEPROM
(words) (bytes) (bytes)
PIC16F785
2048
128
256
17+1
12+2
2
2
1
1
2/1
0
PIC16HV785
2048
128
256
17+1
12+2
2
2
1
1
2/1
1
Dual in Line Pin Diagram
1
2
3
4
5
6
7
8
9
10
VDD
RA5/T1CKI/OSC1/CLKIN
RA4/AN3/T1G/OSC2/CLKOUT
RA3/MCLR/VPP
RC5/CCP1
RC4/C2OUT/PH2
RC3/AN7/C12IN3-/OP1
RC6/AN8/OP1RC7/AN9/OP1+
RB7/SYNC
TABLE 1:
PIC16F785/HV785
20-pin PDIP, SOIC, SSOP
20
19
18
17
16
15
14
13
12
11
VSS
RA0/AN0/C1IN+/ICSPDAT
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-/PH1
RC2/AN6/C12IN2-/OP2
RB4/AN10/OP2RB5/AN11/OP2+
RB6
DUAL IN LINE PIN SUMMARY
I/O
Pin
Analog
Comp.
Op
Amps
PWM
Timers
CCP
RA0
19
AN0
C1IN+
—
—
—
—
RA1
18
—
—
—
—
RA2
17
AN2
C1OUT
—
—
T0CKI
—
RA3(1)
4
—
—
—
—
—
—
IOC
RA4
3
AN3
—
—
—
T1G
—
RA5
2
—
—
—
—
T1CKI
—
RB4
13
AN10
—
OP2-
—
—
—
—
—
—
RB5
12
AN11
—
OP2+
—
—
—
—
—
—
AN1/VREF C12IN0-
Interrupt Pull-ups
IOC
Basic
Y
ICSPDAT
IOC
Y
ICSPCLK
INT/IOC
Y
—
Y
MCLR/VPP
IOC
Y
OSC2/CLKOUT
IOC
Y
OSC1/CLKIN
RB6(2)
11
—
—
—
—
—
—
—
—
—
RB7
10
—
—
—
SYNC
—
—
—
—
—
RC0
16
AN4
C2IN+
—
—
—
—
—
—
—
RC1
15
AN5
C12IN1-
—
PH1
—
—
—
—
—
RC2
14
AN6
C12IN2-
OP2
—
—
—
—
—
—
RC3
7
AN7
C12IN3-
OP1
—
—
—
—
—
—
RC4
6
—
C2OUT
—
PH2
—
—
—
—
—
RC5
5
—
—
—
—
—
CCP1
—
—
—
RC6
8
AN8
—
OP1-
—
—
—
—
—
—
RC7
9
AN9
—
OP1+
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
VDD
—
20
—
—
—
—
—
—
—
—
VSS
Note 1:
2:
Input only.
Open drain.
DS41249E-page 2
© 2008 Microchip Technology Inc.
PIC16F785/HV785
RA3/MCLR/VPP
RC5/CCP1
RC4/C2OUT/PH2
RC3/AN7/C12IN3-/OP1
RC6/AN8/OP1-
1
2
3
4
5
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-/PH1
RC2/AN6/C12IN2-/OP2
15
14
13
12
11
6
7
8
9
10
20-PIN QFN
20
19
18
17
16
RA4/AN3/T1G/OSC2/CLKOUT
RA5/T1CKI/OSC1/CLKIN
VDD
VSS
RA0/AN0/C1IN+/ICSPDAT
QFN (4x4x0.9) Pin Diagram
RC7/AN9/OP1+
RB7/SYNC
RB6
RB5/AN11/OP2+
RB4/AN10/OP2-
PIC16F785/HV785
TABLE 2:
I/O
QFN PIN SUMMARY
Pin
RA0
16
RA1
15
RA2
14
RA3(1)
RA4
Analog
Comp.
AN0
C1IN+
AN1/VREF C12IN0-
Op
Amps
PWM
Timers
CCP
Interrupt Pull-ups
Basic
—
—
—
—
IOC
Y
ICSPDAT
—
—
—
—
IOC
Y
ICSPCLK
T0CKI
—
INT/IOC
Y
—
AN2
C1OUT
—
—
1
—
—
—
—
—
—
IOC
Y
MCLR/VPP
20
AN3
—
—
—
T1G
—
IOC
Y
OSC2/CLKOUT
RA5
19
—
—
—
—
T1CKI
—
IOC
Y
OSC1/CLKIN
RB4
10
AN10
—
OP2-
—
—
—
—
—
—
RB5
9
AN11
—
OP2+
—
—
—
—
—
—
RB6(2)
8
—
—
—
—
—
—
—
—
—
RB7
7
—
—
—
SYNC
—
—
—
—
—
RC0
13
AN4
C2IN+
—
—
—
—
—
—
—
RC1
12
AN5
C12IN1-
—
PH1
—
—
—
—
—
RC2
11
AN6
C12IN2-
OP2
—
—
—
—
—
—
RC3
4
AN7
C12IN3-
OP1
—
—
—
—
—
—
RC4
3
—
C2OUT
—
PH2
—
—
—
—
—
RC5
2
—
—
—
—
—
CCP1
—
—
—
RC6
5
AN8
—
OP1-
—
—
—
—
—
—
RC7
6
AN9
—
OP1+
—
—
—
—
—
—
—
18
—
—
—
—
—
—
—
—
VDD
—
17
—
—
—
—
—
—
—
—
VSS
Note 1:
2:
Input only.
Open drain.
© 2008 Microchip Technology Inc.
DS41249E-page 3
PIC16F785/HV785
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization ................................................................................................................................................................... 9
3.0 Clock Sources ............................................................................................................................................................................ 23
4.0 I/O Ports ..................................................................................................................................................................................... 35
5.0 Timer0 Module ........................................................................................................................................................................... 49
6.0 Timer1 Module with Gate Control............................................................................................................................................... 51
7.0 Timer2 Module ........................................................................................................................................................................... 55
8.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 57
9.0 Comparator Module.................................................................................................................................................................... 63
10.0 Voltage References .................................................................................................................................................................... 70
11.0 Operational Amplifier (OPA) Module .......................................................................................................................................... 75
12.0 Analog-to-Digital Converter (A/D) Module .................................................................................................................................. 79
13.0 Two-Phase PWM ....................................................................................................................................................................... 91
14.0 Data EEPROM Memory ........................................................................................................................................................... 103
15.0 Special Features of the CPU .................................................................................................................................................... 107
16.0 Voltage Regulator..................................................................................................................................................................... 126
17.0 Instruction Set Summary .......................................................................................................................................................... 127
18.0 Development Support............................................................................................................................................................... 137
19.0 Electrical Specifications............................................................................................................................................................ 141
20.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 163
21.0 Packaging Information.............................................................................................................................................................. 187
Appendix A: Data Sheet Revision History.......................................................................................................................................... 193
Appendix B: Migrating from other PIC® Devices................................................................................................................................ 193
Index .................................................................................................................................................................................................. 195
The Microchip Web Site ..................................................................................................................................................................... 201
Customer Change Notification Service .............................................................................................................................................. 201
Customer Support .............................................................................................................................................................................. 201
Reader Response .............................................................................................................................................................................. 202
Product Identification System............................................................................................................................................................. 203
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DS41249E-page 4
© 2008 Microchip Technology Inc.
PIC16F785/HV785
1.0
DEVICE OVERVIEW
This document contains device specific information for
the PIC16F785/HV785. It is available in 20-pin PDIP,
SOIC, SSOP and QFN packages. Figure 1-1 shows a
block diagram of the PIC16F785/HV785 device.
Table 1-1 shows the pinout description.
FIGURE 1-1:
PIC16F785/HV785 BLOCK DIAGRAM
INT
Configuration
13
Flash
2k X 14
Program
Memory
Program
Bus
8
Data Bus
Program Counter
PORTA
RA0
RA1
14
RA2
RAM
128 bytes
File
Registers
8-Level Stack
(13-bit)
RAM Addr
RA3
RA4
RA5
PORTB
9
ADDR MUX
Instruction Reg
7
Direct Addr
RB4
RB5
Indirect
Addr
8
RB6
RB7
FSR Reg
PORTC
STATUS Reg
RC0
8
RC1
RC2
3
MUX
Power-up
Timer
32 kHz Internal Instruction
Oscillator
Decode and
Control
Power-on
Reset
Timing
Generation
OSC2/CLKOUT
RC4
Oscillator
Start-up Timer
OSC1/CLKIN
RC5
ALU
RC6
RC7
8
Watchdog
Timer
Brown-out
Reset
8 MHz Internal
Oscillator
RC3
W Reg
OP1
OP1+
Dual
Op Amps
OP1OP2
OP2+
CCP1
T1G
VDD
MCLR
OP2-
VSS
EEDATA
256 bytes
Data
EEPROM
T1CKI
Timer0
T0CKI
Timer1
CCP
Timer2
Two-Phase
PWM
EEADDR
SYNC
8
C2OUT
C2IN+
C2IN-
C1OUT
C1IN+
2 Analog
Comparators
C1IN-
AN11
AN10
AN9
AN8
AN3
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
© 2008 Microchip Technology Inc.
VREF
Voltage
Reference
Analog-to-Digital Converter
PH1
PH2
DS41249E-page 5
PIC16F785/HV785
TABLE 1-1:
PIC16F785/HV785 PINOUT DESCRIPTION
Name
RA0/AN0/C1IN+/ICSPDAT
RA1/AN1/C12IN0-/VREF/
ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RA3/MCLR/Vpp
RA4/AN3/T1G/OSC2/
CLKOUT
RA5/T1CKI/OSC1/CLKIN
RB4/AN10/OP2-
RB5/AN11/OP2+
RB6
RB7/SYNC
RC0/AN4/C2IN+
Function
Input
Type
RA0
TTL
AN0
AN
Output
Type
Description
CMOS PORTA I/O with prog. pull-up and interrupt-on-change
—
A/D Channel 0 input
—
Comparator 1 non-inverting input
C1IN+
AN
ICSPDAT
ST
CMOS Serial Programming Data I/O
RA1
TTL
CMOS PORTA I/O with prog. pull-up and interrupt-on-change
AN1
AN
C12IN0VREF
ICSPCLK
ST
RA2
ST
—
A/D Channel 1 input
AN
—
Comparator 1 and 2 inverting input
AN
AN
External Voltage Reference for A/D, buffered reference
output
—
Serial Programming Clock
CMOS PORTA I/O with prog. pull-up and interrupt-on-change
AN2
AN
—
A/D Channel 2 input
T0CKI
ST
—
Timer0 clock input
—
External Interrupt
INT
ST
C1OUT
—
RA3
TTL
CMOS Comparator 1 output
—
PORTA input with prog. pull-up and interrupt-onchange
MCLR
ST
—
Master Clear with internal pull-up
VPP
HV
—
Programming voltage
RA4
TTL
AN3
AN
T1G
ST
—
OSC2
—
XTAL
CLKOUT
—
CMOS FOSC/4 output
RA5
TTL
CMOS PORTA I/O with prog. pull-up and interrupt-on-change
—
A/D Channel 3 input
Timer1 gate
Crystal/Resonator
CMOS PORTA I/O with prog. pull-up and interrupt-on-change
T1CKI
ST
—
Timer1 clock
OSC1
XTAL
—
Crystal/Resonator
—
External clock input/RC oscillator connection
CLKIN
ST
RB4
TTL
AN10
AN
—
A/D Channel 10 input
OP2-
—
AN
Op Amp 2 inverting input
RB5
TTL
AN11
AN
CMOS PORTB I/O
CMOS PORTB I/O
—
A/D Channel 11 input
OP2+
—
AN
Op Amp 2 non-inverting input
RB6
TTL
OD
PORTB I/O. Open drain output
RB7
TTL
CMOS PORTB I/O
SYNC
ST
CMOS Master PWM Sync output or slave PWM Sync input
RC0
TTL
CMOS PORTC I/O
AN4
AN
—
A/D Channel 4 input
C2IN+
AN
—
Comparator 2 non-inverting input
Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, AN = Analog, OD = Open Drain output,
HV = High Voltage
DS41249E-page 6
© 2008 Microchip Technology Inc.
PIC16F785/HV785
TABLE 1-1:
PIC16F785/HV785 PINOUT DESCRIPTION (CONTINUED)
Name
RC1/AN5/C12IN1-/PH1
RC2/AN6/C12IN2-/OP2
RC3/AN7/C12IN3-/OP1
RC4/C2OUT/PH2
RC5/CCP1
RC6/AN8/OP1-
RC7/AN9/OP1+
Function
Input
Type
RC1
TTL
AN5
AN
C12IN1-
AN
PH1
—
RC2
TTL
AN6
AN
C12IN2OP2
RC3
TTL
AN7
AN
C12IN3OP1
RC4
TTL
C2OUT
—
Output
Type
Description
CMOS PORTC I/O
—
A/D Channel 5 input
—
Comparator 1 and 2 inverting input
CMOS PWM phase 1 output
CMOS PORTC I/O
—
A/D Channel 6 input
AN
—
Comparator 1 and 2 inverting input
—
AN
Op Amp 2 output
CMOS PORTC I/O
—
A/D Channel 7 input
AN
—
Comparator 1 and 2 inverting input
—
AN
Op Amp 1 output
CMOS PORTC I/O
CMOS Comparator 2 output
PH2
—
RC5
TTL
CMOS PORTC I/O
CMOS PWM phase 2 output
CCP1
ST
CMOS Capture input/Compare output
RC6
TTL
CMOS PORTC I/O
AN8
AN
—
A/D Channel 8 input
OP1-
AN
—
Op Amp 1 inverting input
RC7
AN9
CMOS PORTC I/O
AN
—
A/D Channel 9 input
OP1+
AN
—
Op Amp 1 non-inverting input
VSS
VSS
Power
—
Ground reference
VDD
VDD
Power
—
Positive supply
Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, AN = Analog, OD = Open Drain output,
HV = High Voltage
© 2008 Microchip Technology Inc.
DS41249E-page 7
PIC16F785/HV785
NOTES:
DS41249E-page 8
© 2008 Microchip Technology Inc.
PIC16F785/HV785
2.0
MEMORY ORGANIZATION
2.1
Program Memory Organization
The PIC16F785/HV785 has a 13-bit program counter
capable of addressing an 8k x 14 program memory
space. Only the first 2k x 14 (0000h-07FFh) for the
PIC16F785/HV785 is physically implemented. Accessing a location above these boundaries will cause a
wrap around within the first 2k x 14 space. The Reset
vector is at 0000h and the interrupt vector is at 0004h
(see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F785/HV785
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
2.2
Data Memory Organization
The data memory (see Figure 2-2) is partitioned into
four banks, which contain the General Purpose
Registers (GPR) and the Special Function Registers
(SFR). The Special Function Registers are located in
the first 32 locations of each bank. Register locations
20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General
Purpose Registers, implemented as static RAM. The
last sixteen register locations in Bank 1 (F0h-FFh),
Bank 2 (170h-17Fh), and Bank 3 (1F0h-1FFh) point to
addresses 70h-7Fh in Bank 0. All other RAM is
unimplemented and returns ‘0’ when read.
Seven address bits are required to access any location
in a data memory bank. Two additional bits are required
to access the four banks. When data memory is
accessed directly, the seven Least Significant address
bits are contained within the opcode and the two Most
Significant bits are contained in the STATUS register.
RP0 and RP1 bits of the STATUS register are the two
Most Significant data memory address bits and are
also known as the bank select bits. Table 2-1 lists how
to access the four banks of registers.
TABLE 2-1:
Stack Level 8
Reset Vector
Interrupt Vector
0000h
0004
0005
RP1
RP0
Bank 0
0
0
Bank 1
0
1
Bank 2
1
0
Bank 3
1
1
2.2.1
On-chip Program
Memory
07FFh
0800h
1FFFh
BANK SELECTION
GENERAL PURPOSE REGISTER
FILE
The register file banks are organized as 128 x 8 in the
PIC16F785/HV785. Each register is accessed, either
directly, by seven address bits within the opcode, or
indirectly, through the File Select Register (FSR).
When the FSR is used to access data memory, the
eight Least Significant data memory address bits are
contained in the FSR and the ninth Most Significant
address bit is contained in the IRP bit in the STATUS
Register. (see Section 2.4 “Indirect Addressing,
INDF and FSR Registers”).
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-2). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
© 2008 Microchip Technology Inc.
DS41249E-page 9
PIC16F785/HV785
FIGURE 2-2:
DATA MEMORY MAP OF THE PIC16F785/HV785
File
Address
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
WDTCON
ADRESH
ADCON0
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
Indirect addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
1Dh
1Eh
1Fh
20h
General
Purpose
Register
96 Bytes
6Fh
70h
7Fh
Bank 0
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
EECON2(1)
ADRESL
ADCON1
General
Purpose
Register
9Dh
9Eh
9Fh
A0h
OPA2CON
32 Bytes
BFh
C0h
PCLATH
INTCON
PIE1
PCON
OSCCON
OSCTUNE
ANSEL0
PR2
ANSEL1
WPUA
IOCA
REFCON
VRCON
EEDAT
EEADR
EECON1
accesses
Bank 0
PCLATH
INTCON
PWMCON1
PWMCON0
PWMCLK
PWMPH1
PWMPH2
CM1CON0
CM2CON0
CM2CON1
OPA1CON
EFh
F0h
FFh
Bank 1
accesses
Bank 0
Bank 2
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
File
Address
Indirect addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
11Dh
11Eh
11Fh
120h
19Dh
19Eh
19Fh
1A0h
16Fh
170h
17Fh
1EFh
1F0h
1FFh
accesses
Bank 0
Bank 3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
DS41249E-page 10
© 2008 Microchip Technology Inc.
PIC16F785/HV785
TABLE 2-2:
Addr
Name
PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
22,114
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
49,114
02h
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
21,114
03h
STATUS
15,114
04h
FSR
05h
PORTA(1)
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
22,114
RA4
RA3
RA2
RA1
RA0
--x0 x000
35,114
Indirect Data Memory Address Pointer
—
—
RA5
06h
PORTB(1)
RB7
RB6
RB5
RB4
—
—
—
—
xx00 ----
42,114
07h
PORTC(1)
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
00xx 0000
45,114
—
08h
—
Unimplemented
—
09h
—
Unimplemented
—
—
---0 0000
21,114
0Ah
PCLATH
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
17,114
0Ch
PIR1
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
0000 0000
19,114
—
—
—
Write Buffer for Upper 5 bits of Program Counter
0Dh
—
—
—
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx
52,114
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx
52,114
10h
T1CON
11h
TMR2
12h
T2CON
13h
CCPR1L
14h
CCPR1H
Unimplemented
0000 0000
53,114
0000 0000
55,114
-000 0000
55,114
Capture/Compare/PWM Register1 Low Byte
xxxx xxxx
58,114
Capture/Compare/PWM Register1 High Byte
xxxx xxxx
58,114
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
Timer2 Module Register
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
15h
CCP1CON
--00 0000
58,114
16h
—
Unimplemented
—
—
17h
—
Unimplemented
—
—
18h
WDTCON
—
—
DC1B1
DC1B0
---0 1000
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
xxxx xxxx
81,114
0000 0000
83,114
1Eh
ADRESH
1Fh
ADCON0
Legend:
Note 1:
WDTPS0
CCP1M0
—
—
WDTPS1
CCP1M1
19h
—
WDTPS2
CCP1M2
122,114
—
WDTPS3
CCP1M3
SWDTEN
Most Significant 8 bits of the left justified A/D result or 2 bits of right justified result
ADFM
VCFG
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
© 2008 Microchip Technology Inc.
DS41249E-page 11
PIC16F785/HV785
TABLE 2-3:
Addr
PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
xxxx xxxx
22,114
1111 1111
17,114
Bank 1
80h
INDF
81h
OPTION_REG
Addressing this location uses contents of FSR to address data memory (not a physical register)
82h
PCL
83h
STATUS
84h
FSR
85h
TRISA
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
—
TRISA5
21,114
15,114
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
22,114
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111
35,114
Indirect Data Memory Address Pointer
—
0000 0000
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
1111 ----
42,114
87h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
45,114
—
88h
—
Unimplemented
—
89h
—
Unimplemented
—
—
8Ah
PCLATH
---0 0000
21,114
—
—
—
Write Buffer for Upper 5 bits of Program Counter
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 000x
17,114
8Ch
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 0000
18,114
8Dh
8Eh
—
Unimplemented
PCON
—
—
—
SBOREN
—
—
POR
—
—
BOR
---1 --qq
20,114
8Fh
OSCCON
—
IRCF2
IRCF1
IRCF0
OSTS(1)
HTS
LTS
SCS
-110 q000
33,114
90h
OSCTUNE
—
—
—
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000
28,114
91h
ANSEL0
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
82,114
92h
PR2
93h
ANSEL1
Timer2 Module Period Register
94h
—
95h
WPUA
96h
IOCA
97h
—
98h
REFCON
99h
9Ah
—
1111 1111
55,114
82,114
—
—
—
ANS11
ANS10
ANS9
ANS8
---- 1111
—
—
—
—
WPUA5
WPUA4
WPUA3(2)
WPUA2
WPUA1
WPUA0
--11 1111
36,114
—
—
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
--00 0000
37,114
Unimplemented
Unimplemented
000- 0000
72,114
C1VREN
C2VREN
VRR
—
VR3
VR2
VR1
VR0
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
EEDAT0
9Bh
EEADR
EEADR7
EEADR6
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
0000 0000 103,114
9Ch
EECON1
—
—
—
—
WRERR
WREN
WR
RD
---- x000 104,114
9Dh
EECON2
EEPROM Control Register 2 (not a physical register)
9Eh
ADRESL
Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result
9Fh
ADCON1
Legend:
Note 1:
2:
CVROE
—
EEDAT
ADCS0
VROE
73,114
VRCON
ADCS1
VREN
--00 000-
—
ADCS2
VRBB
—
—
—
BGST
—
0000 0000 103,114
---- ---- 104,114
—
—
—
—
xxxx xxxx
81,114
-000 ----
84,114
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled, otherwise this
bit resets to ‘1’.
RA3 pull-up is enabled when MCLRE is ‘1’ in Configuration Word.
DS41249E-page 12
© 2008 Microchip Technology Inc.
PIC16F785/HV785
TABLE 2-4:
Addr
Name
PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 2
100h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
22,114
101h
TMR0
Timer0 Module’s Register
xxxx xxxx
49,114
102h
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
21,114
103h
STATUS
15,114
104h
FSR
105h
PORTA(1)
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
22,114
RA4
RA3
RA2
RA1
RA0
--x0 x000
35,114
Indirect Data Memory Address Pointer
—
—
RA5
106h
PORTB(1)
RB7
RB6
RB5
RB4
—
—
—
—
xx00 ----
42,114
107h
PORTC(1)
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
00xx 0000
45,114
—
108h
—
Unimplemented
—
109h
—
Unimplemented
—
—
---0 0000
21,114
10Ah
PCLATH
10Bh
INTCON
—
—
—
GIE
PEIE
T0IE
Write Buffer for Upper 5 bits of Program Counter
0000 0000
17,114
10Ch
—
Unimplemented
—
—
10Dh
—
Unimplemented
—
—
10Eh
—
Unimplemented
—
—
10Fh
—
Unimplemented
—
—
110h
PWMCON1
111h
PWMCON0
112h
PWMCLK
113h
PWMPH1
114h
PWMPH2
—
INTE
RAIE
T0IF
INTF
RAIF
COMOD1
COMOD0
CMDLY4
CMDLY3
CMDLY2
CMDLY1
CMDLY0
-000 0000
101,114
PRSEN
PASEN
BLANK2
BLANK1
SYNC1
SYNC0
PH2EN
PH1EN
0000 0000
93,114
PWMASE
PWMP1
PWMP0
PER4
PER3
PER2
PER1
PER0
0000 0000
94,114
POL
C2EN
C1EN
PH4
PH3
PH2
PH1
PH0
0000 0000
95,114
POL
C2EN
C1EN
PH4
PH3
PH2
PH1
PH0
0000 0000
96,114
115h
—
Unimplemented
—
—
116h
—
Unimplemented
—
—
117h
—
Unimplemented
—
—
118h
—
Unimplemented
—
—
119h
CM1CON0
0000 0000
65,114
11Ah
CM2CON0
11Bh
CM2CON1
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0
0000 0000
67,114
MC1OUT
MC2OUT
—
—
—
—
T1GSS
C2SYNC
00-- --10
68,114
11Ch
OPA1CON
OPAON
—
—
—
—
—
—
—
0--- ----
76,114
11Dh
OPA2CON
OPAON
—
—
—
—
—
—
—
0--- ----
76,114
11Eh
—
Unimplemented
—
—
11Fh
—
Unimplemented
—
—
Legend:
Note 1:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
© 2008 Microchip Technology Inc.
DS41249E-page 13
PIC16F785/HV785
TABLE 2-5:
Addr
Name
PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
xxxx xxxx
22,114
1111 1111
17,114
Bank 3
180h
INDF
181h
OPTION_RE
G
Addressing this location uses contents of FSR to address data memory (not a physical register)
182h
PCL
183h
STATUS
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter’s (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
0000 0000
21,114
0001 1xxx
15,114
xxxx xxxx
22,114
184h
FSR
185h
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111
36,114
186h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
1111 ----
42,114
187h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
45,114
188h
—
Unimplemented
—
—
189h
—
Unimplemented
—
—
18Ah
PCLATH
---0 0000
21,114
—
—
—
GIE
PEIE
T0IE
Write Buffer for Upper 5 bits of Program Counter
18Bh
INTCON
0000 0000
17,114
18Ch
—
Unimplemented
—
—
18Dh
—
Unimplemented
—
—
18Eh
—
Unimplemented
—
—
18Fh
—
Unimplemented
—
—
190h
—
Unimplemented
—
—
191h
—
Unimplemented
—
—
192h
—
Unimplemented
—
—
193h
—
Unimplemented
—
—
194h
—
Unimplemented
—
—
195h
—
Unimplemented
—
—
196h
—
Unimplemented
—
—
197h
—
Unimplemented
—
—
198h
—
Unimplemented
—
—
199h
—
Unimplemented
—
—
19Ah
—
Unimplemented
—
—
19Bh
—
Unimplemented
—
—
19Ch
—
Unimplemented
—
—
19Dh
—
Unimplemented
—
—
19Eh
—
Unimplemented
—
—
19Fh
—
Unimplemented
—
—
Legend:
INTE
RAIE
T0IF
INTF
RAIF
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
DS41249E-page 14
© 2008 Microchip Technology Inc.
PIC16F785/HV785
2.2.2.1
STATUS Register
The STATUS register contains arithmetic status of the
ALU, the Reset status and the bank select bits for data
memory (SRAM).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 2-1:
R/W-0
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits, see Section 17.0
“Instruction Set Summary”.
Note:
The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
STATUS: STATUS REGISTER
R/W-0
IRP
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
R/W-x
R/W-x
(1)
Z
C(1)
DC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRP: Register Bank Select bit (used for Indirect addressing)
1 = Bank 2,3 (100h-1FFh)
0 = Bank 0,1 (00h-FFh)
bit 6-5
RP<1:0>: Register Bank Select bits (used for Direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
© 2008 Microchip Technology Inc.
DS41249E-page 15
PIC16F785/HV785
2.2.2.2
OPTION_REG Register
Note:
The Option register is a readable and writable register,
which contains various control bits to configure the
TMR0/WDT prescaler, the external RA2/INT interrupt,
the TMR0 and the weak pull-ups on PORTA.
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by
setting PSA bit to ‘1’ in the OPTION Register. See Section 5.4 “Prescaler”.
OPTION_REG: OPTION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RAPU: PORTA Pull-up Enable bit
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual port latch values in WPUA register
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RA2/AN2/T0CKI/INT/C1OUT pin
0 = Interrupt on falling edge of RA2/AN2/T0CKI/INT/C1OUT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA2/AN2/T0CKI/INT/C1OUT pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA2/AN2/T0CKI/INT/C1OUT pin
0 = Increment on low-to-high transition on RA2/AN2/T0CKI/INT/C1OUT pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate WDT Rate(1)
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F785/HV785.
See Section 15.5 “Watchdog Timer (WDT)” for more information.
DS41249E-page 16
© 2008 Microchip Technology Inc.
PIC16F785/HV785
2.2.2.3
INTCON Register
Note:
The Interrupt Control register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, PORTA change and external
RA2/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE bit of the INTCON register.
User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RAIE(1)
T0IF(2)
INTF
RAIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RA2/AN2/T0CKI/INT/C1OUT External Interrupt Enable bit
1 = Enables the RA2/AN2/T0CKI/INT/C1OUT external interrupt
0 = Disables the RA2/AN2/T0CKI/INT/C1OUT external interrupt
bit 3
RAIE: PORTA Change Interrupt Enable bit(1)
1 = Enables the PORTA change interrupt
0 = Disables the PORTA change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RA2/AN2/T0CKI/INT/C1OUT External Interrupt Flag bit
1 = The RA2/AN2/T0CKI/INT/C1OUT external interrupt occurred (must be cleared in software)
0 = The RA2/AN2/T0CKI/INT/C1OUT external interrupt did not occur
bit 0
RAIF: PORTA Change Interrupt Flag bit
1 = When at least one of the PORTA <5:0> pins changed state (must be cleared in software)
0 = None of the PORTA <5:0> pins have changed state
Note 1: IOCA register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit.
© 2008 Microchip Technology Inc.
DS41249E-page 17
PIC16F785/HV785
2.2.2.4
PIE1 Register
Note:
The Peripheral Interrupt Enable Register 1 contains the
interrupt enable bits, as shown in Register 2-4.
REGISTER 2-4:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 4
C2IE: Comparator 2 Interrupt Enable bit
1 = Enables the Comparator 2 interrupt
0 = Disables the Comparator 2 interrupt
bit 3
C1IE: Comparator 1 Interrupt Enable bit
1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt
bit 2
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 1
TMR2IE: Timer2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
DS41249E-page 18
x = Bit is unknown
© 2008 Microchip Technology Inc.
PIC16F785/HV785
2.2.2.5
PIR1 Register
The Peripheral Interrupt Register 1 contains the
interrupt flag bits.
REGISTER 2-5:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE, in the INTCON Register).
User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
PIR1: PERIPHERAL INTERRUPT REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6
ADIF: A/D Interrupt Flag bit
1 = A/D conversion complete
0 = A/D conversion has not completed or has not been started
bit 5
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 4
C2IF: Comparator 2 Interrupt Flag bit
1 = Comparator 2 output has changed (must be cleared in software)
0 = Comparator 2 output has not changed
bit 3
C1IF: Comparator 1 Interrupt Flag bit
1 = Comparator 1 output has changed (must be cleared in software)
0 = Comparator 1 output has not changed
bit 2
OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 1
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match has not occurred
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Timer1 register overflowed (must be cleared in software)
0 = Timer1 has not overflowed
© 2008 Microchip Technology Inc.
DS41249E-page 19
PIC16F785/HV785
2.2.2.6
PCON Register
The Power Control register contains flag bits to allow
differentiation between a Power-on Reset (POR), a
Brown-out Reset (BOR), a Watchdog Timer (WDT)
Reset (WDT) and an external MCLR Reset.
REGISTER 2-6:
U-0
PCON: POWER CONTROL REGISTER
U-0
—
U-0
—
R/W-1
—
U-0
(1)
SBOREN
U-0
R/W-0
R/W-x
—
—
POR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
SBOREN: Software BOR Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 3-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: BOREN<1:0> = 01 in Configuration Word for this bit to control the BOR.
DS41249E-page 20
© 2008 Microchip Technology Inc.
PIC16F785/HV785
2.3
PCL and PCLATH
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The program counter
is 13 bits wide. The low byte is called the PCL register.
The PCL register is readable and writable. The high
byte of the PC Register is called the PCH register. This
register contains PC<12:8> bits which are not directly
readable or writable. All updates to the PCH register
goes through the PCLATH register.
On any Reset, the PC is cleared. Figure 2-3 shows the
two situations for loading the PC. The upper example
of Figure 2-3 shows how the PC is loaded on a write to
PCL in the PCLATH Register→ PCH. The lower example of Figure 2-3 shows how the PC is loaded during a
CALL or GOTO instruction in the PCLATH Register→
PCH).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH<4:0>
5
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
GOTO, CALL
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
2.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register, all
13 bits of the program counter will change to the values
contained in the PCLATH register and those being
written to the PCL register.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
2.3.2
2.3.3
STACK
The PIC16F785/HV785 family has an 8-level deep x
13-bit wide hardware stack (see Figure 2-1). The stack
space is not part of either program or data space and
the Stack Pointer is not readable or writable. The PC is
PUSHed onto the stack when a CALL instruction is
executed or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLW or RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
PROGRAM MEMORY PAGING
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When using a CALL or GOTO instruction,
the Most Significant bits of the address are provided by
PCLATH<4:3> (page select bits). When using a CALL
or GOTO instruction, the user must ensure that the page
select bits are programmed so that the desired destination program memory page is addressed. When the
CALL instruction (or interrupt) is executed, the entire
13-bit PC return address is PUSHed onto the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the RETURN or RETFIE instructions
(which POPs the address from the stack).
© 2008 Microchip Technology Inc.
DS41249E-page 21
PIC16F785/HV785
2.4
Indirect Addressing, INDF and
FSR Registers
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-1:
MOVLW
MOVWF
NEXT CLRF
INCF
BTFSS
GOTO
CONTINUE
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR and the IRP bit in the
STATUS Register, as shown in Figure 2-4.
FIGURE 2-4:
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
DIRECT/INDIRECT ADDRESSING PIC16F785/HV785
Direct Addressing
RP1RP0
;initialize pointer
;to RAM
;clear INDF register
;increment pointer
;all done?
;no clear next
;yes continue
Indirect Addressing
From Opcode
6
Bank Select
0
IRP
7
Bank Select
Location Select
00
01
10
File Select Register
0
Location Select
11
00H
180h
Data
Memory
7FH
1FFh
Bank 0
Note:
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 2-2.
DS41249E-page 22
© 2008 Microchip Technology Inc.
PIC16F785/HV785
3.0
CLOCK SOURCES
The PIC16F785/HV785 can be configured in one of
eight clock modes.
3.1
Overview
1.
2.
The PIC16F785/HV785 has a wide variety of clock
sources and selection features to allow it to be used in
a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1
illustrates a block diagram of the PIC16F785/HV785
clock sources.
3.
4.
5.
Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two
internal oscillators, with a choice of speeds selectable
via software. Additional clock features include:
6.
7.
8.
• Selectable system clock source between external
or internal via software.
• Two-Speed Clock Start-up mode, which minimizes latency between external oscillator start-up
and code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch to the
internal oscillator.
FIGURE 3-1:
EC – External clock with I/O on RA4.
LP – 32.768 kHz Watch Crystal or Ceramic
Resonator Oscillator mode.
XT – Medium Gain Crystal or Ceramic
Resonator Oscillator mode.
HS – High Gain Crystal or Ceramic Resonator
mode.
RC – External Resistor-Capacitor (RC) with
FOSC/4 output on RA4
RCIO – External Resistor-Capacitor with I/O on
RA4.
INTOSC – Internal Oscillator with FOSC/4 output
on RA4 and I/O on RA5.
INTOSCIO – Internal Oscillator with I/O on RA4
and RA5.
Clock Source modes are configured by the
FOSC<2:0> bits in the Configuration Word (see
Section 15.0 “Special Features of the CPU”). Once
the PIC16F785/HV785 is programmed and the Clock
Source mode configured, it cannot be changed in the
software.
PIC16F785/HV785 CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0>
(Configuration Word)
SCS
(OSCCON<0>)
External Oscillator
OSC2
Sleep
IRCF<2:0>
(OSCCON<6:4>)
8 MHz
Internal Oscillator
4 MHz
MUX
LP, XT, HS, RC, RCIO, EC
OSC1
System Clock
(CPU and Peripherals)
111
110
101
1 MHz
100
500 kHz
250 kHz
125 kHz
LFINTOSC
31 kHz
31 kHz
011
MUX
HFINTOSC
8 MHz
Postscaler
2 MHz
010
001
000
Power-up Timer (PWRT)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
© 2008 Microchip Technology Inc.
DS41249E-page 23
PIC16F785/HV785
3.2
Clock Source Modes
3.3
Clock Source modes can be classified as external or
internal.
External Clock Modes
3.3.1
• External Clock modes rely on external circuitry for
the clock source. Examples are oscillator modules
(EC mode), quartz crystal resonators or ceramic
resonators (LP, XT, and HS modes) and resistorcapacitor (RC mode) circuits.
• Internal clock sources are contained internally
within the PIC16F785/HV785. The PIC16F785/
HV785 has two internal oscillators; the 8 MHz
High-frequency Internal Oscillator (HFINTOSC)
and 31 kHz Low-frequency Internal Oscillator
(LFINTOSC).
OSCILLATOR START-UP TIMER
(OST)
When the PIC16F785/HV785 is configured for any of
the Crystal Oscillator modes (LP, XT or HS), the Oscillator Start-up Timer (OST) is enabled, which extends
the Reset period to allow the oscillator additional time
to stabilize. The OST counts 1024 clock periods present on the OSC1 pin following a Power-on Reset
(POR), a wake from Sleep, or when the Power-up
Timer (PWRT) has expired (if the PWRT is enabled).
During this time, the program counter does not increment and program execution is suspended. The OST
ensures that the oscillator circuit, using a quartz crystal
resonator or ceramic resonator, has started and is providing a stable system clock to the PIC16F785/HV785.
Table 3-1 shows examples where the oscillator delay is
invoked.
The system clock can be selected between external or
internal clock sources via the System Clock Selection
(SCS) bit (see Section 3.5 “Clock Switching”).
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 3.6 “TwoSpeed Clock Start-up Mode”).
TABLE 3-1:
OSCILLATOR DELAY EXAMPLES
Switch
To
Frequency
Oscillator Delay
Comments
Sleep/POR
INTRC
INTOSC
31 kHz
125 kHz-8 MHz
5 μs-10 μs (approx.)
CPU Start-up(1)
Sleep
EC, RC
DC – 20 MHz
Following a wake-up from Sleep mode or
POR, CPU start-up is invoked to allow the
CPU to become ready for code execution.
LFINTOSC
(31 kHz)
EC, RC
DC – 20 MHz
Sleep/POR
LP, XT,
HS
31 kHz-20 MHz
1024 Clock Cycles
(OST)
LFINTOSC
(31 kHz)
INTOSC
125 kHz-8 MHz
1 μs (approx.)
Switch From
Note 1:
3.3.2
The 5 μs-10 μs start-up delay is based on a 1 MHz System Clock.
EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source.
When operating in this mode, an external clock source
is connected to OSC1 pin and the RA4 pin is available
for general purpose I/O. Figure 3-2 shows the pin
connections for EC mode.
FIGURE 3-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
OSC1/CLKIN
PIC16F785/HV785
Clock from
Ext. System
RA4
I/O (OSC2)
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC16F785/HV785 design is
fully static, stopping the external clock input will have
the effect of halting the device while leaving all data
intact. Upon restarting the external clock, the device
will resume operation as if no time had elapsed.
DS41249E-page 24
© 2008 Microchip Technology Inc.
PIC16F785/HV785
3.3.3
FIGURE 3-4:
LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
the OSC1 and OSC2 pins (Figure 3-1). The mode
selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator
types and speed.
OSC1
RP(3)
FIGURE 3-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC16F785/HV785
Sleep
RF(2)
OSC2
RS(1)
C2 Ceramic
Resonator
XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current
consumption is the medium of the three modes. This
mode is best suited to drive resonators with a medium
drive level specification, for example, AT-cut quartz
crystal resonators.
Figure 3-3 and Figure 3-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
PIC16F785/HV785
C1
LP Oscillator mode selects the lowest gain setting of
the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is
best suited to drive resonators with a low drive level
specification, for example, tuning fork type crystals.
HS Oscillator mode selects the highest gain setting of
the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode
is best suited for resonators that require a high drive
setting, for example, AT-cut quartz crystal resonators or
ceramic resonators.
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
To Internal
Logic
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator
mode selected (typically between 2 MΩ to
10 MΩ).
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation (typical value 1 MΩ).
TABLE 3-2:
Mode
CERAMIC RESONATORS
Freq.
OSC1 (C1)
OSC2 (C2)
XT
455 kHz
2.0 MHz
68-100 pF
15-68 pF
68-100 pF
15-68 pF
HS
4.0 MHz
8.0 MHz
16.0 MHz
10-68 pF
15-68 pF
10-22 pF
10-68 pF
15-68 pF
10-22 pF
Note:
These values are for design guidance
only. See notes following this table.
OSC1
C1
Quartz
Crystal
OSC2
RF(2)
Sleep
RS(1)
C2
To Internal
Logic
Note 1:
A series resistor (RS) may be required for
quartz crystals with low drive level.
2:
The value of RF varies with the Oscillator
mode selected (typically between 2 MΩ to
10 MΩ).
Note 1: Quartz crystal characteristics vary
according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
© 2008 Microchip Technology Inc.
DS41249E-page 25
PIC16F785/HV785
TABLE 3-3:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
In RCIO mode, the RC circuit is connected to the OSC1
pin. The OSC2 pin becomes an additional general
purpose I/O pin. The I/O pin becomes bit 4 of PORTA
(RA4). Figure 3-6 shows the RCIO mode connections.
Crystal
Freq.
Cap. Range
C1
Cap. Range
C2
LP
32 kHz
15-33 pF
15-33 pF
FIGURE 3-6:
XT
200 kHz
47-68 pF
47-68 pF
VDD
1 MHz
15-33 pF
15-33 pF
4 MHz
15-33 pF
15-33 pF
4 MHz
15-33 pF
15-33 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
Osc Type
HS
Note:
These values are for design guidance
only. See notes following this table.
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
3: RS may be required to avoid overdriving
crystals with low drive level specification.
3.3.4
RCIO MODE
REXT
OSC1
Internal
Clock
CEXT
PIC16F785/HV785
VSS
RA4
I/O (OSC2)
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)
10 kΩ ≤ REXT ≤ 100 kΩ (VDD < 3.0V)
CEXT > 20 pF
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT)
values and the operating temperature. In addition to
this, the oscillator frequency will vary from unit-to-unit
due to normal threshold voltage. Furthermore, the difference in lead frame capacitance between package
types will also affect the oscillation frequency or low
CEXT values. The user also needs to take into account
variation due to tolerance of external RC components
used.
EXTERNAL RC MODES
The External Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes, RC and RCIO.
In RC mode, the RC circuit connects to the OSC1 pin.
The OSC2/CLKOUT pin outputs the RC oscillator
frequency divided by 4. This signal may be used to
provide a clock for external circuitry, synchronization,
calibration, test or other application requirements.
Figure 3-5 shows the RC mode connections.
FIGURE 3-5:
RC MODE
VDD
REXT
OSC1
Internal
Clock
CEXT
VSS
PIC16F785/HV785
OSC2/CLKOUT
FOSC/4
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)
10 kΩ ≤ REXT ≤ 100 kΩ (VDD < 3.0V)
CEXT > 20 pF
DS41249E-page 26
© 2008 Microchip Technology Inc.
PIC16F785/HV785
3.4
Internal Clock Modes
The PIC16F785/HV785 has two independent, internal
oscillators that can be configured or selected as the
system clock source.
1.
2.
The HFINTOSC (High-frequency Internal Oscillator) is factory calibrated and operates at
8 MHz. The frequency of the HFINTOSC can be
user adjusted ±12% via software using the
OSCTUNE register (Register 3-1).
The LFINTOSC (Low-frequency Internal
Oscillator) is uncalibrated and operates at
approximately 31 kHz.
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select (IRCF)
bits.
The system clock can be selected between external or
internal clock sources via the System Clock Selection
(SCS) bit (see Section 3.5 “Clock Switching”).
3.4.1
3.4.2.1
Calibration Bits
The 8 MHz High-frequency Internal Oscillator (HFINTOSC) is factory calibrated. The HFINTOSC calibration bits are stored in the Calibration Word (CALIB)
located in program memory location 2008h. The Calibration Word is not erased using the specified bulk
erase sequence in the “PIC16F785/HV785 Memory
Programming Specification” (DS41237) and does not
require reprogramming. Reference the “PIC16F785/
HV785
Memory
Programming
Specification”
(DS41237) for more information on the Calibration
Word register.
Note:
Address 2008h is beyond the user program
memory space. It belongs to the special
Configuration Memory space (2000h3FFFh), which can be accessed only during
programming. See “PIC16F785/HV785
Memory Programming Specification”
(DS41237) for more information.
INTRC AND INTRCIO MODES
The INTRC and INTRCIO modes configure the internal
oscillators as the system clock source when the device
is programmed using the Oscillator Selection (FOSC)
bits in the Configuration Word (Register 12-1).
In INTRC mode, the OSC1 pin is available for general
purpose I/O. The OSC2/CLKOUT pin outputs the
selected internal oscillator frequency divided by 4. The
CLKOUT signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements.
In INTRCIO mode, the OSC1 and OSC2 pins are
available for general purpose I/O.
3.4.2
HFINTOSC
The High-frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 8 MHz internal clock source. The
frequency of the HFINTOSC can be altered
approximately ±12% via software using the OSCTUNE
register (Register 3-1).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). One of seven
frequencies can be selected via software using the
IRCF bits (see Section 3.4.4 “Frequency Select Bits
(IRCF)”).
The HFINTOSC is enabled by selecting any frequency
between 8 MHz and 125 kHz (IRCF ≠ 000) as the
system clock source (SCS = 1) or when Two-Speed
Start-up is enabled (IESO = 1 and IRCF ≠ 000).
The HF Internal Oscillator (HTS) bit, in the OSCCON
Register, indicates whether the HFINTOSC is stable or
not.
© 2008 Microchip Technology Inc.
DS41249E-page 27
PIC16F785/HV785
3.4.2.2
OSCTUNE Register
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the OSCTUNE
register (Register 3-1).
The OSCTUNE register has a nominal tuning range of
±12%. The default value of the OSCTUNE register is
‘0’. The value is a 5-bit two’s complement number. Due
to process variation, the monotonicity and frequency
step cannot be specified.
REGISTER 3-1:
When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
frequency. The HFINTOSC clock will stabilize within
1 ms. Code execution continues during this shift. There
is no indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by
the change in frequency.
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
DS41249E-page 28
© 2008 Microchip Technology Inc.
PIC16F785/HV785
3.4.3
LFINTOSC
The Low-frequency Internal Oscillator (LFINTOSC) is
an uncalibrated (approximate) 31 kHz internal clock
source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). 31 kHz can be
selected via software using the IRCF bits (see
Section 3.4.4 “Frequency Select Bits (IRCF)”). The
LFINTOSC is also the frequency for the Power-up
Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF = 000) as the system clock source (SCS = 1), or
when any of the following are enabled:
•
•
•
•
Two-Speed Start-up (IESO = 1 and IRCF = 000)
Power-up Timer (PWRT)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
The LF Internal Oscillator (LTS) bit, in the OSCCON
register, indicates whether the LFINTOSC is stable or
not.
3.4.4
FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connect to a postscaler and multiplexer (see
Figure 3-1). The Internal Oscillator Frequency select
bits IRCF<2:0> in the OSCCON Register select the frequency output of the internal oscillators. One of eight
frequencies can be selected via software:
•
•
•
•
•
•
•
•
8 MHz
4 MHz (Default after Reset)
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
31 kHz
Note:
3.4.5
HF AND LF INTOSC CLOCK
SWITCH TIMING
When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to
save power. If this is the case, there is a 10 μs delay
after the IRCF bits are modified before the frequency
selection takes place. The LTS/HTS bits will reflect the
current active status of the LFINTOSC and the HFINTOSC oscillators. The timing of a frequency selection is
as follows:
1.
2.
3.
4.
5.
6.
IRCF bits are modified.
If the new clock is shut down, a 10 μs clock startup delay is started.
Clock switch circuitry waits for a falling edge of
the current clock.
CLKOUT is held low and the clock switch
circuitry waits for a rising edge in the new clock.
CLKOUT is now connected with the new clock.
HTS/LTS bits are updated as required.
Clock switch is complete.
If the internal oscillator speed selected is between
8 MHz and 125 kHz, there is no start-up delay before
the new frequency is selected. This is because the old
and the new frequencies are derived from the
HFINTOSC via the postscaler and multiplexer.
Note:
Care must be taken to ensure an invalid
voltage or frequency selection is not
selected. An example of an invalid configuration is selecting 8 MHz when VDD is
2.0V.
Following any Reset, the IRCF bits are set
to ‘110’ and the frequency selection is
forced to 4 MHz. The user can modify the
IRCF bits to select a different frequency.
© 2008 Microchip Technology Inc.
DS41249E-page 29
PIC16F785/HV785
3.5
Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit.
3.5.1
SYSTEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit, in the OSCCON
Register, selects the system clock source that is used
for the CPU and peripherals.
• When SCS = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in
Configuration Word (CONFIG).
• When SCS = 1, the system clock source is chosen by the internal oscillator frequency selected
by the IRCF bits. After a Reset, SCS is always
cleared.
Note:
3.5.2
Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bit. The user can monitor the
OSTS (OSCCON<3>) to determine the
current system clock source.
OSCILLATOR START-UP TIME-OUT
STATUS BIT
The Oscillator Start-up Time-out Status (OSTS) bit,
(OSCCON<3>), indicates whether the system clock is
running from the external clock source as defined by
the FOSC bits, or from internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer
(OST) has timed out for LP, XT or HS modes.
3.6
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up time
from the time spent awake and can reduce the overall
power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC as
the clock source and go back to Sleep without waiting
for the primary oscillator to become stable.
Note:
Executing a SLEEP instruction will abort
the Oscillator Start-up Time and will cause
the OSTS bit in the OSCCON Register to
remain clear.
DS41249E-page 30
When the PIC16F785/HV785 is configured for LP, XT
or HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 3.3.1 “Oscillator Start-up
Timer (OST)”). The OST timer will suspend program
execution until 1024 oscillations are counted. TwoSpeed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the
OST is counting. When the OST count reaches 1024
and the OSTS bit in the OSCCON Register is set, program execution switches to the external oscillator.
3.6.1
TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the following settings:
• IESO = 1 (CONFIG<10>) Internal/External Switch
Over bit.
• SCS = 0.
• FOSC configured for LP, XT or HS mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
PWRT has expired, or
• Wake-up from Sleep.
If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
3.6.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
Wake-up from Power-on Reset or Sleep.
Instructions begin execution by the internal
oscillator at the frequency set in the IRCF bits (in
the OSCCON Register.
OST enabled to count 1024 clock cycles.
OST timed out, wait for falling edge of the internal oscillator.
OSTS is set.
System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
System clock is switched to external clock
source.
3.6.3
CHECKING EXTERNAL/INTERNAL
CLOCK STATUS
Checking the state of the OSTS bit in the OSCCON
Register) will confirm if the PIC16F785/HV785 is running from the external clock source as defined by the
FOSC bits in the Configuration Word (CONFIG) or the
internal oscillator.
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 3-7:
TWO-SPEED START-UP
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
INTOSC
TOST
OSC1
0
1
1022 1023
OSC2
PC
Program Counter
PC + 1
PC + 2
System Clock
3.7
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
FIGURE 3-8:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Primary
Clock
LFINTOSC
Oscillator
÷ 64
31 kHz
(~32 μs)
488 Hz
(~2 ms)
S
Q
C
Q
The frequency of the internal oscillator will depend
upon the value contained in the IRCF bits
(OSCCON<6:4>). Upon entering the Fail-Safe condition, the OSTS bit in the OSCCON Register is automatically cleared to reflect that the internal oscillator is
active and the WDT is cleared. The SCS bit in the OSCCON Register is not updated. Enabling FSCM does not
affect the LTS bit.
The FSCM sample clock is generated by dividing the
LFINTOSC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur. Figure 3-8 shows the FSCM block diagram.
On the rising edge of the sample clock, the monitoring
latch (CM = 0) will be cleared. On a falling edge of the
primary system clock, the monitoring latch will be set
(CM = 1). In the event that a falling edge of the sample
clock occurs, and the monitoring latch is not set, a clock
failure has been detected. The assigned internal
oscillator is enabled when FSCM is enabled as
reflected by the IRCF bits.
Note:
Clock
Failure
Detected
Two-Speed Start-up is automatically
enabled when the Fail-Safe Clock Monitor
mode is enabled.
The FSCM function is enabled by setting the FCMEN
bit in Configuration Word (CONFIG). It is applicable to
all external clock options (LP, XT, HS, EC, RC or I/O
modes).
In the event of an external clock failure, the FSCM will
set the OSFIF bit in the PIR1 Register and generate an
oscillator fail interrupt if the OSFIE bit in the PIE1 Register is set. The device will then switch the system clock
to the internal oscillator. The system clock will continue
to come from the internal oscillator unless the external
clock recovers and the Fail-Safe condition is exited.
© 2008 Microchip Technology Inc.
DS41249E-page 31
PIC16F785/HV785
3.7.1
FAIL-SAFE CONDITION CLEARING
The Fail-Safe condition is cleared after a Reset, the
execution of a SLEEP instruction, or a modification of
the SCS bit. While in Fail-Safe condition, the
PIC16F785/HV785 uses the internal oscillator as the
system clock source. The IRCF bits in the OSCCON
Register can be modified to adjust the internal oscillator
frequency without exiting the Fail-Safe condition.
The Fail-Safe condition must be cleared before the
OSFIF flag can be cleared.
FIGURE 3-9:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
Note:
3.7.2
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect oscillator failure at any
point after the device has exited a Reset or Sleep
condition and the Oscillator Start-up Timer (OST) has
expired. If the external clock is EC or RC mode,
monitoring will begin immediately following these
events.
For LP, XT or HS mode, the external oscillator may
require a start-up time considerably longer than the
FSCM sample clock time; a false clock failure may be
detected (see Figure 3-9). To prevent this, the internal
oscillator is automatically configured as the system
clock and functions until the external clock is stable (the
OST has timed out). This is identical to Two-Speed
Start-up mode. Once the external oscillator is stable,
the LFINTOSC returns to its role as the FSCM source.
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit in the OSCCON Register to verify the oscillator start-up and system clock
switchover has successfully completed.
DS41249E-page 32
© 2008 Microchip Technology Inc.
PIC16F785/HV785
REGISTER 3-2:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
R/W-1
R/W-1
R/W-0
R-q
R-0
R-0
R/W-0
—
IRCF2
IRCF1
IRCF0
OSTS(1)
HTS
LTS
SCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IRCF<2:0>: Internal Oscillator Frequency Select bits
000 = 31 kHz
001 = 125 kHz
010 = 250 kHz
011 = 500 kHz
100 = 1 MHz
101 = 2 MHz
110 = 4 MHz
111 = 8 MHz
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the external system clock defined by FOSC<2:0>
0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC)
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
HTS: HFINTOSC (High Frequency – 8 MHz to 125 kHz) Status bit
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1
LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
bit 0
SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0>
Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled, otherwise this bit resets to ‘1’
© 2008 Microchip Technology Inc.
DS41249E-page 33
PIC16F785/HV785
TABLE 3-4:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
CONFIG
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
—
—
OSCCON
—
IRCF2
IRCF1
IRCF0
OSTS
HTS
LTS
SCS
-110 q000
-110 q000
OSCTUNE
—
—
—
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000
---u uuuu
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
0000 0000
0000 0000
Legend:
Note 1:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’, q = value depends on condition. Shaded cells
are not used by oscillators.
See Register 15.2 for operation of all Configuration Word bits.
DS41249E-page 34
© 2008 Microchip Technology Inc.
PIC16F785/HV785
4.0
I/O PORTS
There are seventeen general purpose I/O pins and one
input only pin available. Depending on which peripherals are enabled, some or all of the pins may not be
available as general purpose I/O. In general, when a
peripheral is enabled, the associated pin may not be
used as a general purpose I/O pin.
4.1
PORTA and TRISA Registers
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 4-2).
Setting a TRISA bit (= 1) will make the corresponding
PORTA pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISA bit
(= 0) will make the corresponding PORTA pin an output
(i.e., put the contents of the output latch on the selected
pin). The exception is RA3, which is input only and its
TRIS bit will always read as ‘1’. Example 4-1 shows how
to initialize PORTA.
Reading the PORTA register (Register 4-1) reads the
status of the pins, whereas writing to it will write to the
port latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read; this value is modified and then
written to the port data latch. RA3 reads ‘0’ when
MCLRE = 1.
REGISTER 4-1:
The TRISA register controls the direction of the
PORTA pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISA
register are maintained set when using them as analog
inputs. I/O pins configured as analog inputs always
read ‘0’.
When RA1 is configured as a voltage reference output,
the RA1 digital output driver will automatically be
disabled while not affecting the TRISA<1> value.
Note:
The ANSEL0 (91h) register must be initialized to configure an analog channel as a
digital input. Pins configured as analog
inputs will read ‘0’.
EXAMPLE 4-1:
INITIALIZING PORTA
BCF
BCF
CLRF
MOVLW
ANDWF
BSF
MOVLW
MOVWF
STATUS,RP0
STATUS,RP1
PORTA
F8h
ANSEL0,f
STATUS,RP0
0Ch
TRISA
BCF
STATUS,RP0
;Bank 0
;
;Init PORTA
;Set RA<2:0> to
; digital I/O
;Bank 1
;Set RA<3:2> as inputs
; and set RA<5:4,1:0>
; as outputs
;Bank 0
PORTA: PORTA REGISTER
U-0
U-0
R/W-x
R/W-x(1)
R/W-x
R/W-x(1)
R/W-x(1)
R/W-x(1)
—
—
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RA<5:0>: PORTA I/O Pin bits
1 = Port pin is greater than VIH
0 = Port pin is less than VIL
x = Bit is unknown
Note 1: Data latches are unknown after a POR, but each port bit reads ‘0’ when the corresponding
analog select bit is ‘1’ (see Register 12-1).
© 2008 Microchip Technology Inc.
DS41249E-page 35
PIC16F785/HV785
REGISTER 4-2:
U-0
—
TRISA: PORTA TRI-STATE REGISTER
U-0
R/W-1
R/W-1
R-1
R/W-1
R/W-1
R/W-1
—
TRISA5(2)
TRISA4(2)
TRISA3(1)
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
TRISA<5:0>: PORTA Tri-State Control bit(1), (2)
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 0
C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: TRISA<3> always reads ‘1’.
2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
4.2
4.2.1
Additional Pin Functions
Every PORTA pin on the PIC16F785/HV785 has an
interrupt-on-change option and a weak pull-up option.
The next three sections describe these functions.
REGISTER 4-3:
WEAK PULL-UPS
Each of the PORTA pins has an individually configurable
internal weak pull-up. Control bits WPUAx enable or
disable each pull-up. Refer to Register 4-3. Each weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
Power-on Reset by the RAPU bit in the (OPTION
Register. The weak pull-up on RA3 is automatically
enabled when RA3 is configured as MCLR.
WPUA: WEAK PULL-UP REGISTER
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
WPUA5(4)
WPUA4(4)
WPUA3(3)
WPUA2
WPUA1
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
WPUA<5:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
x = Bit is unknown
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISA = 0).
3: The RA3 pull-up is automatically enabled when configured as MCLR in the Configuration Word.
4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
DS41249E-page 36
© 2008 Microchip Technology Inc.
PIC16F785/HV785
4.2.2
INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 4-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set, the PORTA Change Interrupt flag
bit (RAIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the interrupt by:
a)
b)
Any read or write of PORTA. This will end the
mismatch condition, then,
Clear the flag bit RAIF.
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared. The latch holding the
last read value is neither affected by an MCLR nor BOR
Reset. After these resets, the RAIF flag will continue to
be set if a mismatch is present.
Note:
REGISTER 4-4:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
IOCA5(2)
IOCA4(2)
IOCA3
IOCA2
IOCA1
IOCA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCA<5:0>: Interrupt-on-change PORTA Control bits(2)
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
x = Bit is unknown
Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized.
2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
© 2008 Microchip Technology Inc.
DS41249E-page 37
PIC16F785/HV785
4.2.3
PORTA PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTA pin is multiplexed with other functions.
The pins and their combined functions are briefly
described here. For specific information about individual functions such as the comparator or the A/D, refer
to the appropriate section in this Data Sheet.
4.2.3.1
RA0/AN0/C1IN+/ICSPDAT
Figure 4-1 shows the diagram for this pin. The RA0 pin
is configurable to function as one of the following:
•
•
•
•
Data Bus
WR
WPUA
General purpose I/O
Analog input for the A/D
Analog input to Comparators 1 and 2
Voltage reference input for the A/D
Buffered or unbuffered voltage reference output
In-Circuit Serial Programming clock
Weak
D
Weak
Q
CK Q
RAPU
RD
WPUA
D
WR
PORTA
D
CK Q
I/O pin
D
CK Q
D
VDD
Q
VDD
Q
I/O pin
WR
TRISA
VDD
RAPU
RD
WPUA
WR
PORTA
BLOCK DIAGRAM OF RA1
ANS1
Data Bus
WR
WPUA
VDD
CK Q
•
•
•
•
•
•
VROE*VREN
CVROE
BLOCK DIAGRAM OF RA0
Q
Figure 4-1 shows the diagram for this pin. The RA1 pin
is configurable to function as one of the following:
VROUT
ANS0
D
RA1/AN1/C12IN0-/VREF/ICSPCLK
FIGURE 4-2:
General purpose I/O
Analog input for the A/D
Analog input to Comparator 1
In-Circuit Serial Programming™ data
FIGURE 4-1:
4.2.3.2
WR
TRISA
Q
CK Q
VSS
Q
CK Q
RD
TRISA
VSS
ANS0
RD
PORTA
RD
TRISA
Q
D
D
Q
EN
RD
PORTA
Q
D
WR
IOCA
D
Q
D
Q
EN
WR
IOCA
CK Q
RD
IOCA
CK Q
Q
RD
IOCA
D
EN
Q
Q
Q1
Q1
D
Q3
Interrupt-onchange
EN
D
Q3
Interrupt-onchange
EN
EN
RD PORTA
To Comparators
To A/D Converter
RD PORTA
To Comparator
To A/D Converter
DS41249E-page 38
© 2008 Microchip Technology Inc.
PIC16F785/HV785
4.2.3.3
4.2.3.4
RA2/AN2/T0CKI/INT/C1OUT
RA3/MCLR/VPP
Figure 4-3 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following:
Figure 4-4 shows the diagram for this pin. The RA3 pin
is configurable to function as one of the following:
•
•
•
•
•
• General purpose input
• Master Clear Reset with weak pull-up
General purpose I/O
Analog input for the A/D
Clock input for TMR0
External edge triggered interrupt
Digital output from Comparator 1
FIGURE 4-4:
Data Bus
D
BLOCK DIAGRAM OF RA3
Q
MCLRE
VDD
FIGURE 4-3:
BLOCK DIAGRAM OF RA2
C1OE
ANS2
WR
WPUA
D
CK
Weak
Q
Q
RAPU
MCLRE
Input
pin
VSS
MCLRE
D
RAPU
Weak
Reset
RD
PORTA
WR
IOCA
CK
VSS
Q
Q
D
Q
EN
D
CK
VDD
Q
Q
D
CK
RD
IOCA
Q
1
D
EN
0
WR
TRISA
Q
RD
TRISA
VDD
RD
WPUA
WR
PORTA
CK
RD
WPUA
C1OUT
Data Bus
WR
WPUA
I/O pin
Interrupt-onChange
Q
Q1
D
Q
Q3
EN
Q
VSS
RD PORTA
ANS2
RD
TRISA
RD
PORTA
Q
D
D
Q
EN
WR
IOCA
CK
Q
Q
RD
IOCA
D
EN
Q
Q1
D
Q3
Interrupt-onChange
EN
RD PORTA
To TMR0
To INT
To A/D Converter
© 2008 Microchip Technology Inc.
DS41249E-page 39
PIC16F785/HV785
4.2.3.5
RA4/AN3/T1G/OSC2/CLKOUT
4.2.3.6
RA5/T1CKI/OSC1/CLKIN
Figure 4-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
Figure 4-6 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
•
•
•
•
•
•
•
•
•
General purpose I/O
Analog input for the A/D
TMR1 gate input
Crystal/resonator connection
Clock output
General purpose I/O
TMR1 clock input
Crystal/resonator connection
Clock input
FIGURE 4-6:
FIGURE 4-5:
ANS3
Data Bus
WR
WPUA
D
CK
BLOCK DIAGRAM OF RA5
BLOCK DIAGRAM OF RA4
INTOSC
Mode
CLK(1)
Modes
Q
VDD
Q
Data Bus
Weak
WR
WPUA
D
CLK modes(1)
VDD
Q
CK
Weak
Q
RAPU
RD
WPUA
Oscillator
Circuit
VDD
OSC1
RAPU
RD
WPUA
VDD
Oscillator
Circuit
OSC2
FOSC/4
D
WR
PORTA
CK
D
0
Q
Q
1
I/O pin
CLKOUT
Enable
INTOSC/
RC/EC(2)
CK
CK
INTOSC
Mode
RD
TRISA
(2)
ANS3
RD
PORTA
RD
PORTA
D
CK
Q
Q
CLKOUT
Enable
D
I/O pin
Q
D S Q
WR
TRISA
RD
TRISA
WR
IOCA
CK
VSS
VSS
D S Q
WR
TRISA
WR
PORTA
Q
Q
Q
WR
IOCA
EN
Q
Q
RD
IOCA
Q
Q
D
EN
Q
D
EN
Q1
Q
D
Q3
Interrupt-onCHANGE
CK
RD
IOCA
D
EN
Q
Q
D
EN
Q1
D
Q3
Interrupt-onChange
EN
RD PORTA
RD PORTA
To TMR1 or CLKGEN
To T1G
To A/D Converter
Note
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
1: CLK modes are XT, HS, LP and LPTMR1.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
2: With CLKOUT option.
DS41249E-page 40
© 2008 Microchip Technology Inc.
PIC16F785/HV785
TABLE 4-1:
Name
ANSEL0
CM1CON0
CM2CON1
IOCA
OPTION_REG
REFCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0
0000 0000
0000 0000
—
—
—
—
T1GSS
C2SYNC
00-- --10
00-- --10
MC1OUT MC2OUT
INTCON
PORTA
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
0000 0000
—
—
IOCA5
IOCA4
IOCA3
IOCA2
IOCA1
IOCA0
--00 0000
--00 0000
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx
--uu uuuu
—
BGST
--00 000-
—
T1CON
T1GINV
TRISA
—
—
—
—
WPUA
Legend:
VRBB
VREN
VROE
CVROE
—
--00 000-
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0000 0000
0000 0000
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111
--11 1111
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
--11 1111
--11 1111
TMR1GE T1CKPS1
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
© 2008 Microchip Technology Inc.
DS41249E-page 41
PIC16F785/HV785
4.3
PORTB and TRISB Registers
The TRISB register controls the direction of the
PORTB pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISB
register are maintained set when using them as analog
inputs. I/O pins configured as analog input always read
‘0’.
PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 46). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding
output driver in a High-Impedance mode). Clearing a
TRISB bit (= 0) will make the corresponding PORTB
pin an output (i.e., put the contents of the output latch
on the selected pin). Example 4-2 shows how to initialize PORTB.
Note:
Reading the PORTB register (Register 4-5) reads the
status of the pins, whereas writing to it will write to the
port latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written to the port data latch.
EXAMPLE 4-2:
Pin RB6 is an open drain output. All other PORTB pins
have full CMOS output drivers.
REGISTER 4-5:
The ANSEL1 (93h) register must be initialized to configure an analog channel as a
digital input. Pins configured as analog
inputs will read ‘0’.
BCF
BCF
CLRF
BSF
BCF
BCF
MOVLW
MOVWF
STATUS,RP0
STATUS,RP1
PORTB
STATUS,RP0
ANSEL1,2
ANSEL1,3
30h
TRISB
BCF
STATUS,RP0
INITIALIZING PORTB
;Bank 0
;
;Init PORTB
;Bank 1
;digital I/O - RB4
;digital I/O - RB5
;Set RB<5:4> as inputs
;and set RB<7:6>
;as outputs
;Bank 0
PORTB: PORTB REGISTER
R/W-x
R/W-x
R/W-x(1)
R/W-x(1)
U-0
U-0
U-0
U-0
RB7
RB6
RB5
RB4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
RB<7:4>: PORTB General Purpose I/O Pin bits
1 = Port pin is greater than VIH
0 = Port pin is less than VIL
bit 3-0
Unimplemented: Read as ‘0’
x = Bit is unknown
Note 1: Data latches are unknown after a POR, but each port bit reads ‘0’ when the corresponding analog select bit is
‘1’ (see Register 12-2 on page 82).
REGISTER 4-6:
TRISB: PORTB TRI-STATE REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
U-0
U-0
U-0
U-0
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
TRISB<7:4>: PORTB Tri-State Control bits
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
bit 3-0
Unimplemented: Read as ‘0’
DS41249E-page 42
x = Bit is unknown
© 2008 Microchip Technology Inc.
PIC16F785/HV785
4.3.1
PORTB PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTB pin is multiplexed with other functions.
The pins and their combined functions are briefly
described here. For specific information about individual functions such as the PWM, operational amplifier,
or the A/D, refer to the appropriate section in this Data
Sheet.
4.3.1.1
FIGURE 4-8:
WR
TRISB
CK
CK
Q
VSS
RD
TRISB
Q
D
4.3.1.4
RB7/SYNC
The RB7/SYNC pin is configurable to function as one
of the following:
• General purpose I/O
• PWM synchronization input and output
VDD
FIGURE 4-9:
Q
I/O Pin
D
I/O Pin
Q
EN
Data Bus
CK
Q
RD
PORTB
BLOCK DIAGRAM OF RB4
AND RB5
Q
CK
VSS
• General purpose I/O
• Analog input to the A/D
• Analog input to Op Amp 2
D
WR
PORTB
Q
N
RB5/AN11/OP2+
FIGURE 4-7:
BLOCK DIAGRAM OF RB6
Data Bus
D
The RB5/AN11/OP2+ pin is configurable to function as
one of the following:
WR
TRISB
• Open drain general purpose I/O
D
• General purpose I/O
• Analog input to the A/D
• Analog input to Op Amp 2
4.3.1.2
RB6
The RB6 pin is configurable to function as the following:
RB4/AN10/OP2-
The RB4/AN10/OP2- pin is configurable to function as
one of the following:
WR
PORTB
4.3.1.3
Q
BLOCK DIAGRAM OF RB7
PH1EN
PH2EN
PWM Master
Q
VSS
ANS10 (RB4)
ANS11 (RB5)
RD
TRISB
Sync out
Data Bus
D
Q
D
WR
PORTB
CK
VDD
Q
Q
1
EN
0
RD
PORTB
D
To A/D Converter
To Op Amp 2
WR
TRISB
CK
I/O Pin
Q
Q
VSS
RD
TRISB
Q
D
EN
RD
PORTB
to PWM Sync Input
© 2008 Microchip Technology Inc.
DS41249E-page 43
PIC16F785/HV785
TABLE 4-2:
Name
ANSEL1
OPA2CON
PORTB
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
—
—
—
—
ANS11
ANS10
ANS9
ANS8
---- 1111
---- 1111
OPAON
—
—
—
—
—
—
—
0--- ----
0--- ----
RB7
RB6
RB5
RB4
—
—
—
—
xxxx ----
uuuu ----
PWMCON0
PRSEN
PASEN
BLANK2
BLANK1
SYNC1
SYNC0
PH2EN
PH1EN
0000 0000
0000 0000
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
1111 ----
1111 ----
Legend:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
DS41249E-page 44
© 2008 Microchip Technology Inc.
PIC16F785/HV785
4.4
PORTC and TRISC Registers
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 48). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding
output driver in a High-Impedance mode). Clearing a
TRISC bit (= 0) will make the corresponding PORTC
pin an output (i.e., put the contents of the output latch
on the selected pin). Example 4-3 shows how to initialize PORTC.
Reading the PORTC register (Register 4-7) reads the
status of the pins, whereas writing to it will write to the
port latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the port data latch.
The TRISC register controls the direction of the
PORTC pins, even when they are being used as
analog inputs. The user must ensure the bits in the
TRISC register are maintained set when using them as
analog inputs. I/O pins configured as analog input
always read ‘0’.
REGISTER 4-7:
When RC4 or RC5 is configured as an op amp output,
the corresponding RC4 or RC5 digital output driver will
automatically be disabled regardless of the TRISC<4>
or TRISC<5> value.
Note:
The ANSEL0 (91h) and ANSEL1 (93h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
EXAMPLE 4-3:
BCF
BCF
CLRF
BSF
CLRF
CLRF
MOVLW
MOVWF
STATUS,RP0
STATUS,RP1
PORTC
STATUS,RP0
ANSEL0
ANSEL1
0Ch
TRISC
BCF
STATUS,RP0
INITIALIZING PORTC
;Bank 0
;Init PORTC
;Bank 1
;digital I/O
;digital I/O
;Set RC<3:2> as inputs
; and set RC<5:4,1:0>
; as outputs
;Bank 0
PORTC: PORTC REGISTER
R/W-x(1)
R/W-x(1)
R/W-x
R/W-x
R/W-x(1)
R/W-x(1)
R/W-x(1)
R/W-x(1)
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
RC<7:0>: PORTC General Purpose I/O Pin bits
1 = Port pin is greater than VIH
0 = Port pin is less than VIL
Note 1: Data latches are unknown after a POR, but each port bit reads ‘0’ when the corresponding analog select bit
is ‘1’ (see Registers 12-1 and 12-2 on page 82).
REGISTER 4-8:
TRISC: PORTC TRI-STATE REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
TRISC<7:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
© 2008 Microchip Technology Inc.
DS41249E-page 45
PIC16F785/HV785
4.4.1
PORTC PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTC pin is multiplexed with other functions.
The pins and their combined functions are briefly
described here. For specific information about individual functions such as the comparator or the A/D, refer
to the appropriate section in this Data Sheet.
4.4.1.1
4.4.1.4
RC1/AN5/C12IN1-/PH1
The RC1 is configurable to function as one of the
following:
•
•
•
•
General purpose I/O
Analog input for the A/D Converter
Analog input to Comparators 1 and 2
Digital output from the Two-Phase PWM
RC0/AN4/C2IN+
The RC0 is configurable to function as one of the
following:
• General purpose I/O
• Analog input for the A/D Converter
• Non-inverting input to Comparator 2
4.4.1.2
FIGURE 4-11:
PH1EN
PH1
Data Bus
D
RC6/AN8/OP1-
The RC6/AN8/OP1- pin is configurable to function as
one of the following:
• General purpose I/O
• Analog input for the A/D
• Inverting input for Op Amp 1
4.4.1.3
BLOCK DIAGRAM OF RC1
WR
PORTC
CK
VDD
Q
Q
1
0
D
WR
TRISC
CK
I/O Pin
Q
Q
VSS
ANS5
RC7/AN9/OP1+
The RC7/AN9/OP1+ pin is configurable to function as
one of the following:
• General purpose I/O
• Analog input for the A/D
• Non-inverting input for Op Amp 1
RD
TRISC
Q
D
EN
RD
PORTC
To Comparators
FIGURE 4-10:
BLOCK DIAGRAM OF
RC0, RC6 AND RC7
To A/D Converter
Data Bus
D
WR
PORTC
CK
VDD
Q
Q
I/O Pin
D
WR
TRISC
CK
Q
Q
VSS
ANS4 (RC0)
ANS8 (RC6)
ANS9 (RC7)
RD
TRISC
Q
D
EN
RD
PORTC
To Comparators (RC0)
To A/D Converter
To Op Amp1 (RC6, RC7)
DS41249E-page 46
© 2008 Microchip Technology Inc.
PIC16F785/HV785
4.4.1.5
4.4.1.7
RC2/AN6/C12IN2-/OP2
RC4/C2OUT/PH2
The RC2 is configurable to function as one of the
following:
The RC4 is configurable to function as one of the
following:
•
•
•
•
• General purpose I/O
• Digital output from Comparator 2
• Digital output from the Two-Phase PWM
General purpose I/O
Analog input for the A/D Converter
Analog input to Comparators 1 and 2
Analog output from Op Amp 2
FIGURE 4-13:
4.4.1.6
The RC3 is configurable to function as one of the
following:
•
•
•
•
BLOCK DIAGRAM OF RC4
RC3/AN7/C12IN3-/OP1
General purpose I/O
Analog input for the A/D Converter
Analog input to Comparators 1 and 2
Analog output for Op Amp 1
FIGURE 4-12:
C2OE
PH2EN
PH2
1
C2OUT
0
Data Bus
BLOCK DIAGRAM OF RC2
AND RC3
D
WR
PORTC
CK
VDD
Q
Q
1
Op Amp out
0
OPAON
Data Bus
D
D
WR
PORTC
CK
WR
TRISC
VDD
Q
WR
TRISC
CK
Q
VSS
RD
TRISC
Q
I/O Pin
D
CK
I/O Pin
Q
Q
D
Q
EN
Q
VSS
ANS6 (RC2)
ANS7 (RC3)
RD
TRISC
Q
RD
PORTC
D
EN
RD
PORTC
To Comparators
To A/D Converter
© 2008 Microchip Technology Inc.
DS41249E-page 47
PIC16F785/HV785
4.4.1.8
RC5/CCP1
FIGURE 4-14:
The RC5 is configurable to function as one of the
following:
CCP1CON<1>
CCP1CON<3>
• General purpose I/O
• Digital input for the capture/compare
• Digital output for the CCP
CCP1CON<2>
BLOCK DIAGRAM OF RC5
CCP out
Data Bus
D
WR
PORTC
CK
VDD
Q
Q
1
0
D
WR
TRISC
CK
I/O Pin
Q
Q
VSS
RD
TRISC
Q
D
EN
RD
PORTC
to CCP Capture Input
TABLE 4-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on all
other Resets
Bit 6
ANSEL1
—
—
—
—
ANS11
ANS10
ANS9
ANS8
---- 1111
---- 1111
CCP1CON
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
0000 0000
OPA1CON
OPAON
—
—
—
—
—
—
—
0--- ----
0--- ----
OPA2CON
OPAON
—
—
—
—
—
—
—
0--- ----
0--- ----
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
PORTC
Bit 5
Value on
POR, BOR
Bit 7
PWMCON0
PRSEN
PASEN
BLANK2
BLANK1
SYNC1
SYNC0
PH2EN
PH1EN
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
DS41249E-page 48
© 2008 Microchip Technology Inc.
PIC16F785/HV785
5.0
TIMER0 MODULE
RA2/AN2/T0CKI/INT/C1OUT. The incrementing edge
is determined by the source edge (T0SE) control bit of
the OPTION Register. Clearing the T0SE bit selects the
rising edge.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Note 1: Counter mode has specific external clock
requirements.
2: The ANSEL0 (91h) register must be initialized to configure an analog channel as
a digital input. Pins configured as analog
inputs will read ‘0’.
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
5.2
Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit of the INTCON Register. The
interrupt can be masked by clearing the T0IE bit of the
INTCON Register. The T0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The Timer0 interrupt
cannot wake the processor from Sleep since the timer
is shut-off during Sleep.
Timer0 Operation
Timer mode is selected by clearing the T0CS bit of the
OPTION Register. In Timer mode, the Timer0 module
will increment every instruction cycle (without prescaler). If TMR0 is written, the increment is inhibited for
the following two instruction cycles. The user can work
around this by writing an adjusted value to the TMR0
register.
Counter mode is selected by setting the T0CS bit of the
OPTION Register. In this mode, the Timer0 module will
increment either on every rising or falling edge of pin
FIGURE 5-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT
(= FOSC/4)
Data Bus
0
8
RA2/AN2/T0CKI/INT/C1OUT
1
SYNC 2
Cycles
1
TMR0
0
T0SE(1)
T0CS(1)
0
8-bit
Prescaler
PSA
Set Flag bit T0IF
on Overflow
(1)
1
WDTE
8
PSA(1)
SWDTEN
PS<0:2>(1)
16-bit
Prescaler
31 kHz
INTRC
1
WDT
Time-out
0
16
Watchdog
Timer
PSA(1)
WDTPS<3:0>(2)
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG (see Register 2.2.2.3).
2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2).
© 2008 Microchip Technology Inc.
DS41249E-page 49
PIC16F785/HV785
5.3
5.4.1
Using Timer0 with an External
Clock
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
Reset, the following instruction sequence (Example 51 and Example 5-2) must be executed when changing
the prescaler assignment between Timer0 and WDT.
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2TOSC (and
a small RC delay of 20 ns) and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
5.4
SWITCHING PRESCALER
ASSIGNMENT
EXAMPLE 5-1:
CHANGING PRESCALER
(TIMER0→WDT)
BCF
STATUS,RP0
BCF
STATUS,RP1
CLRWDT
CLRF
TMR0
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this Data Sheet. The prescaler
assignment is controlled in software by the control bit
PSA of the OPTION Register. Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS<2:0> bits of the OPTION Register.
BSF
;Bank 0
;
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
STATUS,RP0
MOVLW
b’00101111’
MOVWF
OPTION_REG
CLRWDT
MOVLW
MOVWF
BCF
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
;Required if desired
; PS2:PS0 is
; 000 or 001
;
;Set postscaler to
; desired WDT rate
;Bank 0
b’00101xxx’
OPTION_REG
STATUS,RP0
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 5-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 5-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
TABLE 5-1:
BSF
BCF
STATUS,RP0
STATUS,RP1
MOVLW
b’xxxx0xxx’
MOVWF
BCF
OPTION_REG
STATUS,RP0
;Clear WDT and
; prescaler
;Bank 1
;
;Select TMR0,
; prescale, and
; clock source
;
;Bank 0
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
ANSEL0
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
0000 0000
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
OPTION_REG
TMR0
TRISA
Legend:
Timer0 Module Register
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
xxxx xxxx
uuuu uuuu
--11 1111
--11 1111
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
DS41249E-page 50
© 2008 Microchip Technology Inc.
PIC16F785/HV785
6.0
TIMER1 MODULE WITH GATE
CONTROL
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to enable/disable Timer1 and
select the various features of the Timer1 module.
The Timer1 module is the 16-bit counter of the
PIC16F785/HV785. Figure 6-1 shows the basic block
diagram of the Timer1 module. Timer1 has the following features:
•
•
•
•
•
•
•
16-bit timer/counter (TMR1H:TMR1L)
Readable and writable
Internal or external clock selection
Synchronous or asynchronous operation
Interrupt on overflow from FFFFh to 0000h
Wake-up upon overflow (Asynchronous mode)
Optional external enable input:
- Selectable gate source; T1G or C2 output
(T1GSS)
- Selectable gate polarity (T1GINV)
• Optional LP oscillator
FIGURE 6-1:
TIMER1 ON THE PIC16F785/HV785 BLOCK DIAGRAM
TMR1ON
TMR1GE
T1GINV
TMR1ON
TMR1GE
Set flag bit
TMR1IF on
Overflow
To C2 Comparator Module
TMR1 Clock
TMR1(1)
TMR1H
RA5/T1CKI/OSC1/CLKIN
0
TMR1L
Synchronized
clock input
Q D
1
EN
Oscillator
T1SYNC
*
1
RA4/AN3/T1G/OSC2/CLKOUT
T1OSCEN
INTOSC
Without CLKOUT
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
det
0
2
T1CKPS<1:0>
Sleep input
TMR1CS
1
LP
Sleep
SYNCC2OUT(2)
0
T1GSS
*
Note 1:
2:
ST Buffer is low power type when using LP OSC, or high-speed type when using T1CKI.
Timer1 increments on the rising edge.
SYNCC2OUT is the synchronized output from Comparator 2 (See Figure 9-2 on 66).
© 2008 Microchip Technology Inc.
DS41249E-page 51
PIC16F785/HV785
6.1
Timer1 Modes of Operation
Timer1 can operate in one of three modes:
• 16-bit Timer with prescaler
• 16-bit Synchronous counter
• 16-bit Asynchronous counter
In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on
the rising edge of the external clock input T1CKI. In
addition, the Counter mode clock can be synchronized
to the microcontroller system clock or run
asynchronously.
In Counter and Timer modules, the counter/timer clock
can be gated by the Timer1 gate, which can be
selected as either the T1G pin or Comparator 2 output.
If an external clock oscillator is needed (and the
microcontroller is using the LP oscillator or INTOSC
without CLKOUT), Timer1 can use the LP oscillator as
a clock source.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions.
• Timer1 enabled after POR Reset
• Write to TMR1H or TMR1L
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON = 1) when T1CKI
is low. See Figure 6-2.
6.2
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 Register
is set. To enable the interrupt on rollover, you must set
these bits:
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
Note:
6.3
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits, of the
T1CON Register, control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
6.4
Timer1 Gate
Timer1 gate source is software configurable to be T1G
pin or the output of Comparator 2. This allows the
device to directly time external events using T1G or
analog events using Comparator 2. See CM2CON1
(Register 9-3) for selecting the Timer1 gate source.
This feature can simplify the software for a Delta-Sigma
A/D Converter and many other applications. For more
information on Delta-Sigma A/D Converters, see the
Microchip web site (www.microchip.com).
Note:
TMR1GE bit, of the T1CON Register, must
be set to use either T1G or C2OUT as the
Timer1 gate source. See Register 9-3 for
more information on selecting the Timer1
gate source.
Timer1 gate can be inverted using the T1GINV bit of
the T1CON Register, whether it originates from the
T1G pin or Comparator 2 output. This configures
Timer1 to measure either the active high or active low
time between events.
• Timer1 Interrupt Enable bit of the PIE1 Register
• PEIE bit of the INTCON Register
• GIE bit of the INTCON Register
FIGURE 6-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Arrows indicate counter increments.
See note box in Section 6.1 “Timer1 Modes of Operation”.
DS41249E-page 52
© 2008 Microchip Technology Inc.
PIC16F785/HV785
REGISTER 6-1:
R/W-0
(1)
T1GINV
T1CON: TIMER1 CONTROL REGISTER
R/W-0
TMR1GE
(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
T1GINV: Timer1 Gate Invert bit (1)
1 = Timer1 gate is high true (see bit 6)
0 = Timer1 gate is low true (see bit 6)
bit 6
TMR1GE: Timer1 Gate Enable bit (2)
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 is on if Timer1 gate is true (see bit 7)
0 = Timer1 is on independent of Timer1 gate
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
bit 3
T1OSCEN: LP Oscillator Enable Control bit
If System Clock is INTOSC without CLKOUT or LP mode:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
x = Bit is unknown
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by T1GSS bit (CM2CON1<1>), as
a Timer1 gate source.
© 2008 Microchip Technology Inc.
DS41249E-page 53
PIC16F785/HV785
6.5
Timer1 Operation in
Asynchronous Counter Mode
6.6
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN of the T1CON Register.
The oscillator is a low power oscillator rated for 32.768
kHz. It will continue to run during Sleep. It is primarily
intended for a 32.768 kHz tuning fork crystal.
If control bit T1SYNC of the T1CON Register is set, the
external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase
clocks. The timer will continue to run during Sleep and
can generate an interrupt on overflow, which will wakeup the processor. However, special precautions in
software are needed to read/write the timer
(Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Note:
6.5.1
Timer1 Oscillator
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is also the LP oscillator or is
derived from the internal oscillator. As with the system
LP oscillator, the user must provide a software time
delay to ensure proper oscillator start-up.
The ANSEL0 (91h) register must be initialized to configure an analog channel as a
digital input. Pins configured as analog
inputs will read ‘0’.
Sleep mode will not disable the system clock when the
system clock and Timer1 share the LP oscillator.
TRISA<5> and TRISA<4> bits are set when the Timer1
oscillator is enabled. RA5 and RA4 read as ‘0’ and
TRISA<5> and TRISA<4> bits read as ‘1’.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Note:
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
6.7
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
• Timer1 of the T1CON Register must be on
• TMR1IE bit of the PIE1 Register must be set
• PEIE bit of the INTCON Register must be set
The device will wake-up on an overflow. If the GIE bit of
the INTCON Register is set, the device will wake-up
and jump to the Interrupt Service Routine (0004h) on
an overflow. If the GIE bit is clear, execution will continue with the next instruction.
TABLE 6-1:
Name
ANSEL0
CM2CON1
REGISTERS ASSOCIATED WITH TIMER1
Bit 0
Value on all
other Resets
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
—
—
—
—
T1GSS
C2SYNC
00-- --10
00-- --10
0000 0000
MC1OUT MC2OUT
Bit 1
Value on
POR, BOR
Bit 7
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
0000 0000
0000 0000
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
T1CON
0000 0000
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
Legend:
– x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
DS41249E-page 54
© 2008 Microchip Technology Inc.
PIC16F785/HV785
7.0
TIMER2 MODULE
7.1
The Timer2 module timer is an 8-bit timer with the
following features:
•
•
•
•
•
8-bit timer (TMR2 register)
8-bit period register (PR2)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16
by 1’s)
• Interrupt on TMR2 match with PR2
Timer2 has a control register shown in Register 7-1.
TMR2 can be shut-off by clearing control bit TMR2ON,
of the T2CON Register, to minimize power consumption. Figure 7-1 is a simplified block diagram of the
Timer2 module. The prescaler and postscaler selection
of Timer2 are controlled by this register.
Timer2 Operation
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS<1:0> of the T2CON Register. The match output of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit TMR2IF), of the PIR1
Register.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 7-1:
T2CON: TIMER2 CONTROL REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS<3:0>: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Note 1:
x = Bit is unknown
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
© 2008 Microchip Technology Inc.
DS41249E-page 55
PIC16F785/HV785
7.2
Timer2 Interrupt
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
FIGURE 7-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
TMR2
Output
Prescaler
1:1, 1:4, 1:16
FOSC/4
TMR2
2
Reset
Postscaler
1:1 to 1:16
Comparator
EQ
T2CKPS<1:0>
4
PR2
TOUTPS<3:0>
TABLE 7-1:
Name
REGISTERS ASSOCIATED WITH TIMER2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
0000 0000
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 0000
0000 0000
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
PIR1
PR2
T2CON
Timer2 Module Period register
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
0000 0000
0000 0000
1111 1111
1111 1111
-000 0000
-000 0000
0000 0000
0000 0000
TMR2
Holding Register for the 8-bit TMR2 Register
Legend:
– x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
DS41249E-page 56
© 2008 Microchip Technology Inc.
PIC16F785/HV785
8.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
TABLE 8-1:
The Capture/Compare/PWM (CCP) module contains a
16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
CCP MODE – TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP. The special event trigger is
generated by a compare match and will clear both
TMR1H and TMR1L registers.
REGISTER 8-1:
CCP1CON: CCP OPERATION REGISTER
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’.
bit 5-4
DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M<3:0>: CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP module)
0001 = Unused (reserved)
0010 = Compare mode, toggle output on match (CCP1IF bit is set)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin
is unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; TMR1 is reset, and A/D conversion
is started if the A/D module is enabled. CCP1 pin is unaffected.)
110x = PWM mode: CCP1 output is high true.
111x = PWM mode: CCP1 output is low true.
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
© 2008 Microchip Technology Inc.
DS41249E-page 57
PIC16F785/HV785
8.1
8.1.4
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC5/CCP1. An event is defined as one of the
following and is configured by CCP1CON<3:0>:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
When a capture is made, the interrupt request flag bit
CCP1IF of the PIR1 Register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.
8.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the RC5/CCP1 pin should be configured as an input by setting the TRISC<5> bit.
Note:
If the RC5/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
÷ 1, 4, 16
Set Flag bit CCP1IF
(PIR1<5>)
RC5/CCP1
pin
CCPR1H
and
Edge Detect
CCPR1L
Capture
Enable
TMR1H
TMR1L
CCP1CON<3:0>
CCP PRESCALER
There are four prescaler settings specified by bits
CCP1M<3:0> of the CCP1CON Register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1:
CLRF
MOVLW
MOVWF
8.2
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; move value and CCP ON
CCP1CON
;Load CCP1CON with this
; value
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC5/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> of the CCP1CON Register. At the
same time, interrupt flag bit CCP1IF of the PIR1 Register is set.
Q’s
FIGURE 8-2:
8.1.2
COMPARE MODE
OPERATION BLOCK
DIAGRAM
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
8.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE of the PIE1 Register clear to avoid false interrupts and should clear the flag bit CCP1IF of the PIR1
Register following any such change in Operating mode.
CCP1CON<3:0>
Mode Select
Set Flag bit CCP1IF
(PIR1<5>)
4
CCPR1H CCPR1L
RC5/CCP1
Pin
Q
S
R
Output
Logic
Match
Comparator
TMR1H
TRISC<5>
Output Enable
TMR1L
Special Event Trigger
Special Event Trigger will:
• clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• set the GO/DONE bit (ADCON0<1>)
DS41249E-page 58
© 2008 Microchip Technology Inc.
PIC16F785/HV785
8.2.1
CCP1 PIN CONFIGURATION
8.2.4
The user must configure the RC5/CCP1 pin as an
output by clearing the TRISC<5> bit.
Note:
8.2.2
In this mode (CCP1M<3:0> = 1011), an internal
hardware trigger is generated, which may be used to
initiate an action. See Register 8-1.
Clearing the CCP1CON register will force
the RC5/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
The special event trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and CCPR1H, CCPR1L register
pair. The TMR1H, TMR1L register pair is not reset until
the next rising edge of the TMR1 clock. This allows the
CCPR1H, CCPR1L register pair to effectively provide a
16-bit programmable period register for Timer1. The
special event trigger output also starts an A/D
conversion provided that the A/D module is enabled.
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
Note 1: The special event trigger from the CCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the RC5/CCP1 pin is not
affected. The CCP1IF bit of the PIR1 Register is set,
causing a CCP interrupt (if enabled). See Register 8-1.
TABLE 8-2:
Name
CCP1CON
SPECIAL EVENT TRIGGER
2: Removing the match condition by changing the contents of the CCPR1H and
CCPR1L register pair between the clock
edge that generates the special event
trigger and the clock edge that generates
the TMR1 Reset, will preclude the Reset
from occurring.
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
uuuu uuuu
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
uuuu uuuu
CM2CON1
MC1OUT MC2OUT
—
—
—
—
T1GSS
C2SYNC
00-- --10
00-- --10
0000 0000
0000 0000
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
0000 0000
0000 0000
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
T1CON
0000 0000
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
--11 1111
--11 1111
TRISC
Legend:
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare or Timer1
module.
© 2008 Microchip Technology Inc.
DS41249E-page 59
PIC16F785/HV785
8.3
8.3.1
CCP PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the RC5/CCP1 pin. Since the RC5/CCP1 pin is
multiplexed with the PORTC data latch, the TRISC<5>
must be cleared to make the RC5/CCP1 pin an output.
Note:
Clearing the CCP1CON register will force
the PWM output latch to the default
inactive levels. This is not the PORTC I/O
data latch.
Figure 8-3 shows a simplified block diagram of PWM
operation.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.5 “Setup
for PWM Operation”.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
formula of Equation 8-1.
EQUATION 8-1:
PWM period = [ ( PR2 ) + 1 ] • 4 • T OSC •
(TMR2 prescale value)
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The RC5/CCP1 pin is set. (exception: if PWM
duty cycle = 0%, the pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
PWM PERIOD
The Timer2 postscaler (see Section 7.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
CCPR1H (Slave)
RC5/CCP1
Comparator
TMR2
(1)
R
Q
S
TRISC<5>
Comparator
Clear Timer2,
toggle PWM pin and
latch duty cycle
PR2
Note 1:
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits
of the prescaler, to create the 10-bit time
base.
The PWM output (Figure 8-4) has a time base
(period) and a time that the output stays high (duty
cycle). The frequency of the PWM is the inverse of
the period (1/period).
FIGURE 8-4:
CCP PWM OUTPUT
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = 0
DS41249E-page 60
© 2008 Microchip Technology Inc.
PIC16F785/HV785
8.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the DC1B<1:0> bits of the
CCP1CON register. Up to 10 bits of resolution is available. The CCPR1L contains the eight MSbs and the
DC1B<1:0> contains the two LSbs. In PWM mode,
CCPR1H is a read-only register.
Equation 8-2 is used to calculate the PWM duty cycle
in time.
EQUATION 8-2:
PWM DUTY CYCLE
PWM duty cycle = ( CCPR1L:CCP1CON<5:4> ) •
T OSC • (TMR2 prescale value)
CCPR1L and DC1B<1:0> can be written to at any time,
but the duty cycle value is not latched into CCPR1H
until after a match between PR2 and TMR2 occurs
(i.e. the period is complete). In PWM mode, CCPR1H
is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Because of the buffering, the module waits until the
timer resets, instead of starting immediately. This
means that enhanced PWM waveforms do not exactly
match the standard PWM waveforms, but are instead
offset by one full instruction cycle (4 TOSC).
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the RC5/CCP1 pin is cleared.
The maximum PWM resolution is a function of PR2 as
shown by Equation 8-3.
EQUATION 8-3:
PWM RESOLUTION
log [ 4 ( PR2 + 1 ) ]
Resolution = ------------------------------------------ bits
log ( 2 )
Note:
TABLE 8-3:
If the PWM duty cycle value is longer than
the PWM period, the assigned PWM pin(s)
will remain unchanged.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
Timer Prescale (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
1.22 kHz(1)
4.88 kHz(1)
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
Note 1: Changing duty cycle will cause a glitch.
© 2008 Microchip Technology Inc.
DS41249E-page 61
PIC16F785/HV785
8.3.3
OPERATION IN SLEEP MODE
8.3.5
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the RC5/CCP1 pin is driving a value, it will
continue to drive that value. When the device wakes
up, it will continue from this state.
8.3.3.1
OPERATION WITH FAIL-SAFE
CLOCK MONITOR
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the CCP to be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
See Section 3.0 “Clock Sources” for additional
details.
8.3.4
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
6.
TABLE 8-4:
Name
CCP1CON
SETUP FOR PWM OPERATION
Configure the PWM pin (RC5/CCP1) as an input
by setting the TRISC<5> bit.
Set the PWM period by loading the PR2 register.
Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit of the PIR1 Register.
• Set the TMR2 prescale value by loading the
T2CKPS bits of the T2CON Register.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON Register.
Enable PWM output after a new PWM cycle has
started:
• Wait until TMR2 overflows (TMR2IF bit is
set).
• Enable the RC5/CCP1 pin output by clearing
the TRISC<5> bit.
REGISTERS ASSOCIATED WITH CCP AND TIMER2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
0000 0000
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
uuuu uuuu
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
uuuu uuuu
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
0000 0000
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 0000
0000 0000
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
PIR1
PR2
T2CON
TMR2
TRISC
Legend:
Timer2 Module Period Register
—
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
Timer2 Module Register
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
0000 0000
0000 0000
1111 1111
1111 1111
-000 0000
-000 0000
0000 0000
0000 0000
--11 1111
--11 1111
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the CCP or Timer2 modules.
DS41249E-page 62
© 2008 Microchip Technology Inc.
PIC16F785/HV785
9.0
COMPARATOR MODULE
The Comparator module has two separate voltage
comparators: Comparator 1 (C1) and Comparator 2
(C2).
Each comparator offers the following list of features:
•
•
•
•
•
•
•
•
•
•
Control and Configuration register
Comparator output available externally
Programmable output polarity
Interrupt-on-change flags
Wake-up from Sleep
Configurable as feedback input to the PWM
Programmable four input multiplexer
Programmable two input reference selections
Programmable speed/power
Output synchronization to Timer1 clock input
(Comparator C2 only)
9.1
Control Registers
Both comparators have separate control and Configuration registers: CM1CON0 for C1 and CM2CON0 for
C2. In addition, Comparator C2 has a second control
register, CM2CON1, for synchronization control and
simultaneous reading of both comparator outputs.
9.1.1
COMPARATOR C1 CONTROL
REGISTER
The CM1CON0 register (shown in Register 9-1)
contains the control and Status bits for the following:
•
•
•
•
•
Comparator enable
Comparator input selection
Comparator reference selection
Output mode
Comparator speed
Setting C1ON (CM1CON0<7>) enables Comparator
C1 for operation.
Setting C1R of the CM1CON0 Register selects the
C1VREF output of the comparator voltage reference
module as the reference voltage for the comparator.
Clearing C1R selects the C1IN+ input on the RA0/AN0/
C1IN+/ICSPDAT pin.
The output of the comparator is available internally via
the C1OUT flag of the CM1CON0 Register. To make
the output available for an external connection, the
C1OE bit of the CM1CON0 Register must be set.
The polarity of the comparator output can be inverted
by setting the C1POL bit of the CM1CON0 Register.
Clearing C1POL results in a non-inverted output.
A complete table showing the output state versus input
conditions and the polarity bit is shown in Table 9-1.
TABLE 9-1:
C1 OUTPUT STATE VERSUS
INPUT CONDITIONS
Input Condition
C1POL
C1OUT
C1VN > C1VP
0
0
C1VN < C1VP
0
1
C1VN > C1VP
1
1
C1VN < C1VP
1
0
Note 1: The internal output of the comparator is
latched at the end of each instruction
cycle. External outputs are not latched.
2: The C1 interrupt will operate correctly
with C1OE set or cleared.
3: To output C1 on RA2/AN2/T0CKI/INT/
C1OUT:(C1OE = 1) and (C1ON = 1) and
(TRISA<2> = 0).
C1SP of the CM1CON0 Register configures the speed
of the comparator. When C1SP is set, the comparator
operates at its normal speed. Clearing C1SP operates
the comparator in a slower, low-power mode.
Bits C1CH<1:0> of the CM1CON0 Register select the
comparator input from the four analog pins AN<7:5,1>.
Note:
To use AN<7:5,1> as analog inputs the
appropriate bits must be programmed to
‘1’ in the ANSEL0 register.
© 2008 Microchip Technology Inc.
DS41249E-page 63
PIC16F785/HV785
FIGURE 9-1:
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
C1CH<1:0>
C1POL
2
D
RA1/AN1/C12IN0-/VREF/ICSPCLK
RC1/AN5/C12IN1-/PH1
Q1
0
RC2/AN6/C12IN2-/OP2
1
MUX
2
RC3/AN7/C12IN3-/OP1
3
Q
EN
To
Data Bus
RD_CM1CON0
Set C1IF
D
Q
Q3*RD_CM1CON0
C1ON(1)
C1R
EN
CL
NRESET
To PWM Logic
C1OE
C1SP
C1VN
RA0/AN0/C1IN+/ICSPDAT
C1VREF
0
MUX
1
C1OUT
C1VP C1
RA2/AN2/T0CKI/INT/C1OUT(2)
C1POL
Note 1:
2:
When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
Output shown for reference only. For more detail, see Figure 4-3.
DS41249E-page 64
© 2008 Microchip Technology Inc.
PIC16F785/HV785
REGISTER 9-1:
CM1CON0: COMPARATOR C1 CONTROL REGISTER 0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
C1ON: Comparator C1 Enable bit
1 = C1 Comparator is enabled
0 = C1 Comparator is disabled
bit 6
C1OUT: Comparator C1 Output bit
If C1POL = 1 (inverted polarity):
C1OUT = 1, C1VP < C1VN
C1OUT = 0, C1VP > C1VN
If C1POL = 0 (non-inverted polarity):
C1OUT = 1, C1VP > C1VN
C1OUT = 0, C1VP < C1VN
bit 5
C1OE: Comparator C1 Output Enable bit
1 = C1OUT is present on the RA2/AN2/T0CKI/INT/C1OUT pin(1)
0 = C1OUT is internal only
bit 4
C1POL: Comparator C1 Output Polarity Select bit
1 = C1OUT logic is inverted
0 = C1OUT logic is not inverted
bit 3
C1SP: Comparator C1 Speed Select bit
1 = C1 operates in normal speed mode
0 = C1 operates in low-power, slow speed mode
bit 2
C1R: Comparator C1 Reference Select bit (non-inverting input)
1 = C1VP connects to C1VREF output
0 = C1VP connects to RA0/AN0/C1IN+/ICSPDAT
bit 1-0
C1CH<1:0>: Comparator C1 Channel Select bits
00 = C1VN of C1 connects to RA1/AN1/C12IN0-/VREF/ICSPCLK
01 = C1VN of C1 connects to RC1/AN5/C12IN1-/PH1
10 = C1VN of C1 connects to RC2/AN6/C12IN2-/OP2
11 = C1VN of C1 connects to RC3/AN7/C12IN3-/OP1
x = Bit is unknown
Note 1: C1OUT will only drive RA2/AN2/T0CKI/INT/C1OUT if: (C1OE = 1) and (C1ON = 1) and (TRISA<2> = 0).
© 2008 Microchip Technology Inc.
DS41249E-page 65
PIC16F785/HV785
9.1.2
COMPARATOR C2 CONTROL
REGISTERS
The comparator output, C2OUT, can be inverted by
setting the C2POL bit of the CM2CON0 Register.
Clearing C2POL results in a non-inverted output.
The CM2CON0 register is a functional copy of the
CM1CON0 register described in Section 9.1.1 “Comparator C1 Control Register”. A second control register, CM2CON1, is also present for control of an
additional synchronizing feature, as well as mirrors of
both comparator outputs.
A complete table showing the output state versus input
conditions and the polarity bit is shown in Table 9-2.
TABLE 9-2:
C2 OUTPUT STATE VERSUS
INPUT CONDITIONS
Input Condition
C2POL
C2OUT
The CM2CON0 register, shown in Register 9-2,
contains the control and Status bits for Comparator C2.
C2VN > C2VP
0
0
C2VN < C2VP
0
1
Setting C2ON of the CM2CON0 Register enables
Comparator C2 for operation.
C2VN > C2VP
1
1
C2VN < C2VP
1
0
9.1.2.1
Control Register CM2CON0
Bits C2CH<1:0> of the CM2CON0 Register select the
comparator input from the four analog pins, AN<7:5,1>.
Note:
Note 1: The internal output of the comparator is
latched at the end of each instruction
cycle. External outputs are not latched.
To use AN<7:5,1> as analog inputs, the
appropriate bits must be programmed to 1
in the ANSEL0 register.
2: The C2 interrupt will operate correctly
with C2OE set or cleared. An external
output is not required for the C2 interrupt.
C2R of the CM2CON0 Register selects the reference
to be used with the comparator. Setting C2R of the
CM2CON0 Register selects the C2VREF output of the
comparator voltage reference module as the reference
voltage for the comparator. Clearing C2R selects the
C2IN+ input on the RC0/AN4/C2IN+ pin.
3: For C2 output on RC4/C2OUT/PH2:
(C2OE = 1) and (C2ON = 1) and
(TRISA<4> = 0).
The output of the comparator is available internally via
the C2OUT bit of the CM2CON0 Register. To make the
output available for an external connection, the C2OE
bit of the CM2CON0 Register must be set.
FIGURE 9-2:
C2SP of the CM2CON0 Register configures the speed
of the comparator. When C2SP is set, the comparator
operates at its normal speed. Clearing C2SP operates
the comparator in low-power mode.
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2POL
D
Q1
EN
RD_CM2CON0
2
C2CH<1:0>
Set C2IF
D
Q3*RD_CM2CON0
RA1/AN1/C12IN0-/VREF/ICSPCLK
C2ON(1)
0
RC1/AN5/C12IN1-/PH1
RC2/AN6/C12IN2-/OP2
1
MUX
2
RC3/AN7/C12IN3-/OP1
3
C2R
C2SP
C2VREF
Note
1:
2:
3:
0
MUX
1
Q
EN
CL
NRESET
C2VN
C2VP
To PWM Logic
C2OUT
C2
C2SYNC
C2POL
D
RC0/AN4/C2IN+
To
Data Bus
Q
From TMR1
Clock
Q
0
MUX
1
C20E
RC4/C2OUT/PH2(3)
SYNCC2OUT(2)
When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
Timer1 gate control (see Figure 6-1).
Output shown for reference only. For more detail, see Figure 4-13.
DS41249E-page 66
© 2008 Microchip Technology Inc.
PIC16F785/HV785
REGISTER 9-2:
CM2CON0: COMPARATOR C2 CONTROL REGISTER 0
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
C2ON: Comparator C2 Enable bit
1 = C2 Comparator is enabled
0 = C2 Comparator is disabled
bit 6
C2OUT: Comparator C2 Output bit
If C2POL = 1 (inverted polarity):
C2OUT = 1, C2VP < C2VN
C2OUT = 0, C2VP > C2VN
If C2POL = 0 (non-inverted polarity):
C2OUT = 1, C2VP > C2VN
C2OUT = 0, C2VP < C2VN
bit 5
C2OE: Comparator C2 Output Enable bit
1 = C2OUT is present on RC4/C2OUT/PH2(1)
0 = C2OUT is internal only
bit 4
C2POL: Comparator C2 Output Polarity Select bit
1 = C2OUT logic is inverted
0 = C2OUT logic is not inverted
bit 3
C2SP: Comparator C2 Speed Select bit
1 = C2 operates in normal speed mode
0 = C2 operates in low power, slow speed mode.
bit 2
C2R: Comparator C2 Reference Select bits (non-inverting input)
1 = C2VP connects to C2VREF
0 = C2VP connects to RC0/AN4/C2IN+
bit 1-0
C2CH<1:0>: Comparator C2 Channel Select bits
00 = C2VN of C2 connects to RA1/AN1/C12IN0-/VREF/ICSPCLK
01 = C2VN of C2 connects to RC1/AN5/C12IN1-/PH1
10 = C2VN of C2 connects to RC2/AN6/C12IN2-/OP2
11 = C2VN of C2 connects to RC3/AN7/C12IN3-/OP1
x = Bit is unknown
Note 1: C2OUT will only drive RC4/C2OUT/PH2 if: (C2OE = 1) and (C2ON = 1) and (TRISC<4> = 0).
© 2008 Microchip Technology Inc.
DS41249E-page 67
PIC16F785/HV785
9.1.2.2
Control Register CM2CON1
Comparator C2 has one additional feature: its output
can be synchronized to the Timer1 clock input. Setting
C2SYNC of the CM2CON1 Register synchronizes the
output of Comparator 2 to the falling edge of the Timer1
clock input (see Figure 9-2 and Register 9-3).
The CM2CON1 register also contains mirror copies of
both comparator outputs, MC1OUT and MC2OUT of
the CM2CON1 Register. The ability to read both outputs simultaneously from a single register eliminates
the timing skew of reading separate registers.
Note:
Obtaining the status of C1OUT or C2OUT
by reading CM2CON1 does not affect the
comparator interrupt mismatch registers.
REGISTER 9-3:
CM2CON1: COMPARATOR C2 CONTROL REGISTER 1
R-0
R-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
MC1OUT
MC2OUT
—
—
—
—
T1GSS
C2SYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
MC1OUT: Mirror Copy of C1OUT bit (CM1CON0<6>)
bit 6
MC2OUT: Mirror Copy of C2OUT bit (CM2CON0<6>)
bit 5-2
Unimplemented: Read as ‘0’
bit 1
T1GSS: Timer1 Gate Source Select bit
1 = Timer1 gate source is RA4/AN3/T1G/OSC2/CLKOUT
0 = Timer1 gate source is SYNCC2OUT.
bit 0
C2SYNC: C2 Output Synchronous Mode bit
1 = C2 output is synchronous to falling edge of TMR1 clock
0 = C2 output is asynchronous
DS41249E-page 68
x = Bit is unknown
© 2008 Microchip Technology Inc.
PIC16F785/HV785
9.2
Comparator Outputs
The comparator outputs are read through the
CM1CON0, COM2CON0 or CM2CON1 registers.
CM1CON0 and CM2CON0 each contain the individual
comparator output of Comparator 1 and Comparator 2,
respectively. CM2CON2 contains a mirror copy of both
comparator outputs facilitating a simultaneous read of
both comparators. These bits are read-only. The
comparator outputs may also be directly output to the
RA2/AN2/T0CKI/INT/C1OUT and RC4/C2OUT/PH2
I/O pins. When enabled, multiplexers in the output path
of the RA2 and RC4 pins will switch and the output of
each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 9-1 and Figure 9-2
show the output block diagrams for Comparators 1 and
2, respectively.
The TRIS bits will still function as an output enable/
disable for the RA2/AN2/T0CKI/INT/C1OUT and RC4/
C2OUT/PH2 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C1POL and C2POL bits of the CMxCON0
Register.
Timer1 gate source can be configured to use the T1G
pin or Comparator 2 output as selected by the T1GSS
bit of the CM2CON1 Register. The Timer1 gate feature
can be used to time the duration or interval of analog
events. The output of Comparator 2 can also be synchronized with Timer1 by setting the C2SYNC bit of the
CM2CON1 Register. When enabled, the output of
Comparator 2 is latched on the falling edge of the
Timer1 clock source. If a prescaler is used with Timer1,
Comparator 2 is latched after the prescaler. To prevent
a race condition, the Comparator 2 output is latched on
the falling edge of the Timer1 clock source and Timer1
increments on the rising edge of its clock source. See
the Comparator 2 Block Diagram (Figure 9-2) and the
Timer1 Block Diagram (Figure 6-1) for more
information.
It is recommended to synchronize Comparator 2 with
Timer1 by setting the C2SYNC bit when Comparator 2
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if Comparator 2 changes
during an increment.
© 2008 Microchip Technology Inc.
9.3
Comparator Interrupts
The comparator interrupt flags are set whenever there
is a change in the output value of its respective comparator. Software will need to maintain information about
the status of the output bits, as read from
CM2CON0<7:6>, to determine the actual change that
has occurred. The CxIF bits, PIR1<4:3>, are the
Comparator Interrupt Flags. Each comparator interrupt
bit must be reset in software by clearing it to ‘0’. Since
it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
The CxIE bits of the PIE1 Register and the PEIE bit of
the INTCON Register must be set to enable the interrupts. In addition, the GIE bit must also be set. If any of
these bits are cleared, the interrupt is not enabled,
though the CxIF bits will still be set if an interrupt condition occurs.
The comparator interrupt of the PIC16F785/HV785
differs from previous designs in that the interrupt flag is
set by the mismatch edge and not the mismatch level.
This means that the interrupt flag can be reset without
the additional step of reading or writing the CMxCON0
register to clear the mismatch registers. When the
mismatch registers are not cleared, an interrupt will not
occur when the comparator output returns to the
previous state. When the mismatch registers are
cleared, an interrupt will occur when the comparator
returns to the previous state.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CxIF of the PIR1 Register interrupt flag may not get set.
2: When either comparator is first enabled,
bias circuitry in the Comparator module
may cause an invalid output from the
comparator until the bias circuitry is stable. Allow about 1 μs for bias settling then
clear the mismatch condition and interrupt flags before enabling comparator
interrupts.
9.4
Effects of Reset
A Reset forces all registers to their Reset state. This
disables both comparators.
DS41249E-page 69
PIC16F785/HV785
10.0
VOLTAGE REFERENCES
There are two voltage references available in the
PIC16F785/HV785: The voltage referred to as the
comparator reference (CVREF) is a variable voltage
based on VDD; The voltage referred to as the VR reference (VR) is a fixed voltage derived from a stable band
gap source. Each source may be individually routed
internally to the comparators or output, buffered or
unbuffered, on the RA1/AN1/C12IN0-/VREF/ICSPCLK
pin.
10.1
Comparator Reference
The comparator module also allows the selection of an
internally generated voltage reference for one of the
comparator inputs. The VRCON register (Register 10-1)
controls the voltage reference module shown in
Figure 10-1.
10.1.1
CONFIGURING THE VOLTAGE
REFERENCE
The voltage reference can output 32 distinct voltage
levels, 16 in a high range and 16 in a low range.
The following equation determines the output voltages:
EQUATION 10-1:
CVREF OUTPUT VOLTAGE
VRR = 1 (low range):
CVREF = VR<3:0> x VDD/24
VRR = 0 (high range):
CVREF = (VDD/4) + (VR<3:0> x VDD/32)
10.1.2
VOLTAGE REFERENCE
ACCURACY/ERROR
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 10-1) keep CVREF from approaching VSS or
VDD. The exception is when the module is disabled by
clearing all CVROE, C1VREN and C2VREN bits. When
disabled with VR<3:0> = 0000 and VRR = 1 the reference voltage will be VSS. This allows the comparators
to detect a zero-crossing and not consume CVREF
module current.
The voltage reference is VDD derived and therefore, the
CVREF output changes with fluctuations in VDD. The
tested absolute accuracy of the comparator voltage
reference can be found in Table 19-8.
DS41249E-page 70
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 10-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
8R
VRR
16-1 Analog
MUX
CVREN(1)
15
CVREF
·
·
·
0
VR3:VR0
CVROE
C1VREN
C1VREF to
Comparator 1
Input
1
0
C2VREN
C2VREF to
Comparator 2
Input
1
0
VR
1.2 V
Note 1: See Register 10-1, bits 3-0.
© 2008 Microchip Technology Inc.
DS41249E-page 71
PIC16F785/HV785
REGISTER 10-1:
R/W-0
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
(1)
C1VREN
(1)
C2VREN
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VRR
—
VR3
VR2
VR1
VR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
C1VREN: Comparator 1 Voltage Reference Enable bit(1)
1 = CVREF circuit powered on and routed to C1VREF input of comparator 1
0 = 1.2 Volt VR routed to C1VREF input of comparator 1
bit 6
C2VREN: Comparator 2 Voltage Reference Enable bit(1)
1 = CVREF circuit powered on and routed to C2VREF input of comparator 2
0 = 1.2 Volt VR routed to C2VREF input of comparator 2
bit 5
VRR: Comparator Voltage Reference CVREF Range Selection bit
1 = Low Range
0 = High Range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR<3:0>: Comparator Voltage Reference CVREF Value Selection 0 ≤ VR<3:0> ≤ 15
When VRR = 1 and CVREN = 1: CVREF = (VR<3:0> x VDD/24)
When VRR = 0 and CVREN = 1: CVREF = (VDD/4) + (VR<3:0> x VDD/32)
When CxVREN = 0 and VREN = 1: CxVREF = 1.2V from VR module
Note 1: When C1VREN, C2VREN and CVROE (Register 10-2) are all low, the CVREF circuit is powered down and
does not contribute to IDD current.
DS41249E-page 72
© 2008 Microchip Technology Inc.
PIC16F785/HV785
10.2
VR Reference Module
The VR Reference module generates a 1.2V nominal
output voltage for use by the ADC and comparators.
The output voltage can also be brought out to the VREF
pin for user applications. This module uses a bandgap
as a reference. See Table 19-9 for detailed specifications. Register 10-2 shows the control register for the
VR module.
REGISTER 10-2:
REFCON: VOLTAGE REFERENCE CONTROL REGISTER
U-0
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
—
BGST
VRBB
VREN
VROE
CVROE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
BGST: Band Gap Reference Voltage Stable Flag bit
1 = Reference is stable
0 = Reference is not stable
bit 4
VRBB: Voltage Reference Buffer Bypass bit
1 = VREF output is not buffered. Power is removed from buffer amplifier.
0 = VREF output is buffered(1)
bit 3
VREN: Voltage Reference Enable bit (VR = 1.2V nominal)(2)
1 = VR reference is enabled
0 = VR reference is disabled and does not consume any current
bit 2
VROE: Voltage Reference Output Enable bit
If CVROE = 0:
1 = VREF output on RA1/AN1/C12IN0-/VREF/ICSPCLK pin is 1.2 volt VR analog reference
0 = Disabled, 1.2 volt VR analog reference is used internally only
If CVROE = 1:
VROE has no effect.
bit 1
CVROE: Comparator Voltage Reference Output Enable bit (see Figure 10-2)
1 = VREF output on RA1/AN1/C12IN0-/VREF/ICSPCLK pin is CVREF voltage
0 = VREF output on RA1/AN1/C12IN0-/VREF/ICSPCLK pin is controlled by VROE
bit 0
Unimplemented: Read as ‘0’
Note 1: Buffer amplifier common mode limitations require VREF ≤ (VDD - 1.4)V for buffered output.
2: VREN is fixed high for PIC16HV785 device.
© 2008 Microchip Technology Inc.
DS41249E-page 73
PIC16F785/HV785
10.2.1
VR STABILIZATION PERIOD
When the Voltage Reference module is enabled, it will
require some time for the reference and its amplifier
circuits to stabilize. The user program must include a
small delay routine to allow the module to settle. See
Section 19.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 10-2:
VR REFERENCE BLOCK DIAGRAM
VREN
CVREF
VRBB(1)
CVROE
(CVROE + (VREN*VROE))
1
EN
VROUT
1
0
Voltage
Reference
VRIN
1X
RA1/AN1/C12IN0-/VREF
0
Analog
Buffer
RDY
VR
To CVREF MUX
BGST
Note 1:
2:
Buffered output requires VRIN = (VDD - 1.4)V.
VREN is fixed high for PIC16HV785 device.
TABLE 10-1:
Name
REGISTERS ASSOCIATED WITH COMPARATOR AND VOLTAGE REFERENCE
MODULES
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
ANSEL0
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0
0000 0000
0000 0000
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0
0000 0000
0000 0000
—
—
—
—
T1GSS
C2SYNC
00-- --10
00-- --10
0000 ---0
CM2CON1
MC1OUT MC2OUT
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 ---0
PIR1
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
0000 ---0
0000 ---0
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx
--uu uuuu
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
—
—
BGST
VRBB
VREN
VROE
CVROE
—
--00 000-
--00 000--11 1111
REFCON
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
VRCON
C1VREN
C2VREN
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator.
DS41249E-page 74
© 2008 Microchip Technology Inc.
PIC16F785/HV785
11.0
OPERATIONAL AMPLIFIER
(OPA) MODULE
11.2
The OPA module is enabled by setting the OPAON bit
of the OPAxCON Register. When enabled, OPAON
forces the output driver of RC3/AN7/C12IN3-/OP1 for
OPA1, and RC2/AN6/C12IN2-/OP2 for OPA2, into
tristate to prevent contention between the driver and
the OPA output. The ADC and comparator inputs which
share the op amp pins operate normally when the op
amp is enabled.
The OPA module has the following features:
• Two independent Operational Amplifiers
• External connections to all ports
• 3 MHz Gain Bandwidth Product (GBWP)
11.1
Control Registers
Note:
The OPA1CON register, shown in Register 11-1,
controls OPA1. OPA2CON, shown in Register 11-2,
controls OPA2.
FIGURE 11-1:
OPAxCON Register
When OPA1 or OPA2 is enabled, the
RC3/AN7/C12IN3-/OP1 pin, or
RC2/AN6/C12IN2-/OP2 pin, respectively,
is driven by the op amp output, not by the
PORTC driver. Refer to Table 19-11 for the
electrical specifications for the op amp
output drive capability.
OPA MODULE BLOCK DIAGRAM
OPA1CON<OPAON>
RC7/AN9/OP1+
OPA1
RC6/AN8/OP1RC3/AN7/C12IN3-/OP1
TO ADC and Comparator MUXs
OPA2CON<OPAON>
RB5/AN11/OP2+
OPA2
RB4/AN10/OP2RC2/AN6/C12IN2-/OP2
TO ADC and Comparator MUXs
© 2008 Microchip Technology Inc.
DS41249E-page 75
PIC16F785/HV785
REGISTER 11-1:
OPA1CON: OP AMP 1 CONTROL REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
OPAON
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OPAON: Op Amp Enable bit
1 = Op Amp 1 is enabled
0 = Op Amp 1 is disabled
bit 6-0
Unimplemented: Read as ‘0’
REGISTER 11-2:
x = Bit is unknown
OPA2CON: OP AMP 2 CONTROL REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
OPAON
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OPAON: Op Amp Enable bit
1 = Op Amp 2 is enabled
0 = Op Amp 2 is disabled
bit 6-0
Unimplemented: Read as ‘0’
DS41249E-page 76
x = Bit is unknown
© 2008 Microchip Technology Inc.
PIC16F785/HV785
11.3
Effects of a Reset
Leakage current is a measure of the small source or
sink currents on the OPA+ and OPA- inputs. To minimize the effect of leakage currents, the effective impedances connected to the OPA+ and OPA- inputs should
be kept as small as possible and equal.
A device Reset forces all registers to their Reset state.
This disables both op amps.
11.4
OPA Module Performance
Input offset voltage is a measure of the voltage difference between the OPA+ and OPA- inputs in a closed
loop circuit with the OPA in its linear region. The offset
voltage will appear as a DC offset in the output equal to
the input offset voltage, multiplied by the gain of the
circuit. The input offset voltage is also affected by the
common mode voltage.
Common AC and DC performance specifications for
the OPA module:
•
•
•
•
•
Common Mode Voltage Range
Leakage Current
Input Offset Voltage
Open Loop Gain
Gain Bandwidth Product (GBWP)
Open loop gain is the ratio of the output voltage to the
differential input voltage, (OPA+) - (OPA-). The gain is
greatest at DC and falls off with frequency.
Common mode voltage range is the specified voltage
range for the OPA+ and OPA- inputs, for which the OPA
module will perform to within its specifications. The
OPA module is designed to operate with input voltages
between 0 and VDD-1.4V. Behavior for common mode
voltages greater than VDD-1.4V, or below 0V, are
beyond the normal operating range.
TABLE 11-1:
Gain Bandwidth Product or GBWP is the frequency
at which the open loop gain falls off to 0 dB.
11.5
Effects of Sleep
When enabled, the op amps continue to operate and
consume current while the processor is in Sleep mode.
REGISTERS ASSOCIATED WITH THE OPA MODULE
Bit 2
Value on
POR, BOR
Value on all
other Resets
ANS1
ANS0
1111 1111
1111 1111
ANS9
ANS8
---- 1111
---- 1111
—
—
0--- ----
0--- ----
—
—
0--- ----
0--- ----
Bit 7
Bit 6
Bit 5
Bit 4
ANSEL0
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANSEL1
—
—
—
—
ANS11
ANS10
OPA1CON
OPAON
—
—
—
—
—
OPA2CON
OPAON
—
—
—
—
—
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
1111 ----
1111 ----
TRISC
TRISC7 TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
Bit 3
Bit 0
Name
Bit 1
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for the OPA module.
© 2008 Microchip Technology Inc.
DS41249E-page 77
PIC16F785/HV785
NOTES:
DS41249E-page 78
© 2008 Microchip Technology Inc.
PIC16F785/HV785
12.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a 10-bit binary representation of that signal. The PIC16F785/HV785 has twelve
analog I/O inputs, plus two internal inputs, multiplexed
into one sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
The converter generates a binary result via successive
approximation and stores the result in a 10-bit register.
The voltage reference used in the conversion is software selectable to either VDD or a voltage applied by
the VREF pin. Figure 12-1 shows the block diagram of
the A/D on the PIC16F785/HV785.
FIGURE 12-1:
A/D BLOCK DIAGRAM
VDD
VCFG = 0
VREF
RA0/AN0/C1IN+/ICSPDAT
VCFG = 1
0
RA1/AN1/C12IN0-/VREF/ICSPCLK
RA2/AN2/T0CKI/INT/C1OUT
RA4/AN3/T1G/OSC2/CLKOUT
RC0/AN4/C2IN+
RC1/AN5/C12IN1-/PH1
RC2/AN6/C12IN2-/OP2
A/D
RC3/AN7/C12IN3-/OP1
10
GO/DONE
RC6/AN8/OP1RC7/AN9/OP1+
ADFM
RB4/AN10/OP2-
10
ADON(1)
RB5/AN11/OP2+
ADRESH
CVREF
13
VR
ADRESL
VSS
CHS<3:0>
Note 1:
When ADON = 0 all input channels are disconnected from ADC (no loading).
© 2008 Microchip Technology Inc.
DS41249E-page 79
PIC16F785/HV785
12.1
A/D Configuration and Operation
There are four registers available to control the
functionality of the A/D module:
1.
2.
3.
4.
ANSEL0 (Register 12-1)
ANSEL1 (Register 12-2)
ADCON0 (Register 12-3)
ADCON1 (Register 12-4)
12.1.1
The ANS<11:0> bits, of the ANSEL1 and ANSEL0
Registers, and the TRISA<4,2:0>, TRISB<5:4> and
TRISC<7:6,3:0>> bits control the operation of the A/D
port pins. Set the corresponding TRISx bits to ‘1’ to set
the pin output driver to its high-impedance state. Likewise, set the corresponding ANSx bit to disable the digital input buffer.
12.1.2
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
There are fourteen analog channels on the PIC16F785/
HV785. The CHS<3:0> bits of the ADCON0 Register
control which channel is connected to the sample and
hold circuit.
TABLE 12-1:
VOLTAGE REFERENCE
There are two options for the voltage reference to the
A/D converter: either VDD is used or an analog voltage
applied to VREF is used. The VCFG bit of the ADCON0
Register controls the voltage reference selection. If
VCFG is set, then the voltage on the VREF pin is the reference; otherwise, VDD is the reference.
12.1.4
ANALOG PORT PINS
Note:
12.1.3
CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits of the ADCON1 Register. There are seven
possible clock options:
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
For correct conversion, the A/D conversion clock
(1/TAD) must be selected to ensure a minimum TAD of
1.6 μs. Table 12-1 shows a few TAD calculations for
selected frequencies.
TAD VS. DEVICE OPERATING FREQUENCIES
A/D Clock Source (TAD)
Device Frequency
Operation
ADCS2:ADCS0
20 MHz
5 MHz
4 MHz
1.25 MHz
2 TOSC
000
100 ns(2)
400 ns(2)
500 ns(2)
1.6 μs
4 TOSC
100
200
ns(2)
ns(2)
μs(2)
3.2 μs
8 TOSC
001
400 ns(2)
1.6 μs
2.0 μs
6.4 μs
TOSC
101
800 ns(2)
3.2 μs
4.0 μs
12.8 μs(3)
32 TOSC
010
1.6 μs
6.4 μs
8.0 μs(3)
25.6 μs(3)
64 TOSC
110
3.2 μs
12.8 μs(3)
16.0 μs(3)
51.2 μs(3)
16
A/D RC
Legend:
Note 1:
2:
3:
4:
x11
2-6
μs(1), (4)
800
2-6
μs(1), (4)
1.0
2-6
μs(1), (4)
2-6 μs(1), (4)
Shaded cells are outside of recommended range.
The A/D RC source has a typical TAD time of 4 μs for VDD > 3.0V.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during Sleep.
DS41249E-page 80
© 2008 Microchip Technology Inc.
PIC16F785/HV785
12.1.5
STARTING A CONVERSION
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D
conversion
sample.
Instead,
the
ADRESH:ADRESL registers will retain the value of the
previous conversion. After an aborted conversion, a
2 TAD delay is required before another acquisition can
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled)
Note:
FIGURE 12-2:
The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
A/D CONVERSION TAD CYCLES
TCY to TAD TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
b9
b8
b7
b6
b5
b4
b3
TAD9 TAD10 TAD11
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO bit
12.1.6
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
CONVERSION OUTPUT
The A/D conversion can be supplied in two formats: left
or right justified. The ADFM bit of the ADCON0 register
controls the output format. Figure 12-3 shows the output formats.
FIGURE 12-3:
10-BIT A/D RESULT FORMAT
ADRESH (ADDRESS:1Eh)
(ADFM = 0)
ADRESL (ADDRESS:9Eh)
MSB
LSB
bit 7
bit 0
bit 7
10-bit A/D Result
(ADFM = 1)
bit 0
Unimplemented: Read as ‘0’
MSB
bit 7
Unimplemented: Read as ‘0’
© 2008 Microchip Technology Inc.
LSB
bit 0
bit 7
bit 0
10-bit A/D Result
DS41249E-page 81
PIC16F785/HV785
REGISTER 12-1:
ANSEL0: ANALOG SELECT REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
ANS<7:0>: Analog Select bits
Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Port reads of pins configured assigned as analog inputs will read as
‘0’.
REGISTER 12-2:
ANSEL1: ANALOG SELECT REGISTER
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
—
ANS11
ANS10
ANS9
ANS8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
ANS<11:8>: Analog Select bits
Analog select between analog or digital function on pins AN<11:8>, respectively.
1 = Analog input. Pin is assigned as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. Port reads of pins assigned as analog inputs will read as ‘0’.
TABLE 12-2:
ANALOG SELECT CROSS REFERENCE
Mode
Analog
Select
Reference
ANS11
ANS10
ANS9
ANS8
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
Analog
Channel
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
I/O Pin
RB5
RB4
RC7
RC6
RC3
RC2
RC1
RC0
RA4
RA2
RA1
RA0
DS41249E-page 82
© 2008 Microchip Technology Inc.
PIC16F785/HV785
REGISTER 12-3:
ADCON0: A/D CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
VCFG
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ADFM: A/D Result Formed Select bit
1 = Right justified
0 = Left justified
bit 6
VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
bit 5-2
CHS<3:0>: Analog Channel Select bits
0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Channel 04 (AN4)
0101 = Channel 05 (AN5)
0110 = Channel 06 (AN6)
0111 = Channel 07 (AN7)
1000 = Channel 08 (AN8)
1001 = Channel 09 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = CVREF
1101 = VR
1110 = Reserved. Do not use.
1111 = Reserved. Do not use.
bit 1
GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0
ADON: A/D Enable bit
1 = A/D converter module is enabled
0 = A/D converter is shut-off and consumes no operating current
© 2008 Microchip Technology Inc.
DS41249E-page 83
PIC16F785/HV785
REGISTER 12-4:
ADCON1: A/D CONTROL REGISTER 1
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
—
ADCS2
ADCS1
ADCS0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 3-0
Unimplemented: Read as ‘0’
DS41249E-page 84
© 2008 Microchip Technology Inc.
PIC16F785/HV785
12.1.7
CONFIGURING THE A/D
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Table 19-16 and
Table 19-17. After this sample time has elapsed, the
A/D conversion can be started.
These steps should be followed for an A/D conversion:
1.
2.
3.
4.
5.
6.
7.
Configure the A/D module:
• Configure analog/digital I/O (ANSx)
• Select A/D conversion clock in the ADCON1
Register
• Configure voltage reference in the ADCON0
Register
• Select A/D input channel in the ADCON0
Register
• Select result format in the ADCON0 Register
• Turn on A/D module in the ADCON0 Register
Configure A/D interrupt (if desired):
• Clear ADIF bit of the PIR1 Register
• Set ADIE bit of the PIE1 Register
• Set PEIE and GIE bits of the INTCON Register
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0<1>)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
(with interrupts disabled); OR
• Waiting for the A/D interrupt
Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
© 2008 Microchip Technology Inc.
EXAMPLE 12-1:
A/D CONVERSION
;This code block configures the A/D
;for polling, Vdd reference, R/C clock
;and RA0 input.
;
;Conversion start and wait for complete
;polling code included.
;
BCF
STATUS,RP1 ;Bank 1
BSF
STATUS,RP0 ;
MOVLW B’01110000’ ;A/D RC clock
MOVWF ADCON1
BSF
TRISA,0
;Set RA0 to input
BSF
ANSEL0,0
;Set RA0 to analog
BCF
STATUS,RP0 ;Bank 0
MOVLW B’10000001’ ;Right, Vdd Vref, AN0
MOVWF ADCON0
CALL
SampleTime ;Wait min sample time
BSF
ADCON0,GO
;Start conversion
BTFSC ADCON0,GO
;Is conversion done?
GOTO
$-1
;No, test again
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF RESULTHI
BSF
STATUS,RP0 ;Bank 1
MOVF
ADRESL,W
;Read lower 8 bits
BCF
STATUS,RP0 ;Bank 0
MOVWF RESULTLO
DS41249E-page 85
PIC16F785/HV785
12.2
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-4. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 12-4. The maximum recommended impedance for analog sources is 10 kΩ. As
the impedance is decreased, the acquisition time may
be decreased. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
EQUATION 12-1:
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k Ω 5.0V V DD
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + Tc + T COFF
= 5µs + Tc + [ ( Temperature - 25°C ) ( 0.05µs/°C ) ]
The value for Tc can be approximated with the following equations:
1
V AP P LIED ⎛⎝ 1 – ------------⎞⎠ = V C HOLD
2047
;[1] Vchold charged to within 1/2 lsb
–T C
----------⎞
⎛
RC
V A PP LIED ⎜ 1 – e ⎟ = V CHOLD
⎝
⎠
;[2] Vchold charge response to Vapplied
– Tc
---------⎞
⎛
RC
1
V A PP LIE D ⎜ 1 – e ⎟ = V AP P LI ED ⎛ 1 – ------------⎞
⎝
2047⎠
⎝
⎠
;Combining [1] and [2]
Solving for Tc:
T c = – C HOLD ( Ric + Rss + Rs ) ln(1/2047)
= – 10pF ( 1k Ω + 7k Ω + 10k Ω ) ln(0.0004885)
= 1.37 µs
Therefore:
Tacq = 5µs + 1.37µs + [ ( 50°C- 25°C ) ( 0.05µs/°C ) ]
=
7.62 µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
DS41249E-page 86
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 12-4:
ANALOG INPUT MODEL
VDD
RS
ANx
CPIN
5 pF
VA
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
= 10 pF
ILEAKAGE
± 500 nA
VSS
6V
5V
VDD 4V
3V
2V
Legend: CPIN =
VT =
I LEAKAGE =
RIC =
SS =
CHOLD =
Input Capacitance
Threshold Voltage
Leakage current at the pin due to various junctions
Interconnect Resistance
Sampling Switch
Sample/Hold Capacitance (from DAC)
© 2008 Microchip Technology Inc.
RSS
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
DS41249E-page 87
PIC16F785/HV785
12.3
A/D Operation During Sleep
The A/D Converter module can operate during Sleep.
This requires the A/D clock source to be set to the FRC
option. When the RC clock source is selected, the A/D
waits one instruction before starting the conversion.
This allows the SLEEP instruction to be executed, thus
eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/
DONE bit is cleared and the result is loaded into the
ADRESH:ADRESL registers. If the A/D interrupt is
enabled (ADIE and PEIE bits set), the device awakens
from Sleep. If the GIE bit of the INTCON Register is set,
the program counter is set to the interrupt vector
(0004h). If GIE is clear, the next instruction is executed.
If the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
FIGURE 12-5:
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted and the A/D module is turned off. The
ADON bit remains set.
A/D TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
A/D Output Code
3FDh
3FCh
1 LSb ideal
3FBh
Full-Scale
Transition
004h
003h
002h
001h
000h
Analog Input Voltage
1 LSb ideal
0V
DS41249E-page 88
Zero-Scale
Transition
VREF
© 2008 Microchip Technology Inc.
PIC16F785/HV785
12.4
Effects of Reset
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
A device Reset forces all registers to their Reset state.
Thus, the A/D module is turned off and any pending
conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
12.5
If the A/D module is not enabled (ADON is cleared), then
the “special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 counter. See
Section 8.0 “Capture/Compare/PWM (CCP) Module”
for more information.
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0 bits of the CCP1CON Register be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the
ADRESH:ADRESL to the desired location).
TABLE 12-3:
SUMMARY OF A/D REGISTERS
Name
Bit 7
Bit 6
ADCON0
ADFM
VCFG
ADCON1
—
ADCS2
Bit 5
Value on
POR, BOR
Value on all
other Resets
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
0000 0000
ADCS1
ADCS0
—
—
—
—
-000 ----
-000 ----
ADRESH
Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result
xxxx xxxx
uuuu uuuu
ADRESL
Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result
xxxx xxxx
uuuu uuuu
ANSEL0
ANS7
ANS6
ANS5
ANS4
ANS3
ANS2
ANS1
ANS0
1111 1111
1111 1111
ANSEL1
—
—
—
—
ANS11
ANS10
ANS9
ANS8
---- 1111
---- 1111
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
0000 0000
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
0000 0000
0000 0000
PORTA
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx
--uu uuuu
PORTB
RB7
RB6
RB5
RB4
—
—
—
—
xxxx ----
uuuu ----
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
--11 1111
--11 1111
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
1111 ----
1111 ----
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module.
© 2008 Microchip Technology Inc.
DS41249E-page 89
PIC16F785/HV785
NOTES:
DS41249E-page 90
© 2008 Microchip Technology Inc.
PIC16F785/HV785
13.0
TWO-PHASE PWM
EQUATION 13-2:
The two-phase PWM (Pulse Width Modulator) is a
stand-alone peripheral that supports:
• Single or dual-phase PWM
• Single complementary output PWM with overlap/
delay
• Sync input/output to cascade devices for
additional phases
Setting either, or both, of the PH1EN or PH2EN bits of
the PWMCON0 register will activate the PWM module
(see Register 13-1). If PH1 is used then TRISC<1>
must be cleared to configure the pin as an output. The
same is true for TRISC<4> when using PH2. Both
PH1EN and PH2EN must be set when using
Complementary mode.
13.1
PWM Period
The PWM period is derived from the main clock (FOSC),
the PWM prescaler and the period counter (see
Figure 13-1). The prescale bits of the PWMP Register,
(see Register 13-2) determine the value of the clock
divider which divides the system clock (FOSC) to the
pwm_clk. This pwm_clk is used to drive the PWM
counter. In Master mode, the PWM counter is reset
when the count reaches the period count of the PER
Register, (see Register 13-2), which determines the
frequency of the PWM. The relationship between the
PWM frequency, prescale and period count is shown in
Equation 13-1.
EQUATION 13-1:
PWM FREQ =
PWM FREQUENCY
FOSC
(2PWMP • (PER + 1)
The maximum PWM frequency is FOSC/2, since the
period count must be greater than zero.
In Slave mode, the period counter is reset by the SYNC
input, which is the master device period counter reset.
For proper operation, the slave period count should be
equal to or greater than that of the master.
13.2
PWM Phase
Each enabled phase output is driven active when the
phase counter matches the corresponding PWM phase
count in the PH Register (see Register 13-3 and
Register 13-4). The phase output remains true until terminated by a feedback signal from either of the comparators or the auto-shutdown activates.
PHASE RESOLUTION
PhaseDEG =
13.3
360
(PER + 1)
PWM Duty Cycle
Each PWM output is driven inactive, terminating the
drive period, by asynchronous feedback through the
internal comparators. The duty cycle resolution is in
effect infinitely adjustable. Either or both comparators
can be used to reset the PWM by setting the corresponding comparator enable bit (CxEN, see
Register 13-3). Duty cycles of 100% can be obtained
by suppressing the feedback which would otherwise
terminate the pulse.
The comparator outputs can be “held off”, or blanked,
by enabling the corresponding BLANK bit (BLANKx,
see Register 13-1) for each phase. The blank bit
disables the comparator outputs for 1/2 of a system
clock (FOSC), thus ensuring at least TOSC/2 active time
for the PWM output. Blanking avoids early termination
of the PWM output which may result due to switching
transients at the beginning of the cycle.
13.4
Master/Slave Operation
Multiple chips can operate together to achieve additional phases by operating one as the master and the
others as slaves. When the PWM is configured as a
master, the RB7/SYNC pin is an output and generates
a high output for one pwm_clk period at the end of each
PWM period (see Figure 13-4).
When the PWM is configured as a slave, the RB7/
SYNC pin is an input. The high input from a master in
this configuration resets the PWM period counter which
synchronizes the slave unit at the end of each PWM
period. Proper operation of a slave device requires a
common external FOSC clock source to drive the master and slave. The PWM prescale value of the slave
device must also be identical to that of the master. As
mentioned previously, the slave period count value
must be greater than or equal to that of the master.
The PWM Counter will be reset and held at zero when
both PH1EN and PH2EN of the PWMCON0 Register
are false. If the PWM is configured as a slave, the PWM
Counter will remain reset at zero until the first SYNC
input is received.
Phase granularity is a function of the period count
value. For example, if PER<4:0> = 3, each output can
be shifted in 90° steps (see Equation 13-2).
© 2008 Microchip Technology Inc.
DS41249E-page 91
PIC16F785/HV785
13.5
Active PWM Output Level
The PWMASE bit (see Register 13-2) is set by hardware when a shutdown event occurs. If automatic
restarts are not enabled (PRSEN = 0, see
Register 13-1), PWM operation will not resume until the
PWMASE bit is cleared by firmware after the shutdown
condition clears. The PWMASE bit can not be cleared
as long as the shutdown condition exists. If automatic
restarts are not enabled, the auto-shutdown mode can
be forced by writing a ‘1’ to the PWMASE bit.
The PWM output signal can be made active-high or
active-low by setting or resetting the corresponding
POL bit (see Register 13-3 and Register 13-4). When
POL is ‘1’ the active output state is VOL. When POL is
‘0’ the active output state is VOH.
13.6
Auto-Shutdown and Auto-Restart
If automatic restarts are enabled (PRSEN = 1), the
PWMASE bit is automatically cleared and PWM
operation resumes when the auto-shutdown event
clears (VIH on the RA2/AN2/T0CKI/INT/C1OUT pin).
When the PWM is enabled, the PWM outputs may be
configured for auto-shutdown by setting the PASEN bit
(see Register 13-1). VIL on the RA2/AN2/T0CKI/INT/
C1OUT pin will cause a shutdown event if auto-shutdown is enabled. An auto-shutdown event immediately
places the PWM outputs in the inactive state (see
Section 13.5 “Active PWM Output Level”) and the
PWM phase and period counters are reset and held to
zero.
FIGURE 13-1:
TWO-PHASE PWM SIMPLIFIED BLOCK DIAGRAM
PH1EN
PH2EN
PWMP<1:0>
PWMASE
MASTER
SHUTDOWN
PASEN
÷1,2,4,8
FOSC
Prescale
pwm_clk
S
Phase
Counter
0
Res
1
M
5
RB7/SYNC
PER<4:0>
pwm_count
5
PWMPH1<POL>
5
BLANK1
S
PWMPH1<4:0>
Q
SHUTDOWN
PH1EN
R
pha1
(1)
RC1/AN5/C12IN1-/PH1
PWMPH1<C1EN>
C1OUT
PWMPH1<C2EN>
C2OUT
PWMPH2<POL>
5
BLANK2
PWMPH2<4:0>
SHUTDOWN
PH2EN
S
Q
R
(1)
pha2
RC4/C2OUT/PH2
PWMPH2<C1EN>
PWMPH2<C2EN>
Note 1:
Reset dominant.
DS41249E-page 92
© 2008 Microchip Technology Inc.
PIC16F785/HV785
REGISTER 13-1:
PWMCON0: PWM CONTROL REGISTER 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PRSEN
PASEN
BLANK2
BLANK1
SYNC1
SYNC0
PH2EN
PH1EN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the PWMASE shutdown bit clears automatically once the shutdown condition goes away. The PWM restarts automatically.
0 = Upon auto-shutdown, the PWMASE must be cleared in firmware to restart the PWM.
bit 6
PASEN: PWM Auto-Shutdown Enable bit
0 = PWM auto-shutdown is disabled
1 = VIL on INT pin will cause auto-shutdown event
bit 5
BLANK2: PH2 Blanking bit(1)
1 = The PH2 pin is active for a minimum of 1/2 of an FOSC clock period after it is set
0 = The PH2 pin is reset as soon as the comparator trigger is active
bit 4
BLANK1: PH1 Blanking bit(1)
1 = The PH1 pin is active for a minimum of 1/2 of an FOSC clock period after it is set
0 = The PH1 pin is reset as soon as the comparator trigger is active
bit 3-2
SYNC<1:0>: SYNC Pin Function bits
0X = SYNC pin not used for PWM. PWM acts as its own master. RB7/SYNC pin is available for general purpose I/O.
10 = SYNC pin acts as system slave, receiving the PWM counter reset pulse
11 = SYNC pin acts as system master, driving the PWM counter reset pulse
bit 1
PH2EN: PH2 Pin Enabled bit
1 = The PH2 pin is driven by the PWM signal
0 = The PH2 pin is not used for PWM functions
bit 0
PH1EN: PH1 Pin Enabled bit
1 = The PH1 pin is driven by the PWM signal
0 = The PH1 pin is not used for PWM functions
Note 1: Blanking is disabled when operating in complementary mode. See COMOD<1:0> bits in the PWMCON1
register (Register 13-5) for more information.
© 2008 Microchip Technology Inc.
DS41249E-page 93
PIC16F785/HV785
REGISTER 13-2:
PWMCLK: PWM CLOCK CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWMASE
PWMP1
PWMP0
PER4
PER3
PER2
PER1
PER0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PWMASE: PWM Auto-Shutdown Event Status bit
0 = PWM outputs are operating
1 = A shutdown event has occured. PWM outputs are inactive.
bit 6-5
PWMP<1:0>: PWM Clock Prescaler bits
00 = pwm_clk = FOSC ÷ 1
01 = pwm_clk = FOSC ÷ 2
10 = pwm_clk = FOSC ÷ 4
11 = pwm_clk = FOSC ÷ 8
bit 4-0
PER<4:0>: PWM Period bits
00000 = Not used. (Period = 1/pwm_clk)
00001 = Period = 2/pwm_clk2
0•••• = • • •
01111 = Period = 16/pwm_clk
10000 = Period = 17/pwm_clk
1•••• = • • •
11110 = Period = 31/pwm_clk
11111 = Period = 32/pwm_clk
DS41249E-page 94
x = Bit is unknown
© 2008 Microchip Technology Inc.
PIC16F785/HV785
REGISTER 13-3:
PWMPH1: PWM PHASE 1 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POL
C2EN
C1EN
PH4
PH3
PH2
PH1
PH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
POL: PH1 Output Polarity bit
1 = PH1 Pin is active-low
0 = PH1 Pin is active-high
bit 6
C2EN: Comparator 2 Enable bit
When COMOD<1:0> = 00(1)
1 = PH1 is reset when C2OUT goes high
0 = PH1 ignores Comparator 2
When COMOD<1:0> = X1(1)
1 = Complementary drive terminates when C2OUT goes high
0 = Comparator 2 is ignored
When COMOD<1:0> = 10(1)
C2EN has no effect
bit 5
C1EN: Comparator 1 Enable bit
When COMOD<1:0> = 00(1)
1 = PH1 is reset when C1OUT goes high
0 = PH1 ignores Comparator 1
When COMOD<1:0> = X1(1)
1 = Complementary drive terminates when C1OUT goes high
0 = Comparator 1 is ignored
When COMOD<1:0> = 10(1)
C1EN has no effect
bit 4-0
PH<4:0>: PWM Phase bits
When COMOD<1:0> = 00(1)
00000 = PH1 starts 1 pwm_clk period after falling edge of SYNC pulse. All other PH1 delays are
expressed relative to this time.
00001 = PH1 is delayed by 1 pwm_clk pulse
••••• = • • •
11111 = PH1 is delayed by 31 pwm_clk pulses
When COMOD<1:0> = X1 or 1X(1)
00000 = Complementary drive starts 1 pwm_clk period after falling edge of SYNC pulse. All other
delays are expressed relative to this time.
00001 = Complementary drive start is delayed by 1 pwm_clk pulse
••••• = • • •
11111 = Complementary drive start is delayed by 31 pwm_clk pulses
Note 1: See PWMCON1 register (Register 13-5).
© 2008 Microchip Technology Inc.
DS41249E-page 95
PIC16F785/HV785
REGISTER 13-4:
PWMPH2: PWM PHASE 2 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POL
C2EN
C1EN
PH4
PH3
PH2
PH1
PH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
POL: PH2 Output Polarity bit
1 = PH2 Pin is active low
0 = PH2 Pin is active high
bit 6
C2EN: Comparator 2 Enable bit
When COMOD<1:0> = 00(1)
1 = PH2 is reset when C2OUT goes high
0 = PH2 ignores Comparator 2
When COMOD<1:0> = 1X or X1(1)
C2EN has no effect
bit 5
C1EN: Comparator 1 Enable bit
When COMOD<1:0> = 00(1)
1 = PH2 is reset when C1OUT goes high
0 = PH2 ignores Comparator 1
When COMOD<1:0> = 1X or X1(1)
C1EN has no effect
bit 4-0
PH<4:0>: PWM Phase bits
When COMOD<1:0> = 00(1)
00000 = PH2 starts 1 pwm_clk period after falling edge of SYNC pulse. All other PH2 delays are
expressed relative to this time.
00001 = PH2 is delayed by 1 pwm_clk pulse
••••• = • • •
11111 = PH2 is delayed by 31 pwm_clk pulses
When COMOD<1:0> = 1X(1)
00000 = Complementary drive terminates 1 pwm_clk period after falling edge of SYNC pulse.
All other PH2 delays are expressed relative to this time.
00001 = Complementary drive termination is delayed by 1 pwm_clk pulse
••••• = • • •
11111 = Complementary drive termination is delayed by 31 pwm_clk pulses
When COMOD<1:0> = 01(1)
PH<4:0> has no effect.
Note 1: See PWMCON1 register (Register 13-5).
DS41249E-page 96
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 13-2:
TWO-PHASE PWM AUTO-SHUTDOWN AND SYNC TIMING
FOSC
PWMP<1:0> = 0X01, PER<4:0> = 0X03
MASTER
pwm_clk
pwm_count
0
1
2
0
1
2
1
2
3
0
1
2
1
2
3
0
SYNC
Phase1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0
pha1
SHUTDOWN
SLAVE
pwm_clk
pwm_count
0
1
2
0
3
0
3
0
Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1
pha2
FIGURE 13-3:
TWO-PHASE PWM START-UP TIMING
FOSC
PWMP<1:0> = 0X01, PER<4:0> = 0X03
MASTER
pwm_clk
pwm_count
0
1
2
0
1
2
3
0
1
2
0
SYNC
PHnEN
SLAVE
pwm_clk
pwm_count
3
0
1
2
3
PHnEN
© 2008 Microchip Technology Inc.
DS41249E-page 97
PIC16F785/HV785
13.7
Example Single Phase Application
Figure 13-4 shows an example of a single phase buck
voltage regulator application. The PWM output drives
Q1 with pulses to alternately charge and discharge L1.
C4 holds the charge from L1 during the inactive cycle
of the drive period. R4 and C3 form a ramp generator.
At the beginning of the PWM period, the PWM output
goes high causing the voltage on C3 to rise concurrently with the current in L1. When the voltage across
C3 reaches the threshold level present at the positive
input of Comparator 1, the comparator output changes
and terminates the drive output from the PWM to Q1.
When Q1 is not driven, the current path to L1 through
Q1 is interrupted, but since the current in L1 cannot
stop instantly, the current continues to flow through D2
as L1 discharges into C4. D1 quickly discharges C3 in
preparation of the next ramp cycle.
FIGURE 13-4:
Resistor divider R5 and R6 scale the output voltage,
which is inverted and amplified by Op Amp 1, relative
to the reference voltage present at the non-inverting pin
of the op amp. R3, C5 and C2 form the inverting stabilization gain feedback of the amplifier. The VR reference supplies a stable reference to the non-inverting
input of the op amp, which is tweaked by the voltage
source created by a secondary time based PWM
output of the CCP and R1 and C1.
Output regulation occurs by the following principle: If
the regulator output voltage is too low, then the voltage
to the non-inverting input of Comparator 1 will rise,
resulting in a higher threshold voltage and, consequently, longer PWM drive pulses into Q1. If the output
voltage is too high, then the voltage to the non-inverting
input of Comparator 1 will fall, resulting in shorter PWM
drive pulses into Q1.
EXAMPLE SINGLE PHASE APPLICATION
CCP
PIC16F785
VR
R1
R2
C1
OPA1
VUNREG
FOSC
FET
Driver
R3
TWO-Phase
C2
C5
PH1
Q1
PWM
L1
C4
C1
D2
R4
D1
R5
C3
R6
DS41249E-page 98
© 2008 Microchip Technology Inc.
PIC16F785/HV785
13.8
PWM Configuration
When configuring the Two-Phase PWM, care must be
taken to avoid active output levels from the PH1 and
PH2 pins before the PWM is fully configured. The
following sequence is suggested before the TRISC
register or any of the Two-Phase PWM control registers
are first configured:
• Output inactive (OFF) levels to the PORTC RC1/
AN5/C12IN1-/PH1 and RC4/C2OUT/PH2 pins.
• Clear TRISC bits 1 and 4 to configure the PH1
and PH2 pins as outputs.
• Configure the PWMCLK, PWMPH1, PWMPH2,
and PWMCON1 registers.
• Configure the PWMCON0 register.
EXAMPLE 13-1:
PWM SETUP EXAMPLE
;Example to configure PH1 as a free running PWM output using the SYNC output as the duty cycle
;termination feedback.
;This requires an external connection between the SYNC output and the comparator input.
;SYNC out = RB7 on pin 10
;C1 inverting input = RC2/AN6 on pin 14
;Configure PH1, PH2 and SYNC pins as outputs
;First, ensure output latches are low
BCF
PORTC,1
;PH1 low
BCF
PORTC,4
;PH2 low
BCF
PORTB,7
;SYNC low
;Configure the I/Os as outputs
BANKSEL TRISB
BCF
TRISC,1
;PH1 output
BCF
TRISC,4
;PH2 output
BCF
TRISB,7
;SYNC output
;PH1 shares its function with AN5
;Configure AN5 as digital I/O
BCF
ANSEL0,5
;AN5 is digital, all others default as analog
;Configure the PWM but don't enable PH1 or PH2 yet
BANKSEL PWMCLK
;PWM control setup
MOVLW
B'00001100'
;auto shutdown off, no blanking, SYNC on, PH1 and PH2 off
MOVWF
PWMCON0
;see data sheet page 93
;PWM clock setup
MOVLW
B'00111101'
;pwm_clk = Fosc, 30 clocks in PWM period
MOVWF
PWMCLK
;see data sheet page 94
;PH1 setup
MOVLW
B'00101111'
;non-inverted, terminate on C1, Start on clock 15
MOVWF
PWMPH1
;see data sheet page 95
;PH2 setup
MOVLW
B'00110101'
;non-inverted, terminate on C1, Start on clock 21
MOVWF
PWMPH2
;see data sheet page 96
;Configure Comparator 1
MOVLW
B'10011110'
;C1 on, internal, inverted, normal speed, +:C1VREF, -:AN6
MOVWF
CM1CON0
;see data sheet page 68
;Configure comparator voltage reference
BANKSEL VRCON
MOVLW
B'10101100'
;C1VREN on, low range, CVREF= VDD/2
MOVWF
VRCON
;see data sheet page 72
;Everything is setup at this point so now it is time to enable PH1
BANKSEL PWMCON0
BSF
PWMCON0,PH1EN ;enable PH1
;Module is running autonomously at this point
© 2008 Microchip Technology Inc.
DS41249E-page 99
PIC16F785/HV785
13.9
Complementary Output Mode
The Two-Phase PWM module may be configured to
operate in a Complementary Output mode where PH1
and PH2 are always 180 degrees out-of-phase (see
Figure 13-5). Three complementary modes are
available and are selected by the COMOD<1:0> bits in
the PWMCON1 register (see Register 13-5). The difference between the modes is the method by which the
PH1 and PH2 outputs switch from the active to the
inactive state during the PWM period.
In Complementary mode, there are three methods by
which the duty cycle can be controlled. These modes
are selected with the COMOD<1:0> bits (see
Register 13-5). In each of these modes, the duty cycle
is started when the pwm_count = PWMPH1<4:0> and
terminates on one of the following:
• Feedback through C1 or C2
• When the pwm_count equals PWMPH1<4:0>
• Combined feedback and pwm_count match
When COMOD<1:0> = 01, the duty cycle is controlled
only by feedback through comparator C1 or C2. In this
mode, the active drive cycle starts when pwm_count
equals PWMPH1<4:0> and terminates when comparator C1’s output goes high (if enabled by
PWMPH1<5> = 1) or when comparator C2 output goes
high (if enabled by PWMPH1<6> = 1).
When COMOD<1:0> = 10, the duty cycle is controlled
only by the PWM Phase counter. In this mode, the
active drive cycle starts when the pwm_count equals
PWMPH1<4:0> and terminates when the pwm_count
equals PWMPH2<4:0>. For example, free running
50% duty cycle can be accomplished by setting
COMOD<1:0> = 10 and choosing appropriate values
for PWMPH1<4:0> and PWMPH2<4:0>.
13.9.2
OVERLAP CONTROL
Overlap timing can be accomplished by configuring the
Complementary mode for the desired output polarity
and overlap time (as dead time) then swapping the output connections and inverting the outputs. For example, to configure a complementary drive for 55 ns of
overlap and an active-high drive output on PH1 and an
active-low drive output on PH2, set the PWM control
registers as follows:
•
•
•
•
•
•
•
•
Connect PH1 driver to PH2 output
Connect PH2 driver to PH1 output
Initialize PORTC<1> to 1 (PH2 driver off)
Initialize PORTC<4> to 0 (PH1 driver off)
Set TRISC<1,4> to 0 for output
Set PWMPH1<POL> to 1 (Inverted PH1)
Set PWMPH2<POL> to 1 (Non-Inverted PH2)
Set PWMCON1 for 55 ns delay and desired
termination (comparator, count or both)
• Set PWMCON0 desired SYNC and auto-shutdown
configuration and to enable PH1 and PH2
13.9.3
SHUTDOWN IN COMPLEMENTARY
MODE
During shutdown the PH1 and PH2 complementary
outputs are forced to their inactive states (see
Figure 13-5). When shutdown ceases the PWM outputs revert to their start-up states for the first cycle
which is PH1 inactive (output undriven) and PH2 active
(output driven).
When COMOD<1:0> = 11, the duty cycle is controlled
by the phase counter or feedback through comparator
C1 or C2. For example, in this mode, the maximum
duty cycle is determined by the values of
PWMPH1<4:0> (duty cycle start) and PWMPH2<4:0>
(duty cycle end). The duty cycle can be terminated
earlier than the maximum by feedback through
comparator C1 or C2.
13.9.1
DEAD BAND CONTROL
The Complementary Output mode facilitates driving
series connected MOSFET drivers by providing dead
band drive timing between each phase output (see
Figure 13-6). Dead band times are selectable by the
CMDLY<4:0> bits of the PWMCON1 register. Delays
from 0 to 155 nanoseconds (typical) with a resolution of
5 nanoseconds (typical) are available.
DS41249E-page 100
© 2008 Microchip Technology Inc.
PIC16F785/HV785
REGISTER 13-5:
PWMCON1: PWM CONTROL REGISTER 1
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
COMOD1
COMOD0
CMDLY4
CMDLY3
CMDLY2
CMDLY1
CMDLY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-5
COMOD<1:0>: Complementary Mode Select bits(1)
00 = Normal two-phase operation. Complementary mode is disabled.
01 = Complementary operation. Duty cycle is terminated by C1OUT or C2OUT.
10 = Complementary operation. Duty cycle is terminated by PWMPH2<4:0> = pwm_count.
11 = Complementary operation. Duty cycle is terminated by PWMPH2<4:0> = pwm_count or C1OUT or C2OUT.
bit 4-0
CMDLY<4:0>: Complementary Drive Dead Time bits (typical)
00000 = Delay = 0
00001 = Delay = 5 ns
00010 = Delay = 10 ns
••••• = • • •
11111 = Delay = 155 ns
Note 1:
PWMCON0<1:0> must be set to ‘11’ for Complementary mode operation.
FIGURE 13-5:
COMPLEMENTARY OUTPUT PWM BLOCK DIAGRAM
PH1EN
pwm_reset
PH2EN
PS<1:0>
PWMASE
Shutdown
MASTER
PASEN
FOSC
S
pwm_clk
0
Phase Res
Counter
Prescale
1
M
5
RB7/SYNC
PER<4:0>
pwm_count
5
PWMPH1<POL>
5
Delay
PWMPH1<4:0>
S
Q
5
pha1
RC1/AN5/C12IN1-/PH1
R(1)
CMDLY<4:0>
5
5
PWMPH2<POL>
11
PWMPH2<4:0>
10
PWMPH1<C1EN>
C1OUT
delay
S
01
Q
pwm_reset
PWMPH1<C2EN>
C2OUT
Note
1:
pha2
RC4/C2OUT/PH2
COMOD<1:0>
Shutdown
R(1)
Reset dominant.
© 2008 Microchip Technology Inc.
DS41249E-page 101
PIC16F785/HV785
FIGURE 13-6:
COMPLEMENTARY OUTPUT PWM TIMING
FOSC
PWMP<1:0> = 0X01, PER<4:0> = 0X03
pwm_clk
3
pwm_count
0
2
1
3
0
1
0
2
1
3
0
1
SYNC
C1OUT
Phase 1 setup: PH<4:0> = 0x00, C1EN = 1, BLANKx = X, COMOD<1:0> = 0x01
pha1
pha2
Delay
Delay
Shutdown
TABLE 13-1:
REGISTERS/BITS ASSOCIATED WITH PWM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1SP
C1R
C1CH1
C1CH0
0000 0000
0000 0000
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0
0000 0000
0000 0000
PWMCLK
PWMASE
PWMP1
PWMP0
PER4
PER3
PER2
PER1
PER0
0000 0000
0000 0000
PWMCON0
PRSEN
PASEN
BLANK2
BLANK1
SYNC1
SYNC0
PH2EN
PH1EN
0000 0000
0000 0000
PWMCON1
—
COMOD1 COMOD0
CMDLY4
CMDLY3
CMDLY2
CMDLY1
CMDLY0
-000 0000
-000 0000
PWMPH1
POL
C2EN
C1EN
PH4
PH3
PH2
PH1
PH0
0000 0000
0000 0000
PWMPH2
POL
C2EN
C1EN
PH4
PH3
PH2
PH1
PH0
0000 0000
0000 0000
REFCON
—
—
BGST
VRBB
VREN
VROE
CVROE
—
--00 000-
--00 000-
C1VREN
C2VREN
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
VRCON
Legend:
x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by data PWM
module.
DS41249E-page 102
© 2008 Microchip Technology Inc.
PIC16F785/HV785
14.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are four SFRs used to read
and write this memory:
•
•
•
•
EECON1
EECON2 (not a physically implemented register)
EEDAT
EEADR
EEDAT holds the 8-bit data for read/write, and EEADR
holds the address of the EEPROM location being
accessed. The PIC16F785/HV785 has 256 bytes of
data EEPROM with an address range from 0h to FFh.
REGISTER 14-1:
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature, as well as
from chip-to-chip. Please refer to AC Specifications in
Section 19.0 “Electrical Specifications” for exact
limits.
When the data memory is code-protected, the CPU
may continue to read and write the data EEPROM
memory. The device programmer can no longer access
the data EEPROM data and will read zeroes.
EEDAT: EEPROM DATA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
EEDAT2
EEDAT1
EEDAT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
x = Bit is unknown
EEDATn: Byte Value to Write to or Read From Data EEPROM bits
REGISTER 14-2:
EEADR: EEPROM ADDRESS REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEADR7
EEADR6
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
x = Bit is unknown
EEADR: Specifies one of 256 locations for EEPROM Read/Write Operation bits
© 2008 Microchip Technology Inc.
DS41249E-page 103
PIC16F785/HV785
14.1
EECON1 and EECON2 Registers
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are nonimplemented and read as ‘0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
Interrupt flag EEIF bit of the PIR1 Register is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
Note:
The EECON1, EEDAT and EEADR
registers should not be modified during a
data EEPROM write (WR bit = 1).
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
can check the WRERR bit, clear it and rewrite the location. The EEDAT and EEADR registers are cleared by
a Reset. Therefore, the EEDAT and EEADR registers
will need to be re-initialized.
REGISTER 14-3:
EECON1: EEPROM CONTROL REGISTER
U-0
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
—
—
—
—
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
IUnimplemented: Read as ‘0’
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOR reset)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only
be set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set, not cleared, in software.)
0 = Does not initiate an EEPROM read
DS41249E-page 104
© 2008 Microchip Technology Inc.
PIC16F785/HV785
14.2
Reading the EEPROM Data
Memory
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD of the EECON1 Register, as shown in Example 141. The data is available, in the very next cycle, in the
EEDAT register. Therefore, it can be read in the next
instruction. EEDAT holds this value until another read,
or until it is written to by the user (during a write
operation).
EXAMPLE 14-1:
BSF
BCF
MOVLW
MOVWF
BSF
MOVF
14.3
DATA EEPROM READ
STATUS,RP0
STATUS,RP1
CONFIG_ADDR
EEADR
EECON1,RD
EEDAT,W
;Bank 1
;
;
;Address to read
;EE Read
;Move data to W
Writing to the EEPROM Data
Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 14-2.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in the hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit of the
PIR1 Register must be cleared by software.
14.4
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 14-3) to the
desired value to be written.
EXAMPLE 14-3:
Required
Sequence
BSF
BCF
BSF
BCF
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
DATA EEPROM WRITE
STATUS,RP0
STATUS,RP1
EECON1,WREN
INTCON,GIE
INTCON,GIE
$-2
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
;Bank 1
;
;Enable write
;Disable INTs
;See AN-576
;
;Unlock write
;
;
;
;Start the write
;Enable INTs
The write will not initiate if the sequence in Example 14-2
is not followed exactly (write 55h to EECON2, write AAh
to EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating the EEPROM. The WREN bit is not cleared by
hardware.
© 2008 Microchip Technology Inc.
WRITE VERIFY
BSF
BCF
MOVF
STATUS,RP0
STATUS,RP1
EEDAT,W
BSF
EECON1,RD
XORWF
BTFSS
GOTO
EEDAT,W
STATUS,Z
WRITE_ERR
14.4.1
EXAMPLE 14-2:
Write Verify
;Bank 1
;
;EEDAT not changed
from previous write
;YES, Read the
; value written
;
;Is data the same
;No, handle error
;Yes, continue
USING THE DATA EEPROM
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often). When
variables in one section change frequently, while variables in another section do not change, it is possible to
exceed the total number of write cycles to the
EEPROM (specification D124) without exceeding the
total number of write cycles to a single byte (specifications D120 and D120A). If this is the case, then a
refresh of the array must be performed. For this reason,
variables that change infrequently (such as constants,
IDs, calibration, etc.) should be stored in Flash program
memory.
14.5
Protect Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
Timer
(64 ms
duration)
prevents
EEPROM write.
The write initiate sequence and the WREN bit helps
prevent an accidental write during a brown-out, power
glitch and software malfunction.
DS41249E-page 105
PIC16F785/HV785
14.6
Data EEPROM Operation During
Code-Protect
Data memory can be code-protected by programming
the CPD bit in the Configuration Word (Register 15.2)
to ‘0’.
When the data memory is code-protected, the CPU is
able to read and write data to the data EEPROM. It is
recommended that the user code protect the program
memory when code protecting the data memory. This
prevents anyone from programming zeroes over the
existing code (which will execute as NOPs) to reach an
added routine, programmed in unused program memory, which outputs the contents of data memory.
Programming unused locations in program memory to
‘0’ will also help prevent data memory code protection
from becoming breached.
TABLE 14-1:
Name
EEADR
EECON1
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Bit 7
Bit 6
Bit 5
EEADR7 EEADR6 EEADR5
—
—
—
Bit 4
EEADR4
—
Value on all
other Resets
Bit 2
Bit 1
Bit 0
EEADR3
EEADR2
EEADR1
EEADR0
0000 0000
0000 0000
WRERR
WREN
WR
RD
---- x000
---- q000
EECON2
EEPROM Control register 2 (not a physical register)
EEDAT
EEDAT7 EEDAT6 EEDAT5
EEDAT4
Value on
POR, BOR
Bit 3
EEDAT3
EEDAT2
EEDAT1
---- ----
---- ----
EEDAT0
0000 0000
0000 0000
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
0000 0000
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
0000 0000
0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by
data EEPROM module.
DS41249E-page 106
© 2008 Microchip Technology Inc.
PIC16F785/HV785
15.0
SPECIAL FEATURES OF THE
CPU
The PIC16F785/HV785 has a host of features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power saving features and offer code protection.
These features are:
• Reset:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Oscillator selection
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming™ (ICSP™)
15.1
Configuration Bits
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 15.2.
These bits are mapped in program memory location
2007h.
Note:
Address 2007h is beyond the user program
memory space. It belongs to the special
configuration memory space (2000h3FFFh), which can be accessed only during
programming. See “PIC16F785/HV785
Memory Programming Specification”
(DS41237) for more information.
The PIC16F785/HV785 has two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay of 64 ms (nominal) on power-up only, designed to
keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a
brown-out occurs, which can use the Power-up Timer
to provide at least a 64 ms Reset. With these three
functions on-chip, most applications need no external
Reset circuitry.
The Sleep mode is designed to offer a very low-current
Power-down mode. The user can wake-up from Sleep
through an external Reset, Watchdog Timer Wake-up
or interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost, while the LP crystal option saves
power. A set of configuration bits are used to select
various options (see Register 15.2).
© 2008 Microchip Technology Inc.
DS41249E-page 107
PIC16F785/HV785
REGISTER 15-1:
CONFIG: CONFIGURATION WORD
U-0
U-0
U-0
U-0
R/P-0
R/P-0
R/P-1
R/P-1
—
—
—
—
FCMEN
IESO
BOREN1
BOREN0
bit 15
bit 8
R/P-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 13-12
FCMEN: Fail-Safe Clock Monitor Enabled bit(5)
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 10
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
bit 9-8
BOREN<1:0>: Brown-out Reset Selection bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit (PCON<4>)
00 = BOR disabled
bit 7
CPD: Data Code Protection bit(2), (3)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 6
CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5
MCLRE: RA3/MCLR pin function select bit(4)
1 = RA3/MCLR pin function is MCLR
0 = RA3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3
WDTE: Watchdog Timer Enable bit(5)
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN
110 = RCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on
RA5/T1CKI/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on
RA5/T1CKI/OSC1/CLKIN
011 = EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, CLKIN on RA5/T1CKI/OSC1/CLKIN
010 = HS oscillator: High-speed crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN(5)
001 = XT oscillator: Crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN(5)
000 = LP oscillator: Low-power crystal on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN(5)
Note
1:
2:
3:
4:
5:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
Program memory bulk erase must be performed to turn off code protection.
The entire data EEPROM will be erased when the code protection is turned off.
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
If the HS, XT, or LP oscillator fails In Fail-safe mode the Watchdog time-out can occur only once after which it will be disabled
until the oscillator is restored.
DS41249E-page 108
© 2008 Microchip Technology Inc.
PIC16F785/HV785
15.2
Reset
The PIC16F785/HV785 differentiates between various
kinds of Reset:
•
•
•
•
•
•
Power-on Reset (POR)
WDT Reset during normal operation
WDT Reset during Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
•
•
•
•
•
They are not affected by a WDT wake-up since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 15-2. These bits are
used in software to determine the nature of the Reset.
See Table 15-4 for a full description of Reset states of
all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 15-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 19.0 “Electrical
Specifications” for pulse width specifications.
Power-on Reset
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
FIGURE 15-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP pin
Sleep
WDT
Module
WDT
Time-out
Reset
Power-on Reset
VDD Rise
Detect
VDD
Brown-out(1)
Reset
BOREN
SBOREN
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1/
CLKI pin
PWRT
LFINTOSC
11-bit Ripple Counter
Enable PWRT
Enable OST
Note
1:
Refer to the Configuration Word register (Register 15.2).
© 2008 Microchip Technology Inc.
DS41249E-page 109
PIC16F785/HV785
15.2.1
POWER-ON RESET
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. A minimum rise rate for VDD is required. See
Section 19.0 “Electrical Specifications” for details. If
the BOR is enabled, the minimum rise rate specification does not apply. The BOR circuitry will keep the
device in Reset until VDD reaches VBOR (see
Section 15.2.4 “Brown-Out Reset (BOR)”)
The POR circuit, on this device, has a POR re-arm circuit. This circuit is designed to ensure a re-arm of the
POR circuit if VDD drops below a preset re-arming voltage (VPARM) for at least the minimum required time.
Once VDD is below the re-arming point for the minimum
required time, the POR Reset will reactivate and
remain in Reset until VDD returns to a value greater
than VPOR. At this point, a 1 μs (typical) delay will be initiated to allow VDD to continue to ramp to a voltage
safely above VPOR.
When the device starts normal operation (exits the
Reset condition), device operating parameters
(i.e., voltage, frequency, temperature, etc.) must be
met to ensure operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
15.2.2
MASTER CLEAR (MCLR)
PIC16F785/HV785 has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from earlier devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 15-1, is suggested.
FIGURE 15-2:
RECOMMENDED MCLR
CIRCUIT
VDD
PIC16F785/HV785
R1
1 kΩ (or greater)
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word. When cleared,
MCLR is internally tied to VDD and an internal Weak
Pull-up is enabled for the MCLR pin. The VPP function
of the RA3/MCLR/VPP pin is not affected by selecting
the internal MCLR option.
15.2.3
The Power-up Timer provides a fixed 64 ms (nominal)
time out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.4 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the VDD to rise to an acceptable level. A configuration bit, PWRTE can disable (if ‘1’) or enable (if ‘0’)
the Power-up Timer. The Power-up Timer should be
enabled when Brown-out Reset is enabled, although it
is not required.
The Power-up Time Delay will vary from chip-to-chip
and vary due to:
• VDD variation
• Temperature variation
• Process variation
See DC parameters for details
“Electrical Specifications”).
15.2.4
C1
0.1 μF
(optional, not critical)
DS41249E-page 110
(Section 19.0
BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word select one of four BOR modes. Two modes have
been added to allow software or hardware control of
the BOR enable. When BOREN<1:0> = 01, the SBOREN bit of the PCON Register enables/disables the
BOR allowing it to be controlled in software. By selecting BOREN<1:0>, the BOR is automatically disabled in
Sleep to conserve power, and enabled on wake-up. In
this mode, the SBOREN bit is disabled. See
Register 15.2 for the Configuration Word definition.
If VDD falls below VBOR for greater than parameter
(TBOR), see Section 19.0 “Electrical Specifications”, the Brown-out situation will reset the device.
This will occur regardless of the VDD slew rate. A Reset
is not assured if VDD falls below VBOR for less than
parameter (TBOR).
On any Reset (Power-on, Brown-out Reset, Watchdog,
etc.), the chip will remain in Reset until VDD rises above
VBOR (see Figure 15-3). The Power-up Timer will now
be invoked, if enabled, and will keep the chip in Reset
an additional 64 ms.
Note:
RA3/MCLR/VPP
POWER-UP TIMER (PWRT)
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
© 2008 Microchip Technology Inc.
PIC16F785/HV785
15.2.5
BOR CALIBRATION
The PIC16F785/HV785 stores the BOR calibration
values in fuses located in the Calibration Word (2008h).
The Calibration Word is not erased when using the
specified bulk erase sequence in the “PIC16F785/
HV785
Memory
Programming
Specification”
(DS41237) and thus, does not require reprogramming.
Note:
Address 2008h is beyond the user program
memory space. It belongs to the special
configuration memory space (2000h3FFFh), which can be accessed only during
programming. See “PIC16F785/HV785
Memory Programming Specification”
(DS41237) for more information.
FIGURE 15-3:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
64 ms(1)
VDD
Internal
Reset
VBOR
<64 ms
64 ms(1)
VDD
Internal
Reset
Note 1:
VBOR
64 ms(1)
64 ms delay only if PWRTE bit is programmed to ‘0’.
© 2008 Microchip Technology Inc.
DS41249E-page 111
PIC16F785/HV785
15.2.6
TIME-OUT SEQUENCE
15.2.7
On power-up, the time-out sequence is as follows: first,
PWRT time out is invoked after POR has expired, then
OST is activated after the PWRT time out has expired.
The total time out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode
with PWRTE bit equal to ‘1’ (PWRT disabled), there will
be no time out at all. Figure 15-4, Figure 15-6 and
Figure 15-6 depict time-out sequences. The device can
execute code from the INTOSC, while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 3.6.2 “Two-Speed Start-up Sequence” and
Section 3.7 “Fail-Safe Clock Monitor”).
The Power Control register (address 8Eh) has two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word).
Bit 1 is POR (Power-on Reset). It is ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 15-6). This is useful for testing purposes or
to synchronize more than one PIC16F785/HV785
device operating in parallel.
For more information, see Section 15.2.4 “Brown-Out
Reset (BOR)”.
Table 15-5 shows the Reset conditions for some
special registers, while Table 15-4 shows the Reset
conditions for all the registers.
TABLE 15-1:
POWER CONTROL (PCON)
REGISTER
TIME OUT IN VARIOUS SITUATIONS
Power-up
Brown-out Reset
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up from
Sleep
XT, HS, LP
TPWRT +
1024•TOSC
1024•TOSC
TPWRT +
1024•TOSC
1024•TOSC
1024•TOSC
RC, EC, INTOSC
TPWRT
—
TPWRT
—
—
Oscillator Configuration
TABLE 15-2:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
Condition
0
x
1
1
Power-on Reset
u
0
1
1
Brown-out Reset
u
u
0
u
WDT Reset
u
u
0
0
WDT Wake-up
u
u
u
u
MCLR Reset during normal operation
u
u
1
0
MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
TABLE 15-3:
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
PCON
—
—
—
SBOREN
—
—
POR
BOR
---1 --qq
---1 --qq
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
0001 1xxx
STATUS
Legend:
Note 1:
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
DS41249E-page 112
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 15-4:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
FIGURE 15-5:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 15-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
© 2008 Microchip Technology Inc.
DS41249E-page 113
PIC16F785/HV785
TABLE 15-4:
INITIALIZATION CONDITION FOR REGISTERS
Register
W
INDF
TMR0
Address
Power-on Reset
MCLR Reset
WDT Reset
Brown-out Reset(1)
Wake-up from Sleep through interrupt
Wake-up from Sleep through WDT Time-out
—
xxxx xxxx
uuuu uuuu
uuuu uuuu
00h/80h
xxxx xxxx
xxxx xxxx
uuuu uuuu
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
(6)
(7)
--uu uuuu
PORTA
05h
--x0 x000
--u0 u000
PORTB
06h
xx00 ----(6)
uu00 ----(7)
uuuu ----
PORTC
07h
0000(6)
uuuu(7)
uuuu uuuu
PCLATH
0Ah/8Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh
0000 0000
0000 0000
uuuu uuuu(2)
PIR1
0Ch
0000 0000
0000 0000
uuuu uuuu(2)
TMR1L
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
10h
0000 0000
uuuu uuuu
uuuu uuuu
TMR2
11h
0000 0000
0000 0000
uuuu uuuu
T2CON
12h
-000 0000
-000 0000
-uuu uuuu
CCPR1L
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
15h
--00 0000
--00 0000
--uu uuuu
WDTCON
18h
---0 1000
---0 1000
---u uuuu
ADRESH
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
1Fh
0000 0000
0000 0000
uuuu uuuu
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
TRISA
85h
--11 1111
--11 1111
--uu uuuu
TRISB
86h
1111 ----
1111 ----
uuuu ----
TRISC
87h
1111 1111
1111 1111
uuuu uuuu
PIE1
8Ch
0000 0000
0000 0000
uuuu uuuu
00xx
00uu
(1,5)
PCON
8Eh
---1 --0x
OSCCON
8Fh
-110 q000
-110 q000
-uuu uuuu
OSCTUNE
90h
---0 0000
---u uuuu
---u uuuu
ANSEL0
91h
1111 1111
1111 1111
uuuu uuuu
PR2
92h
1111 1111
1111 1111
1111 1111
ANSEL1
93h
---- 1111
---- 1111
---- uuuu
WPUA
95h
--11 1111
--11 1111
--uu uuuu
IOCA
96h
--00 0000
--00 0000
--uu uuuu
98h
--00 000-
--00 000-
--uu uuu-
REFCON
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
---u --uq
---u --uu
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 15-5 for Reset value for specific condition.
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
Analog channels read 0 but data latches are unknown.
Analog channels read 0 but data latches are unchanged.
DS41249E-page 114
© 2008 Microchip Technology Inc.
PIC16F785/HV785
TABLE 15-4:
Register
VRCON
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Address
Power-on Reset
MCLR Reset
WDT Reset
Brown-out Reset(1)
Wake-up from Sleep through interrupt
Wake-up from Sleep through WDT Time-out
99h
000- 0000
000- 0000
uuu- uuuu
EEDAT
9Ah
0000 0000
0000 0000
uuuu uuuu
EEADR
9Bh
0000 0000
0000 0000
uuuu uuuu
EECON1
9Ch
---- x000
---- q000
---- uuuu
EECON2
9Dh
---- ----
---- ----
---- ----
ADRESL
9Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON1
9Fh
-000 ----
-000 ----
-uuu ----
PWMCON1
110h
-000 0000
-000 0000
-uuu uuuu
PWMCON0
111h
0000 0000
0000 0000
uuuu uuuu
PWMCLK
112h
0000 0000
0000 0000
uuuu uuuu
PWMPH1
113h
0000 0000
0000 0000
uuuu uuuu
PWMPH2
114h
0000 0000
0000 0000
uuuu uuuu
CM1CON0
119h
0000 0000
0000 0000
uuuu uuuu
CM2CON0
11Ah
0000 0000
0000 0000
uuuu uuuu
CM2CON1
11Bh
00-- --10
00-- --10
uu-- --uu
OPA1CON
11Ch
0--- ----
0--- ----
u--- ----
OPA2CON
11Dh
0--- ----
0--- ----
u--- ----
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 15-5 for Reset value for specific condition.
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
Analog channels read 0 but data latches are unknown.
Analog channels read 0 but data latches are unchanged.
© 2008 Microchip Technology Inc.
DS41249E-page 115
PIC16F785/HV785
TABLE 15-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---1 --0x
MCLR Reset during normal operation
000h
000u uuuu
---u --uu
MCLR Reset during Sleep
000h
0001 0uuu
---u --uu
Condition
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt Wake-up from Sleep
000h
0000 uuuu
---u --uu
PC + 1
uuu0 0uuu
---u --uu
000h
0001 1uuu
---1 --u0
PC + 1(1)
uuu1 0uuu
---u --uu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the
interrupt vector (0004h) after execution of PC + 1.
DS41249E-page 116
© 2008 Microchip Technology Inc.
PIC16F785/HV785
15.3
Interrupts
The PIC16F785/HV785 has 11 sources of interrupt:
•
•
•
•
•
•
•
•
•
•
External Interrupt RA2/INT
TMR0 Overflow Interrupt
PORTA Change Interrupt
2 Comparator Interrupts
A/D Interrupt
Timer1 Overflow Interrupt
Timer2 Match Interrupt
EEPROM Data Write Interrupt
Fail-Safe Clock Monitor Interrupt
CCP Interrupt
The Interrupt Control register (INTCON) and Peripheral
Interrupt register (PIR1) record individual interrupt
requests in flag bits. The INTCON register also has
individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE of the INTCON Register enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can
be disabled through their corresponding enable bits in
INTCON register and PIE1 register. GIE is cleared on
Reset.
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 15-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
For additional information on Timer1, Timer2,
comparators, A/D, Data EEPROM or CCP modules,
refer to the respective peripheral section.
The Return from Interrupt instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the INTCON register:
• INT Pin Interrupt
• PORTA Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register PIR1. The corresponding interrupt
enable bit is contained in special register PIE1.
The following interrupt flags are contained in the PIR1
register:
•
•
•
•
•
•
•
EEPROM Data Write Interrupt
A/D Interrupt
2 Comparator Interrupts
Timer1 Overflow Interrupt
Timer2 Match Interrupt
Fail-Safe Clock Monitor Interrupt
CCP Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt
• The return address is PUSHed onto the stack
• The PC is loaded with 0004h
© 2008 Microchip Technology Inc.
DS41249E-page 117
PIC16F785/HV785
15.3.1
RA2/AN2/T0CKI/INT/C1OUT
INTERRUPT
15.3.2
External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin
is edge-triggered; either rising, if INTEDG bit of the
OPTION Register is set, or falling, if INTEDG bit is
clear. When a valid edge appears on the RA2/AN2/
T0CKI/INT/C1OUT pin, the INTF bit of the INTCON
Register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON Register. The
INTF bit must be cleared in software in the Interrupt
Service Routine before re-enabling this interrupt. The
RA2/AN2/T0CKI/INT/C1OUT interrupt can wake-up
the processor from Sleep if the INTE bit was set prior to
going into Sleep. The status of the GIE bit decides
whether or not the processor branches to the interrupt
vector following wake-up (0004h). See Section 15.6
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 15-10 for timing of wake-up from Sleep through
RA2/AN2/T0CKI/INT/C1OUT interrupt.
Note:
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF bit of the INTCON Register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON Register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
15.3.3
PORTA INTERRUPT
An input change on PORTA change sets the RAIF of
the INTCON Register bit. The interrupt can be enabled/
disabled by setting/clearing the RAIE bit of the INTCON
Register. Plus, individual pins can be configured
through the IOCA register.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF interrupt flag may not get set.
The ANSEL0 (91h), and ANSEL1 (93h)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
FIGURE 15-7:
INTERRUPT LOGIC
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
IOC-RA4
IOCA4
IOC-RA5
IOCA5
T0IF
T0IE
TMR2IF
TMR2IE
INTF
INTE
RAIF
RAIE
TMR1IF
TMR1IE
C1IF
C1IE
Wake-up (If in Sleep mode)(1)
Interrupt to CPU
PEIE
GIE
C2IF
C2IE
ADIF
ADIE
EEIF
EEIE
OSFIF
OSFIE
CCP1IF
CCP1IE
DS41249E-page 118
Note 1:
Some peripherals depend upon the system clock for
operation. Since the system clock is suspended during Sleep, only
those peripherals which do not depend upon the system clock will wake
the part from Sleep. See Section 15.6.1 “Wake-up from Sleep”.
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 15-8:
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
(4)
INT pin
(1)
(1)
INTF Flag
(INTCON<1>)
Interrupt Latency (2)
(5)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Inst (PC)
Instruction
Executed
Inst (PC - 1)
Note 1:
2:
3:
4:
5:
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
—
Inst (PC + 1)
Dummy Cycle
Inst (PC)
0005h
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
CLKOUT is available only in INTOSC and RC Oscillator modes.
For minimum width of INT pulse, refer to AC specifications in Section 19.0 “Electrical Specifications”.
INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 15-6:
Name
0004h
PC + 1
PC + 1
PC
Instruction
Fetched
SUMMARY OF INTERRUPT REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
INTCON
GIE
PEIE
T0IE
INTE
RAIE
T0IF
INTF
RAIF
0000 0000
0000 0000
PIE1
EEIE
ADIE
CCP1IE
C2IE
C1IE
OSFIE
TMR2IE
TMR1IE
0000 0000
0000 0000
EEIF
ADIF
CCP1IF
C2IF
C1IF
OSFIF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIR1
Legend:
x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not
used by the Interrupt module.
© 2008 Microchip Technology Inc.
DS41249E-page 119
PIC16F785/HV785
15.4
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Since the last 16 bytes of all banks are common in the
PIC16F785/HV785 (see Figure 2-2), temporary holding registers W_TEMP and STATUS_TEMP should be
placed in here. These 16 locations do not require
banking, therefore, making it easier to save and restore
context. The same code shown in Example 15-1 can
be used to:
•
•
•
•
•
Store the W register
Store the STATUS register
Execute the ISR code
Restore the Status (and Bank Select Bit register)
Restore the W register
Note:
The PIC16F785/HV785 normally does not
require saving the PCLATH. However, if
computed GOTO’s are used in the ISR and
the main code, the PCLATH must be
saved and restored in the ISR.
EXAMPLE 15-1:
SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
:
:(ISR)
:
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Copy
;Swap
;bank
;Save
W to TEMP register
status to be saved into W (swap does not affect status)
0, regardless of current bank, Clears IRP,RP1,RP0
status to bank zero STATUS_TEMP register
;Insert user code here
STATUS_TEMP,W
DS41249E-page 120
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into Status register
;Swap W_TEMP
;Swap W_TEMP into W
© 2008 Microchip Technology Inc.
PIC16F785/HV785
15.5
15.5.2
Watchdog Timer (WDT)
For PIC16F785/HV785, the WDT has been modified
from previous PIC16FXXX devices. The new WDT is
code and functionally compatible with previous
PIC16FXXX WDT modules and adds a 16-bit prescaler
to the WDT. This allows the user to scale the value for
the WDT and TMR0 at the same time. In addition, the
WDT time out value can be extended to 268 seconds.
WDT is cleared under certain conditions described in
Table 15-7.
15.5.1
WDT OSCILLATOR
WDT CONTROL
The WDTE bit is located in the Configuration Word.
When set, the WDT runs continuously.
When the WDTE bit in the Configuration Word register
is set, the SWDTEN bit of the WDTCON Register has
no effect. If WDTE is clear, then the SWDTEN bit can
be used to enable and disable the WDT. Setting the bit
will enable it and clearing the bit will disable it.
The PSA and PS<2:0> bits of the OPTION Register
have the same function as in previous versions of the
PIC16FXXX
family
of
microcontrollers.
See
Section 5.0 “Timer0 Module” for more information.
The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC
is enabled (OSCON<1>).
The value of WDTCON is ‘---0 1000’ on all Resets.
This gives a nominal time base of 16 ms, which is
compatible with the time base generated with previous
PIC16FXXX microcontroller versions.
Note:
When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
A new prescaler has been added to the path between
the INTRC and the multiplexers used to select the path
for the WDT. This prescaler is 16 bits and can be
programmed to divide the INTRC by 128 to 65536,
giving the time base used for the WDT a nominal range
of 1 ms to 268s.
FIGURE 15-9:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
31 kHz
LFINTOSC Clock
0
16-bit WDT Prescaler
1
WDTPS<3:0>
PSA
8-bit
Prescaler(1)
8
PS<2:0>
TO TMR0
WDTE from Configuration Word
SWDTEN from WDTCON
0
1
PSA
WDT Time-out
Note
1:
This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.
TABLE 15-7:
WDT STATUS
Conditions
WDT
WDTE = 0
CLRWDT command
OSC FAIL detected
Cleared
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
© 2008 Microchip Technology Inc.
Cleared until the end of OST
DS41249E-page 121
PIC16F785/HV785
REGISTER 15-2:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
U-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
—
—
—
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-1
WDTPS<3:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
0000 = 1:32
0001 = 1:64
0010 = 1:128
0011 = 1:256
0100 = 1:512 (Reset value)
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16384
1010 = 1:32768
1011 = 1:65536
1100 = reserved
1101 = reserved
1110 = reserved
1111 = reserved
bit 0
SWDTEN: Software Enable or Disable the Watchdog Timer bit(1)
1 = WDT is turned on
0 = WDT is turned off (Reset value)
x = Bit is unknown
Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE configuration bit = 0, then it is possible to turn WDT on/off with this control bit.
TABLE 15-8:
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
OPTION_REG
RAPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
IRP
RP1
RPO
TO
PD
Z
DC
C
0001 1xxx
000q quuu
—
—
—
WDTPS3
WDTPS2
WSTPS1
WDTPS0
SWDTEN
---0 1000
---0 1000
STATUS
WDTCON
Legend:
Note 1:
Shaded cells are not used by the Watchdog Timer.
See Register 15.2 for operation of all Configuration Word bits.
DS41249E-page 122
© 2008 Microchip Technology Inc.
PIC16F785/HV785
15.6
Power-Down Mode (Sleep)
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
•
•
•
•
•
WDT will be cleared but keeps running
PD bit in the STATUS register is cleared
TO bit is set
Oscillator driver is turned off
I/O ports maintain the status they had before
SLEEP was executed (driving high, low or highimpedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD or VSS, with no external
circuitry drawing current from the I/O pin and all unused
peripheral modules should be disabled. Digital I/O pins
that are high-impedance inputs should be pulled high,
or low, externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at VDD
or VSS for lowest current consumption. The
contribution from on-chip pull-ups on PORTA should be
considered.
The MCLR pin must be at a logic high level.
Note:
15.6.1
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding interrupt flag bits set (including PEIE,
where applicable), the device will immediately wake-up from Sleep. The SLEEP
instruction is completely executed.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
15.6.2
WAKE-UP USING INTERRUPTS
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
When global interrupts are disabled (i.e., GIE bit of the
INTCON register is clear) and any interrupt source has
both its interrupt enable bit and interrupt flag bit set, one
of the following will occur:
WAKE-UP FROM SLEEP
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set, and the PD bit will be cleared.
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit (and PEIE bit where applicable)
must be set (enabled). Wake-up is regardless of the
state of the GIE bit. If the GIE bit is clear (disabled), the
device continues execution of the instruction after the
SLEEP instruction. If the GIE bit is set (enabled), the
device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In
cases where the execution of the instruction, following
SLEEP, is not desired, the user should place a NOP
after the SLEEP instruction.
External Reset input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RA2/AN2/T0CKI/INT/C1OUT pin,
PORTA change or a peripheral interrupt.
The first event will cause a device Reset. The two latter
events are considered a continuation of program execution. The TO and PD bits in the STATUS register can
be used to determine the cause of device Reset. The
PD bit, which is set on power-up, is cleared when Sleep
is invoked. TO bit is cleared if WDT Wake-up occurred.
The following peripheral interrupts can wake the device
from Sleep:
• TMR1 interrupt; Timer1 must be operating as an
asynchronous counter.
• CCP Capture mode interrupt
• A/D conversion (when A/D clock source is RC)
• EEPROM write operation completion
• Comparator output changes state
• Interrupt-on-change
• External Interrupt from INT pin
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
When global interrupts are disabled, a CLRWDT
instruction should be executed before a SLEEP
instruction to ensure that the WDT is cleared.
Other peripherals cannot generate interrupts since,
during Sleep, no on-chip clocks are present.
© 2008 Microchip Technology Inc.
DS41249E-page 123
PIC16F785/HV785
FIGURE 15-10:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency (3)
GIE bit
(INTCON<7>)
Processor
in Sleep
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
15.7
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
15.8
Code Protection
If the code protection is turned off, the
entire data EEPROM and Flash program
memory will be erased by performing a
bulk
erase
command.
See
the
“PIC16F785/HV785 Memory Programming Specification” (DS41237) for more
information.
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during Program/Verify. Only the
Least Significant 7 bits of the ID locations are used.
15.9
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP Oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale). This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up
(see Section 3.6 “Two-Speed Clock Start-up Mode”).
GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h.
If GIE = 0, execution will continue in-line.
CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.
Note:
PC + 2
In-Circuit Serial Programming™
(ICSP™)
This allows customers to manufacture boards with
unprogrammed devices and then program the microcontroller just before shipping the product. This also
allows the most recent firmware, or a custom firmware,
to be programmed.
The device is placed into a Program/Verify mode by
holding the RA0 and RA1 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH. See the “PIC16F785/
HV785
Memory
Programming
Specification”
(DS41237) for more information. RA0 becomes the
programming data and RA1 becomes the programming
clock. Both RA0 and RA1 are Schmitt Trigger inputs in
this mode.
After Reset, to place the device into Program/Verify
mode, the Program Counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending on
whether the command was a load or a read. For
complete details of serial programming, please refer to
the “PIC16F785/HV785 Memory Programming Specification” (DS41237).
A typical In-Circuit Serial Programming connection is
shown in Figure 15-11.
The PIC16F785/HV785 microcontrollers can be serially programmed while in the end application circuit.
This is simply done with five lines:
•
•
•
•
•
Clock
Data
Power
Ground
Programming voltage
DS41249E-page 124
© 2008 Microchip Technology Inc.
PIC16F785/HV785
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
*
FIGURE 15-12:
PIC16F785
+5.0V
VDD
0V
VSS
VPP
MCLR/VPP/RA3
CLK
RA1
Data I/O
RA0
*
*
For more information, see “MPLAB® ICD 2 In-Circuit
Debugger User’s Guide” (DS51331), available on
Microchip’s web site (www.microchip.com).
*
To Normal
Connections
28-PIN ICD PINOUT
28-Pin PDIP
In-Circuit Debug Device
SHNTREG
ICDMCLR/VPP
VDD
RA5
RA4
RA3
RC5
RC4
RC3
RC6
RC7
RB7
ICD
NC
1
28
2
3
27
26
4
5
6
7
8
9
10
11
12
13
14
PIC16F785/HV785-ICD
FIGURE 15-11:
25
24
23
22
21
20
19
18
17
16
15
ICDCLK
ICDDATA
Vss
RA0
RA1
RA2
RC0
RC1
RC2
RB4
RB5
RB6
NC
NC
* Isolation devices (as required)
15.10 In-Circuit Debugger
• In-circuit debugging requires clock, data and
MCLR pins. A special 28-pin PIC16F785-ICD
device is used with MPLAB® ICD 2 to provide
separate clock, data and MCLR pins so that no
pins are lost for these functions, leaving all 18 of
the PIC16F785/HV785 I/O pins available to the
user during debug operation.
• This special ICD device is mounted on the top of a
header and its signals are routed to the MPLAB
ICD 2 connector. On the bottom of the header is a
20-pin socket that plugs into the user’s target via
the 20-pin stand-off connector.
• When the ICD pin on the PIC16F785-ICD device
is held low, the In-Circuit Debugger functionality is
enabled. This function allows simple debugging
functions when used with MPLAB ICD 2. When
the microcontroller has this feature enabled, some
of the resources are not available for general use.
Table 15-9 shows which features are consumed
by the background debugger.
TABLE 15-9:
DEBUGGER RESOURCES
Resource
Description
I/O pins
ICDCLK, ICDDATA
Stack
1 level
Data RAM
65h-70h, F0h
Program Memory
Address 0h must be NOP
700h-7FFh
© 2008 Microchip Technology Inc.
DS41249E-page 125
PIC16F785/HV785
16.0
VOLTAGE REGULATOR
The PIC16HV785 includes a permanent internal 5 volt
(nominal) shunt regulator in parallel with the VDD pin.
This eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. All
external devices connected directly to the VDD pin will
share the regulated supply voltage and contribute to
the total VDD supply current (ILOAD).
16.1
An external current limiting resistor, RSER, located
between the unregulated supply, VUNREG, and the VDD
pin, drops the difference in voltage between VUNREG
and VDD. RSER must be between RMAX and RMIN as
defined by Equation 16-1.
EQUATION 16-1:
Regulator Operation
The regulator operates by maintaining a constant
voltage at the VDD pin by adjusting the regulator shunt
current in response to variations of the VDD supply load
and the unregulated supply voltage. The regulator
behaves like a fully compensated Zener diode. (See
Figure 16-1).
FIGURE 16-1:
REGULATOR
RSER LIMITING RESISTOR
RMAX =
(VUMIN - VDD) • 1000
1.05 • (4 MA + ILOAD)
RMIN =
(VUMIN - VDD) • 1000
0.95 • (50 MA)
Where:
RMAX = maximum value of RSER (ohms)
RMIN
= minimum value of RSER (ohms)
VUMIN = minimum value of VUNREG
VUMAX = maximum value of VUNREG
VUNREG
VDD
RSER
VDD
To other circuitry
PIC16HV785
Voltage
Regulator
= regulated voltage (5V nominal)
ILOAD = maximum expected load current in mA
including I/O pin currents and external
circuits connected to VDD.
1.05
= compensation for +5% tolerance of RSER
0.95
= compensation for -5% tolerance of RSER
16.2
Regulator Precautions
The total VDD load current variation must be less than
46 mA so that it falls within the voltage regulator shunt
current dynamic range. If the load current rises above
the expected maximum, the regulator will be starved for
current and go out of regulation causing VDD to drop.
Since the regulator uses the band gap voltage as the
regulated voltage reference, the VR voltage reference
is permanently enabled in the PIC16HV785 device.
(used on blank pages to make page count even)
DS41249E-page 126
© 2008 Microchip Technology Inc.
PIC16F785/HV785
17.0
INSTRUCTION SET SUMMARY
The PIC16F785/HV785 instruction set is highly orthogonal and is comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The format for each of the categories is
presented in Figure 17-1, while the various opcode
fields are summarized in Table 17-1.
Table 17-2 lists the instructions recognized by the
MPASMTM assembler.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 μs. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
Note:
To maintain upward compatibility with
future products, do not use the OPTION
and TRIS instructions.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies
a hexadecimal digit.
For example, a CLRF PORTA instruction will read
PORTA, clear all the data bits, then write the result back
to PORTA. This example would have the unintended
result of clearing the condition that set the RAIF flag.
TABLE 17-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
Program Counter
TO
Time-out bit
PD
Power-down bit
FIGURE 17-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
OPCODE
7
6
0
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
OPCODE
7 6
b (BIT #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
17.1
Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation
is always performed, even if the instruction is a Write
command.
© 2008 Microchip Technology Inc.
0
f (FILE #)
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
DS41249E-page 127
PIC16F785/HV785
TABLE 17-2:
PIC16F785/HV785 INSTRUCTION SET
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Note 1:
2:
3:
k
k
k
–
k
k
k
–
k
–
–
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS41249E-page 128
© 2008 Microchip Technology Inc.
PIC16F785/HV785
17.2
Instruction Descriptions
ADDLW
Add Literal and W
ANDWF
AND W with f
Syntax:
[label] ADDLW
Syntax:
[label] ANDWF
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
(W) + k → (W)
0 ≤ f ≤ 127
d ∈ [0,1]
Status Affected:
C, DC, Z
Operation:
(W) .AND. (f) → (destination)
Description:
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
Status Affected:
Z
Description:
AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
BCF
Bit Clear f
k
ADDWF
Add W and f
Syntax:
[label] ADDWF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) + (f) → (destination)
Status Affected:
C, DC, Z
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW
AND Literal with W
Syntax:
[label] ANDLW
Operands:
0 ≤ k ≤ 255
Operation:
(W) .AND. (k) → (W)
f,d
k
f,d
Syntax:
[label] BCF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
0 → (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
Syntax:
[label] BSF
Operands:
0 ≤ f ≤ 127
0≤b≤7
f,b
f,b
Status Affected:
Z
Operation:
1 → (f<b>)
Description:
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
© 2008 Microchip Technology Inc.
DS41249E-page 129
PIC16F785/HV785
BTFSC
Bit Test f, Skip if Clear
CLRF
Clear f
Syntax:
[label] BTFSC f,b
Syntax:
[label] CLRF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operands:
0 ≤ f ≤ 127
Operation:
skip if (f<b>) = 0
Operation:
00h → (f)
1→Z
Status Affected:
None
Status Affected:
Z
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a two-cycle instruction.
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
BTFSS
Bit Test f, Skip if Set
CLRW
Clear W
Syntax:
[label] BTFSS f,b
Syntax:
[ label ] CLRW
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
None
Operation:
Operation:
skip if (f<b>) = 1
00h → (W)
1→Z
Status Affected:
None
Status Affected:
Z
Description:
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
Description:
W register is cleared. Zero bit (Z)
is set.
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ k ≤ 2047
Operands:
None
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Operation:
Status Affected:
None
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit immediate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL
is a two-cycle instruction.
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
DS41249E-page 130
f
© 2008 Microchip Technology Inc.
PIC16F785/HV785
GOTO
Unconditional Branch
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 2047
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Z
Status Affected:
None
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
Description:
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a twocycle instruction.
DECF
Decrement f
INCF
Increment f
Syntax:
[label] DECF f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Z
Status Affected:
Z
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next instruction is executed. If the result is ‘0’,
a NOP is executed instead, making
it a two-cycle instruction.
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (destination)
Status Affected:
Description:
f,d
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next instruction is executed. If the result is ‘0’,
then a NOP is executed instead,
making it a two-cycle instruction.
© 2008 Microchip Technology Inc.
GOTO k
INCF f,d
INCFSZ f,d
DS41249E-page 131
PIC16F785/HV785
IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
(W) .OR. k → (W)
Operation:
k → (W)
Status Affected:
Z
Status Affected:
None
Description:
The contents of the W register
are OR’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Encoding:
IORLW k
11
MOVLW k
00xx
kkkk
kkkk
Description:
The eight-bit literal ‘k’ is loaded
into W register. The “don’t cares”
will assemble as 0’s.
Move W to f
IORWF
Inclusive OR W with f
MOVWF
Syntax:
[ label ]
Syntax:
[ label ]
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
Operation:
(W) → (f)
Operation:
(W) .OR. (f) → (destination)
Status Affected:
None
Status Affected:
Z
Encoding:
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Description:
Move data from W register to
register ‘f’.
MOVF
Move f
NOP
No Operation
Operands:
IORWF
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (dest)
Status Affected:
Z
Encoding:
Description:
DS41249E-page 132
f,d
MOVF f,d
1000
dfff
ffff
0000
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
Encoding:
00
00
MOVWF
Description:
00
f
1fff
ffff
NOP
0000
0xx0
0000
No operation.
The contents of register ‘f’ is
moved to a destination dependent upon the status of ‘d’. If ‘d’ =
0, destination is W register. If ‘d’
= 1, the destination is file register
‘f’ itself. ‘d’ = 1 is useful to test a
file register since status flag Z is
affected.
© 2008 Microchip Technology Inc.
PIC16F785/HV785
RETFIE
Return from Interrupt
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
Operation:
TOS → PC,
1 → GIE
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
None
Status Affected:
C
Status Affected:
Encoding:
Description:
RETLW
00
RETFIE
0000
0000
1001
Return from Interrupt. Stack is
POPed and Top-of-Stack (TOS)
is loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE of the
INTCON Register. This is a twocycle instruction.
Encoding:
Description:
RLF
00
1101
f,d
dfff
ffff
The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
C
Register f
Return with Literal in W
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
RETLW k
Operands:
Operation:
k → (W);
TOS → PC
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Status Affected:
None
Status Affected:
C
Encoding:
00
Description:
The contents of register ‘f’ are
rotated one bit to the right
through the Carry Flag. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’ the result is
placed back in register ‘f’.
Encoding:
11
Description:
The W register is loaded with
the eight-bit literal ‘k’. The program counter is loaded from the
top of the stack (the return
address). This is a two-cycle
instruction.
01xx
kkkk
kkkk
1100
C
RETURN
Return from Subroutine
SLEEP
Syntax:
[ label ]
Syntax:
[label]
None
RETURN
RRF f,d
dfff
ffff
REGISTER F
Go into Standby mode
SLEEP
Operands:
None
Operands:
Operation:
TOS → PC
Operation:
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Encoding:
00
Description:
The power-down Status bit, PD
is cleared. Time out Status bit,
TO is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with the oscillator
stopped.
Status Affected:
None
Description:
Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
© 2008 Microchip Technology Inc.
0000
0110
0011
DS41249E-page 133
PIC16F785/HV785
SUBLW
Subtract W from Literal
Syntax:
[label]
Operands:
Operation:
Status
Affected:
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
0 ≤ k ≤ 255
Operands:
5≤f≤6
k - (W) → (W)
Operation:
(W) → TRIS register f;
C, DC, Z
Status Affected:
None
Encoding:
00
Description:
The instruction is supported for
code compatibility with the
PIC16C5X products. Since TRIS
registers are readable and
writable, the user can directly
address them.
Words:
1
Cycles:
1
SUBLW k
Encoding:
11
Description:
The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
110x
kkkk
kkkk
C = 1; result is positive or zero
C = 0; result is negative
0000
f
0110
0fff
Example:
SUBWF
To maintain upward compatibility with future PIC®
products, do not use this
instruction.
Subtract W from f
Syntax:
[label]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
SUBWF f,d
Operation:
(f) - (W) → (dest)
Status
Affected:
C, DC, Z
Encoding:
00
Description:
Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
0010
dfff
ffff
C = 1; result is positive or zero
C = 0; result is negative
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR Literal with W
Syntax:
[ label
]
Syntax:
[label]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .XOR. k → (W)
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Status Affected:
Z
Encoding:
11
Status
Affected:
None
Description:
Encoding:
00
The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed
in the W register.
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’
is ‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
DS41249E-page 134
SWAPF f,d
1110
dfff
ffff
XORLW k
1010
kkkk
kkkk
© 2008 Microchip Technology Inc.
PIC16F785/HV785
XORWF
Exclusive OR W with f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) .XOR. (f) → (dest)
Status
Affected:
Z
Encoding:
00
Description:
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’
is ‘0’, the result is stored in the
W register. If ‘d’ is ‘1’ the result is
stored back in register ‘f’.
© 2008 Microchip Technology Inc.
XORWF
0110
f,d
dfff
ffff
DS41249E-page 135
PIC16F785/HV785
NOTES:
DS41249E-page 136
© 2008 Microchip Technology Inc.
PIC16F785/HV785
18.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Programmers
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
18.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Visual device initializer for easy register
initialization
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2008 Microchip Technology Inc.
DS41249E-page 137
PIC16F785/HV785
18.2
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for all PIC MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
18.5
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
18.6
18.3
MPLAB C18 and MPLAB C30
C Compilers
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital
signal controllers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
18.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS41249E-page 138
© 2008 Microchip Technology Inc.
PIC16F785/HV785
18.7
MPLAB ICE 2000
High-Performance
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PIC microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
18.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The MPLAB REAL ICE probe is connected to the design
engineer’s PC using a high-speed USB 2.0 interface and
is connected to the target with either a connector
compatible with the popular MPLAB ICD 2 system
(RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
18.9
MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PIC
MCUs and can be used to develop for these and other
PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes
the in-circuit debugging capability built into the Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by setting breakpoints, single stepping and watching variables, and CPU status and
peripheral registers. Running at full speed enables
testing hardware and applications in real time. MPLAB
ICD 2 also serves as a development programmer for
selected PIC devices.
18.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
MPLAB REAL ICE is field upgradeable through future
firmware downloads in MPLAB IDE. In upcoming
releases of MPLAB IDE, new devices will be supported,
and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE
offers significant advantages over competitive emulators
including low-cost, full-speed emulation, real-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2008 Microchip Technology Inc.
DS41249E-page 139
PIC16F785/HV785
18.11 PICSTART Plus Development
Programmer
18.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PIC devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
18.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer and selected Flash device debugger with
an easy-to-use interface for programming many of
Microchip’s baseline, mid-range and PIC18F families of
Flash memory microcontrollers. The PICkit 2 Starter Kit
includes a prototyping development board, twelve
sequential lessons, software and HI-TECH’s PICC™
Lite C compiler, and is designed to help get up to speed
quickly using PIC® microcontrollers. The kit provides
everything needed to program, evaluate and develop
applications using Microchip’s powerful, mid-range
Flash memory family of microcontrollers.
DS41249E-page 140
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
© 2008 Microchip Technology Inc.
PIC16F785/HV785
19.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias................................................................................................................. -40 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V
Voltage on MCLR with respect to Vss ........................................................................................................-0.3 to +13.5V
Voltage on RB6 open-drain pin with respect to Vss .....................................................................................-0.3 to +8.5V
Voltage on all other pins with respect to VSS ................................................................................. -0.3V to (VDD + 0.3V)
Total power dissipation(1) (PDIP and SOIC).........................................................................................................800 mW
Total power dissipation(1) (SSOP) ........................................................................................................................600 mW
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD)................................................................................................................ ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTC (combined) .................................................................200 mA
Maximum current sourced PORTA, PORTB, and PORTC (combined).................................................................200 mA
Note 1:
Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than
pulling this pin directly to VSS.
© 2008 Microchip Technology Inc.
DS41249E-page 141
PIC16F785/HV785
FIGURE 19-1:
PIC16F785/HV785 WITH ANALOG DISABLED VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA ≤ +125°C(2)
5.5
(3)
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
8
10
12
Frequency
16
20
(MHz)(2)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Frequency denotes system clock frequency. When using the HFINTOSC the system clock is
after the postscaler.
3: The internal shunt regulator of the PIC16HV785 keeps VDD at or below 5.0V (nominal).
DS41249E-page 142
© 2008 Microchip Technology Inc.
PIC16F785/HV785
19.1
DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E (Extended)
DC CHARACTERISTICS
Param
No.
Sym
VDD
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Min
Typ† Max Units
2.0
2.2
2.5
3.0
4.5
—
—
—
—
—
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
FOSC ≤ 4 MHz:
PIC16F785 with A/D off
PIC16F785 with A/D on, 0°C to +125°C
PIC16F785 with A/D on, -40°C to +125°C
4 MHz ≤ FOSC ≤ 10 MHz
10 MHz ≤ FOSC ≤ 20 MHz
1.5*
—
—
V
Device in Sleep mode
—
1.8
—
V
See Section 15.2.1 “Power-On Reset”
for details.
—
1.0
—
V
See Section 15.2.1 “Power-On Reset”
for details.
0.05*
—
—
—
2.1
—
Supply Voltage(2)
D001
D001A
D001B
D001C
D001D
D002
VDR
RAM Data Retention
Voltage(1)
D003
VPOR
VDD voltage above which
the internal POR releases
D003A VPARM VDD voltage below which
the internal POR rearms
D004
SVDD
VDD Rise Rate to ensure
internal Power-on Reset
signal
D005
VBOR
Brown-out Reset
Conditions
V/ms See Section 15.2.1 “Power-On Reset”
for details.
V
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: Maximum supply voltage is VSHUNT for PIC16HV785 device (see Table 19-14).
© 2008 Microchip Technology Inc.
DS41249E-page 143
PIC16F785/HV785
DC Characteristics: PIC16F785/HV785-I (Industrial)(1), (2)
19.2
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Conditions
Param
No.
Device Characteristics
Min
Typ†
Max
Units
VDD
D010
Supply Current (IDD)
D011
D012
D013
D014
D015
D016
D017
D018
†
Note 1:
2:
3:
4:
—
11
23
μA
2.0
—
18
38
μA
3.0
—
35
75
μA
5.0
—
140
240
μA
2.0
—
220
380
μA
3.0
—
380
550
μA
5.0
—
260
360
μA
2.0
—
420
650
μA
3.0
—
0.8
1.1
mA
5.0
—
130
220
μA
2.0
—
215
360
μA
3.0
—
360
520
μA
5.0
—
220
340
μA
2.0
—
375
550
μA
3.0
—
0.65
1
mA
5.0
—
8
20
μA
2.0
—
16
40
μA
3.0
—
31
65
μA
5.0
—
340
450
μA
2.0
—
500
700
μA
3.0
—
800
1200
μA
5.0
—
230
400
μA
2.0
—
400
680
μA
3.0
—
0.63
1.1
mA
5.0
—
2.6
3.25
mA
4.5
—
2.8
3.35
mA
5.0
FOSC = 32 kHz
LP Oscillator mode
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 1 MHz
EC Oscillator mode
FOSC = 4 MHz
EC Oscillator mode
FOSC = 31 kHz
INTRC mode
FOSC = 4 MHz
INTOSC mode
FOSC = 4 MHz
EXTRC mode
FOSC = 20 MHz
HS Oscillator mode
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-torail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current
consumption.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume
any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.
DS41249E-page 144
© 2008 Microchip Technology Inc.
PIC16F785/HV785
DC Characteristics: PIC16F785/HV785-I (Industrial)(1), (2) (Continued)
19.2
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Conditions
Param
No.
Device Characteristics
Min
Typ†
Max
Units
—
0.15
1.2
μA
2.0
—
0.20
1.5
μA
3.0
—
0.35
1.8
μA
5.0
—
1.7
3.0
μA
2.0
—
2
4
μA
3.0
VDD
D020
Power-down Base Current
(IPD)(4)
D021
—
3
7
μA
5.0
D022
—
42
60
μA
3.0
—
85
122
μA
5.0
D023
—
362
465
μA
2.0
—
418
532
μA
3.0
—
500
603
μA
5.0
—
96
125
μA
2.0
—
112
142
μA
3.0
D023A
D024
D024A
D025
D026
D027
D028
†
Note 1:
2:
3:
4:
WDT, BOR, Comparators, VREF, T1OSC,
Op Amps and VR disabled
WDT Current(3)
BOR Current(3)
Comparator Current(3)
CxSP = 1
Comparator Current(3)
CxSP = 0
—
132
162
μA
5.0
—
39
47
μA
2.0
—
59
72
μA
3.0
—
98
124
μA
5.0
—
30
36
μA
2.0
—
45
55
μA
3.0
—
75
95
μA
5.0
—
2.5
7.0
μA
2.0
—
3.2
14
μA
3.0
—
4.8
32
μA
5.0
—
0.30
1.6
nA
3.0
—
0.36
1.9
nA
5.0
A/D Current(3)
(not converting)
—
9
13
μA
2.0
VR Current(3)
—
10
14
μA
3.0
—
11
15
μA
5.0
—
202
370
μA
3.0
—
217
418
μA
5.0
CVREF Current(3)
Low Range
CVREF Current(3)
High Range (VRR = 0)
T1 OSC Current(3)
Op Amp Current(3)
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-torail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current
consumption.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume
any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.
© 2008 Microchip Technology Inc.
DS41249E-page 145
PIC16F785/HV785
DC Characteristics: PIC16F785/HV785-E (Extended)(1), (2)
19.3
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C for extended
Conditions
Param
No.
Device Characteristics
Min
Typ†
Max
Units
VDD
D010E
Supply Current (IDD)
D011E
D012E
D013E
D014E
D015E
D016E
D017E
D018E
†
Note 1:
2:
3:
4:
—
11
23
μA
2.0
—
18
38
μA
3.0
—
35
75
μA
5.0
—
140
240
μA
2.0
—
220
380
μA
3.0
—
380
550
μA
5.0
—
260
360
μA
2.0
—
420
650
μA
3.0
—
0.8
1.1
mA
5.0
—
130
220
μA
2.0
—
215
360
μA
3.0
—
360
520
μA
5.0
—
220
340
μA
2.0
—
375
550
μA
3.0
—
0.65
1.0
mA
5.0
—
8
20
μA
2.0
—
16
40
μA
3.0
—
31
65
μA
5.0
—
340
450
μA
2.0
—
500
700
μA
3.0
—
800
1200
μA
5.0
—
230
400
μA
2.0
—
400
680
μA
3.0
—
0.63
1.1
mA
5.0
—
2.6
3.25
mA
4.5
—
2.8
3.35
mA
5.0
FOSC = 32 kHz
LP Oscillator mode
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
FOSC = 1 MHz
EC Oscillator mode
FOSC = 4 MHz
EC Oscillator mode
FOSC = 31 kHz
INTRC mode
FOSC = 4 MHz
INTOSC mode
FOSC = 4 MHz
EXTRC mode
FOSC = 20 MHz
HS Oscillator mode
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to
rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current
consumption.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not
consume any current other than leakage current. The power-down current spec includes any such leakage from the
A/D module.
DS41249E-page 146
© 2008 Microchip Technology Inc.
PIC16F785/HV785
DC Characteristics: PIC16F785/HV785-E (Extended)(1), (2) (Continued)
19.3
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C for extended
Conditions
Param
No.
Device Characteristics
Min
Typ†
Max
Units
—
0.15
9
μA
2.0
—
0.20
11
μA
3.0
—
0.35
15
μA
5.0
—
1.7
17.5
μA
2.0
—
2
19
μA
3.0
VDD
D020E
Power-down Base Current
(IPD)(4)
D021E
—
3
22
μA
5.0
D022E
—
42
65
μA
3.0
—
85
127
μA
5.0
D023E
—
362
476
μA
2.0
—
418
554
μA
3.0
—
500
625
μA
5.0
—
96
130
μA
2.0
—
112
147
μA
3.0
D023E
D024E
D024E
D025E
D026E
D027E
D028E
†
Note 1:
2:
3:
4:
WDT, BOR, Comparators, VREF, T1OSC,
Op Amps and VR disabled
WDT Current(3)
BOR Current(3)
Comparator Current(3)
CxSP = 1
Comparator Current(3)
CxSP = 0
—
132
168
μA
5.0
—
39
47
μA
2.0
—
59
72
μA
3.0
—
98
124
μA
5.0
—
30
36
μA
2.0
—
45
55
μA
3.0
—
75
95
μA
5.0
—
2.5
21
μA
2.0
—
3.2
28
μA
3.0
—
4.8
45
μA
5.0
—
0.30
12
uA
3.0
—
0.36
16
uA
5.0
A/D Current(3)
(not converting)
—
9
20
μA
3.0
VR Current(3)
—
10
26
μA
3.0
—
11
30
μA
5.0
—
202
417
μA
3.0
—
217
468
μA
5.0
CVREF Current(3)
Low Range
CVREF Current(3)
High Range
T1 OSC Current(3)
Op Amp Current(3)
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to
rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current
consumption.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured
with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not
consume any current other than leakage current. The power-down current spec includes any such leakage from the
A/D module.
© 2008 Microchip Technology Inc.
DS41249E-page 147
PIC16F785/HV785
19.4
DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E
(Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym
VIL
Characteristic
Min
Typ†
Max
Units
VSS
VSS
Conditions
—
0.8
V
4.5V ≤ VDD ≤ 5.5V
—
0.15 VDD
V
Otherwise
VSS
—
0.2 VDD
V
Entire range
VSS
—
0.2 VDD
V
Input Low Voltage
I/O ports
D030
with TTL buffer
D030A
D031
with Schmitt Trigger buffer
D032
MCLR, OSC1 (RC mode)(1)
D033
OSC1 (XT and LP modes)
VSS
—
0.3
V
D033A
OSC1 (HS mode)
VSS
—
0.3 VDD
V
2.0
(0.25 VDD + 0.8)
—
—
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
Otherwise
0.8 VDD
—
VDD
V
Entire range
0.8 VDD
—
VDD
V
1.6
—
VDD
V
V
VIH
Input High Voltage
I/O ports
D040
D040A
—
with TTL buffer
D041
with Schmitt Trigger buffer
D042
MCLR
D043
OSC1 (XT and LP modes)
D043A
OSC1 (HS mode)
0.7 VDD
—
VDD
D043B
OSC1 (RC mode)
0.9 VDD
—
VDD
V
(Note 1)
50*
250
400*
μA
VDD = 5.0V, VPIN = VSS
D070
IPUR
PORTA Weak Pull-up Current
(2)
IIL
Input Leakage Current
D060
I/O ports
—
±0.1
±1
μA
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
D060A
Analog inputs
—
±0.1
±1
μA
VSS ≤ VPIN ≤ VDD
D060B
VREF
—
±0.1
±1
μA
VSS ≤ VPIN ≤ VDD
D061
MCLR(3)
—
±0.1
±5
μA
VSS ≤ VPIN ≤ VDD
D063
OSC1
—
±0.1
±5
μA
VSS ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
VOL
Output Low Voltage
D080
I/O ports
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V
D083
OSC2/CLKOUT (RC mode)
—
—
0.6
V
IOL = 1.6 mA, VDD = 4.5V (Ind.)
IOL = 1.2 mA, VDD = 4.5V (Ext.)
VOH
Output High Voltage
D090
I/O ports
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 4.5V
D092
OSC2/CLKOUT (RC mode)
VDD – 0.7
—
—
V
IOH = -1.3 mA, VDD = 4.5V (Ind.)
IOH = -1.0 mA, VDD = 4.5V (Ext.)
Open-Drain High Voltage
—
—
8.5
V
RB6 pin
D193*
VOD
*
†
Note 1:
2:
3:
4:
These parameters are characterized but not tested.
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
See Section 14.4.1 “Using the Data EEPROM” on page 105.
DS41249E-page 148
© 2008 Microchip Technology Inc.
PIC16F785/HV785
19.4
DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E (Extended)
(Continued)
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Min
Typ†
Max
Units
—
—
15*
pF
—
—
50*
pF
Conditions
Capacitive Loading Specs on Output Pins
D100
COSC2 OSC2 pin
D101
CIO
All I/O pins
In XT, HS and LP modes when
external clock is used to drive
OSC1
Data EEPROM Memory
-40°C ≤ TA ≤ +85°C
D120
ED
Byte Endurance
100K
1M
—
E/W
D120A
ED
Byte Endurance
10K
100K
—
E/W
D121
VDRW
VDD for Read/Write
VMIN
—
5.5
V
D122
TDEW
Erase/Write cycle time
—
5
6
ms
D123
TRETD
Characteristic Retention
40
—
—
Year Provided no other specifications
are violated
D124
TREF
Number of Total Erase/Write
Cycles before Refresh(4)
1M
10M
—
E/W
-40°C ≤ TA ≤ +85°C
D130
EP
Cell Endurance
10K
100K
—
E/W
-40°C ≤ TA ≤ +85°C
+85°C ≤ TA ≤ +125°C
Using EECON1 to read/write
VMIN = Minimum operating
voltage
Program Flash Memory
D130A
EP
Cell Endurance
D131
VPR
VDD for Read
D132
VPEW
D133
TPEW
D134
TRETD
*
†
Note 1:
2:
3:
4:
1K
10K
—
E/W
VMIN
—
5.5
V
VDD for Erase/Write
4.5
—
5.5
V
Erase/Write cycle time
—
2
2.5
ms
Characteristic Retention
40
—
—
+85°C ≤ TA ≤ +125°C
VMIN = Minimum operating
voltage
Year Provided no other specifications
are violated
These parameters are characterized but not tested.
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
See Section 14.4.1 “Using the Data EEPROM” on page 105.
© 2008 Microchip Technology Inc.
DS41249E-page 149
PIC16F785/HV785
19.5
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 19-2:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
Legend: RL = 464Ω
CL = 50 pF
15 pF
DS41249E-page 150
for all pins
for OSC2 output
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 19-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
4
3
4
2
CLKOUT
TABLE 19-1:
Param
No.
Sym
FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic
Min
Typ†
Max
Units
External CLKIN Frequency(1)
—
32.768
—
kHz
DC
DC
DC
—
—
DC
0.1
1
—
—
—
—
32.768
4
—
—
—
0.3052
4
20
20
—
—
4
4
20
—
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
μs
50
—
∞
ns
Oscillator Frequency(1)
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
2
3
TCY
TosL,
TosH
Conditions
LP mode (complementary input
only)
XT mode
HS mode
EC mode
LP Osc mode
INTOSC mode
RC Osc mode
XT Osc mode
HS Osc mode
LP mode (complementary input
only)
HS Osc mode
50
—
∞
ns
EC Osc mode
250
—
∞
ns
XT Osc mode
—
—
250
250
50
0.3052
250
—
—
—
—
—
—
10,000
1,000
μs
ns
ns
ns
ns
LP Osc mode
INTOSC mode
RC Osc mode
XT Osc mode
HS Osc mode
Instruction Cycle Time(1)
External CLKIN (OSC1) High
External CLKIN Low
200
TCY
DC
ns TCY = 4/FOSC
2*
—
—
μs LP oscillator, TOSC L/H duty cycle
20*
—
—
ns HS oscillator, TOSC L/H duty cycle
100 *
—
—
ns XT oscillator, TOSC L/H duty cycle
4
TosR, External CLKIN Rise
—
—
50*
ns LP oscillator
TosF External CLKIN Fall
—
—
25*
ns XT oscillator
—
—
15*
ns HS oscillator
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’
values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle
time limit is ‘DC’ (no clock) for all devices.
© 2008 Microchip Technology Inc.
DS41249E-page 151
PIC16F785/HV785
FIGURE 19-4:
CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
13
12
19
14
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
TABLE 19-2:
Param
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
10
TOSH2CKL
OSC1↑ to CLKOUT↓
—
75
200
ns
(Note 1)
11
TOSH2CKH OSC1↑ to CLKOUT↑
—
75
200
ns
(Note 1)
12
TCKR
CLKOUT rise time
—
35
100
ns
(Note 1)
13
TCKF
CLKOUT fall time
—
35
100
ns
(Note 1)
—
—
20
ns
(Note 1)
TOSC + 200 ns
—
—
ns
(Note 1)
(Note 1)
14
TCKL2IOV
CLKOUT↓ to Port out valid
15
TIOV2CKH
Port input valid before CLKOUT↑
16
TCKH2IOI
Port input hold after CLKOUT↑
0
—
—
ns
17
TOSH2IOV
OSC1↑ (Q1 cycle) to Port out valid
—
50
150 *
ns
18
TOSH2IOI
OSC1↑ (Q2 cycle) to Port input
invalid (I/O in hold time)
19
TIOV2OSH
20
21
22
TINP
23
TRBP
—
—
300
ns
100
—
—
ns
Port input valid to OSC1↑
(I/O in setup time)
0
—
—
ns
TIOR
Port output rise time
—
10
40
ns
TIOF
Port output fall time
—
10
40
ns
INT pin high or low time
25
—
—
ns
PORTA interrupt-on-change high or
low time
TCY
—
—
ns
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
DS41249E-page 152
© 2008 Microchip Technology Inc.
PIC16F785/HV785
TABLE 19-3:
Param
No.
F10
F14
Sym
FOSC
PRECISION INTERNAL OSCILLATOR PARAMETERS
Characteristic
Internal Calibrated
INTOSC Frequency(1)
TIOSCST Oscillator wake-up from
Sleep start-up time*
Freq.
Min
Tolerance
Typ†
Max
Units
Conditions
±1%
7.92
8.00
8.08
MHz VDD = 3.5V, 25°C
±2%
7.84
8.00
8.16
MHz 2.5V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
±5%
7.60
8.00
8.40
MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (Ind.)
-40°C ≤ TA ≤ +125°C (Ext.)
—
—
12
24
μs
VDD = 2.0V, -40°C to +85°C
—
—
7
14
μs
VDD = 3.0V, -40°C to +85°C
—
—
6
11
μs
VDD = 5.0V, -40°C to +85°C
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
FIGURE 19-5:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
34
31
34
I/O Pins
© 2008 Microchip Technology Inc.
DS41249E-page 153
PIC16F785/HV785
FIGURE 19-6:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR
(Device not in Brown-out Reset)
(Device in Brown-out Reset)
36
Reset (due to BOR)
Note 1:
64 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’.
TABLE 19-4:
Param
No.
64 ms time-out(1)
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
TMCL
MCLR Pulse Width (low)
2
11
—
18
—
24
μs
μs
VDD = 5.0V, -40°C to +85°C
Extended temperature
31
TWDT
Watchdog Timer Time-out Period
(No Prescaler)
10
10
17
17
25
30
ms
ms
VDD = 5.0V, -40°C to +85°C
Extended temperature
32
TOST
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
TPWRT
Power-up Timer Period
28*
64
132*
ms
VDD = 5.0V, -40°C to +85°C
34
TIOZ
I/O High-impedance from MCLR
Low or Watchdog Timer Reset
—
—
2.0
μs
35
VBOR
Brown-out Reset Voltage
2.025
—
2.175
V
TBOR
Brown-out Reset Pulse Width
100*
—
—
μs
36
VDD ≤ VBOR (D005)
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS41249E-page 154
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 19-7:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 19-5:
Param
No.
40*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Sym
TT0H
Characteristic
T0CKI High Pulse Width
Min
No Prescaler
With Prescaler
41*
TT0L
T0CKI Low Pulse Width
No Prescaler
With Prescaler
42*
TT0P
T0CKI Period
45*
TT1H
T1CKI High
Time
Synchronous, No Prescaler
Synchronous,
with Prescaler
Asynchronous
46*
TT1L
T1CKI Low Time Synchronous, No Prescaler
Synchronous,
with Prescaler
Units
0.5 TCY + 20
—
—
ns
10
—
—
ns
0.5 TCY + 20
—
—
ns
10
—
—
ns
Greater of:
20 or TCY + 40
N
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
30
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
Asynchronous
30
—
—
ns
Greater of:
30 or TCY + 40
N
—
—
ns
TT1P
T1CKI Input
Period
48
FT1
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
TCKEZTMR1
Delay from external clock edge to timer increment
Asynchronous
*
†
Max
Synchronous
47*
49
Typ†
60
—
—
ns
DC
—
200*
kHz
2 TOSC*
—
7 TOSC*
—
Conditions
N = prescale
value (2, 4, ...,
256)
N = prescale
value (1, 2, 4,
8)
These parameters are characterized but not tested.
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
© 2008 Microchip Technology Inc.
DS41249E-page 155
PIC16F785/HV785
FIGURE 19-8:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP1
(Capture mode)
50
51
52
CCP1
(Compare or PWM mode)
53
54
Note: Refer to Figure 19-2 for load conditions.
TABLE 19-6:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Param
Symbol
No.
50*
TCCL
Characteristic
CCP1 input low time
Min
No Prescaler
With Prescaler
51*
TCCH
CCP1 input high time
No Prescaler
With Prescaler
Typ† Max Units
0.5TCY +
20
—
—
ns
20
—
—
ns
0.5TCY +
20
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
52*
TCCP
CCP1 input period
53*
TCCR
CCP1 output rise time
—
25
50
ns
54*
TCCF
CCP1 output fall time
—
25
45
ns
Conditions
N = prescale value
(1,4 or 16)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS41249E-page 156
© 2008 Microchip Technology Inc.
PIC16F785/HV785
TABLE 19-7:
COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Comparator Specifications
Param
No.
C01
Symbol
Characteristics
VOS
Input Offset Voltage
Min
Typ
Max
Units
—
±5
±10
mV
Comments
C02
VCM
Input Common Mode Voltage
0
—
VDD – 1.5
V
C03
ILC
Input Leakage Current
—
—
200*
nA
C04
CMRR
Common Mode Rejection
Ratio
+70*
—
—
dB
C05
TRT
Response Time(1)
—
—
—
—
20*
40*
ns
ns
*
Note 1:
These parameters are characterized but not tested.
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from
VSS to VDD – 1.5V.
TABLE 19-8:
COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
Comparator Voltage Reference Specifications
Param
No.
Internal
Output to pin
Min
Typ
Max
Units
Resolution
—
—
VDD/24*
VDD/32
—
—
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
CV02
Absolute Accuracy
—
—
—
—
±1/4*
±1/2*
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
CV03
Unit Resistor Value (R)
—
2K*
—
Ω
CV04
Time(1)
—
—
10*
μs
CV01
Symbol
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
CVRES
Characteristics
Settling
*
Note 1:
These parameters are characterized but not tested.
Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
TABLE 19-9:
VOLTAGE REFERENCE (VR) SPECIFICATIONS
VR Voltage Reference Specifications
Param
No.
VR01
Comments
Symbol
VROUT
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C
Operating Voltage
3.0V ≤ VDD ≤ 5.5V
Characteristics
VR voltage output
Min
Typ
Max
Units
1.188
1.176
1.164
1.200
1.200
1.200
1.212
1.224
1.236
V
V
V
Comments
TA = 25°C
0°C ≤ TA ≤ +85°C
-40°C ≤ TA ≤ +125°C
TABLE 19-10: VOLTAGE REFERENCE OUTPUT (VREF) BUFFER SPECIFICATIONS
Voltage Reference Output Buffer
Specifications
Param
No.
VB01*
Symbol
CL
*
Characteristics
External capacitor load
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C
Operating voltage
3.0V ≤ VDD ≤ 5.5V
Min
Typ
Max
Units
—
—
200
pF
Comments
These parameters are characterized but not tested.
© 2008 Microchip Technology Inc.
DS41249E-page 157
PIC16F785/HV785
TABLE 19-11: OPERATIONAL AMPLIFIER (OPA) MODULE DC SPECIFICATIONS
OPA DC CHARACTERISTICS
Param
No.
Sym
Characteristics
Standard Operating Conditions (unless otherwise stated)
VCM = 0V, VOUT = VDD/2, VDD = 5.0V, VSS = 0V, CL = 50pF,
RL = 100k
Operating temperature
-40°C ≤ TA ≤ +125°C
Min
Typ
Max
Units
Comments
VOS
Input Offset Voltage
—
±5
—
mV
OPA02*
OPA03*
IB
IOS
Input current and impedance
Input bias current
Input offset bias current
—
—
±2*
±1*
—
—
nA
pA
OPA04*
OPA05*
VCM
CMR
Common Mode
Common mode input range
Common mode rejection
VSS
65
—
70
VDD – 1.4
—
V
dB
VDD = 5.0V
VCM = VDD/2, Freq. = DC
—
—
90
60
—
—
dB
dB
No load
Standard load
VSS+100
—
VDD – 100
mV
To VDD/2 (20 kΩ
connected to VDD,
20 kΩ + 20 pF to Vss)
OPA01
OPA06A* AOL
OPA06B* AOL
Open Loop Gain
DC Open loop gain
DC Open loop gain
OPA07*
Vout
Output
Output voltage swing
OPA08*
Isc
Output short circuit current
—
25
28
mA
OPA10
PSR
Power Supply
Power supply rejection
80
—
—
dB
*
These parameters are characterized but not tested.
TABLE 19-12: OPERATIONAL AMPLIFIER (OPA) MODULE AC SPECIFICATIONS
OPA AC CHARACTERISTICS
Param
No.
Symbol
Characteristics
Standard Operating Conditions (unless otherwise stated)
VCM = 0V, VOUT = VDD/2, VDD = 5.0V, VSS = 0V, CL = 50 pF,
RL = 100k
Operating temperature
-40°C ≤ TA ≤ +125°C
Min
Typ
Max
Units
OPA11* GBWP
Gain bandwidth product
—
3
—
MHz
OPA12* TON
Turn on time
—
10
15
μs
OPA13* ΘM
Phase margin
—
60
—
deg
OPA14* SR
Slew rate
2
—
—
V/μs
*
Comments
These parameters are characterized but not tested.
TABLE 19-13: TWO-PHASE PWM DEAD TIME DELAY SPECIFICATIONS
Dead Time Delay Characteristics
Param
No.
PW01*
Symbol
TDLY
*
Characteristics
Dead Time Delay
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C
Min
Typ
Max
Units
205
231
275
ns
Comments
FOSC = 4 MHz,
maximum delay,
Complementary mode
These parameters are characterized but not tested.
DS41249E-page 158
© 2008 Microchip Technology Inc.
PIC16F785/HV785
TABLE 19-14: SHUNT REGULATOR SPECIFICATIONS (PIC16HV785 only)
SHUNT REGULATOR CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C
Characteristics
VSHUNT Shunt Voltage
SR01
SR02
ISHUNT
SR03*
TSETTLE Settling Time
SR04*
CLOAD
Load Capacitance
SR05*
ΔISNT
Regulator operating current
*
Min
Typ
Max
Units
4.75
5
5.25
V
Shunt Current
Comments
4
—
50
mA
—
—
150
ns
To 1% of final value
0.01
—
10
μF
Bypass capacitor on VDD
pin
—
—
180
μA
Includes band gap
reference current
These parameters are characterized but not tested.
TABLE 19-15: PIC16F785/HV785 A/D CONVERTER CHARACTERISTICS:
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
10 bits
A03
EIL
Integral Error
—
—
±1
LSb VREF = 5.0V (external)
A04
EDL
Differential Error
—
—
±1
LSb No missing codes to 10 bits
VREF = 5.0V (external)
A06
EOFF Offset Error
—
—
±1
LSb VREF = 5.0V (external)
A07
EGN
Gain Error
—
—
±1
LSb VREF = 5.0V (external)
A20
A20A
VREF Reference Voltage
2.2(4)
—
—
VDD + 0.3
V
A25
VAIN
Analog Input
Voltage
A30
ZAIN
A50
IREF
1.0
bit
Absolute minimum to ensure 10-bit
accuracy
VSS
—
VREF(5)
V
Recommended
Impedance of
Analog Voltage
Source
—
—
10
kΩ
VREF Input
Current*(3)
—
—
150
μA
—
—
1
During VAIN acquisition.
Based on differential of VHOLD to
mA VAIN.
Transient during A/D conversion
cycle.
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Total Absolute Error includes Integral, Differential, Offset and Gain Errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: VREF current is from external VREF or VDD pin, whichever is selected as reference input.
4: Only limited when VDD is at or below 2.5V. If VDD is above 2.5V, VREF is allowed to go as low as 1.0V.
5: Analog input voltages are allowed up to VDD, however the conversion accuracy is limited to VSS to VREF.
© 2008 Microchip Technology Inc.
DS41249E-page 159
PIC16F785/HV785
FIGURE 19-9:
PIC16F785/HV785 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
134
1 TCY
(TOSC/2)(1)
131
Q4
130
A/D CLK
9
A/D DATA
8
7
3
6
2
1
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
DONE
Note 1:
SAMPLING STOPPED
132
SAMPLE
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 19-16: PIC16F785/HV785 A/D CONVERSION REQUIREMENTS
Param
No.
Sym
130
TAD
130
TAD
Characteristic
A/D Clock Period
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time (not
including
Acquisition Time)(1)
132
TACQ
Acquisition Time
134
TGO
*
†
Note 1:
2:
Q4 to A/D Clock Start
Min
Typ†
Max
Units
Conditions
1.6
—
—
μs
TOSC-based, VREF ≥ 3.0V
3.0*
—
—
μs
TOSC-based, VREF full range
3.0*
6.0
9.0*
μs
ADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0*
4.0
6.0*
μs
At VDD = 5.0V
—
11
—
TAD
Set GO bit to new data in A/D result
register
(Note 2)
11.5
—
μs
5*
—
—
μs
The minimum time is the amplifier settling
time. This may be used if the “new” input
voltage has not changed by more than 1
LSb (i.e., 4.1 mV @ 4.096V) from the last
sampled voltage (as stored on CHOLD).
—
TOSC/2
—
—
If the A/D clock source is selected as
RC, a time of TCY is added before the
A/D clock starts. This allows the SLEEP
instruction to be executed.
These parameters are characterized but not tested.
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
ADRESH and ADRESL registers may be read on the following TCY cycle.
See Section 12.2 “A/D Acquisition Requirements” for minimum conditions.
DS41249E-page 160
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 19-10:
PIC16F785/HV785 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
134
(TOSC/2 + TCY)(1)
1 TCY
131
Q4
130
A/D CLK
9
A/D DATA
8
7
3
6
2
1
NEW_DATA
OLD_DATA
ADRES
0
ADIF
1 TCY
GO
DONE
Note 1:
SAMPLING STOPPED
132
SAMPLE
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
TABLE 19-17: PIC16F785/HV785 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param
No.
130
Sym
TAD
Characteristic
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time
(not including
Acquisition Time)(1)
132
TACQ
Acquisition Time
134
TGO
Q4 to A/D Clock
Start
Min
Typ†
Max
Units
Conditions
3.0*
6.0
9.0*
μs
ADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0*
4.0
6.0*
μs
At VDD = 5.0V
—
11
—
TAD
(Note 2)
11.5
—
μs
5*
—
—
μs
The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
CHOLD).
—
TOSC/2 + TCY
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Table 12-1 for minimum conditions.
© 2008 Microchip Technology Inc.
DS41249E-page 161
PIC16F785/HV785
NOTES:
DS41249E-page 162
© 2008 Microchip Technology Inc.
PIC16F785/HV785
20.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents
(mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range.
FIGURE 20-1:
TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
3.5
3.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.5V
5.0V
IDD (mA)
2.5
2.0
4.0V
1.5
3.0V
1.0
2.0V
0.5
0.0
1 MHz
2 MHz
4 MHz
6 MHz
8 MHz
10 MHz
12 MHz
14 MHz
16 MHz
18 MHz
20 MHz
FOSC
© 2008 Microchip Technology Inc.
DS41249E-page 163
PIC16F785/HV785
FIGURE 20-2:
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
4.0
3.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.5V
5.0V
3.0
IDD (mA)
2.5
4.0V
2.0
3.0V
1.5
2.0V
1.0
0.5
0.0
1 MHz
2 MHz
4 MHz
6 MHz
8 MHz
10 MHz
12 MHz
14 MHz
16 MHz
18 MHz
20 MHz
FOSC
FIGURE 20-3:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
HS Mode
4.0
3.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.5V
3.0
5.0V
IDD (mA)
2.5
4.5V
2.0
1.5
4.0V
3.5V
3.0V
1.0
0.5
0.0
4 MHz
10 MHz
16 MHz
20 MHz
FOSC
DS41249E-page 164
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-4:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
HS Mode
5.0
4.5
4.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.5V
IDD (mA)
3.5
5.0V
3.0
4.5V
2.5
2.0
1.5
4.0V
3.5V
3.0V
1.0
0.5
0.0
4 MHz
10 MHz
16 MHz
20 MHz
FOSC
FIGURE 20-5:
TYPICAL IDD vs. VDD OVER FOSC (XT MODE)
900
800
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
700
IDD (μA)
600
500
4 MHz
400
300
1 MHz
200
100
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41249E-page 165
PIC16F785/HV785
FIGURE 20-6:
MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)
1,400
1,200
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
1,000
IDD (μA)
800
4 MHz
600
400
1 MHz
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
4
4.5
5
5.5
VDD (V)
IDD vs. VDD (LP MODE)
FIGURE 20-7:
90
Typical
Typical
Typical:
[email protected]×C
@25°C
Typical:Statistical
Statistical Mean
802.0 Maximum:
(Worst-case
11Mean
Maximum:
Mean (Worst
Case Temp) + 3σ
(-40°C
T
)to+ 125°C)
3
14.5
702.5
3.0
IDD (uA)
603.5
4.0
4.5
405.0
5.5
50
18
22.25
26.5
30.75
35
39.25
Maximum
30
Typical
20
10
Max
0
2.0
2.5
30
Maximum
2
23
30.5
38
DS41249E-page 166
2.5
3
3.5
5.5
VDD (V)
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-8:
TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)
800
700
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
600
IDD (μA)
500
4 MHz
400
300
1 MHz
200
100
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 20-9:
MAXIMUM IDD vs. VDD OVER FOSC (EXTRC MODE)
1,400
1,200
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
IDD (μA)
1,000
4 MHz
800
600
1 MHz
400
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41249E-page 167
PIC16F785/HV785
FIGURE 20-10:
IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)
LFINTOSC Mode, 31KHZ
80
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
70
60
IDD (μA)
50
Maximum
40
30
Typical
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 20-11:
TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)
1,600
1,400
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.5V
5.0V
1,200
IDD (μA)
1,000
4.0V
800
3.0V
600
2.0V
400
200
0
125 kHz
250 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
FOSC
DS41249E-page 168
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-12:
MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE)
2,000
1,800
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5.5V
5.0V
1,600
1,400
4.0V
IDD (μA)
1,200
1,000
3.0V
800
600
2.0V
400
200
0
125 kHz
250 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
FOSC
FIGURE 20-13:
TYPICAL IPD vs. VDD (SLEEP
yp MODE, ALL PERIPHERALS DISABLED)
(Sleep Mode all Periphreals Disabled)
0.50
0.45
Typical: Statistical Mean @25°C
0.40
IPD (uA)
0.35
0.30
0.25
2
2.5
3
3.5
4
4.5
5
5.5
0.20
0.15
0.10
Typ 25×C
0.150
0.175
0.200
0.238
0.275
0.313
0.350
0.388
Max 85×C
1.20
1.285
1.50
1.483
1.585
1.688
1.79
1.893
Max 125×C
9.00
10.000
11.00
11.800
12.600
13.400
14.20
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41249E-page 169
PIC16F785/HV785
FIGURE 20-14:
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Maximum
(Sleep Mode all Periphreals Disabled)
16.0
14.0
Max 125°C
12.0
10.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
IPD (uA)
8.0
6.0
4.0
Max 85°C
2.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 20-15:
COMPARATOR
IPD vs. VDD (BOTH COMPARATORS
ENABLED)
(
)
200
180
160
Max
140
IPD (uA)
120
Typical
100
80
60
40
20
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41249E-page 170
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-16:
COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED) CXSP=1
800
700
Typical:
Statistical
Mean
@25°C
Typical:
Statistical
Mean
@25×C
Maximum:
Mean
(Worst-case
Temp) + 3σ
Maximum:
Mean
(Worst Case
(-40°C
to
125°C)
Temp)+ 3
600
Max
IPD (uA)
500
400
Typical
300
200
100
0
2.0
2.5
2
FIGURE 20-17:
3.0
Typical
Max
362
4 60
3.5
4.0
4.5
5.0
5.5
VDD (V)
BOR IPD vs. VDD OVER TEMPERATURE
160
140
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
120
IPD (μA)
100
Maximum
80
Typical
60
40
20
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41249E-page 171
PIC16F785/HV785
FIGURE 20-18:
TYPICAL WDT IPD vs. VDD OVER TEMPERATURE
3.5
3.0
IPD (uA)
2.5
2.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
Typical
Max 85×C Max 125×C
(-40°C
to 125°C) 3.000
2 1.700
4.5
2.51.850
3.500
4.75
3 2.000
4.000
5
3.52.250
4.750
6.25
4 2.500
5.500
7.5
4.52.750
6.250
8.75
5 3.000
7.000
10
5.53.250
7.750
1.5
1.0
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 20-19:
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
12.0
10.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
IPD (uA)
8.0
Max. 125°C
6.0
Max. 85°C
4.0
2.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41249E-page 172
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-20:
CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE)
High Range
140
120
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
100
IPD (μA)
Max. 125°C
80
Max. 85°C
60
Typical
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
5.0
5.5
VDD (V)
FIGURE 20-21:
CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)
180
160
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
140
120
IPD (μA)
Max. 125°C
100
Max. 85°C
80
Typical
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41249E-page 173
PIC16F785/HV785
FIGURE 20-22:
T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)
60.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
50.0
40.0
IPD (uA)
Max 125°C
30.0
20.0
2
2.5
3
3.5
4
4.5
5
5.5
2.0
10.0
0.0
Typ 25×C
2.500
2.850
3.200
3.600
4.000
4.400
4.800
5.200
2.5
Max 85×C
7.00
10.50
14.00
18.50
23.00
27.50
32.00
36.50
3.0
Max 85°C
Max 125×C
21.00
24.50
28.00
32.25
36.50
Typ 25°C
40.75
45.00
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 20-23:
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
(VDD = 3V, -40×C TO 125×C)
0.8
0.7
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
Max. 125°C
0.6
VOL (V)
0.5
Max. 85°C
0.4
Typical 25°C
0.3
0.2
Min. -40°C
0.1
6.5
0.0 7
7.5 5.0
8
8.5
9
DS41249E-page 174
0.2518
0.2716
5.5
0.2911
0.3116
0.3318
0 3524
0.3336
6.0
0.3609
6.5
0.3884
0.4166
0.4453
0 4744
0.401
7.0
0.4354
7.5
0.4695
IOL 0.5049
(mA)
0.5413
0 5782
0.1503
8.0
0.1622
8.5
0.1743
0.1862
0.1984
0 2107
9.0
9.5
10.0
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-24:
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.45
Typical: Statistical Mean @25°C
Typical:
Statistical
Mean Temp)
@25×C+ 3σ
Maximum:
Mean
(Worst-case
Maximum: Meas(-40×C
+ 3 to 125×C)
(-40°C to 125°C)
0.40
Max. 125°C
0.35
Max. 85°C
VOL (V)
0.30
0.25
Typ. 25°C
0.20
0.15
Min. -40°C
0.10
0.05
0.00
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
FIGURE 20-25:
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.5
3.0
Max. -40°C
Typ. 25°C
2.5
Min. 125°C
VOH (V)
2.0
1.5
1.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
IOH (mA)
© 2008 Microchip Technology Inc.
DS41249E-page 175
PIC16F785/HV785
FIGURE 20-26:
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)
5.5
5.0
Max. -40°C
Typ. 25°C
VOH (V)
4.5
Min. 125°C
4.0
3.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
3.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
IOH (mA)
FIGURE 20-27:
TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(TTL Input, -40×C TO 125×C)
1.7
1.5
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
Max. -40°C
VIN (V)
1.3
Typ. 25°C
1.1
Min. 125°C
0.9
0.7
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41249E-page 176
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-28:
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(ST Input, -40×C TO 125×C)
4.0
VIH Max. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
3.5
VIH Min. -40°C
VIN (V)
3.0
2.5
2.0
VIL Max. -40°C
1.5
VIL Min. 125°C
1.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)
FIGURE 20-29:
LFINTOSC 31Khz
45,000
40,000
Max. -40°C
35,000
Typ. 25°C
Frequency (Hz)
30,000
25,000
20,000
Min. 85°C
Min. 125°C
15,000
10,000
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
5,000
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41249E-page 177
PIC16F785/HV785
FIGURE 20-30:
ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE
8
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
125°C
6
Time (μs)
85°C
25°C
4
-40°C
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 20-31:
TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
16
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
14
85°C
12
25°C
Time (μs)
10
-40°C
8
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41249E-page 178
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-32:
MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
25
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
Time (μs)
20
15
85°C
25°C
10
-40°C
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 20-33:
MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
-40C to +85C
10
9
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-case Temp) + 3σ
(-40°C to 125°C)
8
7
Time (μs)
85°C
6
25°C
5
-40°C
4
3
2
1
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41249E-page 179
PIC16F785/HV785
FIGURE 20-34:
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C)
5
4
Change from Calibration (%)
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 20-35:
TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C)
5
4
Change from Calibration (%)
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41249E-page 180
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-36:
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C)
5
4
Change from Calibration (%)
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 20-37:
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C)
5
4
Change from Calibration (%)
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2008 Microchip Technology Inc.
DS41249E-page 181
PIC16F785/HV785
FIGURE 20-38:
TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (3V)
Typical VP6 Reference Voltage vs. Temperature (VDD=3V)
0.66
0.64
Max.
VP6 (V)
0.62
0.6
Typical
0.58
Min.
0.56
0.54
0.52
-40°C
25°C
85°C
125°C
Temperature (°C)
FIGURE 20-39:
TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (5V)
Typical VP6 Reference Voltage vs. Temperature (VDD=5V)
0.66
0.64
VP6 (V)
0.62
Max.
0.6
Typical
0.58
0.56
Min.
0.54
0.52
-40 °C
25 °C
85 °C
125 °C
Temperature (°C)
DS41249E-page 182
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-40:
TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C)
Number of Parts
100
80
Parts = 150
60
40
20
1.
23
0
1.
22
4
1.
21
8
1.
21
2
1.
20
6
1.
20
0
1.
19
4
1.
18
8
1.
18
2
1.
17
6
1.
17
0
0
Voltage (V)
FIGURE 20-41:
TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 85°C)
Typical VP6 Reference Voltage Distribution (VDD=3V, 85×C)
Number of Parts
70
60
Parts = 150
50
40
30
20
10
1.
23
0
1.
22
4
1.
21
8
1.
21
2
1.
20
6
1.
20
0
1.
19
4
1.
18
8
1.
18
2
1.
17
6
1.
17
0
0
Voltage (V)
© 2008 Microchip Technology Inc.
DS41249E-page 183
PIC16F785/HV785
FIGURE 20-42:
TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125°C)
Number of Parts
60
50
Parts = 150
40
30
20
10
1.
23
0
1.
22
4
1.
21
8
1.
21
2
1.
20
6
1.
20
0
1.
19
4
1.
18
8
1.
18
2
1.
17
6
1.
17
0
0
Voltage (V)
FIGURE 20-43:
TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, -40°C)
50
Number of Parts
45
Parts = 150
40
35
30
25
20
15
10
5
1.
23
0
1.
22
4
1.
21
8
1.
21
2
1.
20
6
1.
20
0
1.
19
4
1.
18
8
1.
18
2
1.
17
6
1.
17
0
0
Voltage (V)
DS41249E-page 184
© 2008 Microchip Technology Inc.
PIC16F785/HV785
FIGURE 20-44:
TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C)
Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C)
90
Number of Parts
80
Parts = 150
70
60
50
40
30
20
10
30
1.
2
24
1.
2
18
1.
2
12
1.
2
06
1.
2
00
1.
2
94
1.
1
88
1.
1
82
1.
1
76
1.
1
1.
1
70
0
Voltage (V)
FIGURE 20-45:
TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 85°C)
Typical VP6 Reference Voltage Distribution (VDD=5V, 85×C)
70
Number of Parts
60
Parts = 150
50
40
30
20
10
0
1.
23
4
1.
22
8
1.
21
2
1.
21
6
1.
20
0
1.
20
4
1.
19
8
1.
18
1.
18
2
6
1.
17
1.
17
0
0
Voltage (V)
© 2008 Microchip Technology Inc.
DS41249E-page 185
PIC16F785/HV785
FIGURE 20-46:
TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C)
Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C)
40
Number of Parts
35
Parts = 150
30
25
20
15
10
5
1.
23
0
1.
22
4
1.
21
8
1.
21
2
1.
20
6
1.
20
0
1.
19
4
1.
18
8
1.
18
2
1.
17
6
1.
17
0
0
Voltage (V)
FIGURE 20-47:
TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, -40°C)
30
Parts = 150
25
20
15
10
5
6
23
1.
0
23
1.
4
22
1.
8
21
1.
2
21
1.
6
20
1.
0
20
1.
4
19
1.
8
18
1.
2
18
1.
17
1.
17
1.
6
0
0
Number of Parts
35
Voltage (V)
DS41249E-page 186
© 2008 Microchip Technology Inc.
PIC16F785/HV785
21.0
PACKAGING INFORMATION
21.1
Package Marking Information
The following sections give the technical details of the packages.
20-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
20-Lead SOIC (.300”)
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
PIC16F785-I/P
0810017
Example
PIC16F785
-E/SO
0810017
YYWWNNN
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
20-Lead QFN
16F785
-I/ML
0810017
YWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
*
PIC16F785
-I/SS
0810017
Example
XXXXXXX
XXXXXXX
Note:
Example
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
© 2008 Microchip Technology Inc.
DS41249E-page 187
PIC16F785/HV785
3&'!&"&
4#*!(
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DS41249E-page 188
© 2008 Microchip Technology Inc.
PIC16F785/HV785
! ! "#$%& !'
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© 2008 Microchip Technology Inc.
DS41249E-page 189
PIC16F785/HV785
()* !
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3&'!&"&
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b
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DS41249E-page 190
© 2008 Microchip Technology Inc.
PIC16F785/HV785
+,#
*-./0/0%1+,
3&'!&"&
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D
D2
EXPOSED
PAD
e
E2
2
E
b
2
1
1
K
N
N
NOTE 1
TOP VIEW
L
BOTTOM VIEW
A
A1
A3
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© 2008 Microchip Technology Inc.
DS41249E-page 191
PIC16F785/HV785
3&'!&"&
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DS41249E-page 192
© 2008 Microchip Technology Inc.
PIC16F785/HV785
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A
APPENDIX B:
MIGRATING FROM
OTHER PIC®
DEVICES
This is a new data sheet.
This discusses some of the issues in migrating from the
PIC16F684 PIC® device to the PIC16F785/HV785.
Revision B
B.1
Updates throughout document.
TABLE B-1:
Revision C
Revised part number to include “HV785”; Added PWM
Setup Example; Added Voltage Regulator secton.
Revision D
PIC16F684 to PIC16F785/HV785
FEATURE COMPARISON
Feature
PIC16F684
PIC16F785
Max Operating
Speed
20 MHz
20 MHz
Max Program
Memory (Words)
2048
2048
SRAM (bytes)
128
128
Revised VROUT min./max. limits in Table 19-9.
A/D Resolution
10-bit
10-bit
Revision E
Data EEPROM
(bytes)
256
256
Timers (8/16-bit)
2/1
2/1
Adding Characterization Data and small updates and
reformatting.
Oscillator modes
8
8
Brown-out Reset
Y
Y
Internal Pull-ups
RA0/1/2/4/5
MCLR
RA0/1/2/3/4/5
MCLR
Interrupt-on-change
RA0/1/2/3/4/5 RA0/1/2/3/4/5
Comparator
© 2008 Microchip Technology Inc.
2
CCP
ECCP
Y
Op Amps
N
2
PWM
N
Two-Phase
Ultra Low-Power
Wake-up
Y
N
Extended WDT
Y
Y
Software Control
Option of WDT/BOR
Y
Y
INTOSC Frequencies
32 kHz 8 MHz
32 kHz 8 MHz
Clock Switching
Y
Y
DS41249E-page 193
PIC16F785/HV785
NOTES:
DS41249E-page 194
© 2008 Microchip Technology Inc.
PIC16F785/HV785
INDEX
A
A/D ...................................................................................... 79
Acquisition Requirements ........................................... 86
Analog Port Pins ......................................................... 80
Associated Registers .................................................. 89
Block Diagram............................................................. 79
Calculating Acquisition Time....................................... 86
Channel Selection....................................................... 80
Configuration and Operation....................................... 80
Configuring.................................................................. 85
Configuring Interrupt ................................................... 85
Conversion Clock........................................................ 80
Effects of Reset........................................................... 89
Internal Sampling Switch (Rss) Impedance ................ 86
Operation During Sleep .............................................. 88
Output Format............................................................. 81
Reference Voltage (VREF)........................................... 80
Source Impedance...................................................... 86
Special Event Trigger.................................................. 89
Specifications............................................ 159, 160, 161
Starting a Conversion ................................................. 81
Using the ECCP Trigger ............................................. 89
Absolute Maximum Ratings .............................................. 141
AC Characteristics
Load Conditions ........................................................ 150
ADCON0 Register............................................................... 83
ADCON1 Register............................................................... 84
Analog-to-Digital Converter. See A/D
ANSEL Register .................................................... 93, 94, 101
ANSEL0 Register ................................................................ 82
ANSEL1 Register ................................................................ 82
Assembler
MPASM Assembler................................................... 138
B
Block Diagrams
(CCP) Capture Mode Operation ................................. 58
A/D .............................................................................. 79
Analog Input Model ..................................................... 87
CCP PWM................................................................... 60
Clock Source............................................................... 23
Comparator 1 .............................................................. 64
Comparator 2 .............................................................. 66
Compare ..................................................................... 58
CVref........................................................................... 71
Fail-Safe Clock Monitor (FSCM) ................................. 31
In-Circuit Serial Programming Connections.............. 125
Interrupt Logic ........................................................... 118
On-Chip Reset Circuit ............................................... 109
OPA Module................................................................ 75
PIC16F785/HV785........................................................ 5
RA0 Pin....................................................................... 38
RA1 Pin....................................................................... 38
RA2 Pin....................................................................... 39
RA3 Pin....................................................................... 39
RA4 Pin....................................................................... 40
RA5 Pin....................................................................... 40
RB4 and RB5 Pins ...................................................... 43
RB6 Pin....................................................................... 43
RB7 Pin....................................................................... 43
RC0 and RC1 Pins...................................................... 43
RC0, RC6 and RC7 Pins ............................................ 46
RC1 Pin....................................................................... 46
© 2008 Microchip Technology Inc.
RC2 and RC3 Pins ..................................................... 47
RC4 Pin ...................................................................... 47
RC5 Pin ...................................................................... 48
Resonator Operation .................................................. 25
Timer1 ........................................................................ 51
Timer2 ........................................................................ 56
TMR0/WDT Prescaler ................................................ 49
Two Phase PWM
Complementary Output Mode .......................... 101
Simplified Diagram ............................................. 92
Single Phase Example ....................................... 98
VR Reference ............................................................. 74
Watchdog Timer (WDT)............................................ 121
Brown-out Reset (BOR).................................................... 110
Associated Registers................................................ 112
Calibration ................................................................ 111
Specifications ........................................................... 154
Timing and Characteristics ....................................... 154
C
C Compilers
MPLAB C18.............................................................. 138
MPLAB C30.............................................................. 138
Capture Module. See Capture/Compare/PWM (CCP)
Capture/Compare/PWM (CCP) .......................................... 57
Associated Registers.................................................. 62
Associated Registers w/ Capture/Compare/Timer1 ... 59
Capture Mode............................................................. 58
CCP1 Pin Configuration ............................................. 58
Compare Mode........................................................... 58
CCP1 Pin Configuration ..................................... 59
Software Interrupt Mode ..................................... 59
Special Event Trigger and A/D Conversions ...... 59
Timer1 Mode Selection....................................... 59
Prescaler .................................................................... 58
PWM Mode................................................................. 60
Duty Cycle .......................................................... 61
Effects of Reset .................................................. 62
Example PWM Frequencies and Resolutions .... 61
Operation in Power Managed Modes ................. 62
Operation with Fail-Safe Clock Monitor .............. 62
Setup for Operation ............................................ 62
Setup for PWM Operation .................................. 62
Specifications ........................................................... 156
Timer Resources ........................................................ 57
CCP. See Capture/Compare/PWM (CCP)
CCP1CON Register............................................................ 57
CCPR1H Register............................................................... 57
CCPR1L Register ............................................................... 57
Clock Sources..................................................................... 23
CM1CON0 .......................................................................... 65
CM2CON1 .......................................................................... 68
Code Examples
Assigning Prescaler to Timer0.................................... 50
Assigning Prescaler to WDT....................................... 50
Changing Between Capture Prescalers ..................... 58
Data EEPROM Read................................................ 105
Data EEPROM Write ................................................ 105
EEPROM Write Verify .............................................. 105
Indirect Addressing..................................................... 22
Initializing A/D............................................................. 85
Initializing PORTA ...................................................... 35
Initializing PORTB ...................................................... 42
Initializing PORTC ...................................................... 45
DS41249E-page 195
PIC16F785/HV785
Interrupt Context Saving ........................................... 120
Code Protection ................................................................ 124
Comparator Module ............................................................ 63
Associated Registers .................................................. 74
C1 Output State Versus Input Conditions ................... 63
C2 Output State Versus Input Conditions ................... 66
Comparator Interrupts ................................................. 69
Effects of Reset........................................................... 69
Comparator Voltage Reference (CVREF)
Specifications ............................................................ 157
Comparators
C2OUT as T1 Gate ..................................................... 52
Specifications ............................................................ 157
Compare Module. See Capture/Compare/PWM (CCP)
CONFIG Register.............................................................. 108
Configuration Bits.............................................................. 107
Customer Change Notification Service ............................. 201
Customer Notification Service........................................... 201
Customer Support ............................................................. 201
D
Data EEPROM Memory
Associated Registers ................................................ 106
Code Protection ................................................ 103, 106
Data Memory......................................................................... 9
DC and AC Characteristics
Graphs and Tables ................................................... 163
DC Characteristics
Extended and Industrial ............................................ 148
Industrial and Extended ............................................ 143
Development Support ....................................................... 137
Device Overview ................................................................... 5
E
EEADR Register ............................................................... 103
EECON1 Register ............................................................. 104
EECON2 Register ............................................................. 104
EEDAT Register................................................................ 103
EEPROM Data Memory
Avoiding Spurious Write............................................ 105
Reading..................................................................... 105
Write Verify ............................................................... 105
Writing ....................................................................... 105
Effects of Reset
A/D module ................................................................. 89
Comparator module .................................................... 69
OPA module................................................................ 77
PWM mode ................................................................. 62
Electrical Specifications .................................................... 141
Errata .................................................................................... 4
F
Fail-Safe Clock Monitor....................................................... 31
Fail-Safe Condition Clearing ....................................... 32
Reset and Wake-up from Sleep .................................. 32
Firmware Instructions........................................................ 127
Fuses. See Configuration Bits
G
General Purpose Register File.............................................. 9
I
ID Locations ...................................................................... 124
In-Circuit Debugger ........................................................... 125
In-Circuit Serial Programming (ICSP) ............................... 124
Indirect Addressing, INDF and FSR Registers.................... 22
DS41249E-page 196
Instruction Format............................................................. 127
Instruction Set................................................................... 127
ADDLW..................................................................... 129
ADDWF..................................................................... 129
ANDLW..................................................................... 129
ANDWF..................................................................... 129
MOVF ....................................................................... 132
RRF .......................................................................... 133
SLEEP ...................................................................... 133
SUBLW ..................................................................... 134
SUBWF..................................................................... 134
SWAPF ..................................................................... 134
TRIS ......................................................................... 134
XORLW .................................................................... 134
XORWF .................................................................... 135
BCF .......................................................................... 129
BSF........................................................................... 129
BTFSC ...................................................................... 130
BTFSS ...................................................................... 130
CALL......................................................................... 130
CLRF ........................................................................ 130
CLRW ....................................................................... 130
CLRWDT .................................................................. 130
COMF ....................................................................... 131
DECF ........................................................................ 131
DECFSZ ................................................................... 131
GOTO ....................................................................... 131
INCF ......................................................................... 131
INCFSZ..................................................................... 131
IORLW ...................................................................... 132
IORWF...................................................................... 132
MOVLW .................................................................... 132
MOVWF .................................................................... 132
NOP .......................................................................... 132
RETFIE ..................................................................... 133
RETLW ..................................................................... 133
RETURN................................................................... 133
RLF ........................................................................... 133
Summary Table ........................................................ 128
INTCON Register................................................................ 17
Internal Oscillator Block
INTOSC
Specifications ................................................... 153
Internal Sampling Switch (Rss) Impedance........................ 86
Internet Address ............................................................... 201
Interrupts........................................................................... 117
(CCP) Compare .......................................................... 58
A/D.............................................................................. 85
Associated Registers ................................................ 119
Comparator................................................................. 69
Context Saving ......................................................... 120
Data EEPROM Memory Write .................................. 104
Interrupt-on-Change ................................................... 37
Oscillator Fail (OSF) ................................................... 31
PORTA Interrupt-on-change..................................... 118
RA2/INT .................................................................... 118
TMR0 ........................................................................ 118
TMR1 .......................................................................... 52
TMR2 to PR2 Match ............................................. 55, 56
INTOSC Specifications ..................................................... 153
IOCA (Interrupt-on-Change) ............................................... 37
IOCA Register..................................................................... 37
L
Load Conditions................................................................ 150
© 2008 Microchip Technology Inc.
PIC16F785/HV785
M
MCLR ................................................................................ 110
Internal ...................................................................... 110
.............................................................................................. 9
Data .............................................................................. 9
Data EEPROM Memory............................................ 103
Program ........................................................................ 9
.......................................... 201, 193, 138, 139, 137, 139, 138
O
OPA2CON Register ............................................................ 76
OPCODE Field Descriptions ............................................. 127
Operational Amplifier (OPA) Module
AC Specifications.............................................. 158, 159
Associated Registers .................................................. 77
DC Specifications...................................................... 158
OPTION_REG Register ...................................................... 17
OSCCON Register .............................................................. 33
Oscillator
Associated Registers .................................................. 34
Oscillator Specifications .................................................... 151
Oscillator Start-up Timer (OST)
Specifications............................................................ 154
Oscillator Switching
Fail-Safe Clock Monitor............................................... 31
Two-Speed Clock Start-up.......................................... 30
OSCTUNE
Oscillator Tuning Register (Address 90h) ................... 28
P
Packaging ......................................................................... 187
PCL and PCLATH ............................................................... 21
Stack ........................................................................... 21
PCON
Power Control Register (Address
8Eh) .................................................................... 20
PCON Register ................................................................. 112
PICSTART Plus Development Programmer ..................... 140
PIE1 Register ...................................................................... 18
Pin Diagram ...................................................................... 2, 3
Pinout Descriptions
PIC16F684.................................................................... 6
PIR1 Register...................................................................... 19
PORTA................................................................................ 35
Additional Pin Functions ............................................. 36
Interrupt-on-change ............................................ 37
Weak Pull-up ...................................................... 36
Associated Registers .................................................. 41
Pin Descriptions and Diagrams................................... 38
RA0 ............................................................................. 38
RA1 ............................................................................. 38
RA2 ............................................................................. 39
RA3 ............................................................................. 39
RA4 ............................................................................. 40
RA5 ............................................................................. 40
Specifications............................................................ 152
PORTB................................................................................ 42
Associated Registers .................................................. 44
Pin Descriptions and Diagrams................................... 43
RB4 ............................................................................. 43
RB5 ............................................................................. 43
RB6 ............................................................................. 43
RB7 ............................................................................. 43
PORTC ............................................................................... 45
Associated Registers ............................................ 34, 48
© 2008 Microchip Technology Inc.
Pin Descriptions and Diagrams .................................. 46
RC0 ............................................................................ 46
RC1 ............................................................................ 46
RC2 ............................................................................ 47
RC3 ............................................................................ 47
RC4 ............................................................................ 47
RC5 ............................................................................ 48
RC6 ............................................................................ 46
RC7 ............................................................................ 46
Specifications ........................................................... 152
Power-Down Mode (Sleep)............................................... 123
Power-up Timer (PWRT) .................................................. 110
Specifications ........................................................... 154
Power-up Timing Delays................................................... 112
Precision Internal Oscillator Parameters .......................... 153
Prescaler
Shared WDT/Timer0................................................... 50
Switching Prescaler Assignment ................................ 50
Program Memory .................................................................. 9
Map and Stack.............................................................. 9
Programming, Device Instructions.................................... 127
PWM. See Two Phase PWM
PWMCLK Register.............................................................. 94
PWMCON0 Register........................................................... 93
PWMCON1 Register......................................................... 101
PWMPH1 Register.............................................................. 95
PWMPH2 Register.............................................................. 96
R
Reader Response............................................................. 202
Read-Modify-Write Operations ......................................... 127
REFCON (VR Control)........................................................ 73
Register
INTCON INTERRUPT CONTROL REGISTER (ADDRESS
0Bh, 8Bh, 10Bh or 183h) .................................... 17
IOCA (Interrupt-on-Change) ....................................... 37
WPUA (Weak Pull-up PORTA)................................... 36
Registers
ADCON0 (A/D Control 0)............................................ 83
ADCON1 (A/D Control 1)............................................ 84
ANSEL (Analog Select) ................................ 93, 94, 101
ANSEL0 (Analog Select 0) ......................................... 82
ANSEL1 (Analog Select 1) ......................................... 82
CCP1CON (CCP Operation) ...................................... 57
CCPR1H..................................................................... 57
CCPR1L ..................................................................... 57
CM1CON0 (C1 Control) ............................................. 65
CM1CON0 (C2 Control)
CM2CON0 .......................................................... 67
CM2CON1 (C2 Control) ............................................. 68
CONFIG (Configuration Word) ................................. 108
Data Memory Map ...................................................... 10
EEADR (EEPROM Address) .................................... 103
EECON1 (EEPROM Control 1) ................................ 104
EECON2 (EEPROM Control 2) ................................ 104
EEDAT (EEPROM Data) .......................................... 103
INTCON (Interrupt Control) ........................................ 17
IOCA (Interrupt-on-Change PORTA).......................... 37
Op Amp 2 Control Register (OPA2CON) ................... 76
OPTION_REG
OPTION REGISTER .......................................... 16
OPTION_REG (Option) .............................................. 17
OSCCON (Oscillator Control)..................................... 33
PCON (Power Control) ............................................. 112
PIE1 (Peripheral Interrupt Enable 1) .......................... 18
DS41249E-page 197
PIC16F785/HV785
PIR1 (Peripheral Interrupt Register 1) ........................ 19
PORTA........................................................................ 35
PORTB........................................................................ 42
PORTC ....................................................................... 45
PWMCLK (PWM Clock Control) ................................. 94
PWMCON0 (PWM Control 0) ..................................... 93
PWMCON1 (PWM Control 1) ................................... 101
PWMPH1 (PWM Phase 1 control) .............................. 95
PWMPH2 (PWM Phase 2 control) .............................. 96
REFCON (VR Control) ................................................ 73
Reset Values............................................................. 114
Reset Values (Special Registers) ............................. 116
Special Function Registers ........................................... 9
Special Register Summary ............................. 12, 13, 14
STATUS ...................................................................... 15
Status .................................................................. 16, 109
T1CON (Timer1 Control)............................................. 53
T2CON (Timer2 Control)............................................. 55
TRISA (Tri-State PORTA) ........................................... 36
TRISB (Tri-State PORTB) ........................................... 42
TRISC (Tri-state PORTC) ........................................... 45
WDTCON (Watchdog Timer Control)........................ 122
WPUA (Weak Pull-up PORTA) ................................... 36
Resets ............................................................................... 109
Power-On Reset ....................................................... 110
Revision History ................................................................ 193
RRF Instruction ................................................................. 133
S
SLEEP
Instruction ................................................................. 133
Power-Down Mode ................................................... 123
Wake-Up ................................................................... 123
Wake-Up Using Interrupts......................................... 123
Software Simulator (MPLAB SIM)..................................... 138
Special Event Trigger.......................................................... 89
Special Function Registers ................................................... 9
Specifications .................................................................... 158
STATUS Register................................................................ 15
Status Register............................................................ 16, 109
SUBLW Instruction............................................................ 134
SUBWF Instruction............................................................ 134
SWAPF Instruction............................................................ 134
T
Time-out Sequence........................................................... 112
Timer0 ................................................................................. 49
Associated Registers .................................................. 50
External Clock ............................................................. 50
Interrupt....................................................................... 49
Operation .................................................................... 49
Prescaler ..................................................................... 50
Specifications ............................................................ 155
Timer1 ................................................................................. 51
Associated Registers .................................................. 54
Asynchronous Counter Mode ..................................... 54
Reading and Writing ........................................... 54
Interrupt....................................................................... 52
Modes of Operations................................................... 52
Operation During Sleep .............................................. 54
Oscillator ..................................................................... 54
Prescaler ..................................................................... 52
Specifications ............................................................ 155
DS41249E-page 198
Timer1 Gate
Inverting Gate ..................................................... 52
Selecting Source ................................................ 52
TMR1H Register ......................................................... 51
TMR1L Register.......................................................... 51
Timer2................................................................................. 55
Associated Registers .................................................. 56
Operation .................................................................... 55
Postscaler ................................................................... 55
PR2 Register .............................................................. 55
Prescaler .................................................................... 55
TMR2 Register............................................................ 55
TMR2 to PR2 Match Interrupt............................... 55, 56
Timing Diagrams
A/D Conversion......................................................... 160
A/D Conversion (Sleep Mode) .................................. 161
Brown-out Reset (BOR)............................................ 154
Brown-out Reset Situations ...................................... 111
Capture/Compare/PWM (CCP) ................................ 156
CLKOUT and I/O ...................................................... 152
External Clock........................................................... 151
Fail-Safe Clock Monitor (FSCM)................................. 32
INT Pin Interrupt ....................................................... 119
Reset, WDT, OST and Power-up Timer ................... 153
Time-out Sequence
Case 1 .............................................................. 113
Case 2 .............................................................. 113
Case 3 .............................................................. 113
Timer0 and Timer1 External Clock ........................... 155
Timer1 Incrementing Edge ......................................... 52
Two Phase PWM
Complementary Output .................................... 102
Start-up............................................................... 97
Two Speed Start-up.................................................... 31
Two-Phase PWM
Auto-Shutdown ................................................... 97
Wake-up from Interrupt............................................. 124
Timing Parameter Symbology .......................................... 150
TRIS Instruction ................................................................ 134
TRISA Register................................................................... 36
TRISB Register................................................................... 42
TRISC Register................................................................... 45
Two Phase PWM ................................................................ 91
Activating .................................................................... 91
Active Output Level .................................................... 92
Associated Registers ................................................ 102
Auto-shutdown............................................................ 92
Clock Control (PWMCLK) ........................................... 94
Control Register 0 (PWMCON0)................................. 93
Control Register 1 (PWMCON1)............................... 101
Master/Slave Operation .............................................. 91
Output Blanking .......................................................... 91
Phase 1 Control (PWMPH1)....................................... 95
Phase 2 Control (PWMPH1)....................................... 96
PWM Duty Cycle......................................................... 91
PWM Frequency ......................................................... 91
PWM Period................................................................ 91
PWM Phase................................................................ 91
PWM Phase Resolution.............................................. 91
Shutdown.................................................................... 92
Two-Phase PWM
Dead Time Delay ...................................................... 158
Two-Speed Clock Start-up Mode........................................ 30
© 2008 Microchip Technology Inc.
PIC16F785/HV785
V
Voltage Reference (VR)
Specifications............................................................ 157
Voltage Reference Output (VREF) BUFFER
Specifications............................................................ 157
Voltage References ............................................................ 70
Associated Registers .................................................. 74
Configuring CVref ....................................................... 70
CVref (Comparator Reference)................................... 70
CVref Accuracy ........................................................... 70
Fixed VR reference ..................................................... 73
VR Stabilization........................................................... 74
VREF. SEE A/D Reference Voltage
W
Wake-up Using Interrupts ................................................. 123
Watchdog Timer (WDT) .................................................... 121
Associated Registers ................................................ 122
Clock Source............................................................. 121
Modes ....................................................................... 121
Period........................................................................ 121
Specifications............................................................ 154
WDTCON Register ........................................................... 122
WPUA (Weak Pull-up PORTA) ........................................... 36
WPUA Register ................................................................... 36
WWW Address.................................................................. 201
WWW, On-Line Support ....................................................... 4
X
XORLW Instruction ........................................................... 134
XORWF Instruction ........................................................... 135
© 2008 Microchip Technology Inc.
DS41249E-page 199
PIC16F785/HV785
NOTES:
DS41249E-page 200
© 2008 Microchip Technology Inc.
PIC16F785/HV785
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
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Users of Microchip products can receive assistance
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•
•
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Technical Support
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CUSTOMER CHANGE NOTIFICATION
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Microchip’s customer notification service helps keep
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To register, access the Microchip web site at
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Notification and follow the registration instructions.
© 2008 Microchip Technology Inc.
DS41249E-page 201
PIC16F785/HV785
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
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Device: PIC16F785/HV785
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Literature Number: DS41249E
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41249E-page 202
© 2008 Microchip Technology Inc.
PIC16F785/HV785
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
PIC16F785(1), PIC16HV785(1), PIC16F785T(2),
PIC16HV785T(2);
VDD range 4.2V to 5.5V
PIC16F785(1), PIC16HV785(1), PIC16F785T(2),
PIC16HV785T(2);
VDD range 2.0V to 5.5V
Temperature
Range:
I
E
=
=
-40°C to +85°C Industrial)
-40°C to +125°C Extended)
Package:
ML
P
SO
SS
=
=
=
=
QFN
PDIP
SOIC
SSOP
Pattern:
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2008 Microchip Technology Inc.
PIC16F785 - E/SO 301 = Extended temp.,
SOIC package.
PIC16F785 - I/ML = Industrial temp., QFN
package.
Note 1:
2:
F = Standard Voltage Range
LF = Wide Voltage Range
T = in tape and reel PLCC, and TQFP
packages only.
DS41249E-page 203
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Fax: 31-416-690340
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Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS41249E-page 204
© 2008 Microchip Technology Inc.