MICROCHIP PIC12F752-I-SN

PIC12F752/HV752
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450.
Additional U.S. and foreign patents and applications may be issued or pending.
 2011 Microchip Technology Inc.
Preliminary
DS41576B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-798-0
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41576B-page 2
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
High-Performance RISC CPU:
Peripheral Features:
• Only 35 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
- DC – 20 MHz clock input
- DC – 200 ns instruction cycle
• 1024 x 14 On-chip Flash Program Memory
• Self Read/Write Program Memory
• 64 x 8 General Purpose Registers (SRAM)
• Interrupt Capability
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• 5 I/O Pins and 1 Input-only Pin
• High Current Source/Sink:
- 50 mA I/O, (2 pins)
- 25 mA I/O, (4 pins)
• 2 High-Speed Analog Comparator modules:
- 20 ns response time
- Fixed Voltage Reference (FVR)
- Programmable on-chip voltage reference via
integrated 5-bit DAC
- Internal/external inputs and outputs (selectable)
- Built-in Hysteresis (software selectable)
• A/D Converter:
- 10-bit resolution
- 4 external channels
- 2 internal reference voltage channels
• Dual Range Digital-to-Analog Converter (DAC):
- 5-bit resolution
- Full Range or Limited Range output
- 4 mV steps @ 2.0V (Limited Range)
- 65 mV steps @ 2.0V (Full Range)
• Fixed Voltage Reference (FVR), 1.2V reference
• Capture, Compare, PWM (CCP) module:
- 16-bit Capture, max. resolution = 12.5 ns
- Compare, max. resolution = 200 ns
- 10-bit PWM, max. frequency = 20 kHz
• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- 16-bit Timer/Counter with Prescaler
- External Timer1 Gate (count enable)
- 4 Selectable Clock sources
• Timer2: 8-Bit Timer/Counter with Prescaler
- 8-Bit Period Register and Postscaler
• Hardware Limit Timer (HLT):
- 8-bit Timer with Prescaler
- 8-bit period register and postscaler
- Asynchronous H/W Reset sources
• Complementary Output Generator (COG):
- Complementary Waveforms from selectable
sources
- 2 I/O (50 mA) for direct MOSFET drive
- Rising and/or Falling edge dead-band control
- Phase control, Blanking control
- Auto-shutdown
Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency:
8 MHz, 4 MHz, 1 MHz or 31 kHz
- Software tunable
• Power-Saving Sleep mode
• Voltage Range (PIC12F752):
- 2.0V to 5.5V
• Shunt Voltage Regulator (PIC12HV752)
- 2.0V to user defined
- 5 volt regulation
- 4 mA to 50 mA shunt range
• Multiplexed Master Clear with Pull-up/Input Pin
• Interrupt-on-Change Pins
• Individually Programmable Weak Pull-ups
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Watchdog Timer (WDT) with Internal Oscillator for
Reliable Operation
• Industrial and Extended Temperature Range
• High Endurance Flash:
- 100,000 write Flash endurance
- Flash retention: >40 years
• Programmable Code Protection
• In-Circuit Debug (ICD) via Two Pins
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
Low-Power Features:
• Standby Current:
- 50 nA @ 2.0V, typical
• Operating Current:
- 11 uA @ 32 kHz, 2.0V, typical
- 260 uA @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
• <1 uA @ 2.0V, typical
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 3
PIC12F752/HV752
4
2
3/1
1
Y
N
6
4
2
3/1
1
Y
Y
Note:
DS41576B-page 4
I/Os
SRAM
(bytes)
8-PIN DIAGRAM, PIC12F752/HV752 (PDIP, SOIC, DFN)
VDD
1
RA5
2
RA4
3
MCLR/VPP/RA3
4
PIC12F752/HV752
FIGURE 1:
CCP
6
64
Timers
8/16-bit
64
Y
Comparators
Y
1024
10-bit A/D (ch)
1024
PIC12HV752
Self Read/Write
Flash Memory
PIC12F752
Device
Flash
Program
Memory
(User)
(words)
Shunt Regulator
PIC12F752/HV752 FEATURE SUMMARY
Complementary
Output Generator
(COG)
TABLE 1:
8
VSS
7
RA0/ICSPDAT
6
RA1/ICSPCLK
5
RA2
See Table 2 for the location of all peripheral functions.
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
CCP
Interrupts
Pull-up
Complementary
Output
Generator (COG)
AN0
C1IN0+
C2IN0+
—
—
IOC
Y
COG1OUT1(2)
DACOUT
REFOUT
ICSPDAT
RA1
6
AN1
C1IN0C2IN0-
—
—
IOC
Y
—
VREF+
ICSPCLK
RA2(5)
5
AN2
C1OUT
C2OUT
T0CKI CCP1
IOC
INT
Y
COG1OUT0(2)
—
—
RA3(1)
4
—
—
T1G(3)
IOC
Y(4)
COG1FLT(3)
—
MCLR/VPP
(2)
—
Basic
Timers
7
Voltage
Reference
ADC
RA0(5)
Comparators
Pin
PIC12F752/HV752 PIN SUMMARY (PDIP, SOIC, DFN)
I/O
TABLE 2:
(2)
—
IOC
Y
COG1FLT
COG1OUT1(3)
—
CLKOUT
—
IOC
Y
COG1OUT0(3)
—
CLKIN
RA4
3
AN3
C1IN1-
T1G
RA5
2
—
C2IN1-
T1CKI
—
1
—
—
—
—
—
—
—
—
VDD
—
8
—
—
—
—
—
—
—
—
VSS
*
Note 1:
2:
3:
4:
5:
Alternate pin function.
Input only.
Default pin function via the APFCON register.
Alternate pin function via the APFCON register.
RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.
The port pins for the primary COG1OUTx pins have High Power (HP) output drivers.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 5
PIC12F752/HV752
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 9
2.0 Memory Organization ................................................................................................................................................................ 11
3.0 Flash Program Memory Self Read/Self Write Control ............................................................................................................... 29
4.0 Oscillator Module ....................................................................................................................................................................... 39
5.0 I/O Ports .................................................................................................................................................................................... 45
6.0 Timer0 Module .......................................................................................................................................................................... 55
7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57
8.0 Timer2 Module .......................................................................................................................................................................... 69
9.0 Hardware Limit Timer (HLT) Module ......................................................................................................................................... 73
10.0 Capture/Compare/PWM Modules ............................................................................................................................................. 77
11.0 Complementary Output Generator (COG) Module .................................................................................................................... 85
12.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 101
13.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 113
14.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................. 115
15.0 Comparator Module ................................................................................................................................................................. 121
16.0 Instruction Set Summary ......................................................................................................................................................... 131
17.0 Special Features of the CPU ................................................................................................................................................... 141
18.0 Shunt Regulator (PIC12HV752 Only) ...................................................................................................................................... 161
19.0 Development Support .............................................................................................................................................................. 163
20.0 Electrical Specifications ........................................................................................................................................................... 167
21.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 191
22.0 Packaging Information ............................................................................................................................................................. 193
Index ................................................................................................................................................................................................. 207
The Microchip Web Site .................................................................................................................................................................... 207
Customer Change Notification Service ............................................................................................................................................. 207
Customer Support ............................................................................................................................................................................. 207
Reader Response ............................................................................................................................................................................. 208
Product Identification System ............................................................................................................................................................ 209
DS41576B-page 6
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TO OUR VALUED CUSTOMERS
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 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 7
PIC12F752/HV752
NOTES:
DS41576B-page 8
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
1.0
DEVICE OVERVIEW
Block Diagrams and pinout descriptions of the devices
are in Figure 1-1 and Table 1-1.
The PIC12F752/HV752 devices are covered by this
data sheet. They are available in 8-pin PDIP, SOIC and
DFN packages.
FIGURE 1-1:
PIC12F752/HV752 BLOCK DIAGRAM
INT
Configuration
13
Flash
1K X 14
Program
Memory
Program
Bus
8
Data Bus
Program Counter
PORTA
RA0
RA1
RA2
RAM
64 Bytes
File
Registers
8-Level Stack
(13-Bit)
14
RAM Addr
RA3
RA4
RA5
9
Addr MUX
Instruction Reg
Direct Addr
7
Indirect
Addr
8
FSR Reg
STATUS Reg
8
3
CLKIN
Instruction
Decode &
Control
Power-up
Timer
Timing
Generation
Watchdog
Timer
MUX
ALU
Power-on
Reset
8
W Reg
Capture/
Compare/
PWM
(CCP)
Shunt Regulator
(PIC12HV752 only)
Hardware
Limit
Timer1
(HLT)
Brown-out
Reset
CLKOUT
Internal
Oscillator
Block
MCLR
T1G
VDD
VSS
T1CKI
T0CKI
Timer0
Fixed Voltage
Reference
(FVR)
Timer1
Dual Range
DAC
Timer2
Complementary
Output
Generator
(COG)
Analog Comparator
and Reference
C1IN0+/C2IN0+
C1IN0-/C2IN0C1IN1C2IN1C1OUT/C2OUT
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 9
PIC12F752/HV752
TABLE 1-1:
PIC12F752/HV752 PINOUT DESCRIPTION
Name
Function
RA0
RA0/COG1OUT1(2)/C1IN0+/
C2IN0+/AN0/DACOUT/
COG1OUT1
REFOUT/
C1IN0+
ICSPDAT
C2IN0+
RA1/C1IN0-/C2IN0-/AN1/
VREF+/ICSPCLK
RA2/INT/CCP1/C2OUT/
C1OUT/T0CKI/
COG1OUT0(2)/AN2
RA3(1)/T1G(3)/COG1FLT(3)/
VPP/MCLR(4)
RA4/T1G(2)/COG1OUT1(3)/
COG1FLT(2)/C1IN1-/AN3/
CLKOUT
RA5/T1CKI/COG1OUT0(3)/
C2IN1-/CLKIN
Input
Type
Output
Type
TTL
HP
General purpose I/O with IOC and WPU.
—
HP
COG output channel 1.
AN
—
Comparator C1 positive input.
Comparator C2 positive input.
Description
AN
—
AN0
AN
—
A/D Channel 0 input.
DACOUT
—
AN
DAC unbuffered Voltage Reference output.
DAC/FVR buffered Voltage Reference output.
REFOUT
—
AN
ICSPDAT
ST
HP
RA1
TTL
CMOS
C1IN0-
AN
—
Comparator C1 negative input.
C2IN0-
AN
—
Comparator C2 negative input.
Serial Programming Data I/O.
General purpose I/O with IOC and WPU.
AN1
AN
—
A/D Channel 1 input.
VREF+
AN
—
A/D Positive Voltage Reference input.
ICSPCLK
ST
—
Serial Programming Clock.
RA2
ST
HP
General purpose I/O with IOC and WPU.
INT
ST
—
External interrupt.
CCP1
ST
HP
Capture/Compare/PWM 1.
C2OUT
—
HP
Comparator C2 output.
C1OUT
—
HP
Comparator C1 output.
T0CKI
ST
—
Timer0 clock input.
COG1OUT0
—
HP
COG output channel 0.
AN2
AN
—
A/D Channel 2 input.
RA3
TTL
—
General purpose input with WPU.
T1G
ST
—
Timer1 Gate input.
COG1FLT
ST
—
COG auto-shutdown fault input.
Programming voltage.
VPP
HV
—
MCLR
ST
—
RA4
TTL
CMOS
T1G
ST
—
COG1OUT1
—
CMOS
COG1FLT
ST
—
COG auto-shutdown fault input.
C1IN1-
AN
—
Comparator C1 negative input.
AN3
AN
—
A/D Channel 3 input.
Master Clear w/internal pull-up.
General purpose I/O with IOC and WPU.
Timer1 Gate input.
COG output channel 1
CLKOUT
—
CMOS
FOSC/4 output.
RA5
TTL
CMOS
General purpose I/O with IOC and WPU.
T1CKI
ST
—
COG1OUT0
—
CMOS
Timer1 clock input.
C2IN1-
AN
—
Comparator C2 negative input.
External Clock input (EC mode).
COG output channel 0.
CLKIN
ST
—
VDD
VDD
Power
—
Positive supply.
VSS
VSS
Power
—
Ground reference.
Legend: AN = Analog input or output
CMOS = CMOS compatible input or output
TTL = TTL compatible input
ST
= Schmitt Trigger input with CMOS levels
HP = High Power
HV
= High Voltage
* Alternate pin function.
Note 1: Input only.
2: Default pin function via the APFCON register.
3: Alternate pin function via the APFCON register.
4: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.
DS41576B-page 10
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
2.0
MEMORY ORGANIZATION
2.1
Program Memory Organization
2.2
The PIC12F752/HV752 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. Only the first 1K x 14 (0000h-03FFh) is
physically implemented. Accessing a location above
these boundaries will cause a wrap-around within the
first 1K x 14 space for PIC12F752/HV752. The Reset
vector is at 0000h and the interrupt vector is at 0004h
(see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F752/HV752
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Data Memory Organization
The data memory (see Figure 2-2) is partitioned into four
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-6Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. Register locations 70h-7Fh in Bank 0 are
Common RAM and shared as the last 16 addresses in
all Banks. All other RAM is unimplemented and returns
‘0’ when read. The RP<1:0> bits of the STATUS register
are the bank select bits.
RP1
RP0
0
0
 Bank 0 is selected
0
1
 Bank 1 is selected
1
0
 Bank 2 is selected
1
1
 Bank 3 is selected
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
03FFh
0400h
Wraps to 0000h-03FFh
1FFFh
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 11
PIC12F752/HV752
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC12F752/HV752. Each register is accessed, either
directly or indirectly, through the File Select Register
(FSR) (see Section 2.4 “Indirect Addressing, INDF
and FSR Registers”).
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
DS41576B-page 12
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
FIGURE 2-2:
DATA MEMORY MAP OF THE PIC12F752/HV752
BANK 0
INDF
TMR0
PCL
STATUS
FSR
PORTA
—
—
IOCAF
—
PCLATH
INTCON
PIR1
PIR2
—
TMR1L
TMR1H
T1CON
T1GCON
CCPR1L
CCPR1H
CCP1CON
—
—
—
—
—
—
ADRESL
ADRESH
ADCON0
ADCON1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
BANK 1
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
—
—
IOCAP
—
PCLATH
INTCON
PIE1
PIE2
—
OSCCON
FVRCON
DACCON0
DACCON1
—
—
—
—
—
—
—
—
CM2CON0
CM2CON1
CM1CON0
CM1CON1
CMOUT
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BANK 2
INDF
TMR0
PCL
STATUS
FSR
LATA
—
—
IOCAN
—
PCLATH
INTCON
WPUA
SLRCONA
—
PCON
TMR2
PR2
T2CON
HLTMR1
HLTPR1
HLT1CON0
HLT1CON1
—
—
—
—
—
—
—
—
—
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
BANK 3
INDF
OPTION_REG
PCL
STATUS
FSR
ANSELA
—
—
APFCON
OSCTUNE
PCLATH
INTCON
PMCON1
PMCON2
PMADRL
PMADRH
PMDATL
PMDATH
COG1PH
COG1BLK
COG1DB
COG1CON0
COG1CON1
COG1ASD
—
—
—
—
—
—
—
—
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
Unimplemented
General
Purpose
Register
3Fh
40h
48 Bytes
6Fh
Common RAM 70h
7Fh
16 Bytes
Legend:
Unimplemented
Unimplemented
Unimplemented
EFh
16Fh
1EFh
Common RAM F0h
(Accesses
FFh
70h-7Fh)
Common RAM 170h
(Accesses
17Fh
70h-7Fh)
Common RAM 1F0h
(Accesses
1FFh
70h-7Fh)
= Unimplemented data memory locations, read as ‘0’.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 13
PIC12F752/HV752
TABLE 2-1:
Adr
PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOR
Reset
Value on
all other
Resets(1)
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx xxxx xxxx
01h
TMR0
Holding register for the 8-bit TMR0
xxxx xxxx uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
03h
STATUS
04h
FSR
05h
PORTA
06h
—
Unimplemented
—
—
07h
—
Unimplemented
—
—
08h
IOCAF
IRP
RP1
RP0
0000 0000 0000 0000
TO
PD
Z
DC
C
0001 1xxx 000q quuu
RA4
RA3
RA2
RA1
RA0
--xx xxxx --uu uuuu
Indirect Data Memory Address Pointer
09h
—
0Ah
PCLATH
—
—
—
RA5
—
IOCAF5
—
—
—
xxxx xxxx uuuu uuuu
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
Unimplemented
--00 0000 --00 0000
—
Write buffer for upper 5 bits of program counter
—
---0 0000 ---0 0000
0Bh
INTCON
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF(2)
0Ch
PIR1
TMR1GIF
ADIF
—
—
—
HLTMR1IF
TMR2IF
TMR1IF
00---000
0Dh
PIR2
—
—
C2IF
C1IF
—
COG1IF
—
CCP1IF
--00 -0-0 --00 -0-0
0Eh
—
Unimplemented
0Fh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1
10h
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1
11h
T1CON
12h
T1GCON
13h
CCPR1L
Capture/Compare/PWM Register1 Low Byte
14h
CCPR1H
Capture/Compare/PWM Register1 High Byte
15h
CCP1CON
16h
to
1Bh
—
—
TMR1CS<1:0>
TMR1GE
T1GPOL
—
—
T1CKPS<1:0>
T1GTM
T1GSPM
T1SYNC
T1GGO/
DONE
T1GVAL
—
T1GSS<1:0>
0000 00-0 uuuu uu-u
0000 0x00 uuuu uxuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M<3:0>
--00 0000 --00 0000
—
ADRESL
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
1Dh
ADRESH
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
1Eh
ADCON0
ADFM
ADCON1
—
Legend:
Note 1:
2:
TMR1ON
Unimplemented
CHS<3:0>
ADCS<2:0>
—
xxxx xxxx uuuu uuuu
Reserved
DC1B<1:0>
VCFG
00---000
xxxx xxxx uuuu uuuu
1Ch
1Fh
0000 0000 0000 0000
—
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
GO/DONE
ADON
0000 0000 0000 0000
—
—
-000 ---- -000 ----
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the
mismatch exists.
DS41576B-page 14
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 2-2:
Addr
Name
PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOR
Reset
Values on
all other
Resets(1)
Bank 1
80h
INDF
81h
OPTION_REG
Addressing this location uses contents of FSR to address data memory (not a physical register)
RAPU
INTEDG
T0CS
T0SE
PSA
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
PS<2:0>
82h
PCL
83h
STATUS
Program Counter's (PC) Least Significant Byte
84h
FSR
85h
TRISA
86h
—
Unimplemented
—
—
87h
—
Unimplemented
—
—
88h
IOCAP
IRP
RP1
0000 0000 0000 0000
TO
PD
Z
DC
C
0001 1xxx 000q quuu
TRISA4
TRISA3(3)
TRISA2
TRISA1
TRISA0
--11 1111 --11 1111
RP0
Indirect Data Memory Address Pointer
—
—
—
TRISA5
—
IOCAP5
—
—
xxxx xxxx uuuu uuuu
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
89h
—
8Ah
PCLATH
8Bh
INTCON
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF(2)
0000 0000 0000 0000
8Ch
PIE1
TMR1GIE
ADIE
—
—
—
HLTMR1IE
TMR2IE
TMR1IE
00-- -000 00-- -000
8Dh
PIE2
—
—
C2IE
C1IE
—
COG1IE
—
CCP1IE
--00 -0-0 --00 -0-0
8Eh
8Fh
—
OSCCON
HTS
LTS
90h
—
—
—
—
—
—
91h
92h
—
—
93h
to
9Ah
Unimplemented
--00 0000 --00 0000
—
—
FVRCON
—
FVRRDY
DACCON0
DACCON1
DACEN
—
DACRNG
—
IRCF<1:0>
FVRBUFEN
FVRBUFSS
DACOE
—
—
—
DACPSS0
DACR<4:0>
—
---0 0000 ---0 0000
Unimplemented
—
FVREN
—
Write buffer for upper 5 bits of program counter
Unimplemented
—
—
--01 -00- --uu -uu0000 ---- 0000 ---000- -0-- 000- -0----0 0000 ---0 0000
—
—
9Bh
CM2CON0
C2ON
C2OUT
C2OE
C2POL
C2ZLF
C2SP
C2HYS
C2SYNC
0000 0100 0000 0100
9Ch
9Dh
CM2CON1
CM1CON0
C2INTP
C1ON
C2INTN
C1OUT
C2PCH<1:0>
C1OE
C1POL
—
C1ZLF
—
C1SP
—
C1HYS
C2NCH0
C1SYNC
0000 ---0 0000 ---0
0000 0100 0000 0100
9Eh
9Fh
CM1CON1
CMOUT
C1INTP
—
C1INTN
—
C1PCH<1:0>
—
—
—
—
—
—
—
MC2OUT
C1NCH0
MC1OUT
0000 ---0 0000 ---0
---- --00 ---- --00
Legend:
Note 1:
2:
3:
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the
mismatch exists.
TRISA3 always reads ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 15
PIC12F752/HV752
TABLE 2-3:
Adr
PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOR
Reset
Value on
all other
Resets(1)
Bank 2
100h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx xxxx xxxx
101h
TMR0
Holding Register for the 8-bit Timer0 Register
xxxx xxxx uuuu uuuu
102h
PCL
Program Counter's (PC) Least Significant Byte
103h
STATUS
IRP
RP1
RP0
0000 0000 0000 0000
TO
PD
Z
DC
C
0001 1xxx 000q quuu
LATA4
—
LATA2
LATA1
LATA0
--xx -xxx --uu -uuu
104h
FSR
105h
LATA
Indirect Data Memory Address Pointer
106h
—
Unimplemented
—
—
107h
—
Unimplemented
—
—
108h
IOCAN
109h
—
—
—
—
—
LATA5
IOCAN5
xxxx xxxx uuuu uuuu
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
Unimplemented
--00 0000 --00 0000
—
—
—
10Bh INTCON
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF(2)
0000 0000 0000 0000
—
—
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
--00 0000 --00 0000
—
—
—
—
—
SLRA2
—
SLRA0
---- -0-0 ---- -0-0
—
—
—
—
POR
BOR
---- --qq ---- --uu
10Ch WPUA
10Dh SLRCONA
10Eh —
—
Write buffer for upper 5 bits of program counter
—
10Ah PCLATH
Unimplemented
10Fh PCON
—
—
—
110h
TMR2
Holding Register for the 8-bit Timer2 Register
111h
PR2
Timer2 Period Register
112h
T2CON
113h
HLTMR1
Holding Register for the 8-bit Hardware Limit Timer1 Register
114h
HLTPR1
Hardware Limit Timer1 Period Register
115h
HLT1CON0
—
116h
HLT1CON1
—
117h
—
to
11Fh
Legend:
Note 1:
2:
---0 0000 ---0 0000
—
0000 0000 0000 0000
1111 1111 1111 1111
TOUTPS<3:0>
TMR2ON
—
T2CKPS<1:0>
-000 0000 -000 0000
0000 0000 0000 0000
1111 1111 1111 1111
H1OUTPS<3:0>
—
—
H1ON
H1ERS<2:0>
Unimplemented
H1CKPS<1:0>
H1FEREN
H1REREN
-000 0000 -000 0000
---0 0000 ---0 0000
—
—
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the
mismatch exists.
DS41576B-page 16
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 2-4:
Addr
Name
PIC12F752/HV752 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Value on
POR/BOR
Reset
Bit 0
Values on
all other
Resets(1)
Bank 3
180h
INDF
181h
OPTION_REG
Addressing this location uses contents of FSR to address data memory (not a physical register)
RAPU
INTEDG
T0CS
T0SE
PSA
TO
PD
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
PS<2:0>
182h
PCL
183h
STATUS
Program Counter's (PC) Least Significant Byte
184h
FSR
185h
ANSELA
186h
—
Unimplemented
—
—
187h
—
Unimplemented
—
—
188h
APFCON
—
—
—
189h
OSCTUNE
IRP
RP1
RP0
0000 0000 0000 0000
Z
DC
0001 1xxx 000q quuu
C
Indirect Data Memory Address Pointer
—
—
xxxx xxxx uuuu uuuu
ANSA5
ANSA4
T1GSEL
—
—
ANSA2
COG1FSEL
ANSA1
ANSA0
COG1O1SEL COG1O0SEL
---0 -000 ---0 -000
—
—
—
18Ah PCLATH
—
—
—
18Bh INTCON
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF(2)
0000 0000 0000 0000
—
—
—
—
—
WREN
WR
RD
---- -000 ---- -000
18Ch PMCON1
TUN<4:0>
--11 -111 --11 -111
18Dh PMCON2
Program Memory Control Register 2 (not a physical register)
18Eh PMADRL
18Fh PMADRH
Program Memory Address Register Low Byte
—
—
—
190h
191h
PMDATL
PMDATH
Program Memory Data Register Low Byte
—
—
Program Memory Data Register High Byte
192h
COG1PH
193h
194h
COG1BLK
COG1DB
195h
COG1CON0
G1EN
G1OE1
196h
COG1CON1
G1FSIM
G1RSIM
197h
COG1ASD
G1ASDE
G1ARSEN
—
—
—
—
—
—
G1POL1
G1POL0
—
G1ASDL0
0000 0000 0000 0000
---- --00 ---- --00
PMADRH<1:0>
0000 0000 0000 0000
--00 0000 --00 0000
G1PH<3:0>
---- xxxx ---- uuuu
G1BLKF<3:0>
G1DBF<3:0>
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
G1LD
G1FS<2:0>
G1ASDL1
---0 0000 ---0 0000
---- ---- ---- ----
G1BLKR<3:0>
G1DBR<3:0>
G1OE0
---0 0000 ---u uuuu
Write buffer for upper 5 bits of program counter
0000 0000 0000 0000
G1CS<1:0>
0000 0000 0000 0000
G1RS<2:0>
G1ASDSHLT
G1ASDSC2
G1ASDSC1
G1ASDSFLT
0000 0000 0000 0000
198h
—
Unimplemented
—
to
19Fh
Legend:
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: MCLR and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the mismatch exists.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 17
—
PIC12F752/HV752
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (RAM)
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
REGISTER 2-1:
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits, see the Section 16.0
“Instruction Set Summary”.
STATUS: STATUS REGISTER
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6
RP1: Register Bank Select bit (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 5
RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h-FFh)
0 = Bank 0 (00h-7Fh)
bit 4
TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit(2) (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed.
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(2) (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
DS41576B-page 18
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
2.2.2.2
OPTION Register
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
•
•
•
•
Note:
Timer0/WDT prescaler
External RA2/INT interrupt
Timer0
Weak pull-ups on PORTA
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting PSA bit to ‘1’ of the OPTION
register. See Section 6.1.3 “Software
Programmable Prescaler”.
OPTION_REG: OPTION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RAPU
INTEDG
T0CS
T0SE
PSA
R/W-1
R/W-1
R/W-1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RAPU: PORTA Pull-up Enable bit
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
BIT VALUE
000
001
010
011
100
101
110
111
 2011 Microchip Technology Inc.
x = Bit is unknown
TIMER0 RATE WDT RATE
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Preliminary
DS41576B-page 19
PIC12F752/HV752
2.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, IOCIE change and external
RA2/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
bit 3
IOCIE: Interrupt-on-Change Interrupt Enable bit(1)
1 = Enables the IOC change interrupt
0 = Disables the IOC change interrupt
bit 2
T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow
bit 1
INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
bit 0
IOCIF: Interrupt-on-Change Interrupt Flag bit
1 = An IOC pin has changed state and generated an interrupt
0 = No pin interrupts have been generated
Note 1:
2:
IOC register must also be enabled.
T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
DS41576B-page 20
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
2.2.2.4
PIE1 Register
The PIE1 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-4.
REGISTER 2-4:
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
TMR1GIE
ADIE
—
—
—
HLTMR1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR1GIE: ADC Interrupt Enable bit
1 = Enables the TMR1 gate interrupt
0 = Disables the TMR1 gate interrupt
bit 6
ADIE: ADC Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5-3
Unimplemented: Read as ‘0’
bit 2
HLTMR1IE: Hardware Limit Timer1 Interrupt Enable bit
1 = Enables the HLTMR1 interrupt
0 = Disables the HLTMR1 interrupt
bit 1
TMR2IE: Timer2 Interrupt Enable bit
1 = Enables the Timer2 interrupt
0 = Disables the Timer2 interrupt
bit 0
TMR1IE: Timer1 Interrupt Enable bit
1 = Enables the Timer1 interrupt
0 = Disables the Timer1 interrupt
 2011 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS41576B-page 21
PIC12F752/HV752
2.2.2.5
PIE2 Register
The PIE2 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-5.
REGISTER 2-5:
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
U-0
R/W-0
R/W-0
U-0
R/W-0
U-0
R/W-0
—
—
C2IE
C1IE
—
COG1IE
—
CCP1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5
C2IE: Comparator 2 Interrupt Enable bit
1 = Enables the Comparator 2 interrupt
0 = Disables the Comparator 2 interrupt
bit 4
C1IE: Comparator 1 Interrupt Enable bit
1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt
bit 3
Unimplemented: Read as ‘0’
bit 2
COG1IE: COG 1 Interrupt Flag bit
1 = COG1 interrupt enabled
0 = COG1 interrupt disabled
bit 1
Unimplemented: Read as ‘0’
bit 0
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
DS41576B-page 22
Preliminary
x = Bit is unknown
 2011 Microchip Technology Inc.
PIC12F752/HV752
2.2.2.6
PIR1 Register
The PIR1 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-6.
REGISTER 2-6:
R/W-0
TMR1GIF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
ADIF
—
—
—
HLTMR1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
TMR1GIF: TMR1 Gate Interrupt Flag bit
1 = Timer1 gate interrupt is pending
0 = Timer1 gate interrupt is not pending
bit 6
ADIF: ADC Interrupt Flag bit
1 = ADC conversion complete
0 = ADC conversion has not completed or has not been started
bit 5-3
Unimplemented: Read as ‘0’
bit 2
HLTMR1IF: Hardware Limit Timer1 to HLTPR1 Match Interrupt Flag bit
1 = HLTMR1 to HLTPR1 match occurred (must be cleared in software)
0 = HLTMR1 to HLTPR1 match did not occur
bit 1
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match did not occur
bit 0
TMR1IF: Timer1 Interrupt Flag bit
1 = Timer1 rolled over (must be cleared in software)
0 = Timer1 has not rolled over
 2011 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS41576B-page 23
PIC12F752/HV752
2.2.2.7
PIR2 Register
The PIR2 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-7.
REGISTER 2-7:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0
U-0
R/W-0
R/W-0
—
—
C2IF
C1IF
U-0
R/W-0
U-0
R/W-0
COG1IF
—
CCP1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
C2IF: Comparator 1 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 4
C1IF: Comparator 1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 3
Unimplemented: Read as ‘0’
bit 2
COG1IF: COG 1 Interrupt Flag bit
1 = COG1 has generated an auto-shutdown interrupt
0 = COG1 has NOT generated an auto-shutdown interrupt
bit 1
Unimplemented: Read as ‘0’
bit 0
CCP1IF: ECCP Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode
Unused in this mode
DS41576B-page 24
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
2.2.2.8
PCON Register
The Power Control (PCON) register (see Table 17-2)
contains flag bits to differentiate between a:
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON register also controls the software enable of
the BOR.
The PCON register bits are shown in Register 2-8.
REGISTER 2-8:
PCON: POWER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-q/u
R/W-q/u
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = unchanged
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 25
PIC12F752/HV752
2.3
PCL and PCLATH
2.3.2
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-3 shows the two
situations for the loading of the PC. The upper example
in Figure 2-3 shows how the PC is loaded on a write to
PCL (PCLATH<4:0>  PCH). The lower example in
Figure 2-3 shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3>  PCH).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
The PIC12F752/HV752 Family has an 8-level x 13-bit
wide hardware stack (see Figure 2-1). The stack space
is not part of either program or data space and the
Stack Pointer is not readable or writable. The PC is
PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no Status bits to indicate Stack
Overflow or Stack Underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
8
PCLATH<4:0>
5
Instruction with
PCL as
Destination
ALU Result
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
GOTO, CALL
2
PCLATH<4:3>
11
2.4
OPCODE <10:0>
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
PCLATH
2.3.1
STACK
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register, all
13 bits of the program counter will change to the values
contained in the PCLATH register and those being
written to the PCL register.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR and the IRP bit of the
STATUS register, as shown in Figure 2-4.
A simple program to clear RAM location 40h-7Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
MOVLW
MOVWF
NEXT
CLRF
INCF
BTFSS
GOTO
CONTINUE
INDIRECT ADDRESSING
0x40
FSR
INDF
FSR
FSR,7
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
DS41576B-page 26
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING PIC12F752/HV752
Direct Addressing
RP1
RP0
Bank Select
6
From Opcode
Indirect Addressing
0
IRP
7
Bank Select
Location Select
00
01
10
File Select Register
0
Location Select
11
00h
180h
Data
Memory
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail, see Figure 2-2.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 27
PIC12F752/HV752
NOTES:
DS41576B-page 28
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
3.0
FLASH PROGRAM MEMORY
SELF READ/SELF WRITE
CONTROL
3.1
PMADRH and PMADRL Registers
The PMADRH and PMADRL registers can address up
to a maximum of 1K words of program memory.
The Flash program memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers (see Registers 3-1 to 3-5). There
are six SFRs used to read and write this memory:
When selecting a program address value, the Most
Significant Byte (MSB) of the address is written to the
PMADRH register and the Least Significant Byte
(LSB) is written to the PMADRL register.
•
•
•
•
•
•
PMCON1 is the control register for the data program
memory accesses.
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
When interfacing the program memory block, the
PMDATL and PMDATH registers form a two-byte word
which holds the 14-bit data for read/write, and the
PMADRL and PMADRH registers form a two-byte
word which holds the 10-bit address of the Flash location being accessed. These devices have 1K words of
program Flash with an address range from 0000h to
03FFh.
3.2
PMCON1 and PMCON2 Registers
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
PMCON2 is not a physical register. Reading PMCON2
will read all ‘0’s. The PMCON2 register is used
exclusively in the Flash memory write sequence.
The program memory allows single word read and a
by four word write. A four word write automatically
erases the row of the location and writes the new data
(erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range
of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the Flash program memory.
Depending on the settings of the Flash Program
Memory Enable (WRT<1:0>) bits, the device may or
may not be able to write certain blocks of the program
memory, however, reads of the program memory are
allowed.
When the Flash program memory Code Protection
(CP) bit in the Configuration Word register is enabled,
the program memory is code-protected, and the
device programmer (ICSP™) cannot access data or
program memory.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 29
PIC12F752/HV752
3.3
Flash Program Memory Control Registers
REGISTER 3-1:
R/W-0
PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMDATL<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
PMDATL<7:0>: 8 Least Significant Data bits to Write or Read from Program Memory
REGISTER 3-2:
R/W-0
PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMADRL<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
PMADRL<7:0>: 8 Least Significant Address bits for Program Memory Read/Write Operation
REGISTER 3-3:
PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMDATH<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PMDATH<5:0>: 6 Most Significant Data bits from Program Memory
REGISTER 3-4:
PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
PMADRH<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
PMADRH<1:0>: Specifies the 2 Most Significant Address bits or High bits for Program Memory Reads.
DS41576B-page 30
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
REGISTER 3-5:
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
—
—
—
—
—
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7-3
Unimplemented: Read as ‘0’
bit 2
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1
WR: Write Control bit
1 = Initiates a program Flash program/erase operation
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0
RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software.
0 = Does not initiate a program Flash read
Note 1:
Unimplemented bit, read as ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 31
PIC12F752/HV752
3.4
Reading the Flash Program
Memory
To read a program memory location, the user must
write two bytes of the address to the PMADRL and
PMADRH registers, and then set control bit RD
(PMCON1<0>). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle after to read the data. This causes the
second instruction immediately following the “BSF
PMCON1,RD” instruction to be ignored. The data is
available in the very next cycle in the PMDATL and
PMDATH registers; it can be read as two bytes in the
following instructions. PMDATL and PMDATH registers will hold this value until another read or until it is
written to by the user (during a write operation).
EXAMPLE 3-1:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL
BSF
FLASH PROGRAM READ
PM_ADR
MS_PROG_PM_ADDR
PMADRH
LS_PROG_PM_ADDR
PMADRL
PMCON1
PMCON1, RD
;
;
;
;
;
;
;
Change STATUS bits RP1:0 to select bank with PMADRL
MS Byte of Program Address to read
LS Byte of Program Address to read
Bank to containing PMCON1
PM Read
NOP
; First instruction after BSF PMCON1,RD executes normally
NOP
;
;
;
;
;
;
BANKSEL
MOVF
MOVF
PMDATL
PMDATL, W
PMDATH, W
DS41576B-page 32
Any instructions here are ignored as program
memory is read in second cycle after BSF PMCON1,RD
Bank to containing PMADRL
W = LS Byte of Program PMDATL
W = MS Byte of Program PMDATL
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
FIGURE 3-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1
Flash ADDR
Q2
Q3
Q4
PC
Flash DATA
Q1
Q2
Q4
PC + 1
INSTR (PC)
INSTR (PC - 1)
Executed here
Q3
Q1
Q2
Q3
Q4
Q1
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
Executed here
Q2
Q3
PC+3
PC
+3
PMDATH,PMDATL
INSTR (PC + 1)
Executed here
Q4
Q1
Q2
Q3
Q4
NOP
Executed here
Q2
Q3
Q4
PC + 5
PC + 4
INSTR (PC + 3)
Q1
INSTR (PC + 4)
INSTR (PC + 3)
Executed here
INSTR (PC + 4)
Executed here
RD bit
PMDATH
PMDATL
Register
PMRHLT
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 33
PIC12F752/HV752
3.5
Writing the Flash Program
Memory
A word of the Flash program memory may only be
written to if the word is in an unprotected segment of
memory.
Flash program memory must be written in four-word
blocks. See Figure 3-2 and Figure 3-3 for more details.
A block consists of four words with sequential
addresses, with a lower boundary defined by an
address, where PMADRL<1:0> = 00. All block writes to
program memory are done as 16-word erase by fourword write operations. The write operation is edgealigned and cannot occur across boundaries.
To write program data, it must first be loaded into the
buffer registers (see Figure 3-2). This is accomplished
by first writing the destination address to PMADRL and
PMADRH and then writing the data to PMDATL and
PMDATH. After the address and data have been set
up, then the following sequence of events must be
executed:
1.
2.
Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
Set the WR control bit of the PMCON1 register.
All four buffer register locations should be written to
with correct data. If less than four words are being
written to in the block of four words, then a read from
the program memory location(s) not being written to
must be performed. This takes the data from the
program location(s) not being written and loads it into
the PMDATL and PMDATH registers. Then the
sequence of events to transfer data to the buffer
registers must be executed.
which the erase takes place (i.e., the last word of the
sixteen-word block erase). This is not Sleep mode as
the clocks and peripherals will continue to run. After
the four-word write cycle, the processor will resume
operation with the third instruction after the PMCON1
write instruction. The above sequence must be
repeated for the higher 12 words.
3.6
Protection Against Spurious Write
There are conditions when the device should not write
to the program memory. To protect against spurious
writes, various mechanisms have been built in. On
power-up, WREN is cleared. Also, the Power-up Timer
(64 ms duration) prevents program memory writes.
The write initiate sequence and the WREN bit help
prevent an accidental write during brown-out, power
glitch or software malfunction.
3.7
Operation During Code-Protect
When the device is code-protected, the CPU is able to
read and write unscrambled data to the program
memory.
3.8
Operation During Write Protect
When the program memory is write-protected, the
CPU can read and execute from the program memory.
The portions of program memory that are write protected can be modified by the CPU using the PMCON
registers, but the protected program memory cannot
be modified using ICSP mode.
To transfer data from the buffer registers to the program
memory, the PMADRL and PMADRH must point to the
last location in the four-word block (PMADRL<1:0> =
11). Then the following sequence of events must be
executed:
1.
2.
Write 55h, then AAh, to PMCON2 (Flash programming sequence).
Set control bit WR of the PMCON1 register to
begin the write operation.
The user must follow the same specific sequence to
initiate the write for each word in the program block,
writing each program word in sequence (000, 001,
010, 011). When the write is performed on the last
word (PMADRL<1:0> = 11), a block of sixteen words is
automatically erased and the content of the four-word
buffer registers are written into the program memory.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOP instructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in
DS41576B-page 34
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
FIGURE 3-2:
BLOCK WRITES TO 1K FLASH PROGRAM MEMORY
7
5
0
0 7
PMDATH
If at a new row
sixteen words of
Flash are erased,
then four buffers
are transferred
to Flash
automatically
after this word
is written
PMDATL
6
8
14
14
First word of block
to be written
14
PMADRL<1:0> = 00
PMADRL<1:0> = 10
PMADRL<1:0> = 01
Buffer Register
Buffer Register
14
PMADRL<1:0> = 11
Buffer Register
Buffer Register
Program Memory
FIGURE 3-3:
FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
PMADRH,PMADRL
PC + 1
Flash
ADDR
INSTR
(PC)
Flash
DATA
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INSTR
(PC + 1)
ignored
read
BSF PMCON1,WR INSTR (PC + 1)
Executed here
Executed here
PMDATH,PMDATL
Processor halted
PM Write Time
PC + 2
PC + 3
INSTR (PC+2)
NOP
Executed here
PC + 4
INSTR (PC+3)
(INSTR (PC + 2)
NOP
INSTR (PC + 3)
Executed here Executed here
Flash
Memory
Location
WR bit
PMWHLT
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 35
PIC12F752/HV752
An example of the complete four-word write sequence
is shown in Example 3-2. The initial address is loaded
into the PMADRH and PMADRL register pair; the four
words of data are loaded using indirect addressing.
EXAMPLE 3-2:
WRITING TO FLASH PROGRAM MEMORY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This write routine assumes the following:
;
A valid starting address (the least significant bits = '00')
;
is loaded in ADDRH:ADDRL
;
ADDRH, ADDRL and DATADDR are all located in data memory
;
BANKSEL
PMADRH
MOVF
ADDRH,W
;Load initial address
MOVWF
PMADRH
;
MOVF
ADDRL,W
;
MOVWF
PMADRL
;
MOVF
DATAADDR,W
;Load initial data address
MOVWF
FSR
;
LOOP MOVF INDF,W
;Load first data byte into lower
MOVWF
PMDATL
;
INCF
FSR,F
;Next byte
MOVF
INDF,W
;Load second data byte into upper
MOVWF
PMDATH
;
INCF
FSR,F
;
BANKSEL PMCON1
BSF
PMCON1,WREN ;Enable writes
BCF
INTCON,GIE
;Disable interrupts (if using)
BTFSC
INTCON,GIE
;See AN576
GOTO
$-2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
Required Sequence
MOVLW
55h
;Start of required write sequence:
MOVWF
PMCON2
;Write 55h
MOVLW
0AAh
;
MOVWF
PMCON2
;Write 0AAh
BSF
PMCON1,WR
;Set WR bit to begin write
NOP
;Required to transfer data to the buffer
NOP
;registers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BCF
PMCON1,WREN ;Disable writes
BSF
INTCON,GIE
;Enable interrupts (comment out if not using interrupts)
BANKSEL PMADRL
MOVF
PMADRL, W
INCF
PMADRL,F
;Increment address
ANDLW
0x03
;Indicates when sixteen words have been programmed
SUBLW
0x03
;Change value for different size write blocks
;0x0F = 16 words
;0x0B = 12 words
;0x07 = 8 words
;0x03 = 4 words
BTFSS
STATUS,Z
;Exit on a match,
GOTO
LOOP
;Continue if more data needs to be written
DS41576B-page 36
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 3-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
—
—
—
—
—
WREN
WR
RD
31
PMCON1
PMCON2
Program Memory Control Register 2
29*
PMADRL
PMADRL<7:0>
30
PMADRH
—
—
—
—
PMDATL
PMDATH
—
—
INTCON
GIE
PEIE
Legend:
*
CONFIG
Legend:
—
PMADRH<1:0>
30
PMDATH<5:0>
T0IE
INTE
30
IOCIE
30
T0IF
INTF
IOCIF
20
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.
Page provides register information.
TABLE 3-2:
Name
—
PMDATL<7:0>
SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
13:8
7:0
—
—
DEBUG
CLKOUTEN
—
CP
MCLRE
PWRTE
Bit 11/3
Bit 10/2
WRT<1:0>
WDTE
Bit 9/1
Bit 8/0
BOREN<1:0>
—
—
FOSC0
Register
on Page
142
— = unimplemented location, read as ‘1’. Shaded cells are not used by Flash program memory.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 37
PIC12F752/HV752
NOTES:
DS41576B-page 38
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
4.0
OSCILLATOR MODULE
The internal oscillator module provides the following
selectable system clock modes:
4.1
Overview
•
•
•
•
The oscillator module has a variety of clock sources
and selection features that allow it to be used in a wide
range of applications while maximizing performance
and minimizing power consumption. Figure 4-1
illustrates a block diagram of the oscillator module.
8 MHz (HFINTOSC)
4 MHz (HFINTOSC Postscaler)
1 MHz (HFINTOSC Postscaler)
31 kHz (LFINTOSC)
The oscillator module can be configured in one of two
clock modes.
1.
2.
EC (external clock)
INTOSC (internal oscillator)
Clock Source modes are configured by the FOSC bit in
the Configuration Word register (CONFIG).
FIGURE 4-1:
PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
EC Enable
(Figure 4-2)
EC
CLKIN
HFINTOSC Enable
(Figure 4-2)
LFINTOSC Enable
(Figure 4-2)
HFINTOSC
8 MHz
Prescaler
÷1
11
÷2
10
÷8
01
LFINTOSC
31 kHz
MUX
Internal Oscillator
1
System Clock
(CPU and
Peripherals)
0
FOSC
00
IRCF<1:0>
COG Clock Source
WDT Clock Source
FIGURE 4-2:
OSCILLATOR ENABLE
FOSC0
Sleep
FOSC0
IRCF<1:0>  00
Sleep
EC Enable
HFINTOSC Enable
FOSC0
IRCF<1:0> = 00
Sleep
LFINTOSC Enable
WDTE
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 39
PIC12F752/HV752
4.2
Clock Source Modes
Clock Source modes can be classified as external or
internal:
• The External Clock mode relies on an external
clock for the clock source. For example, a clock
module or clock output from another circuit.
• Internal clock sources are contained internally
within the oscillator module. The oscillator module
has four selectable clock frequencies:
- 8 MHz
- 4 MHz
- 1 MHz
- 31 kHz
When one of the HFINTOSC frequencies is selected,
the frequency of the internal oscillator can be trimmed
by adjusting the TUN<4:0> bits of the OSCTUNE
register.
Operation after a Power-on Reset (POR) or wake-up
from Sleep is delayed by the oscillator start-up time.
Delays are typically longer for the LFINTOSC than
HFINTOSC because of the very low-power operation
and relatively narrow bandwidth of the LF internal
oscillator. However, when another peripheral keeps the
oscillator running during Sleep, the start-up time is
delayed to allow the memory bias to stabilize.
FIGURE 4-4:
The system clock can be selected between external or
internal clock sources via the FOSC0 bit of the Configuration Word register (CONFIG).
4.2.1
Because the PIC® MCU design is fully static, stopping
the external clock input will have the effect of halting the
device while leaving all data intact. Upon restarting the
external clock, the device will resume operation as if no
time had elapsed.
FIGURE 4-3:
CLKIN(1)
PIC® MCU
When operating in this mode, an external clock source
must be connected to the CLKIN input. The CLKOUT is
available for either general purpose I/O or system clock
output. Figure 4-3 shows the pin connections for EC
mode.
I/O
Note 1:
4.2.2.1
CLKOUT(1)
Alternate pin functions are listed in the
Section 1.0 “Device Overview”.
Oscillator Ready Bits
The HTS and LTS bits of the OSCCON register indicate
the status of the HFINTOSC and LFINTOSC,
respectively. When either bit is set, it indicates that the
corresponding oscillator is running and stable.
EXTERNAL CLOCK (EC)
MODE OPERATION
CLKIN
Clock from
Ext. System
PIC® MCU
I/O
4.2.2
I/O
EC MODE
The External Clock (EC) mode allows an externally
generated logic as the system clock source. The EC
clock mode is selected when the FOSC0 bit of the
Configuration Word is set.
Note 1:
INTERNAL CLOCK MODE
OPERATION
CLKOUT(1)
Alternate pin functions are listed in the
Section 1.0 “Device Overview”.
INTERNAL CLOCK MODE
Internal clock mode configures the internal oscillators
as the system clock source. The internal clock mode is
selected when the FOSC0 bit of the Configuration
Word is cleared. The source and frequency are
selected with the IRCF<1:0> bits of the OSCCON
register.
DS41576B-page 40
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
4.3
System Clock Output
4.4
The CLKOUT pin is available for general purpose I/O or
system clock output. The CLKOUTEN bit of the
Configuration Word controls the function of the
CLKOUT pin.
When the CLKOUTEN bit is cleared, the CLKOUT pin
is driven by the selected internal oscillator frequency
divided by 4. The corresponding I/O pin always reads
‘0’ in this configuration.
The CLKOUT signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements.
When the CLKOUTEN bit is set, the system clock out
function is disabled and the CLKOUT pin is available for
general purpose I/O.
TABLE 4-1:
Oscillator Delay upon Wake-Up,
Power-Up, and Base Frequency
Change
In applications where the OSCTUNE register is used to
shift the HFINTOSC frequency, the application should
not expect the frequency to stabilize immediately. In
this case, the frequency may shift gradually toward the
new value. The time for this frequency shift is less than
eight cycles of the base frequency.
A short delay is invoked upon power-up and when
waking from sleep to allow the memory bias circuitry to
stabilize. Table 4-1 shows examples where the oscillator
delay is invoked.
OSCILLATOR DELAY EXAMPLES
Switch From
Switch To
Frequency
Oscillator Delay
Sleep/POR
INTOSC
31 kHz to 8 MHz
Sleep/POR
EC
DC – 20 MHz
10 s internal delay to allow memory
bias to stabilize.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 41
PIC12F752/HV752
4.5
Oscillator Control Registers
REGISTER 4-1:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
U-0
—
—
R/W-0/u
R/W-1/u
IRCF<1:0>
U-0
R-0/u
R-0/u
U-0
—
HTS
LTS
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
IRCF<1:0>: Internal Oscillator Frequency Select bits
11 = 8 MHz
10 = 4 MHz
01 = 1 MHz (Reset default)
00 = 31 kHz (LFINTOSC)
bit 3
Unimplemented: Read as ‘0’
bit 2
HTS: HFINTOSC Status bit
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1
LTS: LFINTOSC Status bit
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
bit 0
Unimplemented: Read as ‘0’
DS41576B-page 42
Preliminary
x = Bit is unknown
 2011 Microchip Technology Inc.
PIC12F752/HV752
4.5.1
OSCTUNE REGISTER
The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
The oscillator is factory calibrated, but can be adjusted
in software by writing to the OSCTUNE register
(Register 4-2).
REGISTER 4-2:
When the OSCTUNE register is modified, the frequency
will begin shifting to the new frequency. Code execution
continues during this shift. There is no indication that the
shift has occurred.
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
U-0
U-0
—
—
—
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
TUN<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Oscillator module is running at the calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
TABLE 4-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7
Bit 6
OSCCON
—
—
OSCTUNE
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
HTS
LTS
—
42
IRCF<1:0>
—
TUN<4:0>
43
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word register (Register 17-1) for operation of all register bits.
TABLE 4-3:
Name
CONFIG
Legend:
SUMMARY OF CONFIGURATION WORD CLOCK SOURCES
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
13:8
7:0
—
—
DEBUG
CLKOUTEN
—
CP
MCLRE
PWRTE
Bit 11/3
Bit 10/2
WRT<1:0>
WDTE
Bit 9/1
Bit 8/0
BOREN<1:0>
—
—
FOSC0
Register
on Page
142
— = unimplemented location, read as ‘1’. Shaded cells are not used by oscillator module.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 43
PIC12F752/HV752
NOTES:
DS41576B-page 44
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
5.0
I/O PORTS
EXAMPLE 5-1:
For this device there is one port available, PORTA. In
general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
PORTA has three standard registers for its operation.
These registers are:
• TRISA registers (data direction)
• PORTA registers (reads the levels on the pins of
the device)
• LATA registers (output latch)
Some ports may have one or more of the following
additional registers. These registers are:
;
;
;
;
INITIALIZING PORTA
This code example illustrates
initializing the PORTA register. The
other ports are initialized in the same
manner.
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
• ANSELA (analog select)
• WPUA (weak pull-up)
The Data Latch (LATA register) is useful for readmodify-write operations on the value that the I/O pins
are driving.
A write operation to the LATA register has the same
effect as a write to the corresponding PORTA register.
A read of the LATA register reads the values held in the
I/O PORT latches, while a read of the PORTA register
reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSEL register. When an ANSELA bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 5-1.
FIGURE 5-1:
GENERIC I/O PORTA
OPERATION
Read LATA
D
Write LATA
Write PORTA
TRISA
Q
CK
VDD
Data Register
Data Bus
I/O pin
Read PORTA
To peripherals
ANSELA
 2011 Microchip Technology Inc.
VSS
Preliminary
DS41576B-page 45
PIC12F752/HV752
5.1
Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 5-1. For this device family, the
following functions can be moved between different
pins.
• Timer1 Gate
• COG1
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
5.2
Alternate Pin Function Control Register
REGISTER 5-1:
U-0
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0
—
—
U-0
R/W-0/0
R/W-0/0
R/W-0/0
—
T1GSEL
—
COG1FSEL
R/W-0/0
R/W-0/0
COG1O1SEL COG1O0SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’.
bit 4
T1GSEL: Timer 1 Gate Input Pin Selection bit
1 = T1G function is on RA3
0 = T1G function is on RA4
bit 3
Unimplemented: Read as ‘0’.
bit 2
COG1FSEL: COG1 Fault Input Pin Selection bit
1 = COG1FLT is on RA3
0 = COG1FLT is on RA4
bit 1
COG1O1SEL: COG1 Output 1 Pin Selection bit
1 = COG1OUT1 is on RA4
0 = COG1OUT1 is on RA0
bit 0
COG1O0SEL: COG1 Output 0 Pin Selection bit
1 = COG1OUT0 is on RA5
0 = COG1OUT0 is on RA2
DS41576B-page 46
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
5.3
PORTA and the TRISA Registers
PORTA is a 6-bit wide port with 5 bidirectional and 1
input-only pin. The corresponding data direction register
is TRISA (Register 5-2). Setting a TRISA bit (= 1) will
make the corresponding PORTA pin an input (i.e.,
disable the output driver). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e.,
enables output driver and puts the contents of the output
latch on the selected pin). The exception is RA3, which
is input only and its TRIS bit will always read as ‘1’.
Example 5-1 shows how to initialize PORTA.
TABLE 5-1:
Pin Name
Reading the PORTA register (Register 5-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch. RA3 reads ‘0’ when
MCLRE = 1.
The TRISA register controls the direction of the
PORTA pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISA
register are maintained set when using them as analog
inputs. I/O pins configured as analog input always read
‘0’.
Note:
5.3.1
Note 1:
2:
3:
PORTA OUTPUT PRIORITY
Function Priority(1)
RA0
ICSPDAT
REFOUT
DACOUT
COG1OUT1(2)
RA0
RA1
RA1
RA2
COG1OUT0(2)
C1OUT
C2OUT
CCP1
RA2
RA3
None
RA4
CLKOUT
COG1OUT1(3)
RA4
RA5
COG1OUT0(3)
RA5
Priority listed from highest to lowest.
Default function pin (see APFCON register).
Alternate function pin (see APFCON register).
The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’ and cannot generate an interrupt.
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 5-1.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as comparator inputs, are
not shown in the priority lists. These inputs are active
when the peripheral is enabled and the input multiplexer
for the pin is selected. The Analog mode, set with the
ANSELA register, disables the digital input buffer
thereby preventing excessive input current when the
analog input voltage is between logic states. Digital
output functions may control the pin when it is in Analog
mode with the priority shown in Table 5-1.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 47
PIC12F752/HV752
5.4
PORTA Control Registers
REGISTER 5-2:
PORTA: PORTA REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R-x/x
R/W-x/u
R/W-x/u
R/W-x/u
—
—
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O
pin values.
REGISTER 5-3:
TRISA: PORTA TRI-STATE REGISTER
U-0
U-0
R/W-1/1
R/W-1/1
R-1/1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
TRISA5
TRISA4
TRISA3(1)
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
TRISA<5:0>: PORTA Tri-State Control bits(1)
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1:
TRISA3 always reads ‘1’.
REGISTER 5-4:
LATA: PORTA DATA LATCH REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
U-0
R/W-x/u
R/W-x/u
R/W-x/u
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
LATA<5:4>: PORTA Output Latch Value bits(1)
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LATA<2:0>: PORTA Output Latch Value bits(1)
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O
pin values.
DS41576B-page 48
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
5.5
Additional Pin Functions
5.5.3
Every PORTA pin on the PIC12F752 has an interrupton-change option and a weak pull-up option. The next
three sections describe these functions.
5.5.1
ANSELA REGISTER
INTERRUPT-ON-CHANGE
Each PORTA pin is individually configurable as an
interrupt-on-change pin. Control bits IOCA enable or
disable the interrupt function for each pin. Refer to
Register 5-8. The interrupt-on-change is disabled on a
Power-on Reset.
The ANSELA register (Register 5-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (IOCIF) in the INTCON register (Register 2-3).
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
Note:
5.5.2
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
WEAK PULL-UPS
Each of the PORTA pins, except RA3, has an
individually configurable internal weak pull-up. Control
bits WPUx enable or disable each pull-up. Refer to
Register 5-6. Each weak pull-up is automatically turned
off when the port pin is configured as an output. The
pull-ups are disabled on a Power-on Reset by the
RAPU bit of the OPTION_REG register). A weak pullup is automatically enabled for RA3 when configured
as MCLR and disabled when RA3 is an I/O. There is no
software control of the MCLR pull-up.
 2011 Microchip Technology Inc.
a)
Any read of PORTA AND Clear flag bit IOCIF.
This will end the mismatch condition;
OR
b)
Any write of PORTA AND Clear flag bit IOCIF
will end the mismatch condition;
A mismatch condition will continue to set flag bit IOCIF.
Reading PORTA will end the mismatch condition and
allow flag bit IOCIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Reset. After these Resets, the IOCIF flag will continue
to be set if a mismatch is present.
Note:
5.5.4
If a change on the I/O pin should occur
when any PORTA operation is being
executed, then the IOCIF interrupt flag
may not get set.
SLEW RATE CONTROL
Two of the PORTA pins, RA0 and RA2, are equipped
with high current driver circuitry. The SLRCONA register
provides reduced slew rate control to mitigate possible
EMI radiation from these pins.
Preliminary
DS41576B-page 49
PIC12F752/HV752
REGISTER 5-5:
ANSELA: PORTA ANALOG SELECT REGISTER
U-0
U-0
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
—
—
ANSA5
ANSA4
—
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
ANSA<5:4>: Analog Select Between Analog or Digital Function on Pin RA<5:4> bits
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ANSA<2:0> Analog Select Between Analog or Digital Function on Pin RA<2:0> bits
1 = Analog input. Pin is assigned as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
Note 1:
Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-onchange if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of
the voltage on the pin.
REGISTER 5-6:
WPUA: WEAK PULL-UP PORTA REGISTER
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
WPU5
WPU4
WPU3
WPU2
WPU1
WPU0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
WPU<5:0>: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1:
2:
3:
x = Bit is unknown
Global RAPU must be enabled for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
The RA3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled
as an input and reads as ‘0’.
DS41576B-page 50
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
REGISTER 5-7:
SLRCONA: SLEW RATE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
R/W-0
—
—
—
—
—
SLRA2
—
SLRA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2
SLRA2: Slew Rate Control bit
1 = Pin voltage slews at limited rate
0 = Pin voltage slews at maximum rate
bit 1
Unimplemented: Read as ‘0’
bit 0
SLRA0: Slew Rate Control bit
1 = Pin voltage slews at limited rate
0 = Pin voltage slews at maximum rate
Note 1:
2:
3:
x = Bit is unknown
Global RAPU must be enabled for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
The RA3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled
as an input and reads as ‘0’.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 51
PIC12F752/HV752
REGISTER 5-8:
IOCAP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCAP<5:0>: Interrupt-on-Change Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 5-9:
IOCAN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCAN<5:0>: Interrupt-on-Change Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 5-10:
IOCAF: INTERRUPT-ON-CHANGE FLAG REGISTER
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
—
—
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOCAF<5:0>: Interrupt-on-Change Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RBx, or when IOCANx = 1 and a falling edge was
detected on RAx.
0 = No change was detected, or the user cleared the detected change.
DS41576B-page 52
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 5-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
ADCON0
ADFM
VCFG
ADCON1
—
ANSELA
—
APFCON
CM1CON0
Bit 5
Bit 4
Bit 2
ANSA5
ANSA4
Bit 1
Bit 0
Register on
Page
GO/DONE
ADON
106
—
—
—
—
107
—
ANSA2
ANSA1
ANSA0
50
CHS<3:0>
ADCS<2:0>
—
Bit 3
—
—
—
T1GSEL
—
COG1FSEL
COG1O1SEL
COG1O0SEL
46
C1ON
C1OUT
C1OE
C1POL
C1ZLF
C1SP
C1HYS
C1SYNC
127
C2OE
C2POL
CM2CON0
C2ON
C2OUT
CM1CON1
C1INTP
C1INTN
C2ZLF
C2SP
C2HYS
C2SYNC
127
C1PCH<1:0>
—
—
—
C1NCH0
128
C2PCH<1:0>
CM2CON1
C2NTP
C2INTN
—
—
—
C2NCH0
128
DACCON0
DACEN
DACRNG
DACOE
—
—
DACPSS0
—
—
118
IOCAF
—
—
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
52
IOCAN
—
—
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
52
IOCAP
—
—
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
52
LATA
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0
48
RAPU
INTEDG
T0CS
T0SE
PSA
PORTA
—
—
RA5
RA4
RA3
RA0
48
SLRCONA
—
—
—
—
—
SLRA2
—
SLRA0
51
TRISA
—
—
TRISA5
TRISA4
TRISA3(1)
TRISA2
TRISA1
TRISA0
48
OPTION_REG
Legend:
Note 1:
PS<2:0>
RA2
19
RA1
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TRISA3 always reads ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 53
PIC12F752/HV752
NOTES:
DS41576B-page 54
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
6.0
TIMER0 MODULE
6.1
Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the
following features:
When used as a timer, the Timer0 module can be used
as either an 8-bit timer or an 8-bit counter.
•
•
•
•
•
6.1.1
8-bit timer/counter register (TMR0)
8-bit prescaler (shared with Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow
8-BIT TIMER MODE
When used as a timer, the Timer0 module will
increment every instruction cycle (without prescaler).
Timer mode is selected by clearing the T0CS bit of the
OPTION register to ‘0’.
Figure 6-1 is a block diagram of the Timer0 module.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
6.1.2
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
8-BIT COUNTER MODE
When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION_REG register. Counter mode is
selected by setting the T0CS bit of the OPTION register
to ‘1’.
FIGURE 6-1:
TIMER0 WITH SHARED PRESCALE BLOCK DIAGRAM
FOSC/4
Data Bus
0
8
1
1
T0CKI
pin
T0CS
T0SE
Sync
2 TCY
Shared Prescale
TMR0
0
0
Set Flag bit T0IF
on Overflow
PSA
8-bit
Prescaler
1
PSA
8
PS<2:0>
Watchdog
Timer
LFINTOSC
WDT
Time-out
2
(Figure 4-1)
1
0
PSA
PSA
WDTE
Note 1:
2:
T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG register.
WDTE bit is in the Configuration Word register.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 55
PIC12F752/HV752
6.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler.
When the prescaler is assigned to WDT, (PSA = 1), a
CLRWDT instruction will clear the prescaler along with
the WDT.
6.1.3.1
Switching Prescaler Between
Timer0 and WDT Modules
BANKSEL TMR0
CLRWDT
CLRF
TMR0
CHANGING PRESCALER
(TIMER0  WDT)
;
;Clear WDT
;Clear TMR0 and
;prescaler
BANKSEL OPTION_REG
;
BSF
OPTION_REG,PSA ;Select WDT
CLRWDT
;
;
MOVLW
b’11111000’
;Mask prescaler
ANDWF
OPTION_REG,W
;bits
IORLW
b’00000101’
;Set WDT prescaler
MOVWF
OPTION_REG
;to 1:32
DS41576B-page 56
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT  TIMER0)
CLRWDT
;Clear WDT and
;prescaler
BANKSEL OPTION_REG
;
MOVLW
b’11110000’ ;Mask TMR0 select and
ANDWF
OPTION_REG,W ;prescaler bits
IORLW
b’00000011’ ;Set prescale to 1:16
MOVWF
OPTION_REG
;
6.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
Note:
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence
shown in Example 6-1, must be executed.
EXAMPLE 6-1:
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 6-2).
6.1.5
The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.
USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
clock source must meet the timing requirements as
shown in Section 20.0 “Electrical Specifications”.
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
6.2
Option and Timer0 Control Register
REGISTER 6-1:
OPTION_REG: OPTION REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RAPU
INTEDG
T0CS
T0SE
PSA
R/W-1
R/W-1
R/W-1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RAPU: PORTA Pull-up Enable bit
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values in WPU register
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TABLE 6-1:
Name
OPTION_REG
Legend:
*
Note 1:
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOCIE
T0IF
INTF
IOCIF
Holding Register for the 8-bit Timer0 Register
INTCON
TRISA
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
TMR0
TMR0 Rate
T0IE
INTE
Register on
Page
55*
GIE
PEIE
RAPU
INTEDG
T0CS
T0SE
PSA
—
—
TRISA5
TRISA4
TRISA3(1)
PS<2:0>
TRISA2
TRISA1
20
57
TRISA0
48
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0
module.
Page provides register information.
TRISA3 always reads ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 57
PIC12F752/HV752
NOTES:
DS41576B-page 58
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
7.0
TIMER1 MODULE WITH GATE
CONTROL
•
•
•
•
The Timer1 module is a 16-bit timer/counter with the
following features:
Figure 7-1 is a block diagram of the Timer1 module.
•
•
•
•
•
•
•
16-bit timer/counter register pair (TMR1H:TMR1L)
Selectable internal or external clock sources
2-bit prescaler
Synchronous or asynchronous operation
Multiple Timer1 gate (count enable) sources
Interrupt on overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
• Selectable Gate Source Polarity
FIGURE 7-1:
Gate Toggle mode
Gate Single-pulse mode
Gate Value Status
Gate Event Interrupt
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1G
From Timer0
Overflow
01
SYNCC1OUT
10
SYNCC2OUT
T1GSPM
00
0
T1G_IN
D
Q
CK
R
Q
11
Single Pulse
Acq. Control
1
1
Q1
D
Data Bus
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
TMR1GIF
det
T1GPOL
TMR1ON
T1GTM
TMR1GE
TMR1ON
TMR1(2)
Set flag bit
TMR1IF on
Overflow
T1GVAL
0
TMR1H
CCP Special Event Trigger
EN
TMR1L
R
Q
D
T1CLK
0
TMR1CS1
T1SYNC
Synchronized
clock input
1
TMR1CS<1:0>
Temperature Sense
Oscillator
(1)
11
10
T1CKI
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
Synchronize(3)
Prescaler
1, 2, 4, 8
det
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
Note 1: ST buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 59
PIC12F752/HV752
7.1
Timer1 Operation
7.2
Clock Source Selection
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> bits of the T1CON register are used
to select the clock source for Timer1. Table 7-2 displays
the clock source selections.
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and
increments on every selected edge of the external
source.
TABLE 7-2:
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 7-1 displays the Timer1 enable
selections.
TABLE 7-1:
TMR1CS<1:0>
CLOCK SOURCE
SELECTIONS
Clock Source
11
Temperature Sense Oscillator
10
External Clocking on T1CKI Pin
01
System Clock (FOSC)
00
Instruction Clock (FOSC/4)
7.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC or FOSC/4 as determined by the Timer1
prescaler.
TIMER1 ENABLE
SELECTIONS
Timer1
Operation
TMR1ON
TMR1GE
0
0
Off
0
1
Off
1
0
Always On
1
1
Count Enabled
7.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter. When enabled
to count, Timer1 is incremented on the rising edge of the
external clock input T1CKI.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge (see Figure 7-2)
after any one or more of the following
conditions:
• Timer1 enabled after POR Reset
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
7.2.3
TEMPERATURE SENSE
OSCILLATOR
When the Temperature Sense Oscillator source is
selected, the TMR1H:TMR1L register pair will increment
on multiples of the Temperature Sense Oscillator as
determined by the Timer1 prescaler. The Temperature
Sense Oscillator operates at 16 kHz typical.
DS41576B-page 60
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
7.3
Timer1 Prescaler
7.5
Timer1 Gate
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 gate count
enable.
7.4
7.5.1
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 7.4.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Note:
7.4.1
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
 2011 Microchip Technology Inc.
Timer1 gate can also be driven by multiple selectable
sources.
TIMER1 GATE COUNT ENABLE
The Timer1 gate is enabled by setting the TMR1GE bit
of the T1GCON register. The polarity of the Timer1 gate
is configured using the T1GPOL bit of the T1GCON
register.
When Timer1 Gate (T1G) input is active, Timer1 will
increment on the rising edge of the Timer1 clock
source. When Timer1 gate input is inactive, no
incrementing will occur and Timer1 will hold the current
count. See Figure 7-3 for timing details.
TABLE 7-3:
TIMER1 GATE ENABLE
SELECTIONS
T1CLK
T1GPOL
T1G

0
0
Counts

0
1
Holds Count

1
0
Holds Count

1
1
Counts
7.5.2
Timer1 Operation
TIMER1 GATE SOURCE
SELECTION
The Timer1 gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
TABLE 7-4:
T1GSS
TIMER1 GATE SOURCES
Timer1 Gate Source
11
SYNCC2OUT
10
SYNCC1OUT
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
00
Timer1 Gate Pin
Preliminary
DS41576B-page 61
PIC12F752/HV752
7.5.2.1
T1G Pin Gate Operation
7.5.5
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
7.5.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
7.5.2.3
C1OUT/C2OUT Gate Operation
The outputs from the Comparator C1 and C2 modules
can be used as gate sources for the Timer1 module.
7.5.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a Timer1
gate signal, as opposed to the duration of a single level
pulse.
TIMER1 GATE VALUE STATUS
When Timer1 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
7.5.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T1GVAL
occurs, the TMR1GIF flag bit in the PIR1 register will be
set. If the TMR1GIE bit in the PIE1 register is set, then
an interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the signal. See Figure 7-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
7.5.4
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next
incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
cleared. No other gate events will be allowed to
increment Timer1 until the T1GGO/DONE bit is once
again set in software.
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/DONE bit. See Figure 7-5 for
timing details.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 7-6 for timing
details.
DS41576B-page 62
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
7.6
Timer1 Interrupt
7.8
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
•
•
•
•
TMR1ON bit of the T1CON register
TMR1IE bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
7.7
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, the clock
source can be used to increment the counter. To set up
the timer to wake the device:
•
•
•
•
•
TMR1ON bit of the T1CON register must be set
TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set
T1SYNC bit of the T1CON register must be set
TMR1CS bits of the T1CON register must be
configured
• TMR1GE bit of the T1GCON register must be
configured
The CCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
For more information, see Section 10.0 “Capture/
Compare/PWM Modules”.
7.9
CCP Special Event Trigger
When the CCP is configured to trigger a special event,
the trigger will clear the TMR1H:TMR1L register pair.
This special event does not cause a Timer1 interrupt.
The CCP module may still be configured to generate a
CCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized to the FOSC/4 to utilize
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the CCP, the write will
take precedence.
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
FIGURE 7-2:
CCP Capture/Compare Time Base
For more information, see Section 12.2.5 “Special
Event Trigger”.
TIMER1 INCREMENTING EDGE
T1CKI
T1CKI
TMR1 enabled
Note 1:
2:
Arrows indicate counter increments.
In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 63
PIC12F752/HV752
FIGURE 7-3:
TIMER1 GATE COUNT ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TIMER1
N
FIGURE 7-4:
N+1
N+2
N+3
N+4
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TIMER1
DS41576B-page 64
N
N+1 N+2 N+3
N+4
Preliminary
N+5 N+6 N+7
N+8
 2011 Microchip Technology Inc.
PIC12F752/HV752
FIGURE 7-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
TMR1GIF
N
N+1
Set by hardware on
falling edge of T1GVAL
Cleared by software
 2011 Microchip Technology Inc.
N+2
Preliminary
Cleared by
software
DS41576B-page 65
PIC12F752/HV752
FIGURE 7-6:
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
TMR1GIF
DS41576B-page 66
N
Cleared by software
N+1
N+2
N+3
Set by hardware on
falling edge of T1GVAL
Preliminary
N+4
Cleared by
software
 2011 Microchip Technology Inc.
PIC12F752/HV752
7.10
Timer1 Control Registers
REGISTER 7-1:
R/W-0
T1CON: TIMER1 CONTROL REGISTER
R/W-0
TMR1CS<1:0>
R/W-0
R/W-0
T1CKPS<1:0>
R/W-0
R/W-0
U-0
R/W-0
Reserved
T1SYNC
—
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits
11 = Temperature Sense Oscillator
10 = External clock from T1CKI pin (on the rising edge)
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
Reserved: Do not use.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (FOSC)
x = Bit is unknown
TMR1CS<1:0> = 0X
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 1
Unimplemented: Read as ‘0’
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Clears Timer1 gate flip-flop
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 67
PIC12F752/HV752
REGISTER 7-2:
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-x
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
R/W-0
R/W-0
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM: Timer1 Gate Toggle mode bit
1 = Timer1 Gate Toggle mode is enabled.
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single Pulse mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS<1:0>: Timer1 Gate Source Select bits
11 = SYNCC2OUT
10 = SYNCC1OUT
01 = Timer0 overflow output
00 = Timer1 gate pin
DS41576B-page 68
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 7-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
ANSELA
—
—
ANSA5
ANSA4
—
ANSA2
ANSA1
ANSA0
50
APFCON
—
—
—
T1GSEL
—
COG1SEL
COG1O1SEL
COG1O0SEL
46
CCP1CON
—
—
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF
20
PIE1
TMR1GIE
ADIE
—
—
—
HLTMR1IE
TMR2IE
TMR1IE
21
PIR1
TMR1GIF
ADIF
—
—
—
HLTMR1IF
TMR2IF
TMR1IF
23
—
—
RA5
RA4
RA3
RA2
RA1
RA0
INTCON
PORTA
DC1B<1:0>
CCP1M<3:0>
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TRISA
—
T1CON
TMR1CS<1:0>
T1GCON
TMR1GE
Legend:
*
—
T1GPOL
TRISA5
TRISA4
T1CKPS<1:0>
T1GTM
T1GSPM
83
48
59*
59*
TRISA3
TRISA2
TRISA1
TRISA0
48
Reserved
T1SYNC
—
TMR1ON
67
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
68
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Page provides register information.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 69
PIC12F752/HV752
NOTES:
DS41576B-page 70
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
8.0
TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
•
•
•
•
•
8-bit timer register (TMR2)
8-bit period register (PR2)
Interrupt on TMR2 match with PR2
Software programmable prescaler (1:1, 1:4, 1:16)
Software programmable postscaler (1:1 to 1:16)
See Figure 8-1 for a block diagram of Timer2.
8.1
Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (FOSC/4). The clock is fed into the
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescaler is then used to
increment the TMR2 register.
The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
00h and the PR2 register is set to FFh.
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned off by clearing
the TMR2ON bit to a ‘0’.
The Timer2 prescaler is controlled by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
• A write to TMR2 occurs.
• A write to T2CON occurs.
• Any device Reset occurs (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset).
Note:
TMR2 is not cleared when T2CON is
written.
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented
The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
FIGURE 8-1:
FOSC/4
TIMER2 BLOCK DIAGRAM
Prescaler
1:1, 1:4, 1:16
2
TMR2
Comparator
Reset
TMR2 Output
Postscaler
1:1 to 1:16
EQ
Sets Flag bit TMR2IF
T2CKPS<1:0>
4
PR2
TOUTPS<3:0>
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 71
PIC12F752/HV752
8.2
Timer2 Control Registers
REGISTER 8-1:
T2CON: TIMER 2 CONTROL REGISTER
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
TOUTPS<3:0>
R/W-0
R/W-0
TMR2ON
R/W-0
T2CKPS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Postscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
TABLE 8-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 7
INTCON
PIE1
PIR1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 0
Register on
Page
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF
20
ADIE
—
—
—
HLTMR1IE
TMR2IE
TMR1IE
21
TMR1GIF
ADIF
—
—
—
HLTMR1IF
TMR2IF
TMR1IF
TMR2
Holding Register for the 8-bit TMR2 Register
—
*
Bit 1
GIE
Timer2 Module Period Register
Legend:
Bit 2
TMR1GIE
PR2
T2CON
x = Bit is unknown
23
71*
71*
TOUTPS<3:0>
TMR2ON
T2CKPS<1:0>
72
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
Page provides register information.
DS41576B-page 72
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
9.0
HARDWARE LIMIT TIMER (HLT)
MODULE
The HLT module incorporates the following features:
• 8-bit Read-Write Timer Register (HLTMR1)
• 8-bit Read-Write Period register (HLTPR1)
• Software programmable prescaler:
- 1:1
- 1:4
- 1:16
• Software programmable postscaler
- 1:1 to 1:16, inclusive
• Interrupt on HLTMR1 match with HLTPR1
• 8 selectable timer Reset inputs (5 reserved)
• Reset on rising and falling event
The Hardware Limit Timer (HLT) module is a version of
the Timer2-type modules. In addition to all the Timer2type features, the HLT can be reset on rising and falling
events from selected peripheral outputs.
The HLT primary purpose is to act as a timed hardware
limit to be used in conjunction with asynchronous
analog feedback applications. The external reset
source synchronizes the HLTMR1 to an analog
application.
In normal operation, the external reset source from the
analog application should occur before the HLTMR1
matches the HLTPR1. This resets HLTMR1 for the next
period and prevents the HLTimer1 Output from going
active.
Refer to Figure 9-1 for a block diagram of the HLT.
When the external reset source fails to generate a
signal within the expected time, (allowing the HLTMR1
to match the HLTPR1), then the HLTimer1 Output
becomes active.
FIGURE 9-1:
HLTMR1 BLOCK DIAGRAM
CCP1 out
C1OUT
C2OUT
COG1FLT
COG1OUT0
COG1OUT1
‘0’
‘0’
H1ERS<2:0>
FOSC/4
H1ON
000
H1REREN
Detect
Detect
H1FEREN
111
3
Prescaler
1:1, 1:4, 1:16
2
Reset
HLTMR1
Comparator
EQ
Postscaler
1:1 to 1:16
HLTimer1 Output
(to COG module)
Sets Flag bit HLTMR1IF
H1CKPS<1:0>
HLTPR1
4
H1OUTPS<3:0>
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 73
PIC12F752/HV752
9.1
HLT Operation
9.3
The clock input to the HLT module is the system
instruction clock (FOSC/4). HLTMR1 increments on
each rising clock edge.
A 4-bit counter/prescaler on the clock input provides the
following prescale options:
• Direct input
• Divide-by-4
• Divide-by-16
The prescale options are selected by the prescaler
control bits, H1CKPS<1:0> of the HLT1CON0 register.
The value of HLTMR1 is compared to that of the Period
register, HLTPR1, on each clock cycle. When the two
values match,then the comparator generates a match
signal as the HLTimer1 output. This signal also resets
the value of HLTMR1 to 00h on the next clock rising
edge and drives the output counter/postscaler (see
Section 9.2 “HLT Interrupt”).
The HLTMR1 and HLTPR1 registers are both directly
readable and writable. The HLTMR1 register is cleared
on any device Reset, whereas the HLTPR1 register
initializes to FFh. Both the prescaler and postscaler
counters are cleared on any of the following events:
•
•
•
•
•
•
•
•
•
A write to the HLTMR1 register
A write to the HLT1CON0 register
Power-on Reset (POR)
Brown-out Reset (BOR)
MCLR Reset
Watchdog Timer (WDT) Reset
Stack Overflow Reset
Stack Underflow Reset
RESET Instruction
Note:
Resets driven from the selected peripheral output prevents the HLTMR1 from matching the HLTPR1 register
and generating an output. In this manner, the HLT can
be used as a hardware time limit to other peripherals.
In this device, the primary purpose of the HLT is to limit
the COG PWM duty cycle. Normally, the COG operation uses analog feedback to determine the PWM duty
cycle. The same feedback signal is used as an HLT
Reset input. The HLTPR1 register is set to occur at the
maximum allowed duty cycle. If the analog feedback to
the COG exceeds the maximum time, then an
HLTMR1-to-HLTPR1 match will occur and generate the
output needed to limit the COG drive output.
The HLTMR1 can be reset by one of several selectable
peripheral sources. Reset inputs include:
• CCP1 output
• Comparator 1 output
• Comparator 2 output
The Reset input is selected with the H1ERS<2:0> bits
of the HLT1CON1 register.
HLTMR1 Resets are synchronous with the HLT clock.
In other words, HLTMR1 is cleared on the rising edge
of the HLT clock after the enabled Reset event occurs.
The Reset can be enabled to occur on the rising and
falling input event. Rising and falling event enables are
selected with the respective H1REREN and H1FEREN
bits of the HLT1CON1 register. External Resets do not
cause an HLTMR1 output event.
9.4
HLTMR1 is not cleared when HLT1CON0 is
written.
HLT Interrupt
The HLT can also generate an optional device interrupt.
The HLTMR1 output signal (HLTMR1-to-HLTPR1
match) provides the input for the 4-bit counter/
postscaler. The overflow output of the postscaler sets
the HLTMR1IF bit of the PIR1 register. The interrupt is
enabled by setting the HLTMR1 Match Interrupt Enable
bit, HLTMR1IE of the PIE1 register.
HLTimer1 Output
The unscaled output of HLTMR1 is available only to the
COG module, where it is used as a selectable limit to
the maximum COG period.
9.5
9.2
Peripheral Resets
HLT Operation During Sleep
The HLT cannot be operated while the processor is in
Sleep mode. The contents of the HLTMR1 register will
remain unchanged while the processor is in Sleep
mode.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, H1OUTPS<3:0>, of the HLT1CON0 register.
DS41576B-page 74
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
9.6
HLT Control Registers
REGISTER 9-1:
U-0
HLT1CON0: HLT1 CONTROL REGISTER 0
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
H1OUTPS<3:0>
R/W-0/0
R/W-0/0
H1ON
bit 7
R/W-0/0
H1CKPS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
H1OUTPS<3:0>: Hardware Limit Timer 1 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Postscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2
H1ON: Hardware Limit Timer 1 On bit
1 = Timer is on
0 = Timer is off
bit 1-0
H1CKPS<1:0>: Hardware Limit Timer 1 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 75
PIC12F752/HV752
REGISTER 9-2:
HLT1CON1: HLT1 CONTROL REGISTER 1
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
H1ERS<2:0>
R/W-0/0
R/W-0/0
H1FEREN
H1REREN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-2
H1ERS<2:0>: Hardware Limit Timer 1 Peripheral Reset Select bits
000 = CCP1 Out
001 = C1OUT
010 = C2OUT
011 = COG1FLT
100 = COG1OUT0
101 = COG1OUT1
110 = Reserved - ‘0’ input
111 = Reserved - ‘0’ input
bit 1
H1FEREN: Hardware Limit Timer 1 Falling Edge Reset Enable bit
1 = HLTMR1 will reset on the first clock after a falling edge of selected Reset source
0 = Falling edges of selected source have no effect
bit 0
H1REREN: Hardware Limit Timer 1 Rising Edge Reset Enable bit
1 = HLTMR1 will reset on the first clock after a rising edge of selected Reset source
0 = Rising edges of selected source have no effect
TABLE 9-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH HLT
Bit 7
Bit 6
CCP1CON
—
—
CM1CON0
C1ON
C1OUT
CM1CON1
C1INTP
C1INTN
CM2CON0
C2ON
C2OUT
Bit 5
Bit 4
C1POL
C1PCH<1:0>
C2OE
C2POL
Register
on Page
C1HYS
C1SYNC
127
—
—
C1NCH0
128
C2SP
C2HYS
C2SYNC
127
C2NCH0
128
Bit 2
C1ZLF
C1SP
—
C2ZLF
DC1B<1:0>
C1OE
Bit 0
Bit 3
Bit 1
CCP1M<3:0>
83
C2INTP
C2INTN
—
—
—
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF
20
PIE1
TMR1GIE
ADIE
—
—
—
HLTMR1IE
TMR2IE
TMR1IE
21
PIR1
TMR1GIF
ADIF
—
—
—
HLTMR1IF
TMR2IF
TMR1IF
23
CM2CON1
INTCON
C2PCH<1:0>
HLTMR1
Holding Register for the 8-bit Hardware Limit Timer1 Register
73*
HLTPR1
HLTMR1 Module Period Register
73*
HLT1CON0
—
HLT1CON1
—
Legend:
*
H1OUTPS<3:0>
—
—
H1ON
H1ERS<2:0>
H1CKPS<1:0>
H1FEREN
H1REREN
75
76
— = unimplemented location, read as ‘0’. Shaded cells do not affect the HLT module operation.
Page provides register information.
DS41576B-page 76
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
10.0
CAPTURE/COMPARE/PWM
MODULES
10.1.2
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events, and to generate Pulse-Width Modulation
(PWM) signals. In Capture mode, the peripheral allows
the timing of the duration of an event. The Compare
mode allows the user to trigger an external event when
a predetermined amount of time has expired. The
PWM mode can generate Pulse-Width Modulated
signals of varying frequency and duty cycle.
10.1
Capture Mode
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCP1 pin, the
16-bit CCPR1H:CCPR1L register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the CCP1M<3:0> bits of
the CCP1CON register:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
Figure 10-1 shows a simplified diagram of the Capture
operation.
10.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit.
Note:
If the CCP1 pin is configured as an output,
a write to the port can cause a capture
condition.
FIGURE 10-1:
Prescaler
 1, 4, 16
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP1 module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
See Section 7.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
10.1.3
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit of the PIE2 register clear to
avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR2 register
following any change in Operating mode.
Note:
10.1.4
When a capture is made, the Interrupt Request Flag bit
CCP1IF of the PIR2 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPR1H, CCPR1L register pair
is read, the old captured value is overwritten by the new
captured value.
TIMER1 MODE RESOURCE
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCP1
pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
CCP1 PRESCALER
There are four prescaler settings specified by the
CCP1M<3:0> bits of the CCP1CON register.
Whenever the CCP1 module is turned off, or the CCP1
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCP1CON register before changing the
prescaler. Example 10-1 demonstrates the code to
perform this function.
EXAMPLE 10-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCP1CON
CLRF
MOVLW
MOVWF
;Set Bank bits to point
;to CCP1CON
CCP1CON
;Turn CCP1 module off
NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP1 ON
CCP1CON
;Load CCP1CON with this
;value
Set Flag bit CCP1IF
(PIR2 register)
CCP1
pin
CCPR1H
and
Edge Detect
CCPR1L
Capture
Enable
TMR1H
TMR1L
CCP1M<3:0>
System Clock (FOSC)
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 77
PIC12F752/HV752
10.1.5
CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. If the Timer1 clock input source is a
clock that is not disabled during Sleep, Timer1 will continue to operate and Capture mode will operate during
Sleep to wake the device. The T1CKI is an example of
a clock source that will operate during Sleep.
When the input source to Timer1 is disabled during
Sleep, such as the HFINTOSC, Timer1 will not increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
TABLE 10-1:
Name
CCP1CON
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Bit 7
Bit 6
—
—
Bit 5
Bit 4
DC1B<1:0>
CCPR1L
Capture/Compare/PWM Register x Low Byte (LSB)
CCPR1H
Capture/Compare/PWM Register x High Byte (MSB)
INTCON
PIE1
Bit 3
Bit 2
Bit 1
Bit 0
CCP1M<3:0>
Register
on Page
83
77
77
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF
20
TMR1GIE
ADIE
—
—
—
HLTMR1IE
TMR2IE
TMR1IE
21
PIE2
—
—
C2IE
C1IE
—
COG1IE
—
CCP1IE
22
PIR1
TMR1GIF
ADIF
—
—
—
HLTMR1IF
TMR2IF
TMR1IF
23
PIR2
—
—
C2IF
C1IF
—
COG1IF
—
CCP1IF
24
T1CON
TMR1CS<1:0>
Reserved
T1SYNC
—
TMR1ON
67
T1GGO/
DONE
T1GVAL
T1GCON
TMR1GE
T1GPOL
T1CKPS<1:0>
T1GTM
T1GSPM
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TRISA
—
—
TRISA5
TRISA4
TRISA3(1)
TRISA2
T1GSS<1:0>
68
59*
59*
TRISA1
TRISA0
48
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.
* Page provides register information.
Note 1: TRISA3 always reads ‘1’.
DS41576B-page 78
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
10.2
Compare Mode
10.2.2
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPR1H:CCPR1L
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
•
•
•
•
•
Toggle the CCP1 output
Set the CCP1 output
Clear the CCP1 output
Generate a Special Event Trigger
Generate a Software Interrupt
TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section 7.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
Note:
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register. At
the same time, the interrupt flag CCP1IF bit is set.
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCP1
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
All Compare modes can generate an interrupt.
10.2.3
Figure 10-2 shows a simplified diagram of the
Compare operation.
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
register).
FIGURE 10-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
10.2.4
Set CCP1IF Interrupt Flag
(PIR2)
4
CCPR1H CCPR1L
Q
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
Special Event Trigger
10.2.1
SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCP1M<3:0> = 1011), the CCP1 module does the
following:
CCP1M<3:0>
Mode Select
CCP1
Pin
SOFTWARE INTERRUPT MODE
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the associated TRIS bit.
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
The CCP1 module does not assert control of the CCP1
pin in this mode.
The Special Event Trigger output of the CCP1 occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset
until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an A/D conversion (if
the A/D module is enabled). This allows the CCPR1H,
CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1.
TABLE 10-2:
SPECIAL EVENT TRIGGER
Device
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the PORT I/O
data latch.
PIC12F752
PIC12HV752
CCP1
CCP1
Refer to Section 12.0 “Analog-to-Digital Converter
(ADC) Module” for more information.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 79
PIC12F752/HV752
10.2.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
TABLE 10-3:
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Name
Bit 7
Bit 6
CCP1CON
—
—
Bit 5
Bit 4
Bit 3
DC1B<1:0>
Capture/Compare/PWM Register 1 Low Byte (LSB)
CCPR1H
Capture/Compare/PWM Register 1 High Byte (MSB)
GIE
PEIE
T0IE
Bit 1
Bit 0
CCP1M<3:0>
CCPR1L
INTCON
Bit 2
Register
on Page
83
77
77
INTE
IOCIE
T0IF
INTF
IOCIF
20
PIE1
TMR1GIE
ADIE
—
—
—
HLTMR1IE
TMR2IE
TMR1IE
20
PIE2
—
—
C2IE
C1IE
—
COG1IE
—
CCP1IE
20
PIR1
TMR1GIF
ADIF
—
—
—
HLTMR1IF
TMR2IF
TMR1IF
20
PIR2
—
—
C2IF
C1IF
—
COG1IF
—
CCP1IF
20
Reserved
T1SYNC
—
TMR1ON
67
T1GGO/DONE
T1GVAL
T1CON
T1GCON
TMR1CS<1:0>
TMR1GE
T1GPOL
T1CKPS<1:0>
T1GTM
T1GSPM
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TRISA
—
—
TRISA5
TRISA4
TRISA3(1)
TRISA2
T1GSS<1:0>
68
59*
59*
TRISA1
TRISA0
48
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
* Page provides register information.
Note 1: TRISA3 always reads ‘1’.
DS41576B-page 80
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
10.3
PWM Overview
FIGURE 10-3:
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
CCP1 PWM OUTPUT
SIGNAL
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPR1H:CCP1CON<5:4>
TMR2 = 0
FIGURE 10-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
Duty Cycle Registers
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
CCPR1H(2) (Slave)
CCP1CON<5:4>
CCPR1L
CCP1
R
Comparator
TMR2
(1)
Q
S
Figure 10-3 shows a typical waveform of the PWM
signal.
TRIS
Comparator
10.3.1
STANDARD PWM OPERATION
The standard PWM mode generates a Pulse-Width
modulation (PWM) signal on the CCP1 pin with up to 10
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
•
•
•
•
PR2
Note 1:
PR2 registers
T2CON registers
CCPR1L registers
CCP1CON registers
2:
Clear Timer,
toggle CCP1 pin and
latch duty cycle
The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
In PWM mode, CCPR1H is a read-only register.
Figure 10-4 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCP1 pin.
2: Clearing the CCP1CON register will
relinquish control of the CCP1 pin.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 81
PIC12F752/HV752
10.3.2
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP1 module for standard PWM operation:
1.
2.
3.
4.
5.
6.
Disable the CCP1 pin output driver by setting
the associated TRIS bit.
Load the PR2 register with the PWM period
value.
Configure the CCP1 module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
Load the CCPR1L register and the DC1B<1:0>
bits of the CCP1CON register, with the PWM
duty cycle value.
Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register. See Note below.
• Configure the T2CKPS bits of the T2CON
register with the Timer prescale value.
• Enable the Timer by setting the TMR2ON
bit of the T2CON register.
Enable PWM output pin:
• Wait until the Timer overflows and the
TMR2IF bit of the PIR1 register is set. See
Note below.
• Enable the CCP1 pin output driver by clearing the associated TRIS bit.
Note:
10.3.3
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H.
Note:
10.3.4
The Timer postscaler (see Section 8.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR1L register and
DC1B<1:0> bits of the CCP1CON register. The
CCPR1L contains the eight MSbs and the DC1B<1:0>
bits of the CCP1CON register contain the two LSbs.
CCPR1L and DC1B<1:0> bits of the CCP1CON
register can be written to at any time. The duty cycle
value is not latched into CCPR1H until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR1H
register is read-only.
Equation 10-2 is used to calculate the PWM pulse
width.
Equation 10-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 10-2:
PULSE WIDTH
Pulse Width =  CCPR1L:CCP1CON<5:4>  
T OSC  (TMR2 Prescale Value)
PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 10-1.
EQUATION 10-1:
PWM PERIOD
PWM Period =   PR2  + 1   4  T OSC 
(TMR2 Prescale Value)
Note 1:
TOSC = 1/FOSC
EQUATION 10-3:
DUTY CYCLE RATIO
 CCPRxL:CCPxCON<5:4> 
Duty Cycle Ratio = ----------------------------------------------------------------------4  PRx + 1 
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR1H and
2-bit latch, then the CCP1 pin is cleared (see
Figure 10-4).
DS41576B-page 82
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
10.4
CCP Control Registers
REGISTER 10-1:
U-0
CCP1CON: CCP1 CONTROL REGISTER
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
DC1B<1:0>
—
R/W-0/0
R/W-0/0
R/W-0/0
CCP1M<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M<3:0>: CCP1 Mode Select bits
0000 =
0001 =
0010 =
0011 =
Capture/Compare/PWM off (resets CCP1 module)
Reserved
Compare mode: toggle output on match
Reserved
0100 =
0101 =
0110 =
0111 =
Capture mode: every falling edge
Capture mode: every rising edge
Capture mode: every 4th rising edge
Capture mode: every 16th rising edge
1000 =
1001 =
1010 =
1011 =
Compare mode: initialize CCP1 pin low; set output on compare match (set CCP1IF)
Compare mode: initialize CCP1 pin high; clear output on compare match (set CCP1IF)
Compare mode: generate software interrupt only; CCP1 pin reverts to I/O state
Compare mode: Special Event Trigger (CCP1 resets Timer, sets CCP1IF bit, and starts A/D conversion
if A/D module is enabled)
11xx = PWM mode
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 83
PIC12F752/HV752
NOTES:
DS41576B-page 84
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
11.0
11.1
COMPLEMENTARY OUTPUT
GENERATOR (COG) MODULE
The primary purpose of the Complementary Output
Generator (COG) is to convert a single output PWM signal into a two output complementary PWM signal. The
COG can also convert two separate input events into a
single or complementary PWM output.
The COG PWM frequency and duty cycle are determined by a rising event input and a falling event input.
The rising event and falling event may be the same
source. Sources may be synchronous or asynchronous
to the COG_clock.
The rate at which the rising event occurs determines
the PWM frequency. The time from the rising event
input to the falling event input determines the duty
cycle.
A selectable clock input is used to generate the phase
delay, blanking and dead-band times.
A simplified block diagram of the COG is shown in
Figure 11-1.
The COG module has the following features:
•
•
•
•
•
•
•
•
Selectable clock source
Selectable rising event source
Selectable falling event source
Selectable edge or level event sensitivity
Independent output enables
Independent output polarity selection
Phase delay
Dead-band control with independent rising and
falling event dead-band times
• Blanking control with independent rising and falling event blanking times
• Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
Fundamental Operation
The COG generates a two output complementary
PWM waveform from rising and falling event sources.
In the simplest configuration, the rising and falling
event sources are the same signal, which is a PWM
signal with the desired period and duty cycle. The COG
converts this single PWM input into a dual complementary PWM output. The frequency and duty cycle of the
dual PWM output match those of the single input PWM
signal. The off-to-on transition of each output can be
delayed from the on-to-off transition of the other output,
thereby, creating a time immediately after the PWM
transition where neither output is driven. This is
referred to as dead time and is covered in Section 11.5
“Dead-Band Control”.
A typical operating waveform, with dead band, generated
from a single CCP1 input is signal is shown in Figure 11-2.
The COG can also generate a PWM waveform from a
periodic rising event and a separate falling event. In
this case, the falling event is usually derived from
analog feedback within the external PWM driver circuit.
In this configuration, high power switching transients
may trigger a false falling event that needs to be
blanked out. The COG can be configured to blank
falling (and rising) event inputs for a period of time
immediately following the rising (and falling) event drive
output. This is referred to as input blanking and is
covered in Section 11.6 “Blanking Control”.
It may be necessary to guard against the possibility of
circuit faults. In this case, the active drive must be terminated before the Fault condition causes damage.
This is referred to as auto-shutdown and is covered in
Section 11.8 “Auto-shutdown Control”.
A feedback falling event arriving too late or not at all o
can be terminated with auto-shutdown or by using one
of the event inputs that is logically OR’d with the hardware limit timer (HLT). See Section 9.0 “Hardware
Limit Timer (HLT) Module” for more information about
the HLT.
The COG can be configured to operate in phase
delayed conjunction with another PWM. The active
drive cycle is delayed from the rising event by a phase
delay timer. Phase delay is covered in more detail in
Section 11.7 “Phase Delay”.
A typical operating waveform, with phase delay and
dead band, generated from a single CCP1 input is
shown in Figure 11-3.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 85
SIMPLIFIED COG BLOCK DIAGRAM
HFINTOSC
10
Fosc/4
Fosc
01
COG_clock
00
GxCS<1:0>
HLTimer1 or COGxFLT
HLTimer1 or CCP1
HLTimer1 or C2OUT
HLTimer1 or C1OUT
COGxFLT
CCP1
C2OUT
C1OUT
7
6
5
4
3
2
1
0
Preliminary
HLTimer1 or COGxFLT
HLTimer1 or CCP1
HLTimer1 or C2OUT
HLTimer1 or C1OUT
COGxFLT
CCP1
C2OUT
C1OUT
Rising event source
Phase
Delay
Blanking
=
Cnt/R
7
6
5
4
3
2
1
0
GxFS0<2:0>
 2011 Microchip Technology Inc.
COGxFLT
GxASDSFLT
C1OUT
GxASDSC1
C2OUT
GxASDSC2
HLTimer1 output
GxASDSHLT
Write GxASDE High
1
Reset Dominates
Dead Band
Cnt/R
=
GxOE0
GxOUT0SS
1
COG1OUT0
0
S Q
0
GxPOL0
R Q
GxBLKF<3:0>
GxRS0<2:0>
GxDBR<3:0>
GxPH<3:0>
GxRSIM
GxOE1
GxDBF<3:0>
Falling event source
1
Blanking
=
Cnt/R
0
GxBLKR<3:0>
GxFSIM
Dead Band
Cnt/R
=
GxOUT1SS
1
COG1OUT1
0
GxPOL1
S
D Q
GxEN
Auto-shutdown source
GxARSEN
Write GxASDE Low
S Q
R
Set Dominates
GxASDE
PIC12F752/HV752
DS41576B-page 86
FIGURE 11-1:
PIC12F752/HV752
FIGURE 11-2:
TYPICAL COG OPERATION WITH CCP1
COG_clock
Source
CCP1
COGxOUT0
Rising Source Dead Band
Falling Source Dead Band
Falling Source Dead Band
COGxOUT1
FIGURE 11-3:
COG OPERATION WITH CCP1 AND PHASE DELAY
COG_clock
Source
CCP1
COGxOUT0
Rising Source Dead Band
Falling Source Dead Band
Phase Delay
COGxOUT1
 2011 Microchip Technology Inc.
Preliminary
Falling Source Dead
Band
DS41576B-page 87
PIC12F752/HV752
11.2
Clock Sources
FIGURE 11-4:
The COG_clock is used as the reference clock to the
various timers in the peripheral. Timers that use the
COG_clock include:
EDGE VS LEVEL SENSE
Rising (CCP1)
Falling (C1OUT)
• Rising and falling dead-band time
• Rising and falling blanking time
• Rising event phase delay
hyst
C1INCOGOUT
Clock sources available for selection include:
• 8 MHz HFINTOSC
• Instruction clock (Fosc/4)
• System clock (Fosc)
Edge Sensitive
Rising (CCP1)
The clock source is selected with the GxCS<1:0> bits
of the COGxCON0 register (Register 11-1).
Falling (C1OUT)
11.3
C1IN-
Selectable Event Sources
The COG uses two independently selectable event
sources to generate the complementary waveform:
hyst
COGOUT
• Rising event source
• Falling event source
Level or edge sensitive modes are available for each
event input.
The rising event source is selected with the GxRS<2:0>
bits and the mode is controlled with the GxRSIM bit.
The falling event source is selected with the GxFS<2:0>
bits and the mode is controlled with the GxFSIM bit.
Selection and mode control bits for both sources are
located in the COGxCON1 register (Register 11-2).
11.3.1
EDGE VS. LEVEL SENSING
Event input detection may be selected as level or edge
sensitive. In general, events that are driven from a periodic source should be edge detected and events that
are derived from voltage thresholds at the target circuit
should be level sensitive. Consider the following two
examples:
1. The first example is an application in which the
period is determined by a 50% duty cycle clock and the
COG output duty cycle is determined by a voltage level
fed back through a comparator. If the clock input is level
sensitive then duty cycles less than 50% will exhibit
erratic operation.
2. The second example is similar to the first except that
the duty cycle is close to 100%. The feedback comparator high-to-low transition trips the COG drive off but
almost immediately the period source turns the drive
back on. If the off cycle is short enough then the comparator input may not reach the low side of the hysteresis band precluding an output change. The
comparator output stays low and without a high-to-low
transition to trigger the edge sense then the drive of the
COG output will be stuck in a constant drive-on condition. See Figure 11-4.
DS41576B-page 88
11.3.2
RISING EVENT
The rising event starts the PWM output active duty
cycle period. The rising event is the low-to-high
transition of the selected rising event source. When the
phase delay and rising event dead-band time values
are zero, the COGxOUT0 output starts immediately.
Otherwise, the COGxOUT0 output is delayed. The
rising event causes all the following actions:
• Start rising event phase delay counter (if
enabled).
• Clear COGxOUT1 after phase delay.
• Start falling event input blanking (if enabled).
• Start dead-band counter (if enabled).
• Set COGxOUT0 output after dead-band counter
expires.
11.3.3
FALLING EVENT
The falling event terminates the PWM output active duty
cycle period. The falling event is the high-to-low
transition of the selected falling event source. When the
falling event dead-band time value is zero, the
COGxOUT1 output starts immediately. Otherwise, the
COGxOUT1 output is delayed. The falling event causes
all the following actions:
•
•
•
•
Clear COGxOUT0.
Start rising event input blanking (if enabled).
Start falling event dead-band counter (if enabled).
Set COGxOUT1 output after dead-band counter
expires.
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
11.4
Output Control
11.5.1
RISING EVENT DEAD BAND
Immediately after the COG module is enabled, the
complementary drive is configured with COGxOUT0
drive cleared and COGxOUT1 drive active.
Rising event dead-band delays the turn-on of
COGxOUT0 from when COGxOUT1 is turned off. The
rising event dead-band time starts when the rising
event output goes true.
11.4.1
The rising event output into the dead-band counter
may be delayed by the phase delay. When the phase
delay time is zero, the rising event output goes true
coincident with the unblanked rising input event. When
the phase delay time is not zero, the rising event output goes true at the completion of the phase delay
time.
OUTPUT ENABLES
Each COG output pin has individual output enable
controls. Output enables are selected with the GxOE0
and GxOE1 bits of the COGxCON0 register. When an
output enable control is cleared, the module asserts
no control over the pin. When an output enable is set,
the override value or active PWM waveform is applied
to the pin per the port priority selection.
The output pin enables are independent of the module
enable bit, GxEN. When GxEN is cleared, the
shutdown override levels are present on the COG
output pins for which the output enables are active.
11.4.2
POLARITY CONTROL
The polarity of each COG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active low. Clearing the output
polarity bit configures the corresponding output as
active high. However, polarity does not affect the
override levels.
Output polarity is selected with the GxPOL0 and
GxPOL1 bits of the COGxCON0 register.
11.5
The rising event dead-band time is set by the value
contained in the GxDBR<3:0> bits of the COGxDB
register. When the value is zero, rising event dead
band is disabled.
11.5.2
The falling event dead-band time is set by the value
contained in the GxDBF<3:0> bits of the COGxDB
register. When the value is zero, falling event dead
band is disabled.
11.5.3
Dead-Band Control
The dead-band control provides for non-overlapping
PWM output signals to prevent shoot through current
in the external power switches.
The COG contains two 4-bit dead-band counters. One
dead-band counter is used for rising event dead-band
control. The other is used for falling event dead-band
control.
Dead band is timed by counting COG_clock periods
from zero up to the value in the dead-band count
register. Use Equation 11-1 to calculate dead-band
times.
FALLING EVENT DEAD BAND
Falling event dead-band delays the turn-on of
COGxOUT1 from when COGxOUT0 is turned off. The
falling event dead-band time starts when the falling
event output goes true. The falling event output goes
true coincident with the unblanked falling input event.
DEAD-BAND TIME UNCERTAINTY
When the rising and falling events that trigger the
dead-band counters come from asynchronous inputs,
it creates uncertainty in the dead-band time. The maximum uncertainty is equal to one COG_clock period.
Refer to Equation 11-1 for more detail.
11.5.4
DEAD-BAND OVERLAP
There are two cases of dead-band overlap:
• Rising-to-falling
• Falling-to-rising
11.5.4.1
Rising-to-Falling Overlap
In this case, the falling event occurs while the rising
event dead-band counter is still counting. When this
happens, the COGxOUT0 drive is suppressed and the
dead band extends by the falling event dead-band
time. At the termination of the extended dead-band
time, the COGxOUT1 drive goes true.
11.5.4.2
Falling-to-Rising Overlap
In this case, the rising event occurs while the falling
event dead-band counter is still counting. When this
happens, the COGxOUT1 drive is suppressed and the
dead band extends by the rising event dead-band
time. At the termination of the extended dead-band
time, the COGxOUT0 drive goes true.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 89
PIC12F752/HV752
11.6
Blanking Control
11.7
Input blanking is a function whereby the event inputs
can be masked or blanked for a short period of time.
This is to prevent electrical transients caused by the
turn-on/off of power components from generating a
false input event.
The COG contains two 4-bit blanking counters. The
counters are cross coupled with the events they are
blanking. The falling event blanking counter is used to
blank rising input events and the rising event blanking
counter is used to blank falling input events. Once
started, blanking extends for the time specified by the
corresponding blanking counter.
Blanking is timed by counting COG_clock periods from
zero up to the value in the blanking count register. Use
Equation 11-1 to calculate blanking times.
11.6.1
RISING EVENT INPUT BLANKING
The falling event blanking counter inhibits the rising
input from triggering a rising event. The falling event
blanking time starts when the falling event output drive
goes true.
The falling event blanking time is set by the value contained in the GxBLKF<3:0> bits of the COGxBLK register. Blanking times are calculated using the formula
shown in Equation 11-1.
Phase Delay
It is possible to delay the assertion of the rising event.
This is accomplished by placing a non-zero value in
COGxPH register. Refer to Register 11-6 and
Figure 11-3 for COG operation with CCP1 and phase
delay. The delay from the input rising event signal
switching to the actual assertion of the events is calculated the same as the dead-band and blanking delays.
Please see Equation 11-1.
When the COGxPH value is zero, phase delay is disabled and the phase delay counter output is true,
thereby, allowing the event signal to pass straight
through to complementary output driver flop.
11.7.1
CUMULATIVE UNCERTAINTY
It is not possible to create more than one COG_clock of
uncertainty by successive stages. Consider that the
phase delay stage comes after the blanking stage, the
dead-band stage comes after either the blanking or
phase delay stages, and the blanking stage comes
after the dead-band stage. When the preceding stage
is enabled, the output of that stage is necessarily
synchronous with the COG_clock, which removes any
possibility of uncertainty in the succeeding stage.
EQUATION 11-1:
When the GxBLKF<3:0> value is zero, falling event
blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
through to the event trigger circuit.
11.6.2
The rising event blanking time is set by the value
contained in the GxBLKR<3:0> bits of the COGxBLK
register.
When the GxBLKR<3:0> value is zero, rising event
blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
through to the event trigger circuit.
11.6.3
T min = Count
F COG_clock
FALLING EVENT INPUT BLANKING
The rising event blanking counter inhibits the falling
input from triggering a falling event. The rising event
blanking time starts when the rising event output drive
goes true.
Count + 1
T max = -------------------------F COG_clock
T uncertainty = T max – T min
Also:
1
T uncertainty = -------------------------F COG_clock
Where:
T
Count
Phase Delay
GxPH<3:0>
Rising Dead Band
BLANKING TIME UNCERTAINTY
When the rising and falling events that trigger the
blanking counters are asynchronous to the
COG_clock, it creates uncertainty in the blanking time.
The maximum uncertainty is equal to one COG_clock
period. Refer to Equation 11-1 and Example 11-1 for
more detail.
DS41576B-page 90
PHASE, DEAD-BAND,
AND BLANKING TIME
CALCULATION
GxDBR<3:0>
Falling Dead Band
GxDBF<3:0>
Rising Event Blanking
GxBLKR<3:0>
Falling Event Blanking
GxBLKF<3:0>
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
EXAMPLE 11-1:
Given:
TIMER UNCERTAINTY
Count = Ah = 10d
F COG_Clock = 8MHz
Therefore:
1
T uncertainty = -------------------------F COG_clock
1
= --------------- = 125ns
8MHz
Proof:
Count
T min = -------------------------FCOG_clock
= 125ns  10d = 1.25s
Count + 1
T max = -------------------------FCOG_clock
= 125ns   10d + 1 
= 1.375s
Therefore:
T uncertainty = T max – T min
= 1.375s – 1.25s
= 125ns
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 91
PIC12F752/HV752
11.8
Auto-shutdown Control
11.8.2
Auto-shutdown is a method to immediately override
the COG output levels with specific overrides that
allow for safe shutdown of the circuit.
The shutdown state can be either cleared automatically or held until cleared by software.
11.8.1
SHUTDOWN
The shutdown state can be entered by either of the
following two mechanisms:
• Software generated
• External Input
11.8.1.1
Note:
The polarity control does not apply to the
override level.
AUTO-SHUTDOWN RESTART
After an auto-shutdown event has occurred, there are
two ways to have the module resume operation:
Software Generated Shutdown
When auto-restart is disabled, the shutdown state will
persist as long as the GxASDE bit is set.
When auto-restart is enabled, the GxASDE bit will
clear automatically and resume operation on the next
rising event. See Figure 11-5.
External Shutdown Source
External shutdown inputs provide the fastest way to
safely suspend COG operation in the event of a fault
condition. When any of the selected shutdown inputs
goes true, the output drive latches are reset and the
COG outputs will immediately go to the selected override levels without software delay.
Any combination of four input sources can be selected
to cause a shutdown condition. The four sources
include:
•
•
•
•
The levels driven to the output pins, while the shutdown input is true, are controlled by the GxASDL0 and
GxASDL1
bits
of
the
COGxASD
register
(Register 11-3). GxASDL0 controls the GxOUT0 override level and GxASDL1 controls the GxOUT1 override level. The control bit logic level corresponds to the
output logic drive level while in the shutdown state.
11.8.3
Setting the GxASDE bit of the COGxASD register will
force the COG into the shutdown state.
11.8.1.2
PIN OVERRIDE LEVELS
HLTimer1 output
C2OUT (low true)
C1OUT (low true)
COG1FLT pin (low true)
• Software controlled
• Auto-restart
The restart method is selected with the GxARSEN bit
of the COGxASD register. Waveforms of a software
controlled automatic restart are shown in Figure 11-5.
11.8.3.1
Software Controlled Restart
When the GxARSEN bit of the COGxASD register is
cleared, the COG must be restarted after an
auto-shutdown event by software.
The COG will resume operation on the first rising
event after the GxASDE bit is cleared. Clearing the
shutdown state requires all selected shutdown inputs
to be false, otherwise, the GxASDE bit will remain set.
11.8.3.2
Auto-Restart
When the GxARSEN bit of the COGxASD register is
set then the COG will restart from the auto-shutdown
state automatically.
The GxASDE bit will clear automatically and the COG
will resume operation on the first rising event after all
selected shutdown inputs go false.
Shutdown inputs are selected independently with bits
<3:0> of the COGxASD register (Register 11-3).
Note:
Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state cannot
be cleared as long as the shutdown input
level persists, except by disabling
auto-shutdown,
DS41576B-page 92
Preliminary
 2011 Microchip Technology Inc.
FIGURE 11-5:
2
3
4
5
CCP1
GxARSEN
Next rising event
Shutdown input
Next rising event
Preliminary
GxASDE
Cleared in hardware
Cleared in software
GxASDL0
GxASDL1
COGxOUT1
Operating State
NORMAL OUTPUT
SHUTDOWN
NORMAL OUTPUT
SOFTWARE CONTROLLED RESTART
SHUTDOWN
NORMAL OUTPUT
AUTO-RESTART
DS41576B-page 93
PIC12F752/HV752
COGxOUT0
AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT
SOURCE
 2011 Microchip Technology Inc.
1
PIC12F752/HV752
11.9
Buffer updates
11.12 Configuring the COG
Changes to the phase, dead band, and blanking count
registers need to occur simultaneously during COG
operation to avoid unintended operation that may
occur as a result of delays between each register
write. This is accomplished with the GxLD bit of the
COGxCON0 register and double buffering of the
phase, blanking, and dead-band count registers.
Before the COG module is enabled, writing the count
registers loads the count buffers without need of the
GxLD bit. However, when the COG is enabled, the
count buffers updates are suspended after writing the
count registers until after the GxLD bit is set. When the
GxLD bit is set, the phase, dead band, and blanking
register values are transferred to the corresponding
buffers synchronous with COG operation. The GxLD
bit is cleared by hardware when the transfer is
complete.
11.10 Alternate Pin Selection
1.
2.
3.
4.
5.
6.
7.
The COGxOUT0, COGxOUT1 and COGxFLT functions can be directed to alternate pins with control bits
of the APFCON register. Refer to Register 5-1.
Note:
The following steps illustrate how to properly configure
the COG to ensure a synchronous start with the rising
event input:
8.
The default COG outputs have high drive
strength capability, whereas the alternate
outputs do not.
11.11 Operation During Sleep
The COG continues to operate in Sleep provided that
the COG_clock, rising event, and falling event sources
remain active.
9.
The HFINTSOC remains active during Sleep when the
COG is enabled and the HFINTOSC is selected as the
COG_clock source.
10.
11.
12.
13.
DS41576B-page 94
Preliminary
Configure the desired COGxFLT input,
COGxOUT0 and COGxOUT1 pins with the corresponding bits in the APFCON register.
Clear all ANSELA register bits associated with
pins that are used for COG functions.
Ensure that the TRIS control bits corresponding
to COGxOUT0 and COGxOUT1 are set so that
both are configured as inputs. These will be set
as outputs later.
Clear the GxEN bit, if not already cleared.
Set desired dead-band times with the COGxDB
register.
Set desired blanking times with the COGxBLK
register.
Set desired phase delay with the COGxPH
register.
Setup the following controls in COGxASD
auto-shutdown register:
• Select desired shutdown sources.
• Select both output overrides to the desired
levels (this is necessary, even if not using
auto-shutdown because start-up will be from
a shutdown state).
• Set the GxASDE bit and clear the GxARSEN
bit.
Select the desired rising and falling event
sources and input modes with the COGxCON1
register.
Configure the following controls in COGxCON0
register:
• Select the desired clock source
• Select the desired output polarities
• Set the output enables of the outputs to be
used.
Set the GxEN bit.
Clear TRIS control bits corresponding to
COGxOUT0 and COGxOUT1 to be used,
thereby configuring those pins as outputs.
If auto-restart is to be used, set the GxARSEN bit
and the GxASDE will be cleared automatically.
Otherwise, clear the GxASDE bit to start the
COG.
 2011 Microchip Technology Inc.
PIC12F752/HV752
11.13 COG Control Registers
REGISTER 11-1:
COGxCON0: COG CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxEN
GxOE1
GxOE0
GxPOL1
GxPOL0
GxLD
R/W-0/0
bit 7
R/W-0/0
GxCS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
GxEN: COGx Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6
GxOE1: COGxOUT1 Output Enable bit
1 = COGxOUT1 is available on associated I/O pin
0 = COGxOUT1 is not available on associated I/O pin
bit 5
GxOE0: COGxOUT0 Output Enable bit
1 = COGxOUT0 is available on associated I/O pin
0 = COGxOUT0 is not available on associated I/O pin
bit 4
GxPOL1: COGxOUT1 Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 3
GxPOL0: COGxOUT0 Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 2
GxLD: COGx Load Buffers bit
1 = Phase, blanking, and dead-band buffers to be loaded with register values on next input events
0 = Register to buffer transfer is complete
bit 1-0
GxCS<1:0>: COGx Clock Source Select bits
11 = Reserved
10 = 8 MHz HFINTOSC clock
01 = Instruction clock (Fosc/4)
00 = System clock (Fosc)
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 95
PIC12F752/HV752
REGISTER 11-2:
R/W-0/0
COGxCON1: COG CONTROL REGISTER 1
R/W-0/0
GxFSIM
GxRSIM
R/W-0/0
R/W-0/0
R/W-0/0
GxFS<2:0>
R/W-0/0
R/W-0/0
R/W-0/0
GxRS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
GxFSIM: COGx Falling Source Input mode bit
1 = Input is edge sensitive
0 = Input is level sensitive
bit 6
GxRSIM: COGx Rising Source Input mode bit
1 = Input is edge sensitive
0 = Input is level sensitive
bit 5-3
GxFS<2:0>: COGx Falling Source Select bits
111 = COGxFLT or HLTimer1
110 = CCP1 or HLTimer1
101 = C2OUT or HLTimer1
100 = C1OUT or HLTimer1
011 = COGxFLT
010 = CCP1
001 = C2OUT
000 = C1OUT
bit 2-0
GxRS<2:0>: COGx Rising Source Select bits
111 = COGxFLT or HLTimer1
110 = CCP1 or HLTimer1
101 = C2OUT or HLTimer1
100 = C1OUT or HLTimer1
011 = COGxFLT
010 = CCP1
001 = C2OUT
000 = C1OUT
DS41576B-page 96
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
REGISTER 11-3:
COGxASD: COG AUTO-SHUTDOWN CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxASDE
GxARSEN
GxASDL1
GxASDL0
GxASDSHLT
GxASDSC2
GxASDSC1
GxASDSFLT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
GxASDE: Auto-Shutdown Event Status bit
1 = COG is in the shutdown state
0 = COG is not in the shutdown state
bit 6
GxARSEN: Auto-Restart Enable bit
1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5
GxASDL1: COGxOUT1 Auto-shutdown Override Level bit
1 = A logic ‘1’ is placed on COGxOUT1 when a shutdown input is true
0 = A logic ‘0’ is placed on COGxOUT1 when a shutdown input is true
bit 4
GxASDL0: COGxOUT0 Auto-shutdown Override Level bit
1 = A logic ‘1’ is placed on COGxOUT0 when a shutdown input is true
0 = A logic ‘0’ is placed on COGxOUT0 when a shutdown input is true
bit 3
GxASDSHLT: COG Auto-shutdown Source Enable bit 3
1 = COG is shutdown when HLTMR equals HLTPR is low
0 = HLTimer1 pin has no effect on shutdown
bit 2
GxASDSC2: COG Auto-shutdown Source Enable bit 2
1 = COG is shutdown when C2OUT is low
0 = C2OUT pin has no effect on shutdown
bit 1
GxASDSC1: COG Auto-shutdown Source Enable bit 1
1 = COG is shutdown when C1OUT is low
0 = C1OUT pin has no effect on shutdown
bit 0
GxASDSFLT: COG Auto-shutdown Source Enable bit 0
1 = COG is shutdown when COGxFLT pin is low
0 = COGxFLT pin has no effect on shutdown
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 97
PIC12F752/HV752
REGISTER 11-4:
R/W-x/u
COGxDB: COG DEAD-BAND COUNT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxDBR<3:0>
R/W-x/u
R/W-x/u
GxDBF<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-4
GxDBR<3:0>: Rising Event Dead-band Count Value bits
= Number of COG clock periods to delay primary output after rising event input
bit 3-0
GxDBF<3:0>: Falling Event Dead-band Count Value bits
= Number of COG clock periods to delay complementary output after falling event input
REGISTER 11-5:
R/W-x/u
COGxBLK: COG BLANKING COUNT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxBLKR<3:0>
R/W-x/u
R/W-x/u
GxBLKF<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-4
GxBLKR<3:0>: Rising Event Blanking Count Value bits
= Number of COGx clock periods to inhibit falling event input
bit 3-0
GxBLKF<3:0>: Falling Event Blanking Count Value bits
= Number of COGx clock periods to inhibit rising event input
REGISTER 11-6:
U-0
COGxPH: COG PHASE COUNT REGISTER
U-0
—
—
U-0
—
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
GxPH<3:0>
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
GxPH<3:0>: Rising Event Phase Delay Count Value bits
= Number of COG clock periods to delay rising edge event
DS41576B-page 98
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 11-1:
Name
ANSELA
SUMMARY OF REGISTERS ASSOCIATED WITH COG
Bit 7
Bit 6
Bit 5
—
—
APFCON
—
—
COG1PH
—
—
Bit 2
Bit 1
Bit 0
Register
on Page
Bit 4
Bit 3
ANSA5
ANSA4
—
ANSA2
ANSA1
ANSA0
50
—
T1GSEL
—
COG1FSEL
COG1O1SEL
COG1O0SEL
46
—
—
G1PH<3:0>
98
COG1BLK
G1BLKR<3:0>
G1BLKF<3:0>
98
COG1DB
G1DBR<3:0>
G1DBF<3:0>
G1EN
G1OE1
COG1CON1
G1FSIM
G1RSIM
COG1ASD
G1ASDE
G1ARSEN
G1ASDL1
G1ASDL0
G1ASDSHLT
G1ASDSC2
G1ASDSC1
G1ASDSFLT
97
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF
20
LATA
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0
48
PIE2
—
—
C2IE
C1IE
—
COG1IE
—
CCP1IE
22
PIR2
—
—
C2IF
C1IF
—
COG1IF
—
CCP1IF
24
TRISA
—
—
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
48
INTCON
Legend:
Note 1:
2:
G1OE0
G1POL1
G1POL0
G1LD
98
COG1CON0
G1FS<2:0>
G1CS1
G1CS0
G1RS<2:0>
95
96
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by COG.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
See Configuration Word register (Register 17-1) for operation of all register bits.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 99
PIC12F752/HV752
NOTES:
DS41576B-page 100
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
12.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
Note:
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADRESL and ADRESH registers are
read-only.
The ADC voltage reference is software selectable to
either VDD or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 12-1 shows the block diagram of the ADC.
FIGURE 12-1:
ADC BLOCK DIAGRAM
VDD
VCFG = 0
VREF+
AN0
0000
AN1/VREF+
0001
AN2
0010
AN3
0011
dac_ref
1110
fvr_ref
1111
VCFG = 1
A/D
10
GO/DONE
ADFM
0 = Left Justify
1 = Right Justify
ADON
CHS<3:0>
 2011 Microchip Technology Inc.
10
Vss
Preliminary
ADRESH
ADRESL
DS41576B-page 101
PIC12F752/HV752
12.1
ADC Configuration
12.1.3
When configuring and using the ADC the following
functions must be considered:
•
•
•
•
•
•
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Results formatting
12.1.1
12.1.2
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
PORT CONFIGURATION
Analog voltages on any pin that is defined
as a digital input may cause the input buffer to conduct excess current.
CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 12.2
“ADC Operation” for more information.
DS41576B-page 102
The VCFG bit of the ADCON0 register provides control
of the positive voltage reference. The positive voltage
reference can be either VDD or an external voltage
source. The negative voltage reference is always
connected to the ground reference.
12.1.4
The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ANSEL bits. See the corresponding port
section for more information.
Note:
ADC VOLTAGE REFERENCE
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 12-2.
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
Section 20.0 “Electrical Specifications” for more
information. Table 12-1 gives examples of appropriate
ADC clock selections.
Note:
Preliminary
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 12-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD)
ADC Clock Source
Device Frequency (FOSC)
ADCS<2:0>
20 MHz
8 MHz
(2)
2.0 s
1.0 s(2)
4.0 s
2.0 s
8.0 s(3)
2.0 s
4.0 s
16.0 s(3)
4.0 s
8.0 s(3)
32.0 s(3)
FOSC/2
000
100 ns
100
200 ns(2)
500 ns(2)
001
400 ns
(2)
(2)
800 ns
(2)
FOSC/16
101
FOSC/32
010
500 ns
1.0 s
(3)
FOSC/64
110
3.2 s
FRC
x11
2-6 s(1,4)
Legend:
Note 1:
2:
3:
4:
250 ns
1.6 s
1 MHz
(2)
FOSC/4
FOSC/8
4 MHz
(2)
8.0 s
2-6 s(1,4)
(3)
16.0 s
64.0 s(3)
2-6 s(1,4)
2-6 s(1,4)
Shaded cells are outside of recommended range.
The FRC source has a typical TAD time of 4 s for VDD > 3.0V.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
FIGURE 12-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit
12.1.5
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
Note:
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 103
PIC12F752/HV752
12.1.6
RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 12-4 shows the two output formats.
FIGURE 12-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
10-bit A/D Result
Unimplemented: Read as ‘0’
MSB
(ADFM = 1)
bit 7
LSB
bit 0
Unimplemented: Read as ‘0’
12.2
12.2.1
12.2.2
ADC Operation
12.2.4
STARTING A CONVERSION
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 12.2.6 “A/D Conversion Procedure”.
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF flag bit
• Update the ADRESH:ADRESL registers with new
conversion result
12.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion. Additionally, a 2 TAD delay is required before another acquisition can be initiated. Following this delay, an input
acquisition is automatically started on the selected
channel.
Note:
bit 7
bit 0
10-bit A/D Result
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
bit 0
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present
conversion to be aborted and the ADC module is
turned off, although the ADON bit remains set.
12.2.5
SPECIAL EVENT TRIGGER
The CCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 counter resets to zero.
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
See
Section 10.0
“Capture/Compare/PWM
Modules” for more information.
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
DS41576B-page 104
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
12.2.6
A/D CONVERSION PROCEDURE
EXAMPLE 12-1:
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure Port:
• Disable pin output driver (See TRIS register)
• Configure pin as analog
Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Select result format
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result
Clear the ADC interrupt flag (required if interrupt
is enabled).
A/D CONVERSION
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and RA0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL TRISA
;
BSF
TRISA,0
;Set RA0 to input
BANKSEL ADCON1
;
MOVLW
B’01110000’ ;ADC Frc clock,
IORWF
ADCON1
; and RA0 as analog
BANKSEL ADCON0
;
MOVLW
B’10000001’ ;Right justify,
MOVWF
ADCON0
;Vdd Vref, AN0, On
CALL
SampleTime ;Acquisiton delay
BSF
ADCON0,GO
;Start conversion
TEST AGAIN
BTFSC
ADCON0,GO
;Is conversion done?
GOTO
TEST AGAIN ;No, test again
BANKSEL ADRESH
;
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF
RESULTHI
;Store in GPR space
BANKSEL ADRESL
;
MOVF
ADRESL,W
;Read lower 8 bits
MOVWF
RESULTLO
;Store in GPR space
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: See Section 12.4 “A/D Acquisition
Requirements”.
 2011 Microchip Technology Inc.
Preliminary
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PIC12F752/HV752
12.3
ADC Control Registers
REGISTER 12-1:
ADCON0: A/D CONTROL REGISTER 0
R/W-0
R/W-0
ADFM
VCFG
R/W-0
R/W-0
R/W-0
R/W-0
CHS<3:0>
R/W-0
R/W-0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
ADFM: A/D Conversion Result Format Select bit
1 = Right justified
0 = Left justified
bit 6
VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
bit 5-2
CHS<3:0>: Analog Channel Select bits
0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Reserved. Do not use.
•
•
•
1101 = Reserved. Do not use.
1110 = Digital-to-Analog Converter (DAC output)
1111 = Fixed Voltage Reference (FVR)
bit 1
GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
DS41576B-page 106
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
REGISTER 12-2:
U-0
ADCON1: A/D CONTROL REGISTER 1
R/W-0/0
—
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from an internal oscillator with a divisor of 16)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 3-0
Unimplemented: Read as ‘0’
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 107
PIC12F752/HV752
REGISTER 12-3:
R-x
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 12-4:
R-x
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY)
R-x
ADRES<1:0>
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
bit 5-0
Unimplemented: Read as ‘0’
REGISTER 12-5:
x = Bit is unknown
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY)
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R-x
R-x
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1-0
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 12-6:
R-x
x = Bit is unknown
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
x = Bit is unknown
ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
DS41576B-page 108
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
12.4
A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 12-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 12-4.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
EQUATION 12-1:
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 12-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k  5.0V V DD
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
1
V AP PLIE D  1 – ------------ = V CHOLD

2047
;[1] VCHOLD charged to within 1/2 lsb
–TC
----------

RC
V AP P LI ED  1 – e  = V CHOLD


;[2] VCHOLD charge response to VAPPLIED
– Tc
---------

1
RC
V AP P LIED  1 – e  = V A P PLIE D  1 – ------------

2047


;combining [1] and [2]
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 10pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.37 µs
Therefore:
T ACQ = 2µs + 1.37µs +   50°C- 25°C   0.05µs/°C  
= 4.67µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 109
PIC12F752/HV752
FIGURE 12-4:
ANALOG INPUT MODEL
VDD
ANx
Rs
Cpin
5 pF
VA
Vt = 0.6V
Vt = 0.6V
Ric £ 1k
Sampling
Switch
SS Rss
I leakage
± 500 nA
Chold = 10 pF
Vss/VREF-
Legend: Cpin
= Input Capacitance
Vt
= Threshold Voltage
I leakage = Leakage current at the pin due to
various junctions
Ric
= Interconnect Resistance
SS
= Sampling Switch
Chold
= Sample/Hold Capacitance
FIGURE 12-5:
6V
5V
VDD 4V
3V
2V
Rss
5 6 7 8 9 10 11
Sampling Switch
(kW)
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
1 LSB ideal
3FBh
Full-Scale
Transition
004h
003h
002h
001h
000h
Analog Input Voltage
1 LSB ideal
VSS/VREF-
DS41576B-page 110
Zero-Scale
Transition
Preliminary
VDD/VREF+
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 12-2:
Name
SUMMARY OF ASSOCIATED ADC REGISTERS
Bit 7
Bit 6
ADCON0
ADFM
VCFG
ADCON1
—
ANSELA
Bit 5
—
—
ANSA5
A/D Result Register High Byte
ADRESL(2)
A/D Result Register Low Byte
INTCON
Bit 3
Bit 2
CHS<3:0>
ADCS<2:0>
ADRESH(2)
PORTA
Bit 4
ANSA4
Bit 1
Bit 0
Register on
Page
GO/DONE
ADON
106
—
—
—
—
107
—
ANSA2
ANSA1
ANSA0
50
108*
106*
—
—
RA5
RA4
RA3
RA2
RA1
RA0
48
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF
20
PIE1
TMR1GIE
ADIE
—
—
—
HLTMR1IE
TMR2IE
TMR1IE
21
PIR1
TMR1GIF
ADIF
—
—
—
HLTMR1IF
TMR2IF
TMR1IF
23
—
—
TRISA5
TRISA4
TRISA3(1)
TRISA2
TRISA1
TRISA0
48
TRISA
Legend:
*
Note 1:
2:
x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
Page provides register information.
TRISA3 always reads ‘1’.
Read-only register.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 111
PIC12F752/HV752
NOTES:
DS41576B-page 112
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
13.0
FIXED VOLTAGE REFERENCE
(FVR)
13.2
When the Fixed Voltage Reference module is enabled, it
requires time for the reference circuit to stabilize. Once
the circuit stabilizes and is ready for use, the FVRRDY bit
of the FVRCON register will be set. See Section 20.0
“Electrical Specifications” for the minimum delay
requirement.
The Fixed Voltage Reference (FVR) is a stable voltage
reference, independent of VDD, with 1.2V output level.
The output of the FVR can be configured to supply a
reference voltage to the following:
•
•
•
•
FVR Stabilization Period
ADC input channel
Comparator 1 positive input (C1VP)
Comparator 2 positive input (C2VP)
REFOUT pin
13.3
Operation During Sleep
On the PIC12F752, the FVR is enabled by setting the
FVREN bit of the FVRCON register. The FVR is always
enabled on the PIC12HV752 device.
When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the
FVRCON register are not affected. To minimize current
consumption in Sleep mode, FVR the voltage reference
should be disabled.
13.1
13.4
Fixed Voltage Reference Output
The FVR output can be applied to the REFOUT pin by
setting the FVRBUFSS and FVRBUFEN bits of the
FVRCON register. The FVRBUFSS bit selects either
the FVR or DAC output reference to the REFOUT pin
buffer. The FVRBUFEN bit enables the output buffer to
the REFOUT pin.
Effects of a Reset
A device Reset clears the FVRCON register. As a result:
• The FVR module is disabled.
• The FVR voltage output is disabled on the
REFOUT pin.
Enabling the REFOUT pin automatically overrides any
digital input or output functions of the pin. Reading the
REFOUT pin when it has been configured for a reference voltage output will always return a ‘0’.
FIGURE 13-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
5V Shunt
Regulator
VREF+
DACPSS
PIC12HV752 only
DACR<4:0>
DACRNG
DACEN
DAC
dac_ref
EN
To ADC, Comparators
C1 and C2.
Vss
dac_ref
0
fvr_ref
1
VDD
ref
REFOUT
DACOUT
FVRBUFSS
fvr_ref
To ADC, Comparators
C1 and C2.
+
x1
DACOE
FVRBUFEN
1.2V
12HV752
FVREN
rdy
EN
FVRRDY
VSS
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 113
PIC12F752/HV752
13.5
FVR Control Registers
REGISTER 13-1:
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
R-q/q
R/W-0/0
FVREN
FVRRDY
R/W-0/0
FVRBUFEN FVRBUFSS
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
FVREN: Fixed Voltage Reference Enable bit
0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled
bit 6
FVRRDY: Fixed Voltage Reference Ready Flag bit
0 = Fixed Voltage Reference output is not ready or not enabled bit
1 = Fixed Voltage Reference output is ready for use
bit 5
FVRBUFEN: Voltage Reference Output Pin Buffer Enable
0 = Output buffer is disabled
1 = Output buffer is enabled
bit 4
FVRBUFSS: Voltage Reference Pin Buffer Source Select bit
0 = Bandgap (1.2V) is the input to the output voltage buffer
1 = dac_out is the input to the output voltage buffer
bit 3-0
Unimplemented: Read as ‘0’
TABLE 13-1:
Name
FVRCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Bit 7
Bit 6
FVREN
FVRRDY
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on page
—
—
—
—
114
FVRBUFEN FVRBUFSS
Shaded cells are not used with the Fixed Voltage Reference.
DS41576B-page 114
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
14.0
DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The 5-bit, dual range Digital-to-Analog Converter
(DAC) module supplies a variable voltage reference,
with 64 selectable output levels of which 3 levels are
duplicated. The output is ratiometric with respect to the
input source, VSRC+. See Figure 14-1 for a block
diagram of the DAC module.
The input of the DAC can be connected to two external
voltage connections:
• VDD pin
• VREF+ pin
The output of the DAC module provides a reference
voltage to the following:
•
•
•
•
Comparator positive input
ADC input channel
FVR input reference
DACOUT pin
The DAC is enabled by setting the DACEN bit of the
DACCON0 register.
FIGURE 14-1:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
VREF+
1
VDD
0
VSRC+
R2(31)
DACPSS
11111
DACEN
R2(30)
11110
dac_ref
(to Comparator, FVR
FVR and ADC modules)
Full Range
R2(2)
00010
00001
00000
1
DACOUT
0
DACR<4:0>
5
DACRNG
R1(31)
R2(1)
R1(30)
11111
DACOE
11110
R1(16)
10000
R1(15)
01111
Limited Range
R2(0)
R1(1)
00001
R1(0)
00000
Note: R2 = 16*R1
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 115
PIC12F752/HV752
14.1
DAC Positive Voltage Source
14.3
The DACPSS bit of the DACCON0 register selects the
positive voltage source, VSRC+. The following voltage
sources are available:
The DAC output value is derived using a resistor ladder
with one end of the ladder tied to the positive voltage
reference and the other end tied to VSS. If the voltage of
the input source fluctuates, a similar fluctuation will
result in the DAC output value.
• VDD pin (default)
• VREF+ pin
The resistor values within the ladder can be found in
Section 20.0 “Electrical Specifications”.
DAC module can select the positive voltage source
using the DACPSS bit of the DACCON0 register. The
default source, DACPSS = 0, connects VDD to the positive voltage source (VSRC+). VSRC+ can be changed to
the VREF+ pin by setting DACPSS = 1.
14.2
14.4
DAC Output Voltage
The DAC output voltage level of the DAC is determined
by the DACRNG and the DACR<4:0> bits of the
DACCON0 and DACCON1 registers, respectively.
DAC Range Selection
Use Equation 14-1 to determine the value of the DAC
output voltage. Example 14-1 illustrates the calculations
of the minimum, maximum and increment size of the
DAC output voltage in Full Range mode. Example 14-2
illustrates the Limited Range mode of the DAC output
voltage values.
The DACRNG bit of the DACCON0 register selects
between full-range or limited-range DAC output
voltage.
Each range selects the output in 32 equal steps.
In Full-Range mode, the output is (31/32)*VSRC+. In
Limited-Range mode, the maximum VOUT is limited to
6% of VSRC+, (31/512) * VSRC+.
EQUATION 14-1:
Ratiometric Output Level
DAC OUTPUT VOLTAGE

 DACR  4:0  
V OUT =   VSRC+   ------------------------------ 
n



2
Note:
The value of ‘n’ is determined by the DACRNG bit.
When: DACRNG = 0 (Limited Range mode); n = 9;
DACRNG = 1 (Full Range mode); n = 5.
EXAMPLE 14-1:
FULL RANGE MODE
VOUT = [VSRC+ * (DACR<4:0>/25)]
Given: VSRC = VDD = 5V, DACRNG = 1
Minimum VOUT Calculation:
DACR<4:0> = 0 0000b, (0d);
Maximum VOUT Calculation:
DACR<4:0> = 1 1111b, (31d);
VOUT = [5V * (0/32)] = 0V;
VOUT = [5V * (31/32)] = 4.84V;
Step Increment Calculation:
DACR<4:0> = 0 0001b, (1d);
VOUT = [5V * (1/32)] = 156 mV
Full Range Mode Operation:
0V VOUT 4.84V, with 32-step increments of 156 mV.
EXAMPLE 14-2:
LIMITED RANGE MODE
Given: VSRC = VDD = 5V, DACRNG = 0
Minimum VOUT Calculation:
DACR<4:0> = 0 0000b, (0d);
VOUT = [5V * (0/512)] = 0V;
VOUT = [VSRC+ * (DACR<4:0>/29)]
Maximum VOUT Calculation:
DACR<4:0> = 1 1111b, (31d);
VOUT = [5V * (31/512)] = 303 mV;
Step Increment Calculation:
DACR<4:0> = 0 0001b, (1d);
VOUT = [5V * (1/512)] = 9.8 mV
Limited Range Mode Operation:
0V VOUT 303 mV, with 32-step increments of 9.8 mV.
DS41576B-page 116
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
FIGURE 14-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
Module
R
Voltage
Reference
Output
Impedance
14.5
+
–
DACOUT
DAC Voltage Reference Output
Buffered DAC Output
FIGURE 14-3:
DAC/FVR OUTPUT PIN
The DAC output (dac_ref) can be applied to the
DACOUT pin as an unbuffered signal by:
• Setting the DACOE bit of the DACCON0 register
• Clearing the FVRBUFSS bit of the FVRCON
register.
• Clearing the FVRBUFEN bit of the FVRCON
register.
Figure 14-3 shows a block diagram pin configuration
for the dac_ref and fvr_ref signals. This unbuffered
DACOUT pin has limited current drive capability. When
a higher drive current is required, an external buffer can
be used on the DACOUT pin. Figure 14-2 shows an
example of buffering technique.
The DAC output can also be configured to use an internal buffer by:
• Setting the FVRBUFEN bit of the FVRCON register changing the pin configuration to be the
REFOUT pin.
Enabling the DACOUT pin automatically overrides any
digital input or output functions of the pin. Reading the
DACOUT pin when it has been configured for DAC reference voltage output will always return a ‘0’.
dac_ref
0
fvr_ref
1
REFOUT
DACOUT
x1
FVRBUFSS
DACOE
FVRBUFEN
14.6
Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
14.7
Effects of a Reset
A device Reset clears the DACCON0 and DACCON1
registers. As a result:
• the DAC module is disabled.
• the DAC voltage output is disabled on the
DACOUT pin.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 117
PIC12F752/HV752
14.8
DAC Control Registers
REGISTER 14-1:
DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
U-0
U-0
DACEN
DACRNG
DACOE
—
—
DACPSS
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
DACEN: DAC Enable bit
1 = DAC is enabled
0 = DAC is disabled
bit 6
DACRNG: DAC Range Selection bit(1)
1 = DAC is operating in Full Range mode
0 = DAC is operating in Limited Range mode
bit 5
DACOE: DAC Voltage Output Enable bit
1 = DAC reference output is enabled to the DACOUT pin(2)
0 = DAC reference output is disabled
bit 4-3
Unimplemented: Read as ‘0’
bit 2
DACPSS: DAC Positive Source Select bits
0 = VDD
1 = VREF+ pin
bit 1-0
Note 1:
2:
Unimplemented: Read as ‘0’
Refer to Equation 14-1.
The DACOUT pin configuration requires additional control bits in the FVRCON register (see Figure 14-3).
REGISTER 14-2:
DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DACR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
DACR<4:0>: DAC Voltage Output Select bits
1 1111 = DAC Voltage Maximum Output



0 0000 = DAC Voltage Minimum Output
Note 1: Refer to Equation 14-1 to calculate the value of the DAC Voltage Output.
DS41576B-page 118
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 14-1:
SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DACCON0
DACEN
DACRNG
DACOE
—
—
DACCON1
—
—
—
FVREN
FVRRDY
FVRCON
Legend:
Bit 2
Bit 1
Bit 0
DACPSS
—
—
DACR<4:0>
FVRBUFEN FVRBUFSS
—
—
Register
on page
118
118
—
—
114
— = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 119
PIC12F752/HV752
NOTES:
DS41576B-page 120
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
15.0
COMPARATOR MODULE
FIGURE 15-1:
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
•
•
•
•
•
•
•
•
•
Independent comparator control
Programmable input selection
Comparator output is available internally/externally
Programmable output polarity
Interrupt-on-change
Wake-up from Sleep
Programmable Speed/Power optimization
PWM shutdown
Programmable and fixed voltage reference
15.1
SINGLE COMPARATOR
VIN+
+
VIN-
–
Output
VINVIN+
Output
Note:
Comparator Overview
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
A single comparator is shown in Figure 15-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 121
PIC12F752/HV752
FIGURE 15-2:
COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
CxNCH0
CxINTP
Interrupt
CxON(1)
det
Set CxIF
CXIN0-
0
CXIN1-
1
MUX
CxINTN
Interrupt
(2)
det
CXPOL
CxVN
0
Cx
CxVP
dac_ref
To Data Bus
EN
Q1
CXZLF
CxHYS
1 MUX
2
fvr_ref
CXOUT
MCXOUT
Q
1
+
0
CXIN+
ZLF
D
To COG Module
CxSP
(2)
CXSYNC
3
CxON
VSS
0
CXOE
TRIS bit
CXOUT
CXPCH<1:0>
D
2
Note
1:
2:
(from Timer1)
T1CLK
Q
1
To Timer1
SYNCCXOUT
When CxON = 0, the comparator will produce a ‘0’ at the output.
When CxON = 0, all multiplexer inputs are disconnected.
DS41576B-page 122
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
15.2
Comparator Control
15.2.3
Each comparator has 2 control registers: CMxCON0 and
CMxCON1.
The CMxCON0 registers (see Register 15-1) contain
Control and Status bits for the following:
•
•
•
•
•
•
•
Enable
Output selection
Output pin enable
Output polarity
Speed/Power selection
Hysteresis enable
Output synchronization
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 15-1 shows the output state versus input
conditions, including polarity control.
TABLE 15-1:
• Interrupt edge polarity (rising and/or falling)
• Positive input channel selection
• Negative input channel selection
CxPOL
CxOUT
CxVN > CxVP
0
0
CxVN < CxVP
0
1
CxVN > CxVP
1
1
CxVN < CxVP
1
0
15.2.4
COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
15.2.2
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
COMPARATOR SPEED/POWER
SELECTION
The trade-off between speed or power can be optimized during program execution with the CxSP control
bit. The default state for this bit is ‘1’ which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to ‘0’.
15.3
Comparator Hysteresis
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
See Section 20.0 “Electrical Specifications” for more
information.
15.4
Note 1: The CxOE bit of the CMxCON0 register
overrides the PORT data latch. Setting
the CxON bit of the CMxCON0 register
has no impact on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
 2011 Microchip Technology Inc.
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
The CMxCON1 registers (see Register 15-2) contain
Control bits for the following:
15.2.1
COMPARATOR OUTPUT POLARITY
Timer1 Gate Operation
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 7.5 “Timer1 Gate” for more information. This
feature is useful for timing the duration or interval of an
analog event.
It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not
increment while a change in the comparator is occurring.
Preliminary
DS41576B-page 123
PIC12F752/HV752
15.4.1
15.6
COMPARATOR OUTPUT
SYNCHRONIZATION
Comparator Positive Input
Selection
The output from either comparator, C1 or C2, can be
synchronized with Timer1 by setting the CxSYNC bit of
the CMxCON0 register.
Configuring the CxPCH<1:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 15-2) and the Timer1 Block
Diagram (Figure 7-1) for more information.
•
•
•
•
15.5
Comparator Interrupt
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a Falling edge detector are
present.
When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
• CxON, CxPOL and CxSP bits of the CMxCON0
register
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
Note:
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit
of the CMxCON0 register.
DS41576B-page 124
CxIN0+ analog pin
DAC Reference Voltage (dac_ref)
FVR Reference Voltage (fvr_ref)
VSS (Ground)
See Section 13.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 14.0 “Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
15.7
Comparator Negative Input
Selection
The CxNCH0 bit of the CMxCON0 register selects the
analog input pin to the comparator inverting input.
Note:
15.8
To use CxIN0+ and CxIN1x- pins as analog input, the appropriate bits must be set
in the ANSEL register and the corresponding TRIS bits must also be set to
disable the output drivers.
Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage Reference Specifications in Section 20.0 “Electrical Specifications” for more details.
15.9
Interaction with the COG Module
The comparator outputs can be brought to the COG
module in order to facilitate auto-shutdown. If autorestart is also enabled, the comparators can be
configured as a closed loop analog feedback to the
COG, thereby creating an analog controlled PWM.
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
15.10 Zero Latency Filter
In high-speed operation, and under proper circuit
conditions, it is possible for the comparator output to
oscillate. This oscillation can have adverse effects on
the hardware and software relying on this signal.
Therefore, a digital filter has been added to the
comparator output to suppress the comparator output
oscillation. Once the comparator output changes, the
output is prevented from reversing the change for a
nominal time of 20 ns. This allows the comparator
output to stabilize without affecting other dependent
devices. Refer to Figure 15-3.
FIGURE 15-3:
COMPARATOR ZERO LATENCY FILTER OPERATION
CxOUT From Comparator
CxOUT From ZLF
TZLF
Output waiting for TZLF to expire before an output change is allowed
TZLF has expired so output change of ZLF is immediate based on
comparator output change
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 125
PIC12F752/HV752
15.11 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 15-4. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 15-4:
ANALOG INPUT MODEL
VDD
Rs < 10K
Analog
Input
pin
VT  0.6V
RIC
To Comparator
VA
CPIN
5 pF
VT  0.6V
ILEAKAGE(1)
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
= Interconnect Resistance
RIC
RS
= Source Impedance
= Analog Voltage
VA
= Threshold Voltage
VT
Note 1:
DS41576B-page 126
See Section 20.0 “Electrical Specifications”
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
15.12 Comparator Control Registers
REGISTER 15-1:
CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R/W-0/0
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-0/0
CxON
CxOUT
CxOE
CxPOL
CxZLF
CxSP
CxHYS
CxSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CxON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6
CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5
CxOE: Comparator Output Enable bit
1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0 = CxOUT is internal only
bit 4
CxPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3
CxZLF: Zero Latency Filter Enable bit
1 = Zero latency filter is enabled
0 = Zero latency filter is disabled
bit 2
CxSP: Comparator Speed/Power Select bit
1 = Comparator operates in normal power, higher speed mode
0 = Comparator operates in low-power, low-speed mode
bit 1
CxHYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0
CxSYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 127
PIC12F752/HV752
REGISTER 15-2:
CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
R/W-0/0
R/W-0/0
CxINTP
CxINTN
R/W-0/0
R/W-0/0
CxPCH<1:0>
U-0
U-0
U-0
R/W-0/0
—
—
—
CxNCH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CxINTP: Comparator Interrupt on Positive Going Edge Enable bit
1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6
CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4
CxPCH<1:0>: Comparator Positive Input Channel Select bits
00 = CxVP connects to CxIN+ pin
01 = CxVP connects to DAC Voltage Reference (dac_ref)
10 = CxVP connects to FVR Voltage Reference (fvr_ref)
11 = CxVP connects to VSS
bit 3-1
Unimplemented: Read as ‘0’
bit 0
CxNCH0: Comparator Negative Input Channel Select bits
0 = CxVN connects to CXIN0- pin
1 = CxVN connects to CXIN1- pin
REGISTER 15-3:
CMOUT: COMPARATOR OUTPUT REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R-0/0
R-0/0
—
—
—
—
—
—
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented: Read as ‘0’
bit 1
MC2OUT: Mirror Copy of C2OUT bit
bit 0
MC1OUT: Mirror Copy of C1OUT bit
DS41576B-page 128
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 15-2:
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CM1CON0
C1ON
C1OUT
C1OE
C1POL
C1ZLF
C1SP
C1HYS
C1SYNC
127
CM1CON1
C1INTP
C1INTN
CM2CON0
C2ON
C2OUT
CM2CON1
C2INTP
C2INTN
—
—
—
DACCON0
DACEN
DACRNG
DACOE
DACCON1
—
—
—
FVRCON
FVREN
FVRRDY
FVRBUFEN
FVRBUFSS
—
INTCON
Name
CMOUT
C1PCH<1:0>
C2OE
—
—
—
C1NCH0
128
C2ZLF
C2SP
C2HYS
C2SYNC
127
—
—
—
C2NCH0
128
—
—
—
MCOUT2
MCOUT1
128
—
—
DACPSS0
—
—
C2POL
C2PCH<1:0>
DACR<4:0>
118
118
—
—
—
114
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF
20
PIE2
—
—
C2IE
C1IE
—
COG1IE
—
CCP1IE
22
PIR2
—
—
C2IF
C1IF
—
COG1IF
—
CCP1IF
24
TRISA2
TRISA1
TRISA0
48
ANSA2
ANSA1
ANSA0
50
TRISA
—
—
TRISA5
TRISA4
TRISA3(1)
ANSELA
—
—
ANSA5
ANSA4
—
Legend:
Note 1:
— = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
TRISA3 always reads ‘1’.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 129
PIC12F752/HV752
NOTES:
DS41576B-page 130
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
16.0
INSTRUCTION SET SUMMARY
The PIC12F752/HV752 instruction set is highly orthogonal and is comprised of three basic categories:
TABLE 16-1:
Field
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 16-1, while the various opcode
fields are summarized in Table 16-1.
Table 16-2 lists the instructions recognized by the
MPASMTM assembler.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
Program Counter
TO
Time-out bit
DC
Digit carry bit
Zero bit
Z
PD
Power-down bit
FIGURE 16-1:
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
For example, a CLRF PORTA instruction will read
PORTA, clear all the data bits, then write the result back
to PORTA. This example would have the unintended
consequence of clearing the condition that set the
IOCIF flag.
Preliminary
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
Read-Modify-Write Operations
 2011 Microchip Technology Inc.
Carry bit
C
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
16.1
Description
Register file address (0x00 to 0x7F)
f
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
OPCODE FIELD
DESCRIPTIONS
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
DS41576B-page 131
PIC12F752/HV752
TABLE 16-2:
PIC12F752/HV752 INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
1 (2)
1 (2)
01
01
01
01
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Note 1:
2:
3:
k
k
k
–
k
k
k
–
k
–
–
k
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
DS41576B-page 132
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
16.2
Instruction Descriptions
ADDLW
Add literal and W
Syntax:
[ label ] ADDLW
Operands:
0  k  255
Operation:
(W) + k  (W)
Status Affected:
C, DC, Z
Description:
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the
W register.
k
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0  f  127
0b7
Operation:
0  (f<b>)
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
Syntax:
[ label ] BSF
f,b
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0  f  127
d 0,1
Operands:
0  f  127
0b7
Operation:
(W) + (f)  (destination)
Operation:
1  (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
Description:
Bit ‘b’ in register ‘f’ is set.
ANDLW
AND literal with W
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] ANDLW
Syntax:
[ label ] BTFSC f,b
Operands:
0  k  255
Operands:
Operation:
(W) .AND. (k)  (W)
0  f  127
0b7
Status Affected:
Z
Operation:
skip if (f<b>) = 0
Description:
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Status Affected:
None
Description:
ANDWF
AND W with f
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is discarded, and a NOP
is executed instead, making this a
two-cycle instruction.
f,d
k
Syntax:
[ label ] ANDWF
Operands:
0  f  127
d 0,1
Operation:
(W) .AND. (f)  (destination)
f,d
Status Affected:
Z
Description:
AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
 2011 Microchip Technology Inc.
f,b
Preliminary
DS41576B-page 133
PIC12F752/HV752
BTFSS
Bit Test f, Skip if Set
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRWDT
Operands:
0  f  127
0b<7
Operands:
None
Operation:
00h  WDT
0  WDT prescaler,
1  TO
1  PD
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
Operation:
skip if (f<b>) = 1
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction.
CALL
Call Subroutine
COMF
Complement f
Syntax:
[ label ] CALL k
Syntax:
[ label ] COMF
Operands:
0  k  2047
Operands:
Operation:
(PC)+ 1 TOS,
k  PC<10:0>,
(PCLATH<4:3>)  PC<12:11>
0  f  127
d  [0,1]
f,d
Operation:
(f)  (destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Status Affected:
None
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two-cycle instruction.
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0  f  127
Operands:
Operation:
00h  (f)
1Z
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
f
Operands:
None
Operation:
00h  (W)
1Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z)
is set.
DS41576B-page 134
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) - 1  (destination);
skip if result = 0
Operation:
(f) + 1  (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, then a NOP is
executed instead, making it a
two-cycle instruction.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOP is executed
instead, making it a two-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  k  2047
Operands:
0  k  255
Operation:
k  PC<10:0>
PCLATH<4:3>  PC<12:11>
Operation:
(W) .OR. k  (W)
Status Affected:
Z
Status Affected:
None
Description:
Description:
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) + 1  (destination)
Operation:
(W) .OR. (f)  (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
GOTO k
INCF f,d
 2011 Microchip Technology Inc.
Preliminary
INCFSZ f,d
Inclusive OR literal with W
IORLW k
IORWF
f,d
DS41576B-page 135
PIC12F752/HV752
MOVWF
Move W to f
Syntax:
[ label ]
MOVF
Move f
Syntax:
[ label ]
Operands:
0  f  127
d  [0,1]
Operands:
0  f  127
Operation:
(W)  (f)
Operation:
(f)  (dest)
Status Affected:
None
Status Affected:
Z
Description:
Description:
The contents of register ‘f’ is
moved to a destination dependent
upon the status of ‘d’. If d = 0,
destination is W register. If d = 1,
the destination is file register ‘f’
itself. d = 1 is useful to test a file
register since Status flag Z is
affected.
Move data from W register to
register ‘f’.
Words:
1
Cycles:
1
Words:
1
Cycles:
1
Example:
MOVF f,d
MOVF
Example:
MOVW
F
MOVWF
OPTION
Before Instruction
OPTION =
W
=
After Instruction
OPTION =
W
=
FSR, 0
f
0xFF
0x4F
0x4F
0x4F
After Instruction
W =
value in FSR
register
Z = 1
MOVLW
Move literal to W
NOP
No Operation
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0  k  255
Operands:
None
Operation:
k  (W)
Operation:
No operation
Status Affected:
None
Status Affected:
None
Description:
The eight-bit literal ‘k’ is loaded into
W register. The “don’t cares” will
assemble as ‘0’s.
Description:
No operation.
Words:
1
Cycles:
1
Words:
1
Cycles:
1
Example:
MOVLW k
Example:
MOVLW
NOP
0x5A
After Instruction
W =
DS41576B-page 136
NOP
0x5A
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
RETFIE
Return from Interrupt
RETLW
Return with literal in W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0  k  255
Operation:
TOS  PC,
1  GIE
Operation:
k  (W);
TOS  PC
Status Affected:
None
Status Affected:
None
Description:
Return from Interrupt. Stack is
POPed and Top-of-Stack (TOS) is
loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Description:
The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Words:
1
Cycles:
2
Example:
RETFIE
Words:
1
Cycles:
2
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
TABLE
RETLW k
CALL TABLE;W contains
;table offset
;value
GOTO DONE
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ;End of table
DONE
Before Instruction
W = 0x07
After Instruction
W = value of k8
 2011 Microchip Technology Inc.
RETURN
Return from Subroutine
Syntax:
[ label ]
Operands:
None
Operation:
TOS  PC
Status Affected:
None
Description:
Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
Preliminary
RETURN
DS41576B-page 137
PIC12F752/HV752
RLF
Rotate Left f through Carry
SLEEP
Enter Sleep mode
Syntax:
[ label ]
Syntax:
[ label ] SLEEP
Operands:
0  f  127
d  [0,1]
Operands:
None
Operation:
Operation:
See description below
Status Affected:
C
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
00h  WDT,
0  WDT prescaler,
1  TO,
0  PD
RLF
f,d
C
Words:
1
Cycles:
1
Example:
Status Affected:
TO, PD
Description:
The power-down Status bit, PD is
cleared. Time-out Status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
Register f
RLF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
After Instruction
REG1
W
C
RRF
Rotate Right f through Carry
SUBLW
Syntax:
[ label ]
Syntax:
[ label ] SUBLW k
Operands:
0 k 255
k - (W) W)
RRF f,d
Subtract W from literal
Operands:
0  f  127
d  [0,1]
Operation:
Operation:
See description below
Status Affected: C, DC, Z
Status Affected:
C
Description:
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
C
DS41576B-page 138
Register f
Preliminary
The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
Result
Condition
C=0
Wk
C=1
Wk
DC = 0
W<3:0>  k<3:0>
DC = 1
W<3:0>  k<3:0>
 2011 Microchip Technology Inc.
PIC12F752/HV752
SUBWF
Subtract W from f
XORWF
Exclusive OR W with f
Syntax:
[ label ] SUBWF f,d
Syntax:
[ label ] XORWF
Operands:
0 f 127
d  [0,1]
Operands:
0  f  127
d  [0,1]
Operation:
(f) - (W) destination)
Operation:
(W) .XOR. (f) destination)
Status Affected: C, DC, Z
Status Affected:
Z
Description:
Description:
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
C=0
Wf
C=1
Wf
DC = 0
W<3:0>  f<3:0>
DC = 1
W<3:0>  f<3:0>
SWAPF
Swap Nibbles in f
Syntax:
[ label ] SWAPF f,d
Operands:
0  f  127
d  [0,1]
Operation:
(f<3:0>)  (destination<7:4>),
(f<7:4>)  (destination<3:0>)
Status Affected:
None
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW
f,d
Exclusive OR literal with W
Syntax:
[ label ] XORLW k
Operands:
0 k 255
Operation:
(W) .XOR. k W)
Status Affected:
Z
Description:
The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the W register.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 139
PIC12F752/HV752
NOTES:
DS41576B-page 140
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
17.0
SPECIAL FEATURES OF THE
CPU
The PIC12F752/HV752 has a host of features intended
to maximize system reliability, minimize cost through
elimination of external components, provide powersaving features and offer code protection.
These features are:
17.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 17-1.
These bits are mapped in program memory location
2007h.
Note:
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Oscillator selection
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming
Configuration Bits
Address 2007h is beyond the user program
memory space. It belongs to the special
configuration memory space (2000h3FFFh), which can be accessed only during
programming. See Memory Programming
Specification
(DS41561) for more
information.
The Power-up Timer (PWRT), which provides a fixed
delay of 64 ms (nominal) on power-up only, is designed
to keep the part in Reset while the power supply
stabilizes. There is also circuitry to reset the device if a
brown-out occurs, which can use the Power-up Timer
to provide at least a 64 ms Reset. With these functionson-chip, most applications need no external Reset
circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through:
• External Reset
• Watchdog Timer Wake-up
• An interrupt
Oscillator selection options are available to allow the
part to fit the application. The INTOSC options save
system cost, while the External Clock (EC) option
provides a means for specific frequency and accurate
clock sources. Configuration bits are used to select
various options (see Register 17-1).
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 141
PIC12F752/HV752
REGISTER 17-1:
CONFIGURATION WORD
R/P-1
R/P-1
DEBUG
CLKOUTEN
R/P-1
R/P-1
R/P-1
WRT<1:0>
R/P-1
BOREN<1:0>
bit 13
bit 8
U-1
R/P-1
R/P-1
R/P-1
R/P-1
U-1
U-1
—
CP
MCLRE
PWRTE
WDTE
—
—
bit 7
R/P-1
FOSC0
bit 0
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
‘1’ = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
DEBUG: Debug Mode Enable bit(2)
1 = Background debugger is disabled
0 = Background debugger is enabled
bit 12
CLKOUTEN: Clock Out Enable bit
1 = Clock out function disabled. CLKOUT pin acts as I/O pin
0 = General purpose I/O disabled. CLKOUT pin acts as CLKOUT
bit 11-10
WRT<1:0>: Flash Program Memory Self Write Enable bit
11 = Write protection off
10 = 000h to FFh write-protected, 100h to 3FFh may be modified by PMCON1 control
01 = 000h to 1FFh write-protected, 200h to 3FFh may be modified by PMCON1 control
00 = 000h to 3FFh write-protected, entire program is write-protected
bit 8-9
BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
0x = BOR disabled
bit 7
Unimplemented: Read as ‘1’.
bit 6
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5
MCLRE: MCLR/VPP Pin Function Select bit
1 = MCLR pin is MCLR function and weak internal pull-up is enabled
0 = MCLR pin is input function, MCLR function is internally disabled
bit 4
PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 3
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-1
Unimplemented: Read as ‘1’.
bit 0
FOSC: Oscillator Selection bits
1 = EC oscillator selected: CLKIN on RA5/CLKIN
0 = Internal oscillator: I/O function on RA5/CLKIN
Note 1:
2:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The Configuration bit is managed automatically by the device development tools. The user should not
attempt to manually write this bit location. However, the user should ensure that this location has been
programmed to a ‘1’ and the device checksum is correct for proper operation of production software.
DS41576B-page 142
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
17.2
Calibration Bits
The 8 MHz internal oscillator is factory calibrated.
These calibration values are stored in fuses located in
the Calibration Word (2008h). The Calibration Word is
not erased when using the specified bulk erase
sequence in the Memory Programming Specification
(DS41561) and thus, does not require reprogramming.
17.3
Reset
The PIC12F752/HV752 device differentiates between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
Power-on Reset (POR)
WDT Reset during normal operation
WDT Reset during Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
•
•
•
•
•
Power-on Reset
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
WDT wake-up does not cause register resets in the
same manner as a WDT Reset since wake-up is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 17-2. Software can use
these bits to determine the nature of the Reset. See
Table 17-4 for a full description of Reset states of all
registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 17-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 20.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 17-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP pin
Sleep
WDT
Module
WDT
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Reset
BOREN
S
PWRT
On-Chip
RC OSC
Chip_Reset
R
11-bit Ripple Counter
Q
Enable PWRT
Note
1:
Refer to the Configuration Word register (Register 17-1).
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 143
PIC12F752/HV752
TABLE 17-1:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
EC, INTOSC
TABLE 17-2:
Power-up
Brown-out Reset
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up from
Sleep
TPWRT
—
TPWRT
—
—
STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
Condition
0
x
1
1
Power-on Reset
u
0
1
1
Brown-out Reset
u
u
0
u
WDT Reset
u
u
0
0
WDT Wake-up
u
u
u
u
MCLR Reset during normal operation
u
u
1
0
MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
DS41576B-page 144
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
17.3.1
POWER-ON RESET (POR)
FIGURE 17-2:
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
VDD is required. See Section 20.0 “Electrical
Specifications” for details. If the BOR is enabled, the
maximum rise time specification does not apply. The
BOR circuitry will keep the device in Reset until VDD
reaches VBOR (see Section 17.3.4 “Brown-out Reset
(BOR)”).
Note:
VDD
PIC®
MCU
R1
1 kor greater)
R2
MCLR
SW1
(optional)
100 
needed with capacitor)
C1
0.1 F
(optional, not critical)
The POR circuit does not produce an
internal Reset when VDD declines. To reenable the POR, VDD must reach Vss for
a minimum of 100 s.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
RECOMMENDED MCLR
CIRCUIT
17.3.3
POWER-UP TIMER (PWRT)
PIC12F752/HV752 has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from an internal
RC oscillator. For more information, see Section 4.2.2
“Internal Clock Mode”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should be enabled when Brown-out Reset is
enabled, although it is not required.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The Power-up Timer delay will vary from chip-to-chip
due to:
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
directly to VDD. The use of an RC network, as shown in
Figure 17-2, is suggested.
• VDD variation
• Temperature variation
• Process variation
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
17.3.2
MCLR
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the MCLR pin
becomes an external Reset input. In this mode, the
MCLR pin has a weak pull-up to VDD.
 2011 Microchip Technology Inc.
See DC parameters for details
“Electrical Specifications”).
Note:
Preliminary
(Section 20.0
Voltage spikes below VSS at the MCLR
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resistor of 50-100  should be used when
applying a “low” level to the MCLR pin,
rather than pulling this pin directly to VSS.
DS41576B-page 145
PIC12F752/HV752
17.3.4
BROWN-OUT RESET (BOR)
On any Reset (Power-on, Brown-out Reset, Watchdog
timer, etc.), the chip will remain in Reset until VDD rises
above VBOR (see Figure 17-3). If enabled, the Powerup Timer will be invoked by the Reset and keep the chip
in Reset an additional 64 ms.
The BOREN<1:0> bits in the Configuration Word
register select one of three BOR modes. One mode
has been added to allow control of the BOR enable for
lower current during Sleep. By selecting BOREN<1:0>
= 10, the BOR is automatically disabled in Sleep to
conserve power and enabled on wake-up. See
Register 17-1 for the Configuration Word definition.
Note:
A brown-out occurs when VDD falls below VBOR for
greater than parameter TBOR (see Section 20.0
“Electrical Specifications”). The brown-out condition
will reset the device. This will occur regardless of VDD
slew rate. A Brown-out Reset may not occur if VDD falls
below VBOR for less than parameter TBOR.
FIGURE 17-3:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
register.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
Table 17-3 summarizes the registers associated with
BOR.
BROWN-OUT SITUATIONS
VDD
Vbor
Internal
Reset
64 ms(1)
VDD
Vbor
Internal
< 64 ms
Reset
64 ms(1)
Vdd
Vbor
Internal
Reset
Note 1:
TABLE 17-3:
Name
PCON
STATUS
64 ms(1)
64 ms delay only if PWRTE bit is programmed to ‘0’.
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
—
—
—
—
—
—
POR
BOR
25
IRP
RP1
RP0
TO
PD
Z
DC
C
18
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Shaded cells are not used by BOR.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
DS41576B-page 146
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
17.3.5
TIME-OUT SEQUENCE
17.3.6
On power-up, the time-out sequence is as follows:
• PWRT time-out is invoked after POR has expired.
• OST is activated after the PWRT time-out has
expired.
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 17-4, Figure 17-5 and
Figure 17-6 depict time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 17-5). This is useful for testing purposes or
to synchronize more than one PIC12F752/HV752
device operating in parallel.
Table 17-5 shows the Reset conditions for some
special registers, while Table 17-4 shows the Reset
conditions for all the registers.
FIGURE 17-4:
POWER CONTROL (PCON)
REGISTER
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
last.
Bit 0 is BOR (Brown-out). BOR is unknown on Poweron Reset. It must then be set by the user and checked
on subsequent Resets to see if BOR = 0, indicating that
a Brown-out has occurred. The BOR Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (BOREN<1:0> = 00 in the
Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subsequent Reset, if POR is ‘0’, it will indicate that a Poweron Reset has occurred (i.e., VDD may have gone too
low).
For more information, see Section 17.3.4 “Brown-out
Reset (BOR)”.
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TIOSCST
OST Time-out
Internal Reset
FIGURE 17-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TIOSCST
OST Time-out
Internal Reset
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 147
PIC12F752/HV752
FIGURE 17-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TIOSCST
OST Time-out
Internal Reset
DS41576B-page 148
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 17-4:
Register
W
INITIALIZATION CONDITION FOR REGISTERS
Address
Power-on Reset
MCLR Reset
WDT Reset
Brown-out Reset(1)
Wake-up from Sleep through
Interrupt
Wake-up from Sleep through
WDT Time-out
—
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
00h/80h/
100h/180h
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h/
102h/182h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h/
103h/183h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h/
104h/184h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
--xx xxxx
--uu uuuu
--uu uuuu
IOCAF
08h
--00 0000
--00 0000
--uu uuuu
PCLATH
0Ah/8Ah/
10Ah/18Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh/
10Bh/18Bh
0000 0000
0000 0000
uuuu uuuu(2)
PIR1
0Ch
00-- -0-0
00-- -0-0
uu-- -u-u(2)
PIR2
0Dh
--00 -0-0
--00 -0-0
--uu -u-u(2)
TMR1L
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
10h
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
11h
0000 00-0
uuuu uu-u
uuuu uu-u
T1GCON
12h
0000 0x00
0000 0x00
uuuu uuuu
(1)
13h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H(1)
14h
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON(1)
15h
--00 0000
--00 0000
--uu uuuu
ADRESL(1)
1Ch
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESH(1)
1Dh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0(1)
1Eh
0000 0000
0000 0000
uuuu uuuu
ADCON1(1)
1Fh
-000 ----
-000 ----
-uuu ----
81h/181h
1111 1111
1111 1111
uuuu uuuu
TRISA
85h
--11 1111
--11 1111
--uu uuuu
IOCAP
88h
--00 0000
--00 0000
--uu uuuu
PIE1
8Ch
00-- -000
00-- -000
uu-- -uuu
PIE2
8Dh
--00 -0-0
--00 -0-0
--uu -u-u
OSCCON
8Fh
--01 -00-
--uu -uu-
--uu -uu-
FVRCON
90h
0000 ----
0000 ----
uuuu ----
DACCON0
91h
000- -0--
000- -0--
uuu- -u--
DACCON1
92h
---0 0000
---0 0000
---u uuuu
9Bh
0000 0100
0000 0100
uuuu uuuu
CCPR1L
OPTION_REG
CM2CON0
Legend:
Note 1:
2:
3:
4:
5:
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 17-5 for Reset value for specific condition.
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 149
PIC12F752/HV752
TABLE 17-4:
INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Wake-up from Sleep through
Interrupt
Wake-up from Sleep through
WDT Time-out (Continued)
Address
Power-on Reset
MCLR Reset
WDT Reset (Continued)
Brown-out Reset(1)
CM2CON1
9Ch
0000 ---0
0000 ---0
uuuu ---u
CM1CON0
9Dh
0000 0100
0000 0100
uuuu uuuu
CM1CON1
9Eh
0000 ---0
0000 ---0
uuuu ---u
CMOUT
9Fh
---- --00
---- --00
---- --uu
LATA
105h
--xx -xxx
--uu -uuu
--uu -uuu
IOCAN
108h
--00 0000
--00 0000
--uu uuuu
WPUA
10Ch
--00 0000
--00 0000
--uu uuuu
SLRCON0
10Dh
---- -0-0
---- -0-0
---- -u-u
PCON
10Fh
---- --qq
TMR2
110h
0000 0000
0000 0000
uuuu uuuu
PR2
111h
1111 1111
1111 1111
uuuu uuuu
T2CON
112h
-000 0000
-000 0000
-uuu uuuu
HLTMR1
113h
0000 0000
0000 0000
uuuu uuuu
HLTPR1
114h
1111 1111
1111 1111
uuuu uuuu
HLT1CON0
115h
-000 0000
-000 0000
-uuu uuuu
HLT1CON1
116h
---0 0000
---0 0000
---u uuuu
ANSELA
185h
--11 -111
--11 -111
--uu -uuu
APFCON
188h
---0 -000
---0 -000
---u -uuu
OSCTUNE
189h
---0 0000
---u uuuu
---u uuuu
PMCON1
18Ch
---- -000
---- -000
---- -uuu
PMCON2
18Dh
---- ----
---- ----
---- ----
PMADRL
18Eh
0000 0000
0000 0000
uuuu uuuu
PMADRH
18Fh
---- --00
---- --00
---- --uu
PMDATL
190h
0000 0000
0000 0000
uuuu uuuu
PMDATH
191h
--00 0000
--00 0000
--uu uuuu
COG1PH
192h
---- xxxx
---- uuuu
---- uuuu
COG1BLK
193h
xxxx xxxx
uuuu uuuu
uuuu uuuu
COG1DB
194h
xxxx xxxx
uuuu uuuu
uuuu uuuu
COG1CON0
195h
0000 0000
0000 0000
uuuu uuuu
COG1CON1
196h
--00 0000
--00 0000
--uu uuuu
COG1ASD
197h
0000 0000
0000 0000
uuuu uuuu
Register
Legend:
Note 1:
2:
3:
4:
5:
---- --uu(1, 5)
---- --uu
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
See Table 17-5 for Reset value for specific condition.
If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
DS41576B-page 150
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 17-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
Status
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during Sleep
000h
0001 0uuu
---- --uu
000h
0000 uuuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
Condition
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt Wake-up from Sleep
000h
0001 1uuu
---- --u0
PC + 1(1)
uuu1 0uuu
---- --uu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with
the interrupt vector (0004h) after execution of PC + 1.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 151
PIC12F752/HV752
17.4
Interrupts
The PIC12F752/HV752 has multiple sources of interrupt:
•
•
•
•
•
•
•
•
•
•
•
External Interrupt (INT pin)
Interrupt-On-Change (IOC) Interrupts
Timer0 Overflow Interrupt
Timer1 Overflow Interrupt
Timer2 Match Interrupt
Hardware Limit Timer (HLT) Interrupt
Comparator Interrupt (C1/C2)
ADC Interrupt
Complementary Output Generator (COG)
CCP1 Interrupt
Flash Memory Self Write
Figure 17-8). The latency is the same for one or twocycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Registers (PIRx) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
The Global Interrupt Enable bit, GIE of the INTCON
register, enables (if set) all unmasked interrupts, or
disables (if cleared) all interrupts. Individual interrupts
can be disabled through their corresponding enable
bits in the INTCON register and PIEx registers. GIE is
cleared on Reset.
When an interrupt is serviced, the following actions
occur automatically:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
For additional information on Timer1, Timer2,
comparators, ADC, Enhanced CCP modules, refer to
the respective peripheral section.
17.4.1
RA2/INT INTERRUPT
The external interrupt on the RA2/INT pin is edgetriggered; either on the rising edge if the INTEDG bit of
the OPTION register is set, or the falling edge, if the
INTEDG bit is clear. When a valid edge appears on the
RA2/INT pin, the INTF bit of the INTCON register is set.
This interrupt can be disabled by clearing the INTE
control bit of the INTCON register. The INTF bit must
be cleared by software in the Interrupt Service Routine
before re-enabling this interrupt. The RA2/INT interrupt
can wake-up the processor from Sleep, if the INTE bit
was set prior to going into Sleep. See Section 17.7
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 17-10 for timing of wake-up from Sleep through
RA2/INT interrupt.
Note:
• INT Pin Interrupt
• Interrupt-On-Change (IOC) Interrupts
• Timer0 Overflow Interrupt
The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’ and cannot generate an
interrupt.
The peripheral interrupt flags are contained in the PIR1
and PIR2 registers. The corresponding interrupt enable
bit is contained in the PIE1 and PIE2 registers.
The following interrupt flags are contained in the PIR1
register:
•
•
•
•
•
A/D Interrupt
Comparator Interrupt
Timer1 Overflow Interrupt
Timer2 Match Interrupt
Enhanced CCP Interrupt
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
DS41576B-page 152
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
17.4.2
TIMER0 INTERRUPT
An overflow (FFh  00h) in the TMR0 register will set
the T0IF bit of the INTCON register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 6.0 “Timer0 Module”
for operation of the Timer0 module.
17.4.3
PORTA INTERRUPT-ON-CHANGE
An input change on PORTA sets the IOCIF bit of the
INTCON register. The interrupt can be enabled/
disabled by setting/clearing the IOCIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
Note:
If a change on the I/O pin should occur
when any PORTA operation is being
executed, then the IOCIF interrupt flag
may not get set.
FIGURE 17-7:
INTERRUPT LOGIC
T0IF
T0IE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IF) PIR1<0>
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn<7>
PIEn<7>
 2011 Microchip Technology Inc.
GIE
Preliminary
DS41576B-page 153
PIC12F752/HV752
FIGURE 17-8:
INT PIN INTERRUPT TIMING
Q1 Q2
Q3
Q4 Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3 Q4
Q1
Q2
Q3
Q4
CLKIN
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag
(INTCON reg.)
Interrupt Latency (2)
(5)
GIE bit
(INTCON reg.)
INSTRUCTION FLOW
PC
Instruction
Fetched
PC + 1
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
—
Dummy Cycle
Inst (PC)
Inst (PC – 1)
0004h
PC + 1
Inst (PC + 1)
Inst (PC)
Instruction
Executed
Note 1:
PC
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
CLKOUT is available only in INTOSC and RC Oscillator modes.
4:
For minimum width of INT pulse, refer to AC specifications in Section 20.0 “Electrical Specifications”.
5:
INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 17-6:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
T0IE
INTE
IOCIE
T0IF
INTF
IOCIF
20
IOCAF
—
—
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
52
IOCAN
—
—
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
52
IOCAP
—
—
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
52
LATA
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0
48
PIE1
TMR1GIE
ADIE
—
—
—
HLTMR1IE TMR2IE
TMR1IE
21
PIR1
TMR1GIF
ADIF
—
—
—
HLTMR1IF
TMR1IF
23
TMR2IF
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
DS41576B-page 154
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
17.5
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary
holding
registers
W_TEMP
and
STATUS_TEMP should be placed in the last 16 bytes
of GPR (see Figure 2-2). These 16 locations are
common to all banks and do not require banking. This
makes context save and restore operations simpler.
The code shown in Example 17-1 can be used to:
•
•
•
•
•
Store the W register
Store the STATUS register
Execute the ISR code
Restore the Status (and Bank Select Bit register)
Restore the W register
Note:
The PIC12F752/HV752 does not require
saving the PCLATH. However, if computed GOTOs are used in both the ISR and
the main code, the PCLATH must be
saved and restored in the ISR.
EXAMPLE 17-1:
MOVWF
SWAPF
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP
STATUS,W
MOVWF
STATUS_TEMP
:
:(ISR)
:
SWAPF
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
17.6
STATUS
W_TEMP,F
W_TEMP,W
;Copy W to TEMP
;Swap status to
;Swaps are used
;Save status to
;Insert user code here
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
Watchdog Timer (WDT)
17.6.1
The Watchdog Timer is a free running timer, using
LFINTOSC oscillator as its clock source. The WDT is
enabled by setting the WDTE bit of the Configuration
Word (default setting). When WDTE is set, the
LFINTOSC will always be enabled to provide a clock
source to the WDT module.
During normal operation, a WDT time-out generates a
device Reset. If the device is in Sleep mode, a WDT
time-out causes the device to wake-up and continue
with normal operation.
The WDT can be permanently disabled by
programming the Configuration bit, WDTE, as clear
(Section 17.1 “Configuration Bits”).
 2011 Microchip Technology Inc.
register
be saved into W
because they do not affect the status bits
bank zero STATUS_TEMP register
WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION register. Thus, time-out periods
up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
Preliminary
DS41576B-page 155
PIC12F752/HV752
17.6.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worstcase conditions (i.e., VDD = Min., Temperature = Max.,
Max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
FIGURE 17-9:
WATCHDOG TIMER WITH SHARED PRESCALE BLOCK DIAGRAM
FOSC/4
Data Bus
0
8
1
1
Sync
2 TCY
Shared Prescale
T0CKI
pin
0
T0CS
T0SE
TMR0
0
Set Flag bit T0IF
on Overflow
PSA
8-bit
Prescaler
1
PSA
8
PS<2:0>
Watchdog
Timer
LFINTOSC
WDT
Time-out
2
(Figure 4-1)
1
0
PSA
PSA
WDTE
Note 1:
2:
T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG register.
WDTE bit is in the Configuration Word register.
TABLE 17-7:
WDT STATUS
Conditions
WDT
WDTE = 0
CLRWDT Command
Cleared
Exit Sleep
DS41576B-page 156
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 17-8:
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
OPTION_REG
RAPU
INTEDG
T0CS
T0SE
PSA
Bit 2
Bit 1
Bit 0
Register on
Page
PS<2:0>
57
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 17-1 for operation of all Configuration Word register bits.
TABLE 17-9:
Name
CONFIG
Legend:
SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
13:8
7:0
—
—
DEBUG
CLKOUTEN
—
CP
MCLRE
PWRTE
Bit 11/3
Bit 10/2
WRT<1:0>
WDTE
Bit 9/1
Bit 8/0
BOREN<1:0>
—
—
FOSC0
Register
on Page
142
— = unimplemented location, read as ‘1’. Shaded cells are not used by Watchdog Timer.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 157
PIC12F752/HV752
17.7
Power-Down Mode (Sleep)
The Power-Down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
•
•
•
•
•
WDT will be cleared but keeps running.
PD bit in the STATUS register is cleared.
TO bit is set.
Oscillator driver is turned off.
I/O ports maintain the status they had before SLEEP
was executed (driving high, low or high-impedance).
For lowest current consumption in this mode, all I/O pins
should be either at VDD or VSS, with no external circuitry
drawing current from the I/O pin and the comparators,
DAC and FVR should be disabled. I/O pins that are highimpedance inputs should be pulled high or low externally
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip pullups on PORTA should be considered.
The MCLR pin must be at a logic high level.
Note:
17.7.1
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
4.
5.
External Reset input on MCLR pin.
Watchdog Timer wake-up.
Interrupt from INT pin.
Interrupt-On-Change input change.
Peripheral interrupt.
The first event will cause a device Reset. The other
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
Timer1 interrupt. Timer1 must be operating as
an asynchronous counter.
CCP Capture mode interrupt.
A/D conversion (when A/D clock source is RC).
Comparator output changes state.
Interrupt-on-change.
External Interrupt from INT pin.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
Note:
If the global interrupts are disabled (GIE is
cleared) and any interrupt source has both
its interrupt enable bit and the corresponding interrupt flag bits set, the device will
immediately wake-up from Sleep.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
17.7.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
Immediately wake-up from Sleep. The SLEEP
instruction is executed. Therefore, the WDT and
WDT prescaler and postscaler (if enabled) will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction. See
Figure 17-10 for more details.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
DS41576B-page 158
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
FIGURE 17-10:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN
TIOSCST
CLKOUT
INT pin
INTF flag
(INTCON reg.)
Interrupt Latency (3)
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
17.8
Processor in
Sleep
PC
Inst(PC) = Sleep
Inst(PC – 1)
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
1:
HFINTOSC Oscillator mode assumed.
2:
GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line.
Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.
Note:
17.9
The entire Flash program memory will be
erased when the code protection is turned
off.
See
the
“Program
Memory
Specification” (DS41561) for more
information.
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
reported when using MPLAB® IDE.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 159
PIC12F752/HV752
17.10 In-Circuit Serial Programming™
ThePIC12F752/HV752 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with five connections for:
•
•
•
•
•
clock
data
power
ground
programming voltage
This allows customers to manufacture boards with
unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a Program/Verify mode by
holding the ICSPDAT and ICSPCLK pins low, while
raising the MCLR (VPP) pin from VIL to VIHH. See the
Memory Programming Specification (DS41561) for
more information. ICSPDAT becomes the programming
data and ICSPCLK becomes the programming clock.
Both ICSPDAT and ICSPCLK are Schmitt Trigger
inputs in Program/Verify mode.
A typical In-Circuit Serial Programming connection is
shown in Figure 17-11.
FIGURE 17-11:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
*
PIC12F752/HV752
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
ICSPCLK
Data I/O
ICSPDAT
*
*
*
To Normal
Connections
* Isolation devices (as required)
Note:
To erase the device, VDD must be above
the Bulk Erase VDD minimum given in the
“Program
Memory
Specification”
(DS41561)
DS41576B-page 160
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
18.0
SHUNT REGULATOR
(PIC12HV752 ONLY)
The PIC12HV752 devices include a permanent internal
5 volt (nominal) shunt regulator in parallel with the VDD
pin. This eliminates the need for an external voltage
regulator in systems sourced by an unregulated supply.
All external devices connected directly to the VDD pin
will share the regulated supply voltage and contribute
to the total VDD supply current (ILOAD).
18.1
An external current limiting resistor, RSER, located
between the unregulated supply, VUNREG, and the VDD
pin, drops the difference in voltage between VUNREG
and VDD. RSER must be between RMAX and RMIN as
defined by Equation 18-1.
EQUATION 18-1:
RMAX =
RSER LIMITING RESISTOR
(VUMIN - 5V)
1.05 • (4 MA + ILOAD)
Regulator Operation
A shunt regulator generates a specific supply voltage
by creating a voltage drop across a pass resistor RSER.
The voltage at the VDD pin of the microcontroller is
monitored and compared to an internal voltage reference. The current through the resistor is then adjusted,
based on the result of the comparison, to produce a
voltage drop equal to the difference between the supply
voltage VUNREG and the VDD of the microcontroller.
See Figure 18-1 for voltage regulator schematic.
FIGURE 18-1:
RSER
ISHUNT
ILOAD
Feedback
RMIN
= minimum value of RSER (ohms)
VUMIN = minimum value of VUNREG
VUMAX = maximum value of VUNREG
= regulated voltage (5V nominal)
1.05
= compensation for +5% tolerance of RSER
0.95
= compensation for -5% tolerance of RSER
18.2
VSS
Device
RMAX = maximum value of RSER (ohms)
ILOAD = maximum expected load current in mA
including I/O pin currents and external
circuits connected to VDD.
VDD
CBYPASS
(VUMAX - 5V)
0.95 • (50 MA)
Where:
VDD
SHUNT REGULATOR
VUNREG
ISUPPLY
RMIN =
Regulator Considerations
The supply voltage VUNREG and load current are not
constant. Therefore, the current range of the regulator
is limited. Selecting a value for RSER must take these
three factors into consideration.
Since the regulator uses the band gap voltage as the
regulated voltage reference, this voltage reference is
permanently enabled in the PIC12HV752 devices.
The shunt regulator will still consume current when
below operating voltage range for the shunt regulator.
18.3
Design Considerations
For more information on using the shunt regulator and
managing current load, see Application Note AN1035,
“Designing with HV Microcontrollers” (DS01035).
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 161
PIC12F752/HV752
NOTES:
DS41576B-page 162
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
19.0
DEVELOPMENT SUPPORT
19.1
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 163
PIC12F752/HV752
19.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
19.3
HI-TECH C for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
19.4
19.5
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
19.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS41576B-page 164
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
19.7
MPLAB SIM Software Simulator
19.9
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
19.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
 2011 Microchip Technology Inc.
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
19.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
Preliminary
DS41576B-page 165
PIC12F752/HV752
19.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
19.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
19.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS41576B-page 166
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
20.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias..........................................................................................................-40° to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V
Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ............................................................................................................................... 800 mW
Maximum current out of VSS pin ...................................................................................................................... 95 mA
Maximum current into VDD pin ......................................................................................................................... 95 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by PORTA................................................................................................................... 90 mA
Maximum current sourced PORTA .................................................................................................................. 90 mA
Note 1:
Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 167
PIC12F752/HV752
FIGURE 20-1:
PIC12F752 VOLTAGE-FREQUENCY GRAPH,
-40°C  TA  +125°C
5.5
5.0
VDD (V)
4.5
4.0
3.5
3.0
2.5
2.0
0
8
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 20-2:
PIC12HV752 VOLTAGE-FREQUENCY GRAPH,
-40°C  TA  +125°C
5.0
VDD (V)
4.5
4.0
3.5
3.0
2.5
2.0
0
8
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS41576B-page 168
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
20.1
DC Characteristics: PIC12F752/HV752-I (Industrial)
PIC12F752/HV752-E (Extended)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
Param
No.
Min
Typ†
Max
Units
2.0
—
5.5
V
V
FOSC < = 4 MHz
V
FOSC < = 8 MHz
Sym
Characteristic
Conditions
Supply Voltage
D001
VDD
PIC12F752
FOSC < = 4 MHz
D001
PIC12HV752
2.0
—
5.0(2)
D001B VDD
PIC12F752
2.0
—
5.5
D001B
PIC12HV752
2.0
—
5.02)
V
FOSC < = 8 MHz
D001C VDD
PIC12F752
3.0
—
5.5
V
FOSC < = 10 MHz
D001C
PIC12HV752
3.0
—
5.02)
V
FOSC < = 10 MHz
D001D VDD
PIC12F752
4.5
—
5.5
V
FOSC < = 20 MHz
D001D
PIC12HV752
4.5
—
5.0(2)
V
FOSC < = 20 MHz
D002*
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
Device in Sleep mode
D003
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
V
See Section TABLE 17-1: “Time-out in
Various Situations” for details.
D004*
SVDD
VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05
—
—
V/ms See Section TABLE 17-1: “Time-out in
Various Situations” for details.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: On the PIC12HV752, VDD is regulated by a Shunt Regulator and is dependent on series resistor
(connected between the unregulated supply voltage and the VDD pin) to limit the current to 50 mA. See
Section 18.0 “Shunt Regulator (PIC12HV752 Only)” for design requirements.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 169
PIC12F752/HV752
20.2
DC Characteristics: PIC12F752-I (Industrial)
PIC12F752-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
DC CHARACTERISTICS
Param
No.
D010
Device Characteristics
Supply Current (IDD)
PIC12F752
D011*
D012*
D013*
D014
D015
D016
(1, 2)
Min
Typ†
Max
Units
Conditions
VDD
—
8
TBD
A
2.0
—
16
TBD
A
3.0
—
31
TBD
A
5.0
—
140
TBD
A
2.0
—
215
TBD
A
3.0
—
360
TBD
A
5.0
—
185
TBD
A
2.0
—
325
TBD
A
3.0
—
665
TBD
A
5.0
—
270
TBD
A
2.0
—
390
TBD
A
3.0
—
680
TBD
A
5.0
—
0.395
TBD
mA
2.0
—
0.620
TBD
mA
3.0
—
1.2
TBD
mA
5.0
—
2.6
TBD
mA
4.5
—
2.8
TBD
mA
5.0
—
65
—
A
2.0
—
120
—
A
3.0
—
250
—
A
5.0
Note
FOSC = 31 kHz
LFINTOSC mode
FOSC = 1 MHz
HFINTOSC mode
FOSC = 4 MHz
EC Oscillator mode
FOSC = 4 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 20 MHz
EC Oscillator mode
FOSC = 1 MHz
EC Oscillator mode
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square
wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.
DS41576B-page 170
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
20.3
DC Characteristics: PIC12HV752-I (Industrial)
PIC12HV752-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
DC CHARACTERISTICS
Param
No.
D010
Device Characteristics
Supply Current (IDD)
PIC12HV752
D011*
D012*
(1, 2)
Conditions
Min
Typ†
Max
Units
—
20
TBD
A
2.0
—
40
TBD
A
3.0
VDD
—
65
TBD
A
4.5
—
215
TBD
A
2.0
—
375
TBD
A
3.0
—
570
TBD
A
4.5
—
335
TBD
A
2.0
—
535
TBD
A
3.0
Note
FOSC = 31 kHz
LFINTOSC mode
FOSC = 1 MHz
HFINTOSC Oscillator mode
FOSC = 4 MHz
HFINTOSC mode
—
795
TBD
A
4.5
—
0.530
TBD
mA
2.0
—
0.830
TBD
mA
3.0
—
1.35
TBD
mA
4.5
D014
—
3.8
TBD
mA
4.5
FOSC = 20 MHz
EC Oscillator mode
D015
—
130
—
A
2.0
FOSC = 1 MHz
EC Oscillator mode
D013
D016
—
245
—
A
3.0
—
360
—
A
5.0
—
250
—
A
2.0
—
440
—
A
3.0
—
660
—
A
5.0
FOSC = 8 MHz
HFINTOSC mode
FOSC = 4 MHz
EC Oscillator mode
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can
be extended by the formula IR = VDD/2REXT (mA) with REXT in k
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 171
PIC12F752/HV752
20.4
DC Characteristics: PIC12F752 - I (Industrial)
DC CHARACTERISTICS
Param
No.
D020
Device Characteristics
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
Conditions
Min
Typ†
Max
Units
Power-down Base
Current (IPD)(2)
—
0.01
TBD
A
2.0
—
0.3
TBD
A
3.0
PIC12F752
—
0.5
TBD
A
5.0
150
TBD
nA
3.0
-40°C  TA  +25°C for industrial
—
3.0
TBD
A
2.0
WDT Current(1)
—
4.0
TBD
A
3.0
D021
—
7.0
TBD
A
5.0
D022
—
5.0
TBD
A
3.0
—
6.0
TBD
A
5.0
D023
—
362
TBD
A
2.0
D024
D025
D026
D027
Note
VDD
WDT, BOR, Comparator, VREF and
T1OSC disabled
BOR Current(1)
CxSP = 1, Comparator Current(1),
single comparator enabled
—
418
TBD
A
3.0
—
500
TBD
A
5.0
—
96
TBD
A
2.0
—
112
TBD
A
3.0
—
132
TBD
A
5.0
—
0.3
TBD
A
3.0
—
0.36
TBD
A
5.0
A/D Current(1), no conversion in
progress
—
0.2
TBD
A
3.0
DAC Current(1)
—
0.4
TBD
A
5.0
—
59
TBD
A
3.0
—
98
TBD
A
5.0
CxSP = 0, Comparator Current(1),
single comparator enabled
FVR Current(1), FVRBUFEN = 1,
REFOUT buffer enabled
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41576B-page 172
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
20.5
DC Characteristics: PIC12F752 - E (Extended)
DC CHARACTERISTICS
Param
No.
D020E
Device Characteristics
Power-down Base
Current (IPD)(2)
PIC12F752
D021E
D022E
D023E
D024E
D025E
D026E
D027E
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C for extended
Min
Typ†
Max
Units
Conditions
VDD
Note
WDT, BOR, Comparator, DAC and
FVR disabled
—
0.1
TBD
A
2.0
—
0.3
TBD
A
3.0
—
0.5
TBD
A
5.0
—
3.0
TBD
A
2.0
—
4.0
TBD
A
3.0
—
7.0
TBD
A
5.0
—
5.0
TBD
A
3.0
—
6.0
TBD
A
5.0
—
362
TBD
A
2.0
—
418
TBD
A
3.0
WDT Current(1)
BOR Current(1)
CxSP = 1, Comparator Current(1),
single comparator enabled
—
500
TBD
A
5.0
—
96
TBD
A
2.0
—
112
TBD
A
3.0
—
132
TBD
A
5.0
—
.03
TBD
A
3.0
—
0.36
TBD
A
5.0
A/D Current(1), no conversion in
progress
—
0.2
TBD
A
3.0
DAC Current(1,3)
—
0.4
TBD
A
5.0
—
59
TBD
A
3.0
—
98
TBD
A
5.0
CxSP = 0, Comparator Current(1),
single comparator enabled
FVR Current(1), FVRBUFEN = 1,
REFOUT buffer enabled
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Both or one input reference are in high z-state.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 173
PIC12F752/HV752
20.6
DC Characteristics: PIC12HV752 - I (Industrial)
DC CHARACTERISTICS
Param
No.
D020
Device Characteristics
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
Min
Typ†
Max
Units
Conditions
—
135
TBD
A
2.0
—
210
TBD
A
3.0
PIC12HV752
—
260
TBD
A
4.5
—
135
TBD
A
2.0
D021
D022
D023
D024
D025
D026
D027
Note
VDD
Power-down Base
Current (IPD)(2,3)
WDT, BOR, Comparator, DAC and
FVR disabled
WDT Current(1)
—
210
TBD
A
3.0
—
265
TBD
A
4.5
—
215
TBD
A
3.0
—
265
TBD
A
4.5
—
362
TBD
A
2.0
—
418
TBD
A
3.0
—
450
TBD
A
4.5
—
90
TBD
A
2.0
—
107
TBD
A
3.0
—
127
TBD
A
4.5
—
210
TBD
A
3.0
—
260
TBD
A
4.5
A/D Current(1), no conversion in
progress
—
215
TBD
A
3.0
DAC Current(1)
—
265
TBD
A
4.5
—
485
TBD
A
3.0
—
615
TBD
A
4.5
BOR Current(1)
CxSP = 1, Comparator Current(1),
single comparator enabled
CxSP = 0, Comparator Current(1),
single comparator enabled
FVR Current(1), FVRBUFEN = 1,
REFOUT buffer enabled
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Shunt regulator is always on and always draws operating current.
DS41576B-page 174
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
20.7
DC Characteristics: PIC12HV752-E (Extended)
DC CHARACTERISTICS
Param
No.
D020E
Device Characteristics
Power-down Base
Current (IPD)(2,3)
PIC12HV752
D021E
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C for extended
Min
Typ†
Max
Units
—
135
TBD
A
Conditions
VDD
2.0
—
210
TBD
A
3.0
—
260
TBD
A
4.5
—
135
TBD
A
2.0
—
210
TBD
A
3.0
—
265
TBD
A
4.5
D022E
—
215
TBD
A
3.0
—
265
TBD
A
4.5
D023E
—
185
TBD
A
2.0
D024E
—
265
TBD
A
3.0
—
320
TBD
A
4.5
—
90
TBD
A
2.0
—
107
TBD
A
3.0
Note
WDT, BOR, Comparator, DAC and
FVR disabled
WDT Current(1)
BOR Current(1)
CxSP = 1, Comparator Current(1),
single comparator enabled
CxSP = 0, Comparator Current(1),
single comparator enabled
—
127
TBD
A
4.5
D025E
—
210
TBD
A
3.0
—
260
TBD
A
4.5
A/D Current(1), no conversion in
progress
D026E
—
215
TBD
A
3.0
DAC Current(1)
—
265
TBD
A
4.5
D027E
—
485
TBD
A
3.0
—
615
TBD
A
4.5
FVR Current(1), FVRBUFEN = 1,
REFOUT buffer enabled
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral  current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Shunt regulator is always on and always draws operating current.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 175
PIC12F752/HV752
20.8
DC Characteristics:
PIC12F752/HV752-I (Industrial)
PIC12F752/HV752-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym
VIL
Characteristic
Min
Typ†
Max
Units
Vss
Vss
Conditions
—
0.8
V
4.5V  VDD  5.5V
—
0.15 VDD
V
2.0V  VDD  4.5V
Vss
—
0.2 VDD
V
2.0V  VDD  5.5V
2.0
—
VDD
V
4.5V  VDD 5.5V
Input Low Voltage
I/O port:
D030
with TTL buffer
D030A
D031
with Schmitt Trigger buffer
VIH
Input High Voltage
I/O ports:
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
D042
MCLR
—
0.25 VDD + 0.8
—
VDD
V
2.0V  VDD  4.5V
0.8 VDD
—
VDD
V
2.0V  VDD  5.5V
0.8 VDD
—
VDD
V
Input Leakage Current(1,2)
IIL
D060
I/O ports
—
0.1
1
A
VSS VPIN VDD,
Pin at high-impedance
D061
RA3/MCLR(2,3)
—
0.7
5
A
VSS VPIN VDD
—
0.1
5
A
EC Configuration
50
250
400
A
VDD = 5.0V, VPIN = VSS
—
—
0.6
V
—
—
0.6
V
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
—
—
0.6
V
—
—
0.6
V
VDD – 0.7
—
—
V
VDD – 0.7
—
—
V
VDD – 0.7
—
—
V
VDD – 0.7
—
—
V
D063
D070*
IPUR
PORTA Weak Pull-up
Current(4)
D080
VOL
Output Low Voltage
I/O ports (excluding RA0, RA2)
RA0, RA2
D090
VOH
Output High Voltage
I/O ports(1) (excluding RA0, RA2)
RA0, RA2
*
†
Note 1:
2:
3:
4:
IOL = 14 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 17 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5mA, VDD = 4.5V,
-40°C to +125°C
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -5.0 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -6.0 mA, VDD = 4.5V,
-40°C to +85°C
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
This specification applies to RA3/MCLR configured as RA3 with the internal weak pull-up disabled.
This specification applies to all weak pull-up pins, including the weak pull-up found on RA3/MCLR. When RA3/MCLR is
configured as MCLR Reset pin, the weak pull-up is always enabled.
DS41576B-page 176
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
20.8
DC Characteristics:
PIC12F752/HV752-I (Industrial)
PIC12F752/HV752-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
—
—
50
pF
Conditions
Capacitive Loading Specs on
D101*
CIO
All I/O pins
Program Flash Memory
D130
EP
Cell Endurance
10K
100K
—
E/W
-40°C  TA +85°C
D130A
ED
Cell Endurance
1K
10K
—
E/W
+85°C  TA +125°C
D131
VPR
VDD for Read
VMIN
—
5.5
V
D132
VPEW
VDD for Bulk Erase/Write
4.5
—
5.5
V
D132A
VPEW
VDD for Row Erase/Write
VMIN
—
5.5
V
D133
TPEW
Erase/Write cycle time
—
2
2.5
ms
D134
TRETD
Characteristic Retention
40
—
—
*
†
Note 1:
2:
3:
4:
VMIN = Minimum operating
voltage
Year Provided no other specifications
are violated
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
This specification applies to RA3/MCLR configured as RA3 with the internal weak pull-up disabled.
This specification applies to all weak pull-up pins, including the weak pull-up found on RA3/MCLR. When RA3/MCLR is
configured as MCLR Reset pin, the weak pull-up is always enabled.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 177
PIC12F752/HV752
20.9
Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Param
No.
Sym
Characteristic
Typ
Units
84.6*
149.5*
60*
41.2*
39.9*
9*
150*
—
—
C/W
C/W
C/W
C/W
C/W
C/W
C
W
W
—
—
W
W
Conditions
TH01
JA
Thermal Resistance
Junction to Ambient
TH02
JC
Thermal Resistance
Junction to Case
TH03
TH04
TH05
TDIE
Die Temperature
PD
Power Dissipation
PINTERNAL Internal Power Dissipation
TH06
TH07
PI/O
PDER
*
Note 1:
2:
These parameters are characterized but not tested.
IDD is current to run the chip alone without driving any load on the output pins.
TA = Ambient temperature.
DS41576B-page 178
I/O Power Dissipation
Derated Power
Preliminary
8-pin PDIP package
8-pin SOIC package
8-pin DFN 3x3mm package
8-pin PDIP package
8-pin SOIC package
8-pin DFN 3x3mm package
PD = PINTERNAL + PI/O
PINTERNAL = IDD x VDD
(NOTE 1)
PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))
PDER = PDMAX (TDIE - TA)/JA
(NOTE 2)
 2011 Microchip Technology Inc.
PIC12F752/HV752
20.10
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O Port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-Impedance)
L
Low
FIGURE 20-3:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-Impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL=50 pF for all pins
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 179
PIC12F752/HV752
20.11 AC Characteristics: PIC12F752/HV752 (Industrial, Extended)
FIGURE 20-4:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS02
OS04
OS04
OS03
CLKOUT
CLKOUT
(CLKOUT Mode)
TABLE 20-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Param
No.
Sym
OS01
FOSC
Characteristic
External CLKIN Frequency(1)
(1)
Min
Typ†
Max
Units
Conditions
DC
—
20
MHz
EC Oscillator mode
OS02
TOSC
External CLKIN Period
50
—

ns
EC Oscillator mode
OS03
TCY
Instruction Cycle Time(1)
200
TCY
DC
ns
TCY = 4/FOSC
*
†
Note 1:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
DS41576B-page 180
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 20-2:
OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
No.
Sym
Characteristic
OS06
TWARM
Internal Oscillator Switch
when running(3)
OS07
INTOSC
Internal Calibrated
INTOSC Frequency(2)
(4 MHz)
OS08
INTOSC
OS10*
Internal Calibrated
INTOSC Frequency(2)
(8 MHz)
TIOSC ST INTOSC Oscillator Wakeup from Sleep
Start-up Time
Legend:
*
†
Note 1:
2:
3:
Freq.
Tolerance
Min
Typ†
Max
Units
—
—
—
2
TOSC
Conditions
Slowest clock
1%
3.96
4.0
4.04
MHz
VDD = 3.5V, TA = 25°C
2%
3.92
4.0
4.08
MHz
2.5V VDD  5.5V,
0°C  TA  +85°C
5%
3.80
4.0
4.2
MHz
2.0V VDD  5.5V,
-40°C  TA  +85°C (Ind.),
-40°C  TA  +125°C (Ext.)
1%
7.92
8.0
8.08
MHz
VDD = 3.5V, TA = 25°C
2%
7.84
8.0
8.16
MHz
2.5V VDD  5.5V,
0°C  TA  +85°C
5%
7.60
8.0
8.40
MHz
2.0V VDD  5.5V,
-40°C  TA  +85°C (Ind.),
-40°C  TA  +125°C (Ext.)
—
TBD
12
TBD
s
VDD = 2.0V, -40°C to +85°C
—
TBD
7
TBD
s
VDD = 3.0V, -40°C to +85°C
—
TBD
6
TBD
s
VDD = 5.0V, -40°C to +85°C
TBD = To Be Determined
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to the CLKIN pin.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
By design.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 181
PIC12F752/HV752
FIGURE 20-5:
CLKOUT AND I/O TIMING
Cycle
Write
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS20
CLKOUT
OS21
OS19
OS18
OS16
OS13
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 20-3:
CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
OS13
Sym
TCKL2IOV
Characteristic
CLKOUT to Port out valid(1)
CLKOUT(1)
Min
Typ†
Max
Units
—
—
20
ns
Conditions
OS14
TIOV2CKH
Port input valid before
TOSC + 200 ns
—
—
ns
OS15
TOSH2IOV
FOSC (Q1 cycle) to Port out valid
—
50
70*
ns
VDD = 5.0V
OS16
TOSH2IOI
FOSC (Q2 cycle) to Port input invalid
(I/O in hold time)
50
—
—
ns
VDD = 5.0V
OS17
TIOV2OSH
Port input valid to FOSC(Q2 cycle)
(I/O in setup time)
20
—
—
ns
OS18
TIOR
Port output rise time(1)
—
—
15
40
72
32
ns
VDD = 2.0V
VDD = 5.0V
OS19
TIOF
Port output fall time(1)
—
—
28
15
55
30
ns
VDD = 2.0V
VDD = 5.0V
OS20*
TINP
INT pin input high or low time
25
—
—
ns
OS21*
TRAP
PORTA interrupt-on-change new input
level time
TCY
—
—
ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated.
Note 1: Includes CLKOUTEN = 0, CLKOUT function enabled.
DS41576B-page 182
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
FIGURE 20-6:
RESET, WATCHDOG TIMER, AND POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note
1:
FIGURE 20-7:
Asserted low.
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR + VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
*
33*
64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 183
PIC12F752/HV752
TABLE 20-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
TMCL
MCLR Pulse Width (low)
2
5
—
—
—
—
s
s
VDD = 5V, -40°C to +85°C
VDD = 5V, -40°C to +125°C
31*
TWDT
Watchdog Timer Time-out
Period (No Prescaler)
10
10
20
20
TBD
TBD
ms
ms
VDD = 5V, -40°C to +85°C
VDD = 5V, -40°C to +125°C
32*
TPWRT
Power-up Timer Period
40
65
140
ms
33*
TIOZ
I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
—
—
2.0
s
34
VBOR
Brown-out Reset Voltage
2.0
2.15
2.3
V
35*
VHYST
Brown-out Reset Hysteresis
—
100
—
mV
36*
TBOR
Brown-out Reset Minimum
Detection Period
100
—
—
s
(NOTE 4)
VDD  VBOR
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an external clock applied to the CLKIN pin. When an external clock input is used, the “max” cycle time
limit is “DC” (no clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
DS41576B-page 184
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
FIGURE 20-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 20-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
No.
40*
Sym
TT0H
Characteristic
T0CKI High Pulse Width
Min
No Prescaler
TT0L
T0CKI Low Pulse Width
No Prescaler
TT0P
T0CKI Period
45*
TT1H
T1CKI High Synchronous, No Prescaler
Time
Synchronous,
with Prescaler
—
—
ns
—
—
ns
0.5 TCY + 20
—
—
ns
10
—
—
ns
Greater of:
20 or TCY + 40
N
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
Asynchronous
46*
TT1L
T1CKI Low
Time
Synchronous, No Prescaler
30
—
—
ns
0.5 TCY + 20
—
—
ns
15
—
—
ns
Synchronous,
with Prescaler
Asynchronous
47*
TT1P
T1CKI Input Synchronous
Period
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
30
—
—
ns
Greater of:
30 or TCY + 40
N
—
—
ns
Asynchronous
*
†
Units
10
With Prescaler
42*
Max
0.5 TCY + 20
With Prescaler
41*
Typ†
60
—
—
ns
2 TOSC
—
7 TOSC
—
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync
mode
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 185
PIC12F752/HV752
FIGURE 20-9:
PIC12F752/HV752 CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP1
(Capture mode)
CC01
CC02
CC03
Note:
TABLE 20-6:
Refer to Figure 20-3 for load conditions.
PIC12F752/HV752 CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
CC01*
CC02*
CC03*
Sym
TccL
TccH
TccP
Characteristic
CCP1 Input Low Time
CCP1 Input High Time
Min
Typ†
Max
Units
No Prescaler
0.5TCY + 20
—
—
ns
With Prescaler
20
—
—
ns
No Prescaler
0.5TCY + 20
—
—
ns
With Prescaler
20
—
—
ns
3TCY + 40
N
—
—
ns
CCP1 Input Period
Conditions
N = prescale
value (1, 4 or
16)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 20-7:
COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym
Characteristics
Min
Typ†
Max
Units
CM01
VOS
Input Offset Voltage(2)
—
—
 5.0
 7.0
 10
 20
mV
mV
CM02
VCM
Input Common Mode Voltage
0
—
VDD – 1.5
V
CM03* CMRR
Common Mode Rejection Ratio
CM04* TRT
Response Time(1)
CxSP = 1
CxSP = 0
+55
—
—
dB
—
55
TBD
ns
—
65
TBD
ns
CM05* TMC2COV Comparator Mode Change to Output Valid
—
—
10
s
CM06* VHYS
—
20
TBD
mV
Input Hysteresis Voltage
Comments
CxSP = 1
CxSP = 0
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.
The other input is at (VDD -1.5)/2.
2: Input offset voltage is measured with one comparator input at (VDD - 1.5V)/2.
DS41576B-page 186
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 20-8:
DIGITAL-TO-ANALOG (DAC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Param
No.
Sym
Characteristics
Min
Typ†
Max
Units
—
V
DA01*
CLSB
Step Size
—
VDD/32
DA02*
CACC
Absolute Accuracy
—
 1/2
—
LSB
DA03*
CR
Unit Resistor Value (R)
—
TBD
—

DA04*
CST
Settling Time
—
10
—
s
Comments
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 20-9:
FIXED VOLTAGE REFERENCE SPECIFICATIONS
VR Voltage Reference Specifications
Param
No.
Symbol
Characteristics
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Min
Typ
Max
Units
VR01*
VFVR
FVR Voltage Output
—
1.2
—
V
VR02*
TSTABLE
FVR Turn On Time
—
200
—
s
*
Comments
These parameters are characterized but not tested.
TABLE 20-10: SHUNT REGULATOR SPECIFICATIONS (PIC12HV752 only)
SHUNT REGULATOR CHARACTERISTICS
Param
No.
Symbol
Characteristics
SR01
VSHUNT Shunt Voltage
SR02
ISHUNT
SR03*
TSETTLE Settling Time
SR04
CLOAD
Load Capacitance
SR05
ISNT
Regulator operating current
*
Shunt Current
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Min
Typ
Max
Units
Comments
4.75
5
5.4
V
4
—
50
mA
—
—
150
ns
To 1% of final value
0.01
—
10
F
Bypass capacitor on VDD
pin
—
180
—
A
Includes band gap
reference current
These parameters are characterized but not tested.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 187
PIC12F752/HV752
TABLE 20-11: PIC12F752/HV752 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
AD01
NR
Resolution
—
—
10 bits
AD02
EIL
Integral Error
—
—
1
LSb VREF = 5.12V(5)
AD03
EDL
Differential Error
—
—
1
LSb No missing codes to 10 bits
VREF = 5.12V(5)
AD04
EOFF
Offset Error
—
+1.5
+2.0
LSb VREF = 5.12V(5)
AD07
EGN
Gain Error
—
—
1
LSb VREF = 5.12V(5)
2.2
2.5
—
—
VDD
V
(3)
bit
AD06 VREF
AD06A
Reference Voltage
AD07
VAIN
Full-Scale Range
VSS
—
VREF
V
AD08
ZAIN
Recommended
Impedance of Analog
Voltage Source
—
—
10
k
AD09* IREF
VREF Input Current(3)
10
—
1000
A
During VAIN acquisition.
Based on differential of VHOLD to VAIN.
—
—
50
A
During A/D conversion cycle.
Absolute minimum to ensure 1 LSb
accuracy
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current
specification includes any such leakage from the ADC module.
5: VREF = 5V for PIC12HV752.
DS41576B-page 188
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
TABLE 20-12: PIC12F752/HV752 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C  TA  +125°C
Param
No.
Sym
Characteristic
Min
Typ†
1.6
—
9.0
s
TOSC-based, VREF 3.0V
3.0
—
9.0
s
TOSC-based, VREF full range(3)
3.0
6.0
9.0
s
ADCS<2:0> = 11
At VDD = 2.5V
1.6
4.0
6.0
s
At VDD = 5.0V
—
11
—
TAD
Set GO/DONE bit to new data in A/D
Result register
A/D Clock Period
AD130* TAD
A/D Internal RC
Oscillator Period
AD131 TCNV
Conversion Time
(not including
Acquisition Time)(1)
11.5
—
s
Amplifier Settling Time
—
—
5
s
Q4 to A/D Clock Start
—
TOSC/2
—
—
AD132* TACQ Acquisition Time
AD133*
TAMP
AD134 TGO
Max Units
Conditions
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.
2: See Section 12.4 “A/D Acquisition Requirements” for minimum conditions.
3: Full range for PIC12HV752 powered by the shunt regulator is the 5V regulated voltage.
FIGURE 20-10:
PIC12F752/HV752 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
1 TCY
(TOSC/2)
AD134
AD131
Q4
AD130
A/D CLK
9
A/D Data
8
7
6
OLD_DATA
ADRES
2
1
0
NEW_DATA
1 TCY
ADIF
GO
Sample
3
DONE
AD132
 2011 Microchip Technology Inc.
Sampling Stopped
Preliminary
DS41576B-page 189
PIC12F752/HV752
FIGURE 20-11:
PIC12F752/HV752 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
(TOSC/2 + TCY)
1 TCY
AD131
Q4
AD130
A/D CLK
9
A/D Data
7
8
6
OLD_DATA
ADRES
3
2
1
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
DS41576B-page 190
Sampling Stopped
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
21.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 191
PIC12F752/HV752
NOTES:
DS41576B-page 192
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
22.0
PACKAGING INFORMATION
22.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
XXXXXXXX
XXXXXNNN
12F752
E/P e3 121
YYWW
1109
8-Lead SOIC (3.90 mm)
Example
12F752
ESN1109
121
NNN
Legend:
XX...X
Y
YY
WW
NNN
e3
*
Note:
*
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.
Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC
device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP
devices, any special marking adders are included in QTP price.
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 193
PIC12F752/HV752
22.2
Package Marking Information
8-Lead DFN (3x3x0.9 mm)
Example
XXXX
YYWW
NNN
MFU0
1109
121
PIN 1
TABLE 22-1:
PIN 1
8-LEAD 3X3 DFN (MF) TOP MARKING
Part Number
PIC12F752-E/MF
MFU0
PIC12F752-I/MF
MFV0
PIC12HV752-E/MF
MFW0
PIC12HV752-I/MF
MFX0
Legend:
XX...X
Y
YY
WW
NNN
e3
*
Note:
*
Marking
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.
Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For PIC
device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP
devices, any special marking adders are included in QTP price.
DS41576B-page 194
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
22.3
Package Details
The following sections give the technical details of the packages.
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 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 195
PIC12F752/HV752
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41576B-page 196
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 197
PIC12F752/HV752
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41576B-page 198
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
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 2011 Microchip Technology Inc.
Preliminary
DS41576B-page 199
PIC12F752/HV752
NOTES:
DS41576B-page 200
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
APPENDIX A:
DATA SHEET
REVISION HISTORY
APPENDIX B:
MIGRATING FROM
PIC12HV615
This compares the features of the PIC12HV615 to the
PIC12HV752 family of devices.
Revision A
Original release (4/2011).
B.1
Revision B
PIC12HV615 to PIC12HV752
TABLE B-1:
Redefined operation of the COG module; Added slew
rate control to the COG module; Added zero latency
filter to the comparator; Updated Electrical Specifications.
FEATURE COMPARISON
Feature
PIC12HV615
PIC12HV752
20 MHz
20 MHz
Max Program
Memory (Words)
1024
1024
Flash Self Read/
Self Write
No
Yes
SRAM (bytes)
64
64
Oscillator modes
8
2
4/8 MHz
1/4/8 MHz
and 31 kHz
Y
Y
Internal Pull-ups
GP0/1/2/3/4/5
RA0/1/2/3/4/5
Interrupt-on-change
GP0/1/2/3/4/5
RA0/1/2/3/4/5
4
4
10-bit
10-bit
Max Operating Speed
INTOSC Frequencies
Brown-out Reset (BOR)
Analog-to-Digital
Converter (ADC)
Channels
A/D Resolution
Timers (8/16-bit)
2/1
3/1
Comparator
1
2 High Speed
ECCP/CCP
1/0
0/1
Complementary Output
Generator (COG)
No
Yes
Digital-to-Analog Converter
(DAC) 5-bit Dual Range
No
Yes
Fixed Voltage Reference
(FVR)
No
Yes
Internal Shunt Regulator
Yes
Yes
Note:
 2011 Microchip Technology Inc.
Preliminary
This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performance characteristics than its earlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.
DS41576B-page 201
PIC12F752/HV752
NOTES:
DS41576B-page 202
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
INDEX
A
A/D
Specifications.................................................... 188, 189
Absolute Maximum Ratings .............................................. 167
AC Characteristics
Industrial and Extended ............................................ 180
Load Conditions ........................................................ 179
ADC .................................................................................. 101
Acquisition Requirements ......................................... 109
Associated registers.................................................. 111
Block Diagram........................................................... 101
Calculating Acquisition Time..................................... 109
Channel Selection..................................................... 102
Configuration............................................................. 102
Configuring Interrupt ................................................. 105
Conversion Clock...................................................... 102
Conversion Procedure .............................................. 105
Internal Sampling Switch (RSS) Impedance.............. 109
Interrupts................................................................... 103
Operation .................................................................. 104
Operation During Sleep ............................................ 104
Port Configuration ..................................................... 102
Reference Voltage (VREF)......................................... 102
Result Formatting...................................................... 104
Source Impedance.................................................... 109
Special Event Trigger................................................ 104
Starting an A/D Conversion ...................................... 104
ADCON0 Register............................................................. 106
ADCON1 Register............................................................. 107
ADRESH Register (ADFM = 0) ......................................... 108
ADRESH Register (ADFM = 1) ......................................... 108
ADRESL Register (ADFM = 0).......................................... 108
ADRESL Register (ADFM = 1).......................................... 108
Alternate Pin Function......................................................... 46
Analog-to-Digital Converter. See ADC
ANSELA Register ............................................................... 50
APFCON Register............................................................... 46
Assembler
MPASM Assembler................................................... 164
B
Block Diagrams
(CCP) Capture Mode Operation ................................. 77
ADC .......................................................................... 101
ADC Transfer Function ............................................. 110
Analog Input Model ........................................... 110, 126
CCP PWM................................................................... 81
Clock Source............................................................... 39
Compare ..................................................................... 79
Digital-to-Analog Converter (DAC)............................ 115
Generic I/O Port .......................................................... 45
HLTMR1...................................................................... 73
In-Circuit Serial Programming Connections.............. 160
Interrupt Logic ........................................................... 153
MCLR Circuit............................................................. 145
On-Chip Reset Circuit ............................................... 143
PIC12F752/HV752........................................................ 9
Timer1....................................................... 59, 64, 65, 66
Timer2......................................................................... 71
TMR0/WDT Prescaler................................................. 55
Voltage Reference .................................................... 113
Voltage Reference Output Buffer Example............... 117
Watchdog Timer........................................................ 156
 2011 Microchip Technology Inc.
Brown-out Reset (BOR).................................................... 146
Associated Registers................................................ 146
Specifications ........................................................... 184
Timing and Characteristics ....................................... 183
C
C Compilers
MPLAB C18.............................................................. 164
Calibration Bits.................................................................. 143
Capture Module. See Capture/Compare/PWM (CCP)
Capture/Compare/PWM ..................................................... 77
Capture/Compare/PWM (CCP) .......................................... 77
Associated Registers w/ Capture ............................... 78
Associated Registers w/ Compare ............................. 80
Capture Mode............................................................. 77
CCP1 Pin Configuration ............................................. 77
Compare Mode........................................................... 79
CCP1 Pin Configuration ..................................... 79
Software Interrupt Mode ............................... 77, 79
Special Event Trigger ......................................... 79
Timer1 Mode Resource ................................ 77, 79
Prescaler .................................................................... 77
PWM Mode
Duty Cycle .......................................................... 82
PWM Operation .......................................................... 81
PWM Overview........................................................... 81
PWM Period ............................................................... 82
PWM Setup ................................................................ 82
Specifications ........................................................... 186
CCP. See Capture/Compare/PWM
CCP1CON (CCP1) Register............................................... 83
Clock Sources
External Modes
EC ...................................................................... 40
Internal Modes............................................................ 40
CMOUT Register .............................................................. 128
CMxCON0 Register .......................................................... 127
CMxCON1 Register .......................................................... 128
Code Examples
A/D Conversion ........................................................ 105
Assigning Prescaler to Timer0.................................... 56
Assigning Prescaler to WDT....................................... 56
Changing Between Capture Prescalers ..................... 77
Indirect Addressing..................................................... 26
Initializing PORTA ...................................................... 45
Saving Status and W Registers in RAM ................... 155
Writing to Flash Program Memory.............................. 36
Code Protection ................................................................ 159
COGxASD Register ............................................................ 97
COGxBLK Register............................................................. 98
COGxCON0 Register ......................................................... 95
COGxCON1 Register ......................................................... 96
COGxDB Register .............................................................. 98
COGxPH Register .............................................................. 98
Comparator....................................................................... 121
Associated Registers................................................ 129
Operation.................................................................. 121
Comparator Module .......................................................... 121
Cx Output State Versus Input Conditions................. 123
Comparators
C2OUT as T1 Gate..................................................... 61
Specifications ........................................................... 186
Compare Module. See Capture/Compare/PWM (CCP)
CONFIG1 Register ........................................................... 142
Preliminary
DS41576B-page 203
PIC12F752/HV752
Configuration Bits.............................................................. 141
CPU Features ................................................................... 141
Customer Change Notification Service ............................. 207
Customer Notification Service........................................... 207
Customer Support ............................................................. 207
D
DACCON0 (Digital-to-Analog Converter Control 0)
Register..................................................................... 118
DACCON1 (Digital-to-Analog Converter Control 1)
Register..................................................................... 118
Data Memory....................................................................... 11
DC Characteristics
Extended and Industrial ............................................ 176
Industrial and Extended ............................................ 169
Development Support ....................................................... 163
Device Overview ................................................................... 9
Digital-to-Analog (DAC)
Specifications ............................................................ 187
Digital-to-Analog Converter (DAC).................................... 115
Associated Registers ................................................ 119
Effects of a Reset...................................................... 117
E
Electrical Specifications .................................................... 167
Errata .................................................................................... 7
F
Firmware Instructions........................................................ 131
Fixed Voltage Reference (FVR)
Associated Registers ................................................ 114
Specifications ............................................................ 187
Flash Program Memory
Associated Registers .................................................. 37
Configuration Word w/ Flash Program Memory .......... 37
Flash Program Memory Self Read/Self Write Control......... 29
FVRCON (Fixed Voltage Reference Control) Register ..... 114
G
General Purpose Register File............................................ 12
H
Hardware Limit Timer (HLT)................................................ 73
High Temperature Operation ............................................ 190
HLT
Associated registers.................................................... 76
HLT1CON0 (HLT1 Control 0) Register ............................... 75
HLT1CON1 (HLT1 Control 1) Register ............................... 76
I
ID Locations ...................................................................... 159
In-Circuit Serial Programming (ICSP) ............................... 160
Indirect Addressing, INDF and FSR registers ..................... 26
Instruction Format ............................................................. 131
Instruction Set ................................................................... 131
ADDLW ..................................................................... 133
ADDWF ..................................................................... 133
ANDLW ..................................................................... 133
ANDWF ..................................................................... 133
MOVF........................................................................ 136
BCF ........................................................................... 133
BSF ........................................................................... 133
BTFSC ...................................................................... 133
BTFSS ...................................................................... 134
CALL ......................................................................... 134
CLRF......................................................................... 134
DS41576B-page 204
CLRW ....................................................................... 134
CLRWDT .................................................................. 134
COMF ....................................................................... 134
DECF ........................................................................ 134
DECFSZ ................................................................... 135
GOTO ....................................................................... 135
INCF ......................................................................... 135
INCFSZ..................................................................... 135
IORLW ...................................................................... 135
IORWF...................................................................... 135
MOVLW .................................................................... 136
MOVWF .................................................................... 136
NOP .......................................................................... 136
RETFIE ..................................................................... 137
RETLW ..................................................................... 137
RETURN................................................................... 137
RLF ........................................................................... 138
RRF .......................................................................... 138
SLEEP ...................................................................... 138
SUBLW ..................................................................... 138
SUBWF..................................................................... 139
SWAPF ..................................................................... 139
XORLW .................................................................... 139
XORWF .................................................................... 139
Summary Table ........................................................ 132
INTCON Register................................................................ 20
Internal Oscillator Block
INTOSC
Specifications ........................................... 181, 182
Internal Sampling Switch (RSS) Impedance...................... 109
Internet Address ............................................................... 207
Interrupts........................................................................... 152
ADC .......................................................................... 105
Associated Registers ................................................ 154
Context Saving ......................................................... 155
Interrupt-on-Change ................................................... 49
PORTA Interrupt-on-Change .................................... 153
RA2/INT .................................................................... 152
Timer0 ...................................................................... 153
TMR1 .......................................................................... 63
INTOSC Specifications ............................................. 181, 182
IOCAF Register .................................................................. 52
IOCAN Register .................................................................. 52
IOCAP Register .................................................................. 52
L
LATA Register .................................................................... 48
Load Conditions................................................................ 179
M
MCLR................................................................................ 145
Internal...................................................................... 145
Memory Organization ................................................... 11, 85
Data ............................................................................ 11
Program ...................................................................... 11
Microchip Internet Web Site.............................................. 207
Migrating from other PIC Devices..................................... 201
MPLAB ASM30 Assembler, Linker, Librarian ................... 164
MPLAB Integrated Development Environment Software.. 163
MPLAB PM3 Device Programmer .................................... 166
MPLAB REAL ICE In-Circuit Emulator System ................ 165
MPLINK Object Linker/MPLIB Object Librarian ................ 164
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
O
R
OPCODE Field Descriptions ............................................. 131
Operation During Code Protect........................................... 34
Operation During Write Protect ........................................... 34
Operational Amplifier (OPA) Module
AC Specifications...................................................... 187
OPTION Register ................................................................ 19
OPTION_REG Register ...................................................... 57
Oscillator
Associated registers........................................ 43, 69, 99
Configuration Word ..................................................... 43
Oscillator Module .......................................................... 29, 39
Oscillator Parameters ....................................................... 181
Oscillator Specifications .................................................... 180
Oscillator Start-up Timer (OST)
Specifications............................................................ 184
OSCTUNE Register ............................................................ 43
Reader Response............................................................. 208
Reading the Flash Program Memory.................................. 32
Read-Modify-Write Operations ......................................... 131
Registers
ADCON0 (ADC Control 0) ........................................ 106
ADCON1 (ADC Control 1) ........................................ 107
ADRESH (ADC Result High) with ADFM = 0) .......... 108
ADRESH (ADC Result High) with ADFM = 1) .......... 108
ADRESL (ADC Result Low) with ADFM = 0)............ 108
ADRESL (ADC Result Low) with ADFM = 1)............ 108
ANSELA (PORTA Analog Select) .............................. 50
APFCON (Alternate Pin Function Control) ................. 46
CCP1CON (CCP1 Control) ........................................ 83
CMOUT (Comparator Output) .................................. 128
CMxCON0 (Cx Control) ............................................ 127
CMxCON1 (Cx Control 1)......................................... 128
COGxASD (COG Auto-Shutdown Control) ................ 97
COGxBLK (COG Blanking Deadband Counter) ......... 98
COGxCON0 (COG Control 0) .................................... 95
COGxCON1 (COG Control 1) .................................... 96
COGxDB (COG Deadband Counter).......................... 98
COGxPH (COG Blanking Phase Counter) ................. 98
Configuration Word 1................................................ 142
DACCON0 ................................................................ 118
DACCON1 ................................................................ 118
Data Memory Map ...................................................... 13
FVRCON .................................................................. 114
HLT1CON0................................................................. 75
HLT1CON1................................................................. 76
INTCON (Interrupt Control) ........................................ 20
IOCAF (Interrupt-on-Change Flag)............................. 52
IOCAN (Interrupt-on-Change Negative Edge)............ 52
IOCAP (Interrupt-on-Change Positive Edge).............. 52
LATA (Data Latch PORTA) ........................................ 48
OPTION_REG (OPTION)..................................... 19, 57
OSCTUNE (Oscillator Tuning).................................... 43
PCON (Power Control) ....................................... 25, 147
PIE1 (Peripheral Interrupt Enable 1) .......................... 21
PIE2 (Peripheral Interrupt Enable 2) .......................... 22
PIR1 (Peripheral Interrupt Register 1) ........................ 23
PIR2 (Peripheral Interrupt Register 2) ........................ 24
PMCON1 (Program Memory Control 1) ..................... 31
PMDATH (Program Memory Data)............................. 30
PMDATL (Program Memory Data) ............................. 30
PMDRH (Program Memory Address) ......................... 30
PORTA ....................................................................... 48
Reset Values ............................................................ 149
Reset Values (special registers)............................... 151
Special Function Registers......................................... 12
STATUS ..................................................................... 18
T1CON (Timer1 Control) ............................................ 67
T1GCON (Timer1 Gate Control)................................. 68
T2CON ....................................................................... 72
TRISA (Tri-State PORTA) .......................................... 48
WPUA (Weak Pull-up PORTA)................................... 50
Reset ................................................................................ 143
Revision History................................................................ 201
P
Packaging ......................................................................... 193
Marking ............................................................. 193, 194
PDIP Details.............................................................. 194
PCL and PCLATH ............................................................... 26
Stack ........................................................................... 26
PCON Register ........................................................... 25, 147
PIE1 Register ...................................................................... 21
PIE2 Register ...................................................................... 22
Pinout Descriptions
PIC12F752/HV752...................................................... 10
PIR1 Register...................................................................... 23
PIR2 Register...................................................................... 24
PMADRH and PMADRL Registers ..................................... 29
PMCON1 and PMCON2 Registers ..................................... 29
PMCON1 Register .............................................................. 31
PMDATH Register .............................................................. 30
PMDATL Register ............................................................... 30
PMDRH Register ................................................................ 30
PORTA
Additional Pin Functions ............................................. 49
ANSEL Register.................................................. 49
Interrupt-on-Change ........................................... 49
Slew Rate Control ............................................... 49
Weak Pull-Ups .................................................... 49
Associated Registers .................................................. 53
RA2 ............................................................................. 53
RA3 ............................................................................. 53
RA4 ............................................................................. 53
Specifications............................................................ 182
PORTA Register ................................................................. 48
Power-Down Mode (Sleep) ............................................... 158
Power-on Reset (POR) ..................................................... 144
Power-up Timer (PWRT) .................................................. 145
Specifications............................................................ 184
Precision Internal Oscillator Parameters........................... 182
Prescaler
Shared WDT/Timer0 ................................................... 56
Switching Prescaler Assignment................................. 56
Program Memory ................................................................ 11
Map and Stack ............................................................ 11
Programming, Device Instructions .................................... 131
Protection Against Spurious Write ...................................... 34
PWM (CCP Module)
PWM Steering............................................................. 83
PWM Steering ..................................................................... 83
 2011 Microchip Technology Inc.
S
Shunt Regulator................................................................ 161
Sleep
Power-Down Mode ................................................... 158
Wake-up ................................................................... 158
Wake-up using Interrupts ......................................... 158
Preliminary
DS41576B-page 205
PIC12F752/HV752
Slew Rate Control ............................................................... 49
Software Simulator (MPLAB SIM)..................................... 165
Special Event Trigger........................................................ 104
Special Function Registers ................................................. 12
STATUS Register................................................................ 18
T
T1CON Register.................................................................. 67
T1GCON Register............................................................... 68
T2CON Register.................................................................. 72
Thermal Considerations .................................................... 178
Time-out Sequence........................................................... 147
Timer0 ................................................................................. 55
Associated Registers .................................................. 57
External Clock ............................................................. 56
Interrupt....................................................................... 57
Operation .............................................................. 55, 60
Specifications ............................................................ 185
T0CKI .......................................................................... 56
Timer1
Associated registers.................................................... 69
Asynchronous Counter Mode ..................................... 61
Reading and Writing ........................................... 61
Interrupt....................................................................... 63
Modes of Operation .................................................... 60
Operation During Sleep .............................................. 63
Prescaler ..................................................................... 61
Specifications ............................................................ 185
Timer1 Gate
Selecting Source................................................. 61
TMR1H Register ......................................................... 59
TMR1L Register .......................................................... 59
Timer2
Associated registers.............................................. 72, 76
Timers
HLT
HLT1CON0 ......................................................... 75
HLT1CON1 ......................................................... 76
Timer1
T1CON................................................................ 67
T1GCON ............................................................. 68
Timer2
T2CON................................................................ 72
Timing Diagrams
A/D Conversion ......................................................... 189
A/D Conversion (Sleep Mode) .................................. 190
Brown-out Reset (BOR) ............................................ 183
Brown-out Reset Situations ...................................... 146
Capture/Compare/PWM (CCP)................................. 186
CLKOUT and I/O....................................................... 182
Clock Timing ............................................................. 180
Comparator Output ................................................... 121
INT Pin Interrupt........................................................ 154
Time-out Sequence
Case 1............................................................... 147
Case 2............................................................... 147
Case 3............................................................... 148
Timer0 and Timer1 External Clock ........................... 185
Timer1 Incrementing Edge.......................................... 63
Wake-up from Interrupt ............................................. 159
Timing Parameter Symbology........................................... 179
TRISA Register ................................................................... 48
W
Wake-up Using Interrupts ................................................. 158
Watchdog Timer (WDT).................................................... 155
Associated registers ................................................. 157
Configuration Word w/ Watchdog Timer................... 157
Specifications ........................................................... 184
WPUA Register................................................................... 50
Writing the Flash Program Memory .................................... 34
WWW Address ................................................................. 207
WWW, On-Line Support ....................................................... 7
V
VREF. SEE ADC Reference Voltage
DS41576B-page 206
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
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Questions (FAQ), technical support requests,
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program member listing
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ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
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To register, access the Microchip web site at
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“Customer Change Notification” and follow the
registration instructions.
 2011 Microchip Technology Inc.
DS41576B-page 207
PIC12F752/HV752
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
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Please list the following information, and use this outline to provide us with your comments about this document.
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Device: PIC12F752/HV752
Literature Number: DS41576B
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41576B-page 208
Preliminary
 2011 Microchip Technology Inc.
PIC12F752/HV752
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
PART NO.
Device
-
X
Tape and Reel Temperature
Option
Range
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device:
PIC12F752
PIC12HV752
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Temperature
Range:
I
E
= -40C to +85C
= -40C to +125C
Package:
P
SN
MF
c)
d)
Pattern:
=
=
=
(Industrial)
(Extended)
Plastic DIP (PDIP)
8-lead Small Outline (150 mil) (SOIC)
8-lead Plastic Dual Flat, No Lead (3x3) (DFN)
QTP, SQTP, Code or Special Requirements
(blank otherwise)
 2011 Microchip Technology Inc.
Preliminary
PIC12F752T - I/MF 301
Tape and Reel,
Industrial temperature,
DFN 3x3 package,
QTP pattern #301
PIC12F752 - E/P
Extended temperature
PDIP package
PIC12F752 - E/SN
Extended temperature,
SOIC package
PIC12HV752 - E/MF
Extended temperature,
DFN 3x3 package
Note 1:
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
T = in tape and reel for SOIC and DFN
packages only.
DS41576B-page 209
Worldwide Sales and Service
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Corporate Office
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China - Zhuhai
Tel: 86-756-3210040
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DS41576B-page 210
Italy - Milan
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Fax: 39-0331-466781
08/02/11
Preliminary
 2011 Microchip Technology Inc.