LTC1699 Series SMBus VID Voltage Programmers U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ Fully Compliant with Intel 5-Bit Mobile (LTC1699-80) and Desktop VRM8.4 (LTC1699-81) and VRM9.0 (LTC1699-82) VID Specifications Precision ±0.35% Programmable Resistor Divider for Use with 0.8V Referenced DC/DC Converters Two Different Divider Settings Can Be Stored Using a 2-Wire SMBus Serial Interface (Rev 1.1) Built-In Safeguards Minimize Misprogramming Due to Bus Conflicts Three Open-Drain Pins (CPU_ON, IO_ON, CLK_ON) and a Global Control Pin (VRON)to Shutdown or Soft-Start 3 DC/DC Converters Simultaneously PGOOD Pin and 50µs PGOOD Timer Available in MSOP-8 and SSOP-16 Package U APPLICATIO S ■ ■ ■ ■ ■ The LTC®1699-80, LTC1699-81 and LTC1699-82 are precision (±0.35% max), digitally programmed resistor dividers that comply with Intel 5-bit mobile (LTC1699-80), desktop VRM8.4 (LTC1699-81) and VRM9.0 (LTC1699-82) VID specifications. Each IC can switch the output of a DC/DC converter between two set voltages. A digital input pin, SEL, selects one of two divider settings stored into registers via a 2-wire SMBus interface. The SMBus interface uses Write Word protocol to setup the registers and to turn the DC/DC converters on or off. Read Word protocol is used to verify register contents and to return the On/Off status of the converters. The LTC1699-80, LTC1699-81 and LTC1699-82 incorporate safeguards against errors due to bus conflicts. Three open-drain N-channel outputs (CPU_ON, IO_ON and CLK_ON) are provided to turn DC/DC converter supplies on or off via their RUN/SS inputs. A global control pin, VRON is used to turn the converters on or off simultaneously. An internal timer pulls the PGOOD pin low for 50µs if the divider setting changes or the converters are turned on via the SMBus and the VRON pin. Intel Desktop Pentium® III Power Supply Intel Mobile Pentium® Power Supply with Intel SpeedStepTM Technology Desktop AMD AthlonTM Power Supply Software Programmable Remote Power Supply Power Supplies with Voltage Margining , LTC and LT are registered trademarks of Linear Technology Corporation. AMD Athlon is a trademark of Advanced Micro Devices, Inc. Pentium is a registered trademark of Intel Corporation. Intel SpeedStep is a trademark of Intel Corporation. U TYPICAL APPLICATIO SMBus Controlled High Efficiency DC/DC Converter R9 100k VRON SDA SCL SEL 5 3 4 1 2 7 11 14 15 VRON SDA SCL SEL NC NC NC GND GND R1 39k PGOOD U1 LTC1699-81 8 13 9 10 6 12 SENSE 16 VCC CPU_ON FB IO_ON CLK_ON PGOOD VIN 5V R2, 11k C15 220pF C18 2200pF D1 C6 0.01µF C8, 0.01µF R4 10k M1 U2 LTC1778 1 2 3 4 5 6 7 8 16 RUN/SS BOOST 15 PGOOD TG 14 VRNG SW 13 FCB PGND 12 ITH BG 11 SGND INTVCC 10 ION VIN 9 VFB EXTVCC R5 715k, 1% 5VDC C14, 0.1µF C1 10µF 25V C19, 0.01µF C7 0.22µF R3 1Ω C3 10µF 25V C4 10µF 25V + L1, 1µH M2 C12 0.1µF C2 10µF 25V C13 4.7µF 6.3V D2 C9 22µF 6.3V + C10 180µF 4V + VIN 5V C5 TO 20V 10µF 35V ALUM GND VOUT 2.5V AT 10A C11 180µF 4V GND C1, C2, C3, C4, C9: TAIYO YUDAN C5: SANYO C10, C11: PANASONIC, SPCL. POLY. D1: CMDSH-3 D2: DIODES INC., B340A L1: TOKO, 919AS-1RON M1: Si4884DY M2: Si4874DY 1699 TA05 1 LTC1699 Series W W U W ABSOLUTE AXI U RATI GS (Note 1) Supply Voltage (VCC) ................................................. 7V All Pins ........................................................– 0.3V to 7V Operating Temperature Range (Note 2) ................................ –40°C ≤ TA ≤ 85°C Junction Temperature ........................................... 125°C Storage Temperature ...................... -65°C ≤ TA ≤ 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U W U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW SEL SDA SCL PGOOD 8 7 6 5 1 2 3 4 VCC GND FB SENSE LTC1699EMS8-80 LTC1699EMS8-81 LTC1699EMS8-82 MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 200°C/W MS8 PART MARKING ORDER PART NUMBER TOP VIEW SEL 1 16 VCC NC 2 15 GND SDA 3 14 GND LTC1699EGN-80 LTC1699EGN-81 LTC1699EGN-82 SCL 4 13 FB VRON 5 12 SENSE PGOOD 6 11 NC NC 7 10 CLK_ON CPU_ON 8 9 LTPV LTPW LTTB GN PART MARKING IO_ON 169980 169981 169982 GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 130°C/W Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 2.7V ≤ VCC ≤ 5.5V (Notes 3, 4) unless otherwise stated. SYMBOL PARAMETER CONDITIONS MIN TYP VCC Operating Supply Voltage Range ICC Supply Current CPU_ON, IO_ON, CLK_ON, PGOOD Pins Are Open ● RFB-SENSE Resistance between SENSE and FB LTC1699-80, LTC1699-82 ● 7 10 13 kΩ LTC1699-81 ● 14 20 26 kΩ All Divider Settings 0.35 % 2.7 MAX UNITS 5.5 V 350 µA DE Divider Error ● – 0.35 VIH SCL, SDA Input High Voltage ● 2.1 VIL SCL, SDA Input Low Voltage ● VIH SEL, VRON Input High Voltage VIL SEL, VRON Input Low Voltage VHYST SEL, VRON Hysteresis VOL SDA, CPU_ON, IO_ON, CLK_ON Output Low Voltage I = 3mA ● 0.4 V IIN SCL, SDA, SEL, VRON Input Current SDA Not Acknowledging, 0 ≤ VPIN ≤ 5.5V, VPIN = 5.5V for VRON only ● ±10 µA 2 V 1.3 ● 0.8 0.8 V 2.0 V 1.3 V ±50 mV LTC1699 Series ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 2.7V ≤ VCC ≤ 5.5V (Notes 3, 4) unless otherwise stated. SYMBOL PARAMETER CONDITIONS MIN TYP MAX ISK1 SDA, PGOOD, CPU_ON, IO_ON, CLK_ON Sink Current at VCC = 2.7V 0 ≤ VPIN ≤ 2.7V ● 5 19 60 mA ISK2 SDA, PGOOD, CPU_ON, IO_ON, CLK_ON Sink Current at VCC = 5.5V 0 ≤ VPIN ≤ 5.5V ● 35 65 150 mA ILKG PGOOD, CPU_ON, IO_ON, CLK_ON Leakage Current 0 ≤ VPIN ≤ 5.5V ● ±2 µA IPU VRON Pull-Up Current VPIN = 0 ● –7 µA 100 KHz –1 – 2.5 UNITS Timing (Note 5) fSMB SMBus Operating Frequency ● 10 tBUF Bus Free Time Between Stop/Start ● 4.7 µs tHD:STA Hold Time After (Repeated) Start ● 4.0 µs tSU:STA Repeated Start Setup Time ● 4.7 µs tSU:STO Stop Condition Setup Time ● 4.0 µs tHD:DAT Data Hold Time ● 300 ns tSU:DAT Data Setup Time ● 250 ns tLOW Clock Low Period ● 4.7 µs tHIGH Clock High Period ● 4.0 µs tf SCL, SDA Fall Time 0.9VCC to 0.65V ● 300 ns tr SCL, SDA Rise Time 0.65V to 2.25V ● 1000 ns tSSH SEL to SENSE High (Note 6) Toggle SEL to Switch from Min VOUT to Max VOUT, VFB = 0.8V 500 ns tSSL SEL to SENSE Low (Note 6) Toggle SEL to Switch from Max VOUT to Min VOUT, VFB = 0.8V 500 ns tSPL SEL Toggling to PGOOD Low Toggle SEL to Select New Code CL = 100pF, 10kΩ Pull-Up, S2 in Figure 1 ● tPH Stop Bit to CPU_ON, IO_ON or CLK_ON High (Note 7) CL = 100pF, 10kΩ Pull-Up, S2 in Figure 1 ● tPL Stop Bit to CPU_ON, IO_ON or CLK_ON Low (Note 7) CL = 0.1µF, 10kΩ Pull-Up, S1 in Figure 1 ● tPPL Stop Bit to PGOOD Low (Note 6) CL = 100pF, 10kΩ Pull-Up, S2 in Figure 1 tVH VRON High to CPU_ON, IO_ON or CLK_ON High tVL 500 ns 2 µs 50 µs ● 250 ns CL = 100pF, 10kΩ Pull-Up, S2 in Figure 1 ● 2 µs VRON Low to CPU_ON, IO_ON, CLK_ON Low CL = 0.1µF, 10kΩ Pull-Up, S1 in Figure 1 ● 50 µs tVPL VRON Low to PGOOD Low CL = 100pF, 10kΩ Pull-Up, S2 in Figure 1 ● 130 500 ns tPGL PGOOD Low Duration CL = 100pF, 10kΩ Pull-Up, S2 in Figure 1 ● 50 70 µs Note1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC1699-80E, LTC1699-81E and LTC1699-82E are guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 160 20 30 Note 4: All typical numbers are given for VCC = 5V and TA = 25°C. Note 5: These parameters are guaranteed by design and are not tested in production. SMBus timing is referenced to VIL and VIH levels. Note 6: Dominated by the switching regulator. The delay due to the LTC1699-80, LTC1699-81 or LTC1699-82 is typically 500ns. Note 7: Measured from the rising edge of SDA during Data High acknowledgement. 3 LTC1699 Series U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 300 300 250 200 150 100 20.04 20.02 200 VCC = 2.7V 150 100 19.96 19.92 0 – 55 –35 –15 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VCC (V) 5 25 45 65 85 105 125 TEMPERATURE (°C) 1699 G01 10.02 10.00 9.98 9.96 9.94 9.92 – 55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1.5 1.35 INPUT HIGH AND LOW VOLTAGE (V) 10.04 INPUT HIGH AND LOW VOLTAGE (V) 10.06 INPUT HIGH, VCC = 5.5V 1.30 INPUT LOW, VCC = 5.5V 1.25 INPUT HIGH, VCC = 2.7V 1.20 INPUT LOW, VCC = 2.7V 1.15 1.10 – 55 –35 –15 INPUT HIGH 1.3 INPUT LOW 1.2 1.1 1.0 0.9 0.8 2.5 0.07 0.09 VCC = 5.5V OUTPUT LOW VOLTAGE (V) HYSTERESIS (V) 7 IPIN = 3mA 0.07 0.06 0.05 0.04 0.03 0.02 0.01 6.5 0.25 T = 25°C 0.08 0.05 0.02 4 4.5 5 5.5 6 SUPPLY VOLTAGE (V) SDA, CPU_ON, IO_ON, CLK_ON Output Low Voltage vs Temperature 0.10 0.03 3.5 1699 G05 SCL, SDA, SEL and VRON Hysteresis vs Supply Voltage VCC = 2.7V 3 1699 G04 SCL, SDA, SEL and VRON Hysteresis vs Temperature 0 – 55 –35 –15 TA = 25°C 1.4 5 25 45 65 85 105 125 TEMPERATURE (°C) 1699 G18 0.04 SCL, SDA, SEL and VRON Input High and Low Voltage vs Supply Voltage 1.40 VCC = 2.7V TO 5.5V 5 25 45 65 85 105 125 TEMPERATURE (°C) 1699 G03 SCL, SDA, SEL and VRON Input High and Low Voltage vs Temperature 10.08 0.06 19.88 – 55 –35 –15 1699 G02 Resistance Between SENSE and FB Pins vs Temperature (LTC1699-80, LTC1699-82) RSENSE (kΩ) 19.98 19.90 0 0.20 VCC = 2.7V 0.15 0.10 VCC = 5.5V 0.05 0.01 5 25 45 65 85 105 125 TEMPERATURE (°C) 1699 G06 4 20.00 19.94 50 50 VCC = 2.7V TO 5.5V 20.06 VCC = 5.5V 250 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 20.08 TA = 25°C RSENSE (kΩ) 350 HYSTERESIS (V) Resistance Between SENSE and FB Pins vs Temperature (LTC1699-81) Supply Current vs Temperature 0 2.5 3 3.5 4 4.5 5 5.5 6 SUPPLY VOLTAGE (V) 6.5 7 1699 G07 0 – 55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1699 G08 LTC1699 Series U W TYPICAL PERFOR A CE CHARACTERISTICS SDA, PGOOD, CPU_ON, IO_ON, CLK_ON Sink Current vs Temperature 80 7 70 6 VCC = 5.5V, ISK2 60 50 40 30 VCC = 2.7V, ISK1 20 0 – 55 –35 –15 4 3 2 0 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 1699 G11 Power Good Low Duration vs Temperature VRON Pull-Up Current vs Supply Voltage 52.0 3.0 TA = 25°C VRON = 0V VRON PULL-UP CURRENT (µA) 2.45 2.40 VCC = 5.5V 2.30 2.25 2.20 2.15 2.10 2.05 VCC = 2.7V 2.5 POWER GOOD LOW DURATION (µs) 2.50 2.00 5 1699 G10 VRON Pull-Up Current vs Temperature 2.35 VPIN = 5.5V 1 10 1699 G09 VRON PULL-UP CURRENT (µA) PGOOD, CPU_ON, IO_ON, CLK_ON Leakage Current vs Temperature LEAKAGE CURRENT (nA) 15 14 VCC = 5.5V 13 VPIN = 5.5V 12 11 10 9 8 7 6 5 SCL PIN 4 3 2 SEL PIN 1 SDA PIN 0 – 55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) SINK CURRENT (mA) INPUT CURRENT (nA) SCL, SDA and SEL Input Current vs Temperature 2.0 1.5 1.0 0.5 51.5 VCC = 5.5V 51.0 50.5 VCC = 2.7V 50.0 49.5 1.95 1.90 – 55 –35 –15 1.5 2.5 3.5 4.5 5.5 SUPPLY VOLTAGE (V) 1699 G12 6.5 1699 G14 1699 G013 LTC1699-80 Divider Error vs Temperature LTC1699-81 Divider Error vs Temperature LTC1699-82 Divider Error vs Temperature 0.25 VCC = 2.7V (MINIMUM VCC) CODE 31 DIVIDER ERROR (%) 0 0.20 CODE 15 –0.05 CODE 16 –0.10 CODE 0 –0.15 –0.20 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1699 G15 0.16 VCC = 2.7V (MINIMUM VCC) 0.15 CODE 15 0.10 CODE 31 0.14 0.05 CODE 0 0 –0.05 CODE 16 0.10 0.08 0.06 0.04 –0.10 0.02 –0.15 0 –0.20 –55 –35 –15 VCC = 2.7V (MINIMUM VCC) 0.12 DIVIDER ERROR (%) 0.05 DIVIDER ERROR (%) 49.0 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 0 5 25 45 65 85 105 125 TEMPERATURE (°C) 5 25 45 65 85 105 125 TEMPERATURE (°C) 1699 G16 –0.02 – 55 –35 –15 CODE 31 CODE 15 CODE 16 CODE 0 5 25 45 65 85 105 125 TEMPERATURE (°C) 1699 G17 5 LTC1699 Series U U U PI FU CTIO S Note: Pin numbers apply to 16-lead SSOP packages. NC (Pin 7): Not connected. SEL (Pin 1): Register Select Input. A TTL compatible logic input pin that is used to select 1 of 2 resistor divider settings. SEL selects the setting in Register 0 if pulled low and the setting in Register 1 if pulled high. CPU_ON (Pin 8): CPU DC/DC Converter Control. Open drain output, usually connected to the RUN/SS pin of a DC/ DC converter that generates the CPU core supply. It pulls low to shut down the converter or becomes a high impedance state to allow the converter to soft-start. NC (Pin 2): Not connected. SDA (Pin 3): SMBus Data Input/Output. SDA is a high impedance input when address, command or data bits are shifted in. It is an open drain, N-channel output when acknowledging or sending data back to the microprocessor during read-back. It requires a pull-up resistor or current source to VCC. SCL (Pin 4): SMBus Clock Input. Data at the SDA pin is latched into the LTC1699 at the rising edge of the clock and is shifted out of the SDA pin at the falling edge of the clock. SCL is a high impedance input pin. It is driven by the open collector output of a microprocessor and requires a pullup resistor or current source to VCC. IO_ON (Pin 9): I/O DC/DC Converter Control. Open drain output, normally connected to the RUN/SS pin of the DC/ DC converter that generates the I/O supply. It pulls low to shut down the converter or becomes a high impedance state to allow the converter to soft-start. CLK_ON (Pin 10): Clock DC/DC Converter Control. Open drain output, optionally connected to the RUN/SS pin of the DC/DC converter that generates the supply for the clock buffer. It pulls low to shut down the converter or becomes a high impedance state to allow the converter to soft-start. NC (Pin 11): Not connected. VRON (Pin 5): Global Control Input. This TTL compatible input pin is pulled up internally by a 2.5µA current source. Pulling VRON low forces the open drain output pins (CPU_ON, IO_ON, CLK_ON and PGOOD) to pull to ground. If the LTC1699-80, LTC1699-81 or LTC1699-82 is programmed to turn on DC/DC converters, pulling VRON high three-states the CPU_ON, IO_ON and CLK_ON pins and allows the DC/DC converters to soft-start. SENSE (Pin 12): Sense Input. Upper terminal of the resistor divider that is connected directly to the output voltage being regulated. PGOOD (Pin 6): Power Good Output. This open drain output is pulled low for 50µs each time the LTC1699-80, LTC1699-81 or LTC1699-82 turns on the DC/DC converters or SEL is toggled to select a new code. PGOOD may be connected to the FCB input of an LTC DC/DC converter to force the converter into continuous mode operation. This reduces the time needed for the converter output to settle to a lower output voltage under light load conditions if the SEL pin is toggled. GND (Pin 15): Divider Ground. Short to Pin 14. 6 FB (Pin 13): Feedback Input. Center tap of the divider that is connected to the feedback pin of an LTC 0.8V referenced DC/DC converter. GND (Pin 14): Ground. Connect to regulator signal ground. VCC (Pin 16): Positive Supply. 2.7V ≤ VCC ≤ 5.5V. Bypass this pin to ground with a 0.1µF ceramic capacitor. LTC1699 Series W FU CTIO AL BLOCK DIAGRA U U SDA SMBus INTERFACE SCL 5 VCC POWER-ON RESET LATCH CONTROL 5 REGISTER 1 REGISTER 0 5 REGISTER CONTROL LOGIC SETUP ON/OFF STATE MACHINE ON READBACK COMMAND LATCH AND DECODER 5 MUX/DECODER SEL 3 OFF DCON SMBON SENSE R1* 5 2.5µA 50µs TIMER FB VRON R2 PGOOD GND CPU_ON *LTC1699-80, R1 = 10k LTC1699-81, R1 = 20k LTC1699-82, R1 = 10k CONVERTER CONTROL LOGIC IO_ON CLK_ON 1699 FBD TEST CIRCUIT 5V 5V S1 10k VCC SCL SCL SDA SDA SEL SEL CPU_ON OR IO_ON OR CLK_ON OR PGOOD S2 0.8V VRON VRON GND FB 0.1µF 100pF + – SENSE 1699 F01 Figure 1. Load for Timing Tests 7 S 1 1 1 1 0 4 5 6 SLAVE ADDRESS 0 3 2 0 1 7 1 8 X X X X VID0 VID1 VID3 VID2 R/W R/W X X X 9 DATA HIGH X X X DCON VID2 VID4 P X X X X X 1 1 1 0 0 0 1 0 0 0 0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SLAVE COMMAND CODE DATA LOW DATA HIGH ADDRESS S SMBus READ WORD PROTOCOL, WITH SMBus ADDRESS = 1110001B, COMMAND BYTE = 010X XXXB, DATA LOW = 0100 1000B, DATA HIGH = 0101 1000B X VID4 NOTE 1: S = START CONDITION, P = STOP CONDITION NOTE 2: C7, C6, C5 = 001 FOR SETUP, 010 FOR READ-BACK, 000 FOR ON AND 011 FOR OFF SDA SCL 0 C7 C7 0 C6 C6 0 C5 C5 1 ACK ACK 1 VID4 ACK 1 ACK RD SDA VID4 DATA LOW VID1 VID2 COMMAND CODE VID3 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 VID0 VID1 9 VID2 VID3 8 DCON 7 VID0 4 5 6 SLAVE ADDRESS ACK 3 ACK 2 VID3 1 VID1 ACK ACK P VID0 S 1699 TD01 ACK SCL TI I G DIAGRA S UW W 8 SMBus WRITE WORD PROTOCOL, WITH SMBus ADDRESS = 1110001B, COMMAND BYTE = 001X XXXB, DATA LOW = 0100 1XXXB, DATA HIGH = 0101 1XXXB Operating Sequences LTC1699 Series LTC1699 Series W UW TI I G DIAGRA S Timing for SMBus Interface t BUF SDA t HD:STA t HD:STA tf tr SCL t LOW STOP t HIGH START t SU:STO t SU:STA t HD:DAT t SU:DAT 1699 TD02 START STOP CLK_ON, IO_ON, CLK_ON, PGOOD TIMING P P SCL SDA 2nd ON PROTOCOL STOP SMBON 1.3V DCON 1.3V SEL 1.3V 2nd OFF PROTOCOL tPH CPU_ON IO_ON CLK_ON PGOOD tSPL tVL tPL 1.3V tPGL tPGL tPPL tVH 0.7V tVPL tPGL VRON VSENSE VMAX (VREF = 0.8V) VMIN 0V tSSL 10% tSSH 90% 0V NOTE: TIMING RELATIVE TO THE STOP BIT (P) IS MEASURED FROM THE RISING EDGE OF SDA SEE TABLE 1 FOR VMIN AND VMAX SENSE VOLTAGES 1699 TD03 9 LTC1699 Series U W U U APPLICATIO S I FOR ATIO In general, adjustable DC/DC Converters regulate the output voltage by dividing it down with a resistor divider and comparing the result against a precision reference voltage (VREF). As shown in the Block Diagram, the LTC1699-80, LTC1699-81 and LTC1699-82 are variable resistor dividers, which are programmed through a 2-wire SMBus interface. They are specifically designed to sim- plify the implementation of a voltage regulator module (VRM) in both portable and desktop computers. Two 5-bit divider settings can be programmed into Register 0 and Register 1 using the SMBus interface. The microprocessor selects one of these settings using the TTL compatible SEL pin to control a 10:5 multiplexer (MUX). The precision ±0.35% divider is intended to set the Table 1. DC/DC Converter Output Voltage for VREF = 0.8V 10 VID4 VID3 VID2 VID1 VID0 LTC1699-80 LTC1699-81 LTC1699-82 0 0 0 0 0 2.000V 2.05V 1.850V 0 0 0 0 1 1.950V 2.00V 1.825V 0 0 0 1 0 1.900V 1.95V 1.800V 0 0 0 1 1 1.850V 1.90V 1.775V 0 0 1 0 0 1.800V 1.85V 1.750V 0 0 1 0 1 1.750V 1.80V 1.725V 0 0 1 1 0 1.700V 1.75V 1.700V 0 0 1 1 1 1.650V 1.70V 1.675V 0 1 0 0 0 1.600V 1.65V 1.650V 0 1 0 0 1 1.550V 1.60V 1.625V 0 1 0 1 0 1.500V 1.55V 1.600V 0 1 0 1 1 1.450V 1.50V 1.575V 0 1 1 0 0 1.400V 1.45V 1.550V 0 1 1 0 1 1.350V 1.40V 1.525V 0 1 1 1 0 1.300V 1.35V 1.500V 0 1 1 1 1 1.250V 1.30V 1.475V 1 0 0 0 0 1.275V 3.50V 1.450V 1 0 0 0 1 1.250V 3.40V 1.425V 1 0 0 1 0 1.225V 3.30V 1.400V 1 0 0 1 1 1.200V 3.20V 1.375V 1 0 1 0 0 1.175V 3.10V 1.350V 1 0 1 0 1 1.150V 3.00V 1.325V 1 0 1 1 0 1.125V 2.90V 1.300V 1 0 1 1 1 1.100V 2.80V 1.275V 1 1 0 0 0 1.075V 2.70V 1.250V 1 1 0 0 1 1.050V 2.60V 1.225V 1 1 0 1 0 1.025V 2.50V 1.200V 1 1 0 1 1 1.000V 2.40V 1.175V 1 1 1 0 0 0.975V 2.30V 1.150V 1 1 1 0 1 0.950V 2.20V 1.125V 1 1 1 1 0 0.925V 2.10V 1.100V 1 1 1 1 1 0.900V 2.00V 1.075V LTC1699 Series U W U U APPLICATIO S I FOR ATIO output voltage of a DC/DC converter that generates the CPU core supply voltage. Its programmable ratios (see Table 1) are designed for 0.8V-referenced converters such as the LTC1628, LTC1702, LTC1735 and LTC1778 and comply with the Intel 5-bit desktop (VRM8.4 for LTC1699-81 and VRM9.0 for LTC1699-82) and 5-bit mobile VID codes. On power-up, the outputs of both registers are internally set to 11111B. The LTC1699-80, LTC1699-81 and LTC1699-82 provide three pins, CPU_ON, IO_ON, and CLK_ON to (optionally) control three DC/DC converters that generate the CPU, I/O and clock buffer VCC voltages in a VRM. These open drain, N-channel output pins usually connect to the RUN/SS pins of the converters and pull low to shut down the converters or become a high impedance state to allow the converters to soft-start. The PGOOD pin is driven from an internal timer that pulls PGOOD low for 50µs typical whenever the resistor divider setting is changed or the converters are allowed to softstart. Over the entire temperature and supply voltage range, the timer low period is 70µs max which meets the 100µs max converter output settling time specified by Intel. The PGOOD pin, if tied to the FCB pin of an LTC DC/ DC converter, reduces the time needed for the converter output to decrease to a lower voltage under light load conditions by forcing the converter into continuous mode for 50µs. The TTL compatible VRON input pin and the output of the internal on/off state machine (SMBON) control the state of the CPU_ON, IO_ON, CLK_ON and PGOOD pins. SMBON is accessed using SMBus protocols and must be programmed to a high state before the converters can turn on. The SMBus protocols (see Figure 2) incorporate safeguards against errors caused by bus conflicts. Resistor Divider The resistor divider is designed specifically for DC/DC converters, such as the LTC1628, LTC1702, LTC1735, LTC1778 and LTC1929 with a reference voltage of 0.8V. It consists of a fixed resistor, RFB1 connected between the SENSE and FB pins and a variable resistor, RFB2, connected between the FB and GND pins. The SENSE and FB pins are tied to the output and feedback nodes of the DC/ DC converter respectively. The output of the DC/DC converter is given by: VOUT = VREF • (RFB2+RFB1)/RFB2 where VREF is the internal reference voltage of the converter. Each resistor has a tolerance of ±30% but the ratio, (RFB2+RFB1)/RFB2, is specified to within ±0.35% over temperature. The error budget for the DC/DC converter output voltage must include the ±0.35% ratio tolerance and the tolerance in VREF. The value of RFB1 is fixed and RFB2 is changed to vary the divider setting. The value of RFB2 for any divider setting can be calculated from the above equation, assuming that RFB1 = 10kΩ for the LTC1699-80 and LTC1699-82 and 20kΩ for the LTC1699-81. Table 1 shows the output voltage of a DC/DC converter (VREF = 0.8V) for all 32 settings of the resistor divider. The divider setting is determined by the outputs (VID0-VID4) of the register selected by the SEL pin. SMBus Interface The SMBus interface uses two wires: SDA and SCL. Data to the LTC1699-80, LTC1699-81 or LTC1699-82, is latched at the rising edge of the SCL clock input and shifted out at the falling edge. The VIL and VIH logic threshold voltages of the SDA and SCL pins are 0.8V and 2.1V respectively and comply with Rev 1.1 version of the Intel System Management Bus Specifications. The Write Word and Read Word protocols (Figure 2) share three common features. First, the 7-bit slave address for both protocols is internally hardwired to 1110 001B = E2H. A single R/W bit follows the slave address. This bit is low for data transfer from the microprocessor to the LTC169980, LTC1699-81 or LTC1699-82 and high for transfers in the opposite direction. Second, the LTC1699-80, LTC1699-81 and LTC1699-82 decode only the three most significant bits of the 8-bit command code. Table 2 shows the four valid combinations. All other combinations are ignored. Third, the Data Low and Data High bytes correspond to Registers 0 and 1 respectively. In Write Word protocol with C7 = C6 = 0, C5 = 1, the five most significant bits (VID0VID4) of these bytes specify a resistor divider setting. 11 LTC1699 Series U U W U APPLICATIO S I FOR ATIO SLAVE ADDRESS ON COMMAND DATA LOW (REGISTER 0) S 1110001 R/W A 000XXXXX A DATA HIGH (REGISTER 1) DON’T CARE A DON’T CARE A P UPDATE DCON SLAVE ADDRESS OFF COMMAND DATA LOW (REGISTER 0) S 1110001 R/W A 011XXXXX A DATA HIGH (REGISTER 1) DON’T CARE A DON’T CARE A P UPDATE DCON SLAVE ADDRESS SETUP COMMAND DATA LOW (REGISTER 0) S 1110001 R/W A 001XXXXX A VID4 VID3 VID2 VID1 VID0 DATA HIGH (REGISTER 1) X X X A VID4 VID3 VID2 VID1 VID0 COMMAND LATCHED SLAVE ADDRESS XXX DATA LOW LATCHED READ-BACK COMMAND DATA HIGH LATCHED DATA LOW (REGISTER 0) S 1110001 R/W A 010XXXXX A S 1110010 RD A VID4 VID3 VID2 VID1 VID0 DCON COMMAND LATCHED DATA LOW LOADED A P UPDATE DCON DATA HIGH (REGISTER 1) 0 0 A VID4 VID3 VID2 VID1 VID0 DCON DATA HIGH LOADED 00 A P STOP (IGNORED) Figure 2. Write Word and Read Word Protocols Table 2. LTC1699-80, LTC1699-81 and LTC1699-82 Command Bits C7 C6 C5 COMMAND PROTOCOL 0 0 0 On Write Word 0 1 1 Off Write Word 0 0 1 Setup Write Word 0 1 0 Read-Back Read Word Write Word Protocol Each Write Word protocol (Figure 2) begins with a start bit (S) and ends with a stop bit (P). As shown in the Timing Diagram the start and stop bits are defined as high to low and low to high transitions respectively, while SCL is high. In between the start and stop bits, the microprocessor transmits four bytes to the LTC1699-80, LTC1699-81 or LTC1699-82. These are the address byte, an 8-bit command code and two data bytes. The LTC1699-80, LTC1699-81 and LTC1699-82 sample each bit at the rising edges of the SCL clock. When the microprocessor issues a start bit, all the slave devices on the bus, including the LTC1699-80, LTC1699-81 or LTC1699-82 clock in the address byte, which consists of a 7-bit slave address and the R/W bit (set to 0). If the 12 slave address from the microprocessor does not match the internal hardwired address, the LTC1699-80, LTC1699-81 or LTC1699-82 returns to an idle state and waits for the next start bit. If the slave address matches, the LTC1699-80, LTC1699-81 or LTC1699-82 acknowledges by pulling the SDA line low for one clock cycle after the address byte. After detecting the acknowledgement bit (A), the microprocessor transmits the second byte or command code. The command code identifies the type of Write Word protocol as Setup, On or Off (Table 2). The Setup protocol is used to load two resistor divider settings into Register 0 and 1. The On and Off protocols turn the converters on or off in conjunction with the VRON pin. Once all 8 bits of the command code are clocked in, the LTC1699-80, LTC1699-81 or LTC1699-82 issues a second acknowledgement bit to the microprocessor. After detecting the acknowledgement bit, the microprocessor transmits two data bytes. Each data byte is acknowledged in turn for all three Write Word protocols but is only latched into Register 0 or 1 in Setup protocol. This prevents previously loaded settings from accidentally being changed. The first or Data Low byte is loaded into Register 0. The second or Data High byte is loaded into LTC1699 Series U W U U APPLICATIO S I FOR ATIO Register 1. After issuing the final acknowledgement bit, the SMBus interface returns to an idle state and waits for the next start bit. Read Word Protocol The Read Word protocol starts off like Write Word protocol but after the command code acknowledgment, the microprocessor issues a second start bit (called a repeated start). This is followed by the slave address but with the R/W bit set high to indicate that data direction is now from the LTC1699-80, LTC1699-81 or LTC1699-82 to the microprocessor. The LTC1699-80, LTC1699-81 or LTC1699-82 then acknowledges the slave address and clocks the contents of Register 0 (Data Low byte) to the microprocessor. The Data Low byte is acknowledged by the microprocessor. On detecting the acknowledgment bit, the LTC1699-80, LTC1699-81 or LTC1699-82 clocks out the contents of Register 1 (Data High byte). As defined in the SMBus specifications, the microprocessor does not acknowledge the last data byte. The LTC1699-80, LTC1699-81 or LTC1699-82 enters an idle state to wait for the next start bit after clocking out the Data High byte. The five most significant bits (VID0-VID4) of the Data Low and High bytes are the resistor divider settings previously loaded using the Setup protocol. The next bit below the VID0-VID4 bits is the status of the DCON signal. If this bit is low (high), the DC/DC converters are switched on (off). The two unused, least significant bits of the Data Low and Data High bytes are clocked out as zeros which removes the need to mask out these bits in software. After power-up, the microprocessor must set up the registers before the LTC1699-80, LTC1699-81 and LTC1699-82 recognizes On protocols. This requirement ensures that the correct DC/DC converter output is programmed before the converters are turned on. After setup, Read-Back allows the contents of Registers 0 and 1 to be verified in case the VID codes were corrupted by noise or bus conflicts. In order to turn on the DC/DC converter, two On protocols must be sent to slave address E2H without any other (E2H) protocols in between. Protocols to other slave addresses are still allowed and are ignored. Similarly, two Off protocols must be sent to slave address E2H to turn the converters off. The On and Off protocols are monitored by an internal state machine. The output of the state machine, SMBON, is high after two On commands and low after two Off commands. Repeated On and Off protocols reduce the chances of bus conflicts and noise turning the converter on or off accidentally. In both On and Off protocols, the LTC1699-80, LTC1699-81 and LTC1699-82, do not latch in the Data Low and Data High bytes. This protects the settings that have already been loaded into the registers and verified by read-back. Once the converters are turned on (both SMBON and VRON are high) the contents of Registers 0 and 1 are protected and can only be altered with Setup protocols if VRON is pulled low or two Off protocols are sent to the LTC1699-80, LTC1699-81 or LTC1699-82 (to force SMBON low). Safeguards DC/DC Converter Control The LTC1699-80, LTC1699-81 and LTC1699-82 provide safeguards against incorrect divider codes and the unintentional turn-on or turn-off of the DC/DC converters. Incorrect codes due to bus conflicts during Setup protocols can cause damage to circuits powered by the DC/DC converters. The safeguards built into the LTC1699-80, LTC1699-81 and LTC1699-82 include Read-Back, repeated On and Off protocols, ignoring On protocols if the registers have not been setup, locking out registers while the DC/DC converters are operating and latching in VID codes only in Setup protocols. The LTC1699-80, LTC1699-81 and LTC1699-82 provide six pins for DC/DC converter control: SEL, VRON, CPU_ON, IO_ON, CLK_ON and PGOOD. These pins (except SEL) and the output of the internal on/off state machine (SMBON) determine if the DC/DC converters are operating or in shutdown. The SEL and VRON pins are TTL compatible, high impedance inputs with a logic threshold of 1.3V over the entire 2.7V to 5.5V supply range. They are compatible with 3.3V logic and have ±50mV of hysterisis for noise rejection. When pulled high or low, the SEL pin selects Register 1 and 0 respectively as the active divider setting. The VRON 13 LTC1699 Series U W U U APPLICATIO S I FOR ATIO pin is used to shut down the converters without the need for lengthy SMBus Off protocols and can also be used to turn on up to three DC/DC converters simultaneously. The VRON pin has an internal 2.5uA current source pull-up. and is the status bit that is returned during Read-back. Table␣ 3 shows the state of the CPU_ON, IO_ON, and CLK_ON pins for various combinations of VRON and SMBON. The CPU_ON, IO_ON and CLK_ON pins are N-channel, open drain outputs. These outputs can be connected to the RUN/SS pin of LTC DC/DC converters that generate the VCC supplies of the CPU, I/O circuits and the clock buffer. The RUN/SS pin shuts down the converter if pulled low and also serves as a connection for the soft-start capacitor. The CPU_ON, IO_ON and CLK_ON pins are open drain outputs and do not interfere with soft-start when switched into a high impedance state. To keep the I/O and clock buffer VCC supplies alive at all times, disconnect the IO_ON and CLK_ON pins from the corresponding RUN/SS pins. The N-channel FETs at the CPU_ON, IO_ON and CLK_ON pins typically discharge a 0.1µF (0.01µF) soft-start capacitor from 3V to 0.35V in 21µs (2.3µs) with VCC = 2.7V. Table 3. DC/DC Converter Control Pins The PGOOD or “Power Good” pin is also an open drain, N-channel output. The PGOOD pin pulls low if the DC/DC converters are shutdown. If the converters are turned on, an internal timer keeps PGOOD low for 50µs (typical) which allows time for the converters to enter regulation. Toggling the SEL pin while the converters are turned on also causes the PGOOD pin to pull low for 50µs. The PGOOD pin may be used to force continuous operation in an LTC DC/DC converter. If the SEL pin is toggled to select a lower output voltage, it may take an unacceptably long time for the output of the DC/DC converter to decrease to the new voltage under light load conditions. To reduce this time needed, the PGOOD pin can be connected to the FCB (force continuous bar) pin of the converter. When the SEL pin is toggled to select a new code, FCB pin is forced low for 50µs. This forces the DC/DC converter out of Burst ModeTM operation and into continuous mode. The VRON pin and SMBON, the output of the internal on/ off state machine, control the state of the CPU_ON, IO_ON, CLK_ON and PGOOD pins. The DCON signal is a logical NAND function of the logical states of VRON and SMBON VRON SMBON DCON PGOOD CPU_ON, IO_ON, CLK_ON 0 X (Note 3) 1 0 0 1 0 1 0 0 1 ↑ ↓ 0 for 50µs (Note 1) Z (Note 2) ↑ 1 ↓ 0 for 50µs (Note 1) Z (Note 2) Note 1: Also triggered by SEL pin toggling. Note 2: Z = High Impedance Note 3: X = Don’t care If the DCON control bit goes high, the N-channel transistor at the CPU_ON, IO_ON, CLK_ON and PGOOD pins turn on, pulling these pins to ground. Any connected RUN/SS pins are pulled to ground, shutting down the converters. If the DCON control bit goes low, the N-channel transistor at the CPU_ON, CLK_ON, IO_ON and PGOOD pins turn off and become high impedance outputs. This allows the softstart capacitor at each RUN/SS pin to charge up and the DC/DC converters wake up gradually with a soft-start cycle. The PGOOD pin also pulls low for typically 50µs to indicate that the converter outputs are temporarily out of regulation. An internal timer determines the duration of the low pulse. The timer is triggered by SEL toggling or DCON going low. Power-Up Reset On power-up, the internal POR circuit generates a low reset pulse, which stays low until VCC rises above approximately 2.2V. The reset pulse forces the SMBus interface into an idle state in which it listens for a start bit. At the same time the outputs of both Register 0 and Register 1 are set to 11111B. The DCON bit is pulled high so that the CPU_ON, IO_ON, CLK_ON and PGOOD pins are pulled low to shut down the DC/DC converters. Burst Mode is a trademark of Linear Technology Corporation. 14 LTC1699 Series U W U U APPLICATIO S I FOR ATIO Operating Sequence A typical control sequence for the LTC1699-80, LTC1699-81 and LTC1699-82 is as follows: • Pull VRON high. Since DCON = 0, the CPU_ON, IO_ON and CLK_ON pins enter a high impedance state, allowing the DC/DC converters to soft-start. PGOOD stays low for 50µs. • On power up, the DCON bit is preset to a high state by the power-on reset (POR) circuit. The CPU_ON, IO_ON and CLK_ON pins are pulled low to shut down the DC/ DC converters. PGOOD pulls low to indicate that the converters are not in regulation. • To shut down the supply, send two Off protocols to set the DCON bit high or pull VRON low if immediate shutdown is required. • Pull VRON low as a precaution. Take SEL high or low to select the divider setting; e.g., one that suits the existing power source (battery or wall-pack). The VRON signal in the 8-pin MSOP versions of the LTC1699-80, LTC1699-81 and LTC1699-82 are pulled high internally by a 2.5µA current source. For these versions, the converters are turned on or off only through the SMBus interface. • Use the Setup protocol to load the appropriate divider settings in Registers 0 and 1 and enable the on/off state machine. Overvoltage Protection Faults • Use the Read-Back protocol to verify the contents of Registers 0 and 1. • Repeat the setup and read-back if the codes are incorrect (due to bus conflicts). • Send two On protocols in succession to clear the DCON bit. • Use the Read-Back protocol to verify that the DCON is low. A high state will indicate that an On command code was corrupted by bus conflicts. Toggling the SEL pin, i.e. changing the ladder setting “on the fly” can trigger some converters with over-voltage fault protection (OVP) into a fault state if the new setting calls for a lower output voltage. For some converters such as the LTC1702, cycling the power supply is the only way to clear the fault and restore normal operation. For the LTC1702, an OVP fault is triggered if the difference between the programmed and prevailing output voltages is greater than 15%, and persists for more than 25µs. To prevent the OVP fault from disabling the LTC1702, tie the FAULT pin of the LTC1702 low. Tying FAULT low does not disable the OVP circuit but blocks its effects. 15 16 TO µP SENSE PWRGD1 LTC1699-80 VRON FB SCL PGOOD SDA CPU_ON SEL CLK_ON IO_ON GND VCC 0.1µF VOUT1 0.9V TO 2V AT 15A + 10k VIN 1µF 220pF 100k COUT1 180µF 4V ×6 10k D3 L1 1µH Q2 Q1 15pF 1µF 220pF Q3 0.22µF 1µF D2 18.7k 1µF 12 11 10 9 8 7 6 5 4 3 2 1 FB1 SGND COMP1 FAULT PGOOD2 PGND SW2 TG2 BG2 BOOST2 IMAX2 VCC FB2 COMP2 RUN/SS2 LTC1702 RUN/SS1 FCB PGOOD1 IMAX1 SW1 TG1 BG1 BOOST1 PVCC 13 14 15 16 17 18 19 20 21 22 23 24 10Ω 10µF VIN = 5V ±10% + 1µF 20k D1 CIN 150µF 10V ×2 0.22µF SMBus Programmed Dual Output Mobile Pentium Processor Supply 15pF Q5 L2 2.2µH 220pF 100k 2200pF Q4 11.5k 0.1% 10.2k 0.1% 1k + 10k VIN COUT2 180µF 4V 1699 TA02 PWRGD2 1µF VOUT2 1.5V/3A COUT1, COUT2: PANASONIC EEFUE0G181R CIN: KEMET TS10X157M010AS D1, D2: MOTOROLA MBR0520LT1 D3: MOTOROLA MBRS320T3 L1: MURATA LQT12535C1R5N12 L2: COILTRONICS UP2B-2R2 Q1, Q2, Q3: INTERNATIONAL RECTIFIER IRF7811 Q4, Q5: 1/2 FAIRCHILD NDS8926 LTC1699 Series TYPICAL APPLICATIO S U PGOOD VRON SCL SDA SEL PGOOD VRON SCL SDA NC SEL 16 FB 13 SENSE 12 VCC GND 15 GND 14 U2 LTC1699-81 C25 0.1µF VIN+ C11, 1nF R5, 10k R3 10k 7 NC R6, 100k NC 11 CLK_ON 10 8 9 CPU_ON IO_ON 6 5 4 3 2 1 R2 2.7k C10, 100pF C9, 0.01µF C7 0.1µF C15 180pF C17 1000pF C1, 1000pF 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SW1 SENSE1 – TG2 AMPMD SENSE2 + SW2 BOOST2 BG2 SENSE2 – VOS + VOS – VDIFFOUT PGND INTVCC SGND EXTVCC ITH BG1 PLLIN NC VIN PLLFLTR BOOST1 SENSE1 + EAIN NC TG1 RUN/SS U1 LTC1929 15 16 17 18 19 20 21 22 23 24 25 26 27 28 C2 1µF C13 2.2µF C8 0.47µF C3, C4: OS-CON PS680M C18–C21: T510E108M004 L1, L2: SUMIDA CEP149-1R0MC Q1–Q8: FDS6670A OR FDS7760A C12 1µF R1 10Ω C14 10µF 1 + 2 SMBus Controlled 5V Input, 1.6V/40A CPU Power Supply + R9 50Ω C18 C16 0.47µF D1 BAT54A C19 + Q7 Q5 C20 Q3 Q1 C22 1µF R10 50Ω + Q8 Q6 C21 Q4 + 1699 TA06 C24 10µF C3 L1 1µH L2 2µH + Q2 C23 1µF VIN– 5V VIN+ VOSENSE + REMOTE SENSE VOSENSE – VOUT – 1.6V/40A VOUT + R8 0.002Ω R4 0.002Ω C4 LTC1699 Series TYPICAL APPLICATIO S 17 U LTC1699 Series U TYPICAL APPLICATIO S SMBus Programmed CPU Core Voltage Regulator for 2-Step Applications (VIN = 5V) with Burst Mode Operation Disabled VIN 5V 100k* COSC 39pF 1 CSS 0.1µF 2 INTVCC 10k POWER GOOD 100k 470k RC 20k CC 220pF 3 CC2 220pF COSC RUN/SS TG BOOST ITH SW 16 CB 0.22µF PGOOD VIN SENSE – INTVCC COUT: PANASONIC EEFUEOG181R CIN: PANASONIC EEFUEOJ151R CO: TAIYO YUDEN LMK550BJ476MM-B L1: COILCRAFT 1705022P-781HC Q4, Q5: 2N2222 RSENSE: IRC LRF 2512-01-R004-J 15 14 LTC1735-1 4 Q5 Q1 FDS6680A 13 DB MBR0530 CIN 150µF 6.3V ×2 L1 0.78µH RSENSE 0.004Ω VOUT 1.6V 12A Q4 5 0.1µF TO µP 180pF + 4.7µF SENSE + BG VOSENSE PGND 11 1µF 47pF SENSE LTC1699-81 VRON FB SCL CPU_ON SDA PGOOD SEL CLK_ON IO_ON GND + 1000pF 6 VCC 12 7 10 Q2, Q3 FDS6680A ×2 MBRD835L SGND 8 SGND EXTVCC 9 VIN 5V SGND *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF 18 1699 TA03 COUT 180µF 4V ×3 CO 47µF 10V LTC1699 Series U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 0.009 (0.229) REF 16 15 14 13 12 11 10 9 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 2 3 4 5 6 8 7 0.053 – 0.068 (1.351 – 1.727) 0.004 – 0.0098 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.0250 (0.635) BSC 0.008 – 0.012 (0.203 – 0.305) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 1098 MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 ± 0.004* (3.00 ± 0.102) 8 7 6 5 0.118 ± 0.004** (3.00 ± 0.102) 0.193 ± 0.006 (4.90 ± 0.15) 1 2 3 4 0.043 (1.10) MAX 0.007 (0.18) 0.034 (0.86) REF 0° – 6° TYP 0.021 ± 0.006 (0.53 ± 0.015) SEATING PLANE 0.009 – 0.015 (0.22 – 0.38) 0.0256 (0.65) BSC 0.005 ± 0.002 (0.13 ± 0.05) MSOP (MS8) 1100 * DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1699 Series U TYPICAL APPLICATIO Enhanced Data Transmission Speed VCC LTC1694 1 5 VCC SMBus1 0.1µF 2 GND SMBus2 SMBus 4 3 µP 2 1 4 LTC1699 SCL VCC SDA SENSE SEL FB PGOOD GND 8 5 0.1µF 6 TO DC/DC CONVERTER 7 1699 TA04 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1628/ LTC1628-PG High Efficiency, 2-phase, Synchronous Step Down Switching Regulators Dual Controller, 0.8V Reference, Wide Input Voltage Range LTC1694/ LTC1694-1 SMBus/I2C Accelerators in SOT-23 Improves SMBus/I2C Data Integrity LTC1702 Dual 1 MHz Synchronous 5V to 2.xV/1.xV Switching Regulator Controller Low Input Voltages, High Efficiency LTC1735/ LTC1735-1 High Efficiency Synchronous Step Down Switching Regulators 0.8V Reference, Wide Input Voltage Range, Synchronizable/ Programmable Fixed Frequency LTC1878 Monolithic Synchronous Step Down Switching Regulator 0.8V Reference, Internal Synchronous Switch, 2.65V ≤ VIN ≤ 6V LTC1706-19 VID Voltage Programmer Parallel Interface, Designed for 1.19V Referenced Switching Regulators LTC1706-81 5-Bit Desktop VID Programmer Parallel Interface, 0.8V Reference Intel Desktop VID Codes (VRM8.4) LTC1706-82 VID Programmer for Intel VRM9.0 Parallel Interface, 0.8V Reference Intel Desktop VID codes (VRM9.0) LTC1778 Wide Operating Range, No RSENSETM Step-Down Controller 2% to 90% Duty Cycle at 200kHz, tON(MIN) ≤ 100ns, Stable with Ceramic COUT LTC1929/ LTC1929-PG 2-Phase High Efficiency Synchronous Step-Down Switching Regulators 2-Phase Single Output Controller, Wide VIN Range: 4V to 36V Operation No RSENSE is a trademark of Linear Technology Corporation. 20 Linear Technology Corporation sn1699 1699fs LT/TP 0201 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2001