19-2317; Rev 0; 1/02 Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC Applications Digital Gain and Offset Adjustments Features ♦ Ultra-Low Supply Current 230µA at VDD = 3.6V 280µA at VDD = 5.5V ♦ 300nA Low-Power Power-Down Mode ♦ Single 2.7V to 5.5V Supply Voltage ♦ Fast 400kHz I2C-Compatible 2-Wire Serial Interface ♦ Schmitt-Trigger Inputs for Direct Interfacing to Optocouplers ♦ Rail-to-Rail Output Buffer Amplifiers ♦ Three Software-Selectable Power-Down Output Impedances 100kΩ, 1kΩ, and High Impedance ♦ Read-Back Mode for Bus and Data Checking ♦ Power-On Reset to Zero ♦ 10-Pin µMAX Package Ordering Information TEMP RANGE PART PINPACKAGE ADDRESS -40oC to +85oC 10 µMAX MAX5842LEUB o 0111 10X o MAX5842MEUB -40 C to +85 C 10 µMAX Programmable Voltage and Current Sources 1011 10X Typical Operating Circuit Programmable Attenuation VCO/Varactor Diode Control VDD Low-Cost Instrumentation µC Battery-Powered Equipment SDA VDD SCL RP ATE RP Pin Configuration VDD RS OUTA SCL RS TOP VIEW ADD 1 10 OUTD SCL 2 9 OUTC VDD 3 8 OUTB RS GND 4 7 OUTA RS SDA 5 6 REF MAX5842 SDA MAX5842 REF OUTD VDD SCL SDA REF MAX5842 OUTA OUTB OUTC µMAX Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. I2C is a trademark of Philips Corp. OUTB OUTC OUTD REF ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5842 General Description The MAX5842 is a quad, 12-bit voltage-output, digitalto-analog converter (DAC) with an I2C™-compatible, 2-wire interface that operates at clock rates up to 400kHz. The device operates from a single 2.7V to 5.5V supply and draws only 230µA at VDD = 3.6V. A powerdown mode decreases current consumption to less than 1µA. The MAX5842 features three software-selectable power-down output impedances: 100kΩ, 1kΩ, and high impedance. Other features include internal precision Rail-to-Rail® output buffers and a power-on reset (POR) circuit that powers up the DAC in the 100kΩ power-down mode. The MAX5842 features a double-buffered I2C-compatible serial interface that allows multiple devices to share a single bus. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5842 minimizes digital noise feedthrough by disconnecting the clock (SCL) signal from the rest of the device when an address mismatch is detected. The MAX5842 is specified over the extended temperature range of -40°C to +85°C and is available in a miniature 10-pin µMAX package. Refer to the MAX5841 data sheet for the 10-bit version. MAX5842 Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC ABSOLUTE MAXIMUM RATINGS VDD, SCL, SDA to GND ............................................-0.3V to +6V OUT_, REF, ADD to GND..............................-0.3V to VDD + 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 10-Pin µMAX (derate 5.6mW above +70°C) .................444mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY (NOTE 2) Resolution N 12 Integral Nonlinearity INL (Note 3) Differential Nonlinearity DNL Guaranteed monotonic (Note 3) Zero-Code Error ZCE Code = 000 hex, VDD = 2.7V ±2 6 Zero-Code Error Tempco Gain Error ±16 LSB ±1 LSB 40 mV ppm/oC 2.3 GE Code = FFF hex -0.8 Gain-Error Tempco Power-Supply Rejection Ratio Bits PSRR Code = FFF hex, VDD = 4.5V to 5.5V DC Crosstalk -3 %FSR 0.26 ppm/oC 58.8 dB 30 µV REFERENCE INPUT Reference Input Voltage Range VREF 0 Reference Input Impedance 32 Reference Current Power-down mode VDD 45 ±0.3 V kΩ ±1 µA DAC OUTPUT Output Voltage Range No load (Note 4) DC Output Impedance Code = 800 hex 1.2 VDD = 5V, VOUT = full scale (short to GND) 42.2 VDD = 3V, VOUT = full scale (short to GND) 15.1 Short-Circuit Current Wake-Up Time 0 VDD = 5V 8 VDD = 3V 8 Power-down mode = high impedance, VDD = 5.5V, VOUT_ = VDD or GND DAC Output Leakage Current VDD ±0.1 V Ω mA µs ±1 µA DIGITAL INPUTS (SCL, SDA) Input High Voltage VIH Input Low Voltage VIL 2 0.7 ✕ VDD _______________________________________________________________________________________ V 0.3 ✕ VDD V Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 0.05 ✕ VDD Input Hysteresis Input Leakage Current V ±0.1 Digital inputs = 0 or VDD Input Capacitance UNITS ±1 6 µA pF DIGITAL OUTPUT (SDA) Output Logic Low Voltage Three-State Leakage Current VOL IL ISINK = 3mA ±0.1 Digital inputs = 0 or VDD Three-State Output Capacitance 0.4 V ±1 µA 6 pF 0.5 V/µs DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Voltage Output Settling Time To 1/2LSB code 400 hex to C00 hex or C00 hex to 400 hex (Note 5) 4 Digital Feedthrough Code = 000 hex, digital inputs from 0 to VDD 0.2 nV-s Digital-to-Analog Glitch Impulse Major carry transition (code = 7FF hex to 800 hex and 800 hex to 7FF hex) 12 nV-s 2.4 nV-s DAC-to-DAC Crosstalk 12 µs POWER SUPPLIES Supply Voltage Range VDD Supply Current with No Load IDD Power-Down Supply Current IDDPD 2.7 5.5 V All digital inputs at 0 or VDD = 3.6V 230 395 All digital inputs at 0 or VDD = 5.5V 280 420 All digital inputs at 0 or VDD = 5.5V 0.3 1 µA 400 kHz µA TIMING CHARACTERISTICS (FIGURE 1) Serial Clock Frequency fSCL 0 Bus Free Time Between STOP and START Conditions tBUF 1.3 µs START Condition Hold Time tHD,STA 0.6 µs SCL Pulse Width Low tLOW 1.3 µs SCL Pulse Width High tHIGH 0.6 µs Repeated START Setup Time tSU,STA 0.6 Data Hold Time tHD,DAT 0 Data Setup Time tSU,DAT 100 µs 0.9 µs ns SDA and SCL Receiving Rise Time tr (Note 5) 0 300 ns SDA and SCL Receiving Fall Time tf (Note 5) 0 300 ns SDA Transmitting Fall Time tf (Note 5) 20 + 0.1Cb 250 ns STOP Condition Setup Time tSU,STO 0.6 µs _______________________________________________________________________________________ 3 MAX5842 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25°C.) (Note 1) PARAMETER SYMBOL Bus Capacitance Cb Maximum Duration of Suppressed Pulse Widths tSP Note 1: Note 2: Note 3: Note 4: Note 5: CONDITIONS MIN TYP (Note 5) MAX UNITS 400 pF 50 ns 0 All devices are 100% production tested at TA = +25°C and are guaranteed by design for TA = TMIN to TMAX. Static specifications are tested with the output unloaded. Linearity is guaranteed from codes 115 to 3981. Offset and gain error limit the FSR. Guaranteed by design. Not production tested. Typical Operating Characteristics (VDD = +5V, RL = 5kΩ.) INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE 3 5 MAX5842 toc02 5 MAX5842 toc01 4 INTEGRAL NONLINEARITY vs. TEMPERATURE 4 MAX5842 toc03 INTEGRAL NONLINEARITY vs. INPUT CODE 4 0 -1 -2 3 INL (LSB) 1 INL (LSB) INL (LSB) 2 2 1 3 2 1 -3 0 1024 2048 3072 0 2.7 4096 3.4 4.1 4.8 INPUT CODE SUPPLY VOLTAGE (V) DIFFERENTIAL NONLINEARITY vs. INPUT CODE DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE 0 MAX5842 toc04 1.00 0.75 5.5 -40 0 35 60 0 85 -0.25 DNL (LSB) DNL (LSB) 0.25 10 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE -0.25 0.50 -15 TEMPERATURE (°C) MAX5842 toc05 0 MAX5842 toc06 -4 DNL (LSB) MAX5842 Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC -0.50 -0.50 -0.25 -0.75 -0.50 -0.75 -0.75 -1.00 -1.00 0 1024 2048 INPUT CODE 4 3072 4096 -1.00 2.7 3.4 4.1 SUPPLY VOLTAGE (V) 4.8 5.5 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC ZERO-CODE ERROR vs. TEMPERATURE 4 2 6 4 2 3.4 4.1 4.8 5.5 -15 10 35 60 85 2.7 3.4 4.1 SUPPLY VOLTAGE (V) GAIN ERROR vs. TEMPERATURE DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT (NOTE 6) DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT (NOTE 6) -0.4 DAC OUTPUT VOLTAGE (V) 4 3 2 10 35 60 1.5 1.0 CODE = 400 hex CODE = FFF hex NO LOAD -15 2.0 0.5 1 0 MAX5842 toc12 5 DAC OUTPUT VOLTAGE (V) -0.8 2.5 MAX5842 toc11 6 MAX5842 toc10 -1.2 0 85 0 0 2 4 6 8 10 0 2 4 6 8 TEMPERATURE (°C) OUTPUT SOURCE CURRENT (mA) OUTPUT SINK CURRENT (mA) SUPPLY CURRENT vs. INPUT CODE SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. SUPPLY VOLTAGE 280 300 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 300 280 260 260 300 280 260 CODE = FFF hex NO LOAD N0 LOAD CODE = FFF hex 240 240 819 1638 2457 INPUT CODE 3276 4096 10 MAX5842 toc15 320 MAX5842 toc14 320 MAX5842 toc13 320 0 5.5 4.8 TEMPERATURE (°C) -1.6 GAIN ERROR (%FSR) NO LOAD 0 -40 SUPPLY VOLTAGE (V) -2.0 -40 -0.8 NO LOAD 0 2.7 -1.2 -0.4 NO LOAD 0 SUPPLY CURRENT (µA) -1.6 GAIN ERROR (%FSR) 6 -2.0 MAX5842 toc08 8 ZERO-CODE ERROR (mV) ZERO-CODE ERROR (mV) 8 GAIN ERROR vs. SUPPLY VOLTAGE 10 MAX5842 toc07 10 MAX5842 toc09 ZERO-CODE ERROR vs. SUPPLY VOLTAGE 240 -40 -15 10 35 TEMPERATURE (°C) 60 85 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5 MAX5842 Typical Operating Characteristics (continued) (VDD = +5V, RL = 5kΩ.) Typical Operating Characteristics (continued) (VDD = +5V, RL = 5kΩ.) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE POWER-UP GLITCH MAX5842 toc17 MAX5842 toc16 500 POWER-DOWN SUPPLY CURRENT (nA) MAX5842 Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC ZOUT = HIGH IMPEDANCE NO LOAD 400 300 5V VDD TA = -40°C TA = +25°C 0 200 10mV/div OUT_ 100 TA = +85°C 0 2.7 3.4 4.1 4.8 5.5 100µs/div SUPPLY VOLTAGE (V) MAJOR CARRY TRANSITION (POSITIVE) EXITING SHUTDOWN MAX5842 toc18 MAX5842 toc19 500mV/div OUT_ 5mV/div OUT_ CLOAD = 200pF RL = 5kΩ CODE = 7FF hex TO 800 hex CLOAD = 200pF CODE = 800 hex 2µs/div 2µs/div SETTLING TIME (POSITIVE) MAJOR CARRY TRANSITION (NEGATIVE) MAX5842 toc21 MAX5842 toc20 5mV/div OUT_ CLOAD = 200pF RL = 5kΩ CODE = 800 hex TO 7FF hex 2µs/div 6 500mV/div OUT_ CLOAD = 200pF CODE = 400 hex TO C00 hex 2µs/div _______________________________________________________________________________________ Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC SETTLING TIME (NEGATIVE) DIGITAL FEEDTHROUGH MAX5842 toc22 MAX5842 toc23 SCL 2V/div 500mV/div OUT_ OUT_ 2mV/div CLOAD = 200pF fSCL = 12kHz CODE = 000 hex CLOAD = 200pF CODE = C00 hex TO 400 hex 2µs/div 40µs/div CROSSTALK MAX5842 toc24 VOUTA 2V/div VOUTB 1mV/div 4µs/div Note 6: The ability to drive loads less than 5kΩ is not implied. _______________________________________________________________________________________ 7 MAX5842 Typical Operating Characteristics (continued) (VDD = +5V, RL = 5kΩ.) Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5842 Pin Description PIN NAME FUNCTION 1 ADD Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to zero. 2 SCL Serial Clock Input 3 VDD Power Supply 4 GND Ground 5 SDA Bidirectional Serial Data Interface 6 REF Reference Input 7 OUTA DAC A Output 8 OUTB DAC B Output 9 OUTC DAC C Output 10 OUTD DAC D Output Detailed Description The MAX5842 is a quad, 12-bit, voltage-output DAC with an I2C/SMBus-compatible 2-wire interface. The device consists of a serial interface, power-down circuitry, four input and DAC registers, four 12-bit resistor string DACs, four unity-gain output buffers, and output resistor networks. The serial interface decodes the address and control bits, routing the data to the proper input or DAC register. Data can be directly written to the DAC register, immediately updating the device output, or can be written to the input register without changing the DAC output. Both registers retain data as long as the device is powered. DAC Operation The MAX5842 uses a segmented resistor string DAC architecture, which saves power in the overall system and guarantees output monotonicity. The MAX5842’s input coding is straight binary, with the output voltage given by the following equation: V × (D) VOUT _ = REF N 2 Power-Down Modes The MAX5842 has three software-controlled, lowpower, power-down modes. All three modes disable the output buffers and disconnect the DAC resistor strings from REF, reducing supply current draw to 1µA and the reference current draw to less than 1µA. In power-down mode 0, the device output is high impedance. In power-down mode 1, the device output is internally pulled to GND by a 1kΩ termination resistor. In power-down mode 2, the device output is internally pulled to GND by a 100kΩ termination resistor. Table 1 shows the power-down mode command words. Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode. Digital Interface where N = 12 (bits), and D = the decimal value of the input code (0 to 4095). Output Buffer The MAX5842 analog outputs are buffered by precision, unity-gain followers that slew 0.5V/µs. Each buffer output swings rail-to-rail, and is capable of driving 5kΩ in parallel with 200pF. The output settles to ±0.5LSB within 4µs. Power-On Reset The MAX5842 features an internal POR circuit that initializes the device upon power-up. The DAC registers 8 are set to zero scale and the device is powered down, with the output buffers disabled and the outputs pulled to GND through the 100kΩ termination resistor. Following power-up, a wake-up command must be initiated before any conversions are performed. The MAX5842 features an I 2 C/SMBus-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). The MAX5842 is SMBus compatible within the range of VDD = 2.7V to 3.6V. SDA and SCL facilitate bidirectional communication between the MAX5842 and the master at rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX5842 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX5842 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed _______________________________________________________________________________________ Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC POWER-DOWN COMMAND BITS MODE/FUNCTION PD1 PD0 0 0 Power-up device. DAC output restored to previous value. 0 1 Power-down mode 0. Power down device with output floating. 1 0 Power-down mode 1. Power down device with output terminated with 1kΩ to GND. 1 1 Power-down mode 2. Power down device with output terminated with 100kΩ to GND. by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX5842 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor to generate a logic high voltage (see Typical Operating Circuit). Series resistors RS are optional. These series resistors protect the input stages of the MAX5842 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see START and START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high (Figure 2). A START condition from the master signals the beginning of a transmission to the MAX5842. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see Acknowledge Bit (ACK)). The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. When a STOP condition or incorrect address is detected, the MAX5842 internally disconnects SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. Early STOP Conditions The MAX5842 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP conditions. Repeated START Conditions A REPEATED START (S r ) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. S r may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5842 serial interface supports continuous write operations with or without an Sr condition separating them. Continuous SDA tSU, STA tSU, DAT tLOW tHD, STA tBUF tSP tSU, STO tHD, DAT SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. 2-Wire Serial Interface Timing Diagram _______________________________________________________________________________________ 9 MAX5842 STOP Conditions). Both SDA and SCL idle high when the I2C bus is not busy. Table 1. Power-Down Command Bits MAX5842 Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC S Sr P SCL SDA Figure 2. START and STOP Conditions SCL SDA The MAX5842 has four different factory/user-programmed addresses (Table 2). Address bits A6 through A1 are preset, while A0 is controlled by ADD. Connecting ADD to GND sets A0 = 0. Connecting ADD to V DD sets A0 = 1. This feature allows up to four MAX5842s to share the same bus. Table 2. MAX5842 I2C Slave Addresses STOP START LEGAL STOP CONDITION SCL SDA START PART VADD DEVICE ADDRESS (A6...A0) MAX5842L GND 0111 100 0111 101 MAX5842L VDD MAX5842M GND 1011 100 MAX5842M VDD 1011 101 ILLEGAL STOP ILLEGAL EARLY STOP CONDITION Figure 3. Early STOP Conditions read operations require Sr conditions because of the change in direction of data flow. Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The MAX5842 generates an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data, the MAX5842 waits for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address (Figure 4). When idle, the MAX5842 waits for a START condition followed by its slave 10 address. The serial interface compares each address value bit by bit, allowing the interface to power down immediately if an incorrect address is detected. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX5842 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX5842 issues an ACK by pulling SDA low for one clock cycle. Write Data Format In write mode (R/W = 0), data that follows the address byte controls the MAX5842 (Figure 5). Bits C3-C0 configure the MAX5842 (Table 3). Bits D11-D0 are DAC data. Input and DAC registers update on the falling edge of SCL during the acknowledge bit. Should the write cycle be prematurely aborted, data is not updated and the write cycle must be repeated. Figure 6 shows two example write data sequences. Extended Command Mode The MAX5842 features an extended command mode that is accessed by setting C3-C0 = 1 and D11-D8 = 0. The next data byte writes to the shutdown registers (Figure 7). Setting bits A, B, C, or D to 1 sets that DAC S A6 A5 A4 A3 A2 A1 A0 R/W Figure 4. Slave Address Byte Definition C3 C2 C1 C0 D11 D10 Figure 5. Command Byte Definition ______________________________________________________________________________________ D9 D8 Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC S LSB A6 A5 A4 A3 A2 A1 A0 R/W MSB D7 MSB ACK C3 MAX5842 MSB LSB C2 C1 C0 D11 D10 D9 D8 ACK LSB D6 D5 D4 D3 D2 D1 D0 ACK P EXAMPLE WRITE DATA SEQUENCE MSB S LSB A6 A5 A4 A3 A2 A1 A0 R/W MSB X MSB ACK C3 LSB C2 C1 C0 X X D11 D10 D9 D8 ACK LSB X D C B A PD1 PD0 ACK P EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE Figure 6. Example Write Command Sequences to the selected power-down mode based on the states of PD0 and PD1 (Table 1). Any combination of the four DACs can be controlled with a single write sequence. Read Data Format In read mode (R/W = 1), the MAX5842 writes the contents of the DAC register to the bus. The direction of data flow reverses following the address acknowledge by the MAX5842. The device transmits the first byte of data, waits for the master to acknowledge, then transmits the second byte. Figure 8 shows an example read data sequence. I2C Compatibility The MAX5842 is compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports the standard I 2 C 8-bit communications. The general call address is ignored. The MAX5842 address is compatible with the 7-bit I2C addressing protocol only. No 10-bit address formats are supported. Digital Feedthrough Suppression When the MAX5842 detects an address mismatch, the serial interface disconnects the SCL signal from the core circuitry. This minimizes digital feedthrough caused by the SCL signal on a static output. The serial interface reconnects the SCL signal once a valid START condition is detected. D C B A PD1 PD0 Figure 7. Extended Command Byte Definition Applications Information Digital Inputs and Interface Logic The MAX5842 2-wire digital interface is I 2C/SMBus compatible. The two digital inputs (SCL and SDA) load the digital input serially into the DAC. Schmitt-trigger buffered inputs allow slow-transition interfaces such as optocouplers to interface directly to the device. The digital inputs are compatible with CMOS logic levels. Power-Supply Bypassing and Ground Management Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the power-supply ground is short and low impedance. Bypass V DD with a 0.1µF capacitor to ground as close to the device as possible. Chip Information TRANSISTOR COUNT: 17,213 PROCESS: BiCMOS ______________________________________________________________________________________ 11 MAX5842 Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC Table 3. Command Byte Definitions SERIAL DATA INPUT C0 D11 D10 C3 C2 C1 0 0 0 0 DAC DATA 0 0 0 1 0 0 1 12 FUNCTION D9 D8 DAC DATA DAC DATA DAC DATA Load DAC A input and DAC registers with new data. Contents of DAC B, C, and D input registers are transferred to the respective DAC registers. All outputs are updated. DAC DATA DAC DATA DAC DATA DAC DATA Load DAC B input and DAC registers with new data. Contents of DAC A, C, and D input registers are transferred to the respective DAC registers. All outputs are updated. 0 DAC DATA DAC DATA DAC DATA DAC DATA Load DAC C input and DAC registers with new data. Contents of DAC A, B, and D input registers are transferred to the respective DAC registers. All outputs are updated. DAC DATA DAC DATA DAC DATA Load DAC D input and DAC registers with new data. Contents of DAC A, B, and C input registers are transferred to the respective DAC registers. All outputs are updated simultaneously. 0 0 1 1 DAC DATA 0 1 0 0 DAC DATA DAC DATA DAC DATA DAC DATA Load DAC A input register with new data. DAC outputs remain unchanged. 0 1 0 1 DAC DATA DAC DATA DAC DATA DAC DATA Load DAC B input register with new data. DAC outputs remain unchanged. 0 1 1 0 DAC DATA DAC DATA DAC DATA DAC DATA Load DAC C input register with new data. DAC outputs remain unchanged. 0 1 1 1 DAC DATA DAC DATA DAC DATA DAC DATA Load DAC D input register with new data. DAC outputs remain unchanged. 1 0 0 0 DAC DATA DAC DATA DAC DATA DAC DATA Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC A input register. 1 0 0 1 DAC DATA DAC DATA DAC DATA DAC DATA Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC B input register. 1 0 1 0 DAC DATA DAC DATA DAC DATA DAC DATA Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC C input register. 1 0 1 1 DAC DATA DAC DATA DAC DATA DAC DATA Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC D input register. 1 1 0 0 DAC DATA DAC DATA DAC DATA DAC DATA Load all DACs with new data and update all DAC outputs simultaneously. Both input and DAC registers are updated with new data. 1 1 0 1 DAC DATA DAC DATA DAC DATA DAC DATA Load all input registers with new data. DAC outputs remain unchanged. ______________________________________________________________________________________ Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC SERIAL DATA INPUT FUNCTION C3 C2 C1 C0 D11 D10 D9 D8 1 1 1 0 X X X X Update all DAC outputs simultaneously. Device ignores D11-D8. Do not send the data byte. 1 1 1 1 0 0 0 0 Extended command mode. The next word writes to the powerdown registers (Extended Command Mode). 1 1 1 1 0 0 0 1 Read DAC A data. The device expects an Sr condition followed by an address word with R/W = 1. 1 1 1 1 0 0 1 0 Read DAC B data. The device expects an Sr condition followed by an address word with R/W = 1. 1 1 1 1 0 1 0 0 Read DAC C data. The device expects an Sr condition followed by an address word with R/W = 1. 1 1 1 1 1 0 0 0 Read DAC D data. The device expects an Sr condition followed by an address word with R/W = 1. MSB S A6 LSB A4 A5 A3 A2 A1 R/W =0 A0 MSB ACK C3 LSB C2 C1 C0 D11 D10 D9 D8 ACK DATA BYTES GENERATED BY MASTER DEVICE Sr MSB LSB A6 R/W =1 A4 A5 A3 A2 A1 A0 MSB ACK X D7 X PD1 PD0 D11 D10 D9 D8 ACK ACK GENERATED BY MASTER DEVICE DATA BYTES GENERATED BY MAX5842 MSB LSB LSB D6 D5 D4 D3 D2 D1 D0 ACK P Figure 8. Example Read Word Data Sequence ______________________________________________________________________________________ 13 MAX5842 Table 3. Command Byte Definitions (continued) Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5842 Functional Diagram REF INPUT REGISTER A 12-BIT DAC A MUX AND DAC REGISTER MAX5842 OUTA RESISTOR NETWORK INPUT REGISTER B 12-BIT DAC B MUX AND DAC REGISTER OUTB RESISTOR NETWORK INPUT REGISTER C 12-BIT DAC C MUX AND DAC REGISTER OUTC RESISTOR NETWORK INPUT REGISTER D 12-BIT DAC D MUX AND DAC REGISTER OUTD RESISTOR NETWORK SERIAL INTERFACE SDA ADD SCL 14 POWER-DOWN CIRCUITRY VDD GND ______________________________________________________________________________________ Quad, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 10LUMAX.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5842 Package Information