LTC2925 Multiple Power Supply Tracking Controller with Power Good Timeout DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Flexible Power Supply Tracking Up and Down Power Supply Sequencing Supply Stability Is Not Affected Controls Three Supplies Without Series FETs Controls an Optional Fourth Supply With a Series FET Electronic Circuit Breaker Remote Sense Switch Compensates for Voltage Drop Across a Series FET Supply Shutdown Outputs FAULT Output Adjustable Power Good Timeout Available in Narrow 24-Lead SSOP and Tiny 24-Lead QFN Packages U APPLICATIO S ■ ■ ■ ■ The LTC®2925 provides a simple solution to power supply tracking and sequencing requirements. By selecting a few resistors, the supplies can be configured to ramp-up and ramp-down together or with voltage offsets, time delays or different ramp rates. The LTC2925 controls the outputs of three independent supplies without inserting any pass element losses. For systems that require a fourth supply, or when a supply does not allow direct access to its feedback resistors, one supply can be controlled with a series FET. When the FET is used, an internal remote sense switch compensates for the voltage drop across the FET and current sense resistor, and an electronic circuit breaker provides protection from short-circuit conditions. The LTC2925 also includes a power good timeout feature that turns off the supplies if an external supply monitor fails to indicate that the supplies have entered regulation within an adjustable time-out period. VCORE and VI/O Supply Tracking Microprocessor, DSP and FPGA Supplies Servers Communication Systems , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO S 0.015Ω Si4412ADY 3.3V VIN MASTER 0.1µF 3.3V 0.1µF 10Ω SUPPLY MONITOR 154k VCC SENSEP SENSEN GATE ON RAMP 2.5V 1.8V 1.5V 1V/DIV RST 3.3V PGI 100k SD1 REMOTE FB1 VIN 10k RUN/SS IN DC/DC FB = 1.235V OUT 35.7k 10ms/DIV 16.5k STATUS LTC2925 SD2 10k FB2 FAULT RAMPBUF 1.65k IN RUN/SS DC/DC FB = 0.8V OUT 41.2k 2.5V SLAVE2 88.7k TRACK1 SD3 TRACK2 86.6k FB3 RUN/SS IN DC/DC FB = 0.8V OUT TRACK3 100k GND SCTMR 0.47µF SDTMR 0.082µF PGTMR 0.82µF 100k 2925 TA01 3.3V 2.5V 1.8V 1.5V 3.3V 88.7k 41.2k 2925 TA02a 3.3V VIN 13k 1.8V SLAVE1 1V/DIV 1.5V SLAVE3 86.6k 10ms/DIV 2925 TA02b 2925f 1 LTC2925 W W U W ABSOLUTE AXI U RATI GS (Notes 1, 2) GATE (Note 3) ........................................ –0.3 to 11.5V Average Current TRACK1, TRACK2, TRACK3 .................................. 5mA FB1, FB2, FB3 ....................................................... 5mA Operating Temperature Range LTC2925C ............................................... 0°C to 70°C LTC2925I ............................................. –40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS Package ..................................................... 300°C Supply Voltage (VCC) ................................. –0.3V to 10V Input Voltages ON, PGI, SENSEP, SENSEN ..................... –0.3V to 10V TRACK1, TRACK2, TRACK3 .......... –0.3V to VCC + 0.3V SCTMR, SDTMR, PGTMR ............. –0.3V to VCC + 0.3V Output Voltages FAULT, SD1, SD2, SD3, FB1, FB2, FB3, STATUS ......................... –0.3V to 10V RAMPBUF, REMOTE ..................... –0.3V to VCC + 0.3V RAMP .............................................. –0.3V to VCC + 1V U W U PACKAGE/ORDER I FOR ATIO SD1 6 ON 1 19 GATE SD2 7 18 RAMP SD2 4 SD3 8 17 REMOTE SD3 5 RAMPBUF 9 16 FB1 15 TRACK1 FB3 11 14 TRACK2 13 FB2 TRACK3 12 18 STATUS SDTMR 2 SD1 3 GND 10 PGI SDTMR 20 FAULT PGTMR 21 STATUS 5 GN PART MARKING LTC2925CUF LTC2925IUF 24 23 22 21 20 19 17 FAULT 16 GATE 25 15 RAMP 14 REMOTE RAMPBUF 6 LTC2925CGN LTC2925IGN GN PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 85°C/W UF PART MARKING 13 FB1 7 8 9 10 11 12 TRACK1 4 SCTMR ON LTC2925CGN LTC2925IGN TRACK2 22 PGI VCC 23 PGTMR 3 FB2 2 SENSEP SENSEP SENSEN FB3 24 SCTMR TRACK3 1 ORDER PART NUMBER TOP VIEW SENSEN VCC ORDER PART NUMBER GND TOP VIEW 2925 2925 UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN EXPOSED PAD (PIN 25) INTERNALLY CONNECTED TO GND (PCB CONNECTION OPTIONAL) TJMAX = 125°C, θJA = 37°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise noted. SYMBOL PARAMETER VCC Input Supply Range ICC Input Supply Current VCC(UVL) Input Supply Undervoltage Lockout CONDITIONS MIN ● TYP 2.9 MAX UNITS 5.5 V IFBx = 0, ITRACKx = 0, IRAMPBUF = 0 ● 1.5 3 mA IFBx = –1mA, ITRACKx = –1mA, IRAMPBUF = –3mA ● 10.5 15 mA VCC Rising ● 2.5 2.7 V 2.3 2925f 2 LTC2925 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN ∆VCC(UVL, HYST) Input Supply Undervoltage Lockout Hysteresis ∆VGATE External N-Channel Gate Drive (VGATE – VCC) IGATE GATE pin current VON(TH) ON Pin Threshold Voltage ∆VON(HYST) ON Pin Hysteresis VON(FC) ON Pin Fault Clear Threshold Voltage ION(IN) ON Pin Input Current TYP MAX 25 UNITS mV IGATE = –1µA ● 5 5.5 6 V Gate On, VGATE = 0V, No Faults ● –7 –10 –13 µA Gate Off, VGATE = 5V, No Faults ● 7 10 13 µA Gate Off, VGATE = 5V, Short-Circuit or Power Good Timeout ● 5 20 50 mA VON rising ● 1.214 1.232 1.250 ● 30 75 150 ● 0.3 0.4 0.5 V 0 ±100 nA VON = 1.2V, VCC = 5.5V ● V mV ∆VRS-SENSE(TH) Sense Resistor Over-Current Voltage Threshold 1V < VSENSEP < VCC 0V < VSENSEP < 1V (VSENSEP – VSENSEN) ● ● 40 30 50 50 60 70 mV mV ISENSEN SENSEN Pin Input Current 0V < VSENSEN < VCC ● –1 5 10 µA ISENSEP SENSEP Pin Input Current 0V < VSENSEP < VCC ● –1 5 10 µA VOS Ramp Buffer Offset (VRAMPBUF – VRAMP) VRAMPBUF = VCC/2, IRAMPBUF = 0A ● –30 0 30 mV VFAULT(OL) FAULT Output Low Voltage IFAULT = 3mA ● 0.2 0.4 V VSDx(OL) SDx Output Low Voltage ISDx = 1mA, VCC = 2.3 ● 0.2 0.4 V VSTATUS(OL) STATUS Output Low Voltage ISTATUS = 3mA ● 0.2 0.4 V IRAMP RAMP Pin Input Current 0V < RAMP < VCC, VCC = 5.5V ● 0 ±1 µA VRAMPBUF(OL) RAMPBUF Low Voltage IRAMPBUF = 3mA ● 90 150 mV VRAMPBUF(OH) RAMPBUF High Voltage (VCC – VRAMPBUF ) IRAMPBUF = –3mA ● 100 200 mV IERROR(%) IFBx to ITRACKx Current Mismatch IERROR(%) = (IFBx – ITRACKx)/ITRACKx ITRACKx = –10µA ITRACKx = –1mA ● ● 0 0 ±5 ±5 % % VTRACKx TRACK pin voltage ITRACKx = –10µA ITRACKx = –1mA ● ● 0.8 0.8 0.82 0.82 V V IFB(LEAK) IFB Leakage Current VFB = 1.5V, VCC = 5.5V ● ±10 nA VFB(CLAMP) VFB Clamp Voltage 1µA < IFB < 1mA ● 2.5 V RREMOTE REMOTE Feedback Switch Resistance 2V < VREMOTE < VCC ● ISCTMR(UP) Short-Circuit Timer Pullup Current VSCTMR = 1V ISCTMR(DN) Short-Circuit Timer Pulldown Current VSCTMR = 1V VSCTMR(TH) Short-Circuit Timer Threshold Voltage ISDTMR(UP) Shutdown Timer Pullup Current VSDTMR(TH) Shutdown Timer Threshold Voltage IPGI(UP) Power Good Input Pullup Current VPGI(TH) Power Good Input Threshold Voltage IPGTMR(UP) Power Good Timer Pullup Current VPGTMR(TH) Power Good Timer Threshold Voltage VSDTMR = 1V VPGI = 0V VPGTMR = 1V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into the device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. 0.78 0.78 1.6 2.1 15 30 Ω ● –35 –50 –65 µA ● 1 2 3 µA ● 1.1 1.23 1.4 V ● –7 –10 –13 µA ● 1.1 1.23 1.4 V ● –5 –10 –15 µA ● 0.8 1.4 V ● –8 –10 –14 µA ● 1.1 1.23 1.4 V Note 3: The GATE pin is internally limited to a minimum of 11.5V. Driving this pin to voltages beyond the clamp may damage the part. 2925f 3 LTC2925 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are at TA = 25°C. ICC vs VCC 1.4 0.8 VSDx(OL) (V) ICC (mA) 12 1.0 ITRACKx = IFBx = 0mA IRAMPBUF = 0mA 1.3 1.2 11 0.6 VGATE (V) 1.5 VGATE vs VCC VSDx(OL) vs VCC 0.4 10 ISDx = 5mA 9 1.1 1.0 2.9 0.2 3.5 4.5 4 VCC (V) 0 5 5.5 ISDx = 10µA 0 1 2925 G01 U U U PI FU CTIO S 2 3 VCC (V) 4 5 2925 G02 8 2 3 4 VCC (V) 5 6 2925 G03 GN/UF Packages VCC (Pin 1/Pin 22): Positive Supply Input. The operating supply input range is 2.9V to 5.5V. An undervoltage lockout circuit resets the part when the supply is below 2.5V. VCC should be bypassed to GND with a 0.1µF capacitor. ramping the supplies down. Pulling the ON pin below 0.4V resets the electronic circuit breaker in the LTC2925. If a resistive divider connected to VCC drives the ON pin, the supplies will automatically start up when VCC is fully powered. SENSEP (Pin 2/Pin 23): Circuit Breaker Positive Sense Input. SENSEP and SENSEN measure the voltage across the sense resistor and trigger the circuit breaker function when the current exceeds the level programmed by the sense resistor for longer than a short circuit timer cycle (see SCTMR). If unused, tie SENSEN and SENSEP to VCC. SDTMR (Pin 5/Pin 2): Shutdown Timer. A capacitor from SDTMR to GND sets the delay time between the ON pin transitioning high (which releases the SDx pins) and the supplies beginning to ramp-up. Float SDTMR when it is unused. SENSEN (Pin 3/Pin 24): Circuit Breaker Negative Sense Input. SENSEN connects to the low side of the current sense resistor. SENSEP and SENSEN monitor the current through the external FET by measuring the voltage across the sense resistor. The circuit breaker turns off the FET when the sense voltage exceeds 50mV for longer than a short circuit timer cycle (see SCTMR). If the short-circuit timer times out, the GATE pin will be pulled low immediately to protect the FET. If unused, tie SENSEN and SENSEP to VCC. ON (Pin 4/Pin 1): On Control Input. The ON pin has a threshold of 1.23V with 75mV of hysteresis. An active high will cause 10µA to flow from the GATE pin, ramping up the supplies. An active low pulls 10µA from the GATE pin, SD1, SD2, SD3 (Pins 6, 7, 8/Pins 3, 4, 5): Outputs for Slave Supply Shutdowns. The SDx pins are open-drain outputs that hold the shutdown (RUN/SS) pins of the slave supplies low until the ON pin is pulled above 1.23V. The SDx pins will be pulled low again when RAMP <100mV and ON <1.23V. If a slave supply is capable of operating with an input supply that is lower than the LTC2925’s minimum operating voltage of 2.9V, the SDx pins can be used to hold off the slave supplies. Each SDx pin is capable of sinking greater than 1mA with supplies as low as 2.3V. RAMPBUF (Pin 9/Pin 6): Ramp Buffer Output. Provides a low impedance buffered version of the signal on the RAMP pin. This buffered output drives the resistive dividers that connect to the TRACKx pins. Limit the capacitance at the RAMPBUF pin to less than 100pF. 2925f 4 LTC2925 U U U PI FU CTIO S GN/UF Packages GND (Pin 10/Pins 7, 25): Circuit Ground. TRACK1, TRACK2, TRACK3 (Pins 15, 14, 12/Pins 12, 11, 9): Tracking Control Input Pin. A resistive divider between RAMPBUF, TRACKx and GND determines the tracking profile of OUTx (see Applications Information). TRACKx pulls up to 0.8V and the current supplied at TRACKx is mirrored at FBx. The TRACKx pin is capable of supplying at least 1mA when VCC = 2.9V. It may be capable of supplying up to 10mA when the supply is at 5.5V, so care should be taken not to short this pin for extended periods. Limit the capacitance at the TRACKx pin to less than 25pF. Float the TRACKx pins if unused. FB1, FB2, FB3 (Pins 16, 13, 11/Pins 13, 10, 8): Feedback Control Output. FBx connects to the feedback node of slave supplies. Tracking is achieved by mirroring the current from TRACKx into FBx. If the appropriate resistive divider connects RAMPBUF and TRACKx, the FBx current will force OUTx to track RAMP. The LTC2925 is capable of controlling slave supplies with feedback voltages between 0V and 1.6V. To prevent damage to the slave supply, the FBx pin will not force the slave’s feedback node above 2.5V. In addition, it will not actively sink current from this node even when the LTC2925 is unpowered. Float the FBx pins if unused. REMOTE (Pin 17/Pin 14): Remote Sense Switch. A 15Ω switch connects REMOTE to RAMP when the GATE is fully enhanced (GATE > RAMP + 4.9V). Otherwise, it presents a high-impedance. When the slave supplies track the master supply, REMOTE can be used to compensate for the voltage drop across the external sense resistor and Nchannel FET. A resistor between the output and the sense nodes of the master supply provides feedback before the external FET is fully enhanced. If an external FET is not used, float REMOTE. RAMP (Pin 18/Pin15): Ramp Buffer Input. When the RAMP pin is connected to the source of the external Nchannel FET, the slave supplies track the FET’s source as it ramps up and down. Alternatively, when no external FET is used, the RAMP pin can be tied directly to the GATE pin. In this configuration, the supplies track the capacitor on the GATE pin as it is charged and discharged by the 10µA current source controlled by the ON pin. When the GATE is fully enhanced (GATE > RAMP + 4.9V) the open-drain STATUS pin goes high-impedance and the remote sense switch connects the RAMP pin to the REMOTE pin. GATE (Pin 19/Pin 16): Gate Drive for External N-Channel FET. When the ON pin is high, an internal 10µA current source charges the gate of the external N-channel MOSFET. A capacitor connected from GATE to GND sets the ramp rate. It is a good practice to add a 10Ω resistor between this capacitor and the FET’s gate to prevent high frequency FET oscillations. An internal charge pump guarantees that GATE will pull up to 5V above VCC ensuring that logic level N-channel FETs are fully enhanced. When the ON pin is pulled low, the GATE pin is pulled to GND with a 10µA current source. Under a short-circuit condition, the electronic circuit breaker in the LTC2925 pulls the GATE low immediately with 20mA. Tie GATE to GND if unused. FAULT (Pin 20/Pin 17): Circuit Breaker and Power Good Timer Fault Output. FAULT is an open-drain output that pulls low when the electronic circuit breaker is activated or a power good timeout fault is detected. FAULT is reset by pulling ON below 0.4V. To allow retry, tie FAULT to ON. STATUS (Pin 21/Pin 18): Power Good Status Indicator. The STATUS pin is an open-drain output that pulls low until GATE has been fully charged at which time all supplies will have reached their final operating voltage. PGI (Pin 22/Pin 19): Power Good Timer Input. PGI connects to the RST pin of the downstream supply monitor. If PGI has not transitioned high within a power good timer cycle (see PGTMR), the FAULT pin will be pulled low and the supplies will be turned off by pulling the GATE pin low with 20mA. PGI is pulled up with 10µA. An internal schottky diode allows PGI to be pulled safely above VCC. Float PGI when it is unused. PGTMR (Pin 23/Pin 20): Power Good Timer. A capacitor from PGTMR to GND sets the Power Good Timer duration. While ON > 1.23V, the PGTMR pin will pull up to VCC with 10µA. Otherwise, it pulls to GND. If the voltage on the PGTMR pin exceeds 1.23V and PGI is still low, FAULT will be pulled low and the GATE will be pulled to ground with 20mA until the power good timer fault is cleared by pulling ON below 0.4V. If FAULT is tied back to ON the system will automatically retry after a FAULT. In this mode, verify that the slave supplies’ current limits provide sufficient protection under short-circuit conditions. Float PGTMR when it is unused. 2925f 5 LTC2925 U U U PI FU CTIO S GN/UF Packages SCTMR (Pin 24/Pin 21): Circuit Breaker Timer. A capacitor from SCTMR to GND programs the maximum time that a short circuit can be sustained before GATE is pulled low. When (SENSEP – SENSEN) > 50mV, SCTMR will pull up with 50µA, otherwise it pulls down with 2µA. When the voltage at SCTMR exceeds 1.23V, the GATE will be pulled to ground with 20mA and the FAULT pin will be pulled low. W FU CTIO AL BLOCK DIAGRA The circuit breaker function is reset by pulling ON below 0.4V. The GATE pin will not rise again until SCTMR has been pulled below 100mV by the 2µA current source. If FAULT is tied back to ON the system will automatically retry after a fault. Tie SCTMR to GND if the circuit breaker is not used. Pin numbers in parentheses are for the UF package. U U (22) 1 VCC VCC (9) 12 (11) 14 (12) 15 FB3 TRACK3 + – TRACK2 TRACK1 0.8V FB2 FB1 11 (8) 13 (10) 16 (13) VCC SENSEP > SENSEN + 50mV SENSEP 50µA (21) 24 SCTMR 50mV 2µA GATE PGI VCC – + 1.2V PGTMR 2 (23) 3 (24) 20 (17) 19 (16) CHARGE PUMP 10µA + – 10µA (20) 23 FAULT + – 1.2V (19) 22 SENSEN ONSIG 1.2V 10µA SCTMR 0.1V 0.4V (1) 4 ON 1.2V – + + – S R S R 10µA SDTMR + – SDx – + 10 2.6V RAMP 1× 18 (15) REMOTE – + (14) 17 5 (2) + – VCC RAMPBUF VCC Q 0.1V (6) 9 Q STATUS 4.9V 10 GND VCC GATE GATE > RAMP + 4.9V 2925 FBD (7, 25) 2925f 6 LTC2925 U W U U APPLICATIO S I FOR ATIO Power Supply Tracking and Sequencing The LTC2925 handles a variety of power-up profiles to satisfy the requirements of digital logic circuits including FPGAs, PLDs, DSPs and microprocessors. These requirements fall into one of the four general categories illustrated in Figures 1 to 4. Some applications require that the potential difference between two power supplies must never exceed a specified voltage. This requirement applies during power-up and power-down as well as during steady-state operation, often to prevent destructive latch-up in a dual supply IC. Typically, this is achieved by ramping the supplies up and down together (Figure 1). In other applications it is desirable to have the supplies ramp up and down with fixed voltage offsets between them (Figure 2) or to have them ramp up and down ratiometrically (Figure 3). Certain applications require one supply to come up after another. For example, a system clock may need to start before a block of logic. In this case, the supplies are sequenced as in Figure 4 where the 1.8V supply ramps up completely followed by the 2.5V supply and then the 1.5V supply. Operation The LTC2925 provides a simple solution to all of the power supply tracking and sequencing profiles shown in Figures 1 to 4. A single LTC2925 controls up to four supplies with three “slave” supplies that track a “master” signal. With just two resistors, a slave supply is configured to ramp up as a function of the master signal. This master signal can be a fourth supply that is ramped up through an external FET, whose ramp rate is set with a single capacitor, or it can be a signal generated by tying the GATE and RAMP pins to an external capacitor. MASTER MASTER SLAVE1 1V/DIV SLAVE2 SLAVE3 10ms/DIV SLAVE1 SLAVE2 SLAVE3 1V/DIV 10ms/DIV 2925 F01 Figure 1. Coincident Tracking 2925 F02 Figure 2. Offset Tracking MASTER SLAVE1 SLAVE2 SLAVE3 2V/DIV 10ms/DIV Figure 3. Ratiometric Tracking 2925 F03 SLAVE1 2V/DIV SLAVE2 SLAVE3 10ms/DIV 2925 F04 Figure 4. Supply Sequencing 2925f 7 LTC2925 U U W U APPLICATIO S I FOR ATIO Tracking Cell The LTC2925’s operation is based on the tracking cell shown in Figure 5, which uses a proprietary wide-range current mirror. The tracking cell shown in Figure 5 servos the TRACK pin at 0.8V. The current supplied by the TRACK pin is mirrored at the FB pin to establish a voltage at the output of the slave supply. The slave output voltage varies with the master signal, enabling the slave supply to be controlled as a function of the master signal with terms set by RTA and RTB. By selecting appropriate values of RTA and RTB, it is possible to generate any of the profiles in Figures 1 to 4. VCC In a properly designed system, when the master signal has reached its maximum voltage the current from the TRACK1 pin is zero. In this case, there is no current from the FB1 pin and the LTC2925 has no effect on the output voltage accuracy, transient response or stability of the slave supply. When the ON pin falls below VON(TH) – ∆VON(HYST), typically 1.225V, the GATE pin pulls down with 10µA and the master signal and the slave supplies will fall at the same rate as they rose previously. The ON pin can be controlled by a digital I/O pin or it can be used to monitor an input supply. By connecting a resistive divider from an input supply to the ON pin, the supplies will ramp up only after the monitored supply has reached a preset voltage. VCC + + – MASTER 0.8V SENSEP – SENSEN > 50mV – RTB TRACK 50µA DC/DC FB FB OUT SENSEP SCTMR SLAVE 50mV RTA SENSEN RFA RFB 2µA 2925 F05 + Figure 5. Simplified Tracking Cell Controlling the Ramp-Up and Ramp-Down Behavior The operation of the LTC2925 is most easily understood by referring to the simplified functional diagram in Figure 6. When the ON pin is low, the GATE pin is pulled to ground causing the master signal to remain low. Since the current through RTB1 is at its maximum when the master signal is low, the current from FB1 is also at its maximum. This current drives the slave’s output to its minimum voltage. When the ON pin rises above 1.23V, the master signal rises and the slave supply tracks the master signal. The ramp rate is set by an external capacitor driven by a 10µA current source from an internal charge pump. If no external FET is used, the ramp rate is set by tying the RAMP and GATE pins together at one terminal of the external capacitor (see the Ratiometric Tracking Example). 1.2V – ON + RONB 10µA GATE RONA 1.2V – 10µA RAMPBUF Q1 CGATE RAMP 1× MASTER VCC + 0.8V – RTB1 TRACK1 FB1 DC/DC SLAVE1 RTA1 R RFA1 FB1 2925 F06 Figure 6. Simplified Functional Block Diagram 2925f 8 LTC2925 U U W U APPLICATIO S I FOR ATIO Optional External FET Figure 7 illustrates how an optional external N-channel FET can ramp up a single supply that becomes the master signal. When used, the FET’s gate is tied to the GATE pin and its source is tied to the RAMP pin. Under normal operation, the GATE pin sources or sinks 10µA to ramp the FET’s gate up or down at a rate set by the external capacitor connected to the GATE pin. The series FET easily controls any supply with an output voltage between 0V and VCC. See the Typical Applications section for examples. RSENSE VIN Q1 MASTER 0.1µF 10Ω CGATE SUPPLY MONITOR RONB VCC SENSEP SENSEN RAMP GATE ON RST 3.3V PGI RONA SD1 REMOTE FB1 VIN RUN/SS IN DC/DC FB = 1.235V OUT 10k RFA1 STATUS RFB1 3.3V VIN LTC2925 SD2 10k FB2 FAULT RAMPBUF RTB1 2.5V SLAVE2 RFB2 SD3 RTB3 FB3 RUN/SS IN DC/DC FB = 0.8V OUT TRACK3 RTA3 CSCTMR = 50µA • tSCTMR 1.23V Because the slave supplies track the RAMP pin which is driven by the external FET, they are pulled low by the tracking circuit when a short-circuit fault occurs. Following a short-circuit fault, the FET is latched off and FAULT is pulled low until the fault is cleared by pulling the ON pin below 0.4V. Note that the supplies will not be allowed to ramp up again until SCTMR has been pulled below about 100mV by the 2µA pull down current source. The electronic circuit breaker supports any supply voltage between 0V and VCC. Although it is normally used to monitor current through the optional series FET, it is capable of monitoring other currents, including the current from a slave supply. The Typical Applications section shows one such example. 3.3V RTB2 TRACK2 RTA2 IN RUN/SS DC/DC FB = 0.8V OUT RFA2 TRACK1 RTA1 1.8V SLAVE1 The short-circuit timer duration is configured by a capacitor tied between SCTMR and GND. SCTMR will pull up with 50µA when SENSEP – SENSEN > 50mV. Otherwise, it pulls down with 2µA. When the voltage at SCTMR exceeds 1.23V, the GATE will be pulled to ground with 20mA and the FAULT pin will be pulled low. Thus, the capacitor, CSCTMR, required to configure the short-circuit timer duration, tSCTMR is determined from: GND SCTMR CSCTMR SDTMR CSDTMR PGTMR CPGTMR RFA3 1.5V SLAVE3 RFB3 2925 F07 Figure 7. Typical Application With External FET Electronic Circuit Breaker The LTC2925 features an electronic circuit breaker function that protects the optional series FET against short circuits. An external sense resistor is used to measure the current flowing in the FET. If the voltage across the sense resistor exceeds 50mV for more than a short-circuit timer cycle, the gate of the FET is pulled low with 20mA, turning it off. If the electronic circuit breaker is not used, tie SENSEP and SENSEN to VCC and SCTMR to GND. Power Good Timeout The power good timeout circuit turns off the supplies if an external supply monitor, connected to the PGI pin, fails to indicate that all supplies have entered regulation in time after power up begins. After power up is complete, it turns off the supplies if any supply exits regulation. The power good timer duration is configured by a capacitor tied between PGTMR and GND. PGTMR will pull up the CPGTMR capacitor with 10µA starting when the ON pin is driven above 1.23V. Once the voltage at the PGTMR exceeds 1.23V, a fault will trip if the PGI pin is low. When the power good timeout circuit detects a fault, the GATE pin is 2925f 9 LTC2925 U U W U APPLICATIO S I FOR ATIO pulled low, the supplies are latched off, and the FAULT pin is held low until the fault is cleared by taking the ON pin below 0.4V. The PGI pin, which is normally connected to the RST pin of an external supply monitor, is pulled up with 10µA through a schottky diode allowing it to be pulled safely above VCC. Since, PGTMR pulls up with a 10µA current source, the capacitor, CPGTMR, required to configure the power good timeout duration, tPGTMR, is determined from: CPGTMR = 10µA • tPGTMR 1.23V If the power good timeout circuit is unused, tie PGTMR low and float PGI. The Ramp Buffer The RAMPBUF pin provides a buffered version of the RAMP pin voltage that drives the resistive dividers on the TRACKx pins. When there is no external FET, it provides up to 3mA to drive the resistors even though the GATE pin only supplies 10µA (Figure 8). The RAMPBUF pin also proves useVIN CGATE 0.1µF ful in systems with an external FET. Since the track cell drives 0.8V on the TRACKx pins, if RTBx is connected directly to the FET’s source, the TRACKx pin could potentially pull up the FET’s source towards 0.8V when the FET is off. RAMPBUF blocks this path. Shutdown Outputs In some applications it might be necessary to control the shutdown or RUN/SS pins of the slave supplies. The LTC2925 may not be able to supply the rated 1mA of current from the FB1, FB2, and FB3 pins when VCC is below 2.9V. If the slave power supplies are capable of operating at low input voltages, use the open-drain SDx outputs to drive the SHDN or RUN/SS pins of the slave supplies (Figures 7 and 8). The SDx pins are released when the ON pin rises above 1.23V, VCC is above the 2.6V undervoltage lockout condition, and there are no faults latched. The shutdown timer begins at the same time, and the supplies begin to ramp up after the shutdown timer cycle completes. The duration of the timer cycle is configured by a capacitor tied between SDTMR and GND. The capacitor voltage is ramped up by a 10µA current source and the SDTMR cycle completes when its voltage reaches 1.23V. Thus, the capacitor, CSDTMR, required for a given shutdown timer cycle, tSDTMR, is determined from: SUPPLY MONITOR RONB VCC SENSEP SENSEN GATE RAMP ON VIN PGI RONA SD1 REMOTE FB1 VIN RUN/SS IN DC/DC FB OUT RFA1 STATUS The SDx pins pull low again when the ON pin is pulled below 1.23V and the RAMP pin is below about 100mV. VIN LTC2925 SD2 FB2 FAULT RAMPBUF RTB1 IN RUN/SS DC/DC FB OUT RFA2 TRACK1 SLAVE2 RFB2 VIN RTB2 SD3 TRACK2 RTA2 SLAVE1 10µA • tSDTMR 1.23V RFB1 VIN RTA1 CSDTMR = RST RTB3 FB3 RUN/SS IN DC/DC FB OUT SLAVE3 TRACK3 RTA3 GND SCTMR SDTMR CSDTMR PGTMR CPGTMR RFA3 RFB3 2925 F08 Figure 8. Typical Application Without External FET 2925f 10 LTC2925 U U W U APPLICATIO S I FOR ATIO Status Output Retry on Fault The STATUS pin provides an indication that the supplies are finished ramping up. This pin is an open-drain output that pulls low until the GATE has been fully charged. Since the GATE pin drives the gate of the external FET, or the RAMP pin directly when no FET is used, the supplies are completely ramped up when the GATE pin is fully charged. The STATUS pin will go low again when the GATE pin is pulled low, either because of a short-circuit fault, a power good timeout fault, or because the ON pin has been pulled low. The LTC2925 continuously attempts to ramp up the outputs after a fault if the FAULT pin is tied to the ON pin (Figure 9). If a short-circuit fault occurs in this configuration, the SCTMR pin ramps up the CSCTMR capacitor with 50µA until it reaches 1.23V. Then, GATE is pulled low turning off the shorted FET. At the same time, the FAULT pin’s open-drain output pulls ON low. The CSCTMR capacitor is pulled down with 2µA until it reaches about 100mV. After the CSCTMR capacitor reaches 100mV, the shutdown timer begins and upon completing a shutdown timer cycle, the supplies start ramping up again. If there is no short-circuit this time, the supplies will come up normally. Otherwise, the retry cycle will repeat. If a longer off time is required between retry attempts, the CSDTMR capacitor value can be increased, providing a greater delay before the FET’s GATE ramps up on each cycle. Note that tying FAULT to ON also causes the LTC2925 to retry on Power Good Timeout faults. In this mode, verify that the slave supplies’ current limits provide sufficient protection under short-circuit conditions. Fault Output The FAULT pin is an open-drain output that pulls low when the electronic circuit breaker is activated due to a shortcircuit or power good timeout fault. FAULT is reset by pulling ON below 0.4V. The supplies will not be allowed to ramp up again until the SCTMR, PGTMR, and SDTMR pins are below about 100mV, and the ON pin is pulled above 1.23V. RSENSE VIN Q1 MASTER 0.1µF 10Ω CGATE SUPPLY MONITOR RONB VCC SENSEP SENSEN RAMP GATE ON RST VIN PGI RONA SD1 REMOTE FB1 VIN RUN/SS IN DC/DC FB OUT 10k RFA1 STATUS SD2 FB2 FAULT RAMPBUF RTB1 IN RUN/SS DC/DC FB OUT RFA2 TRACK1 SLAVE2 RFB2 VIN RTB2 SD3 TRACK2 RTA2 RFB1 VIN LTC2925 RTA1 SLAVE1 RTB3 FB3 RUN/SS IN DC/DC FB OUT SLAVE3 TRACK3 RTA3 GND SCTMR CSCTMR SDTMR CSDTMR PGTMR CPGTMR RFA3 RFB3 2925 F09 Figure 9. Retry on Fault 2925f 11 LTC2925 U U W U APPLICATIO S I FOR ATIO 3-Step Design Procedure The following 3-step design procedure allows one to choose the TRACK resistors, RTAx and RTBx, and the gate capacitor, CGATE, that give any of the tracking or sequencing profiles shown in Figures 1 to 4. A basic four supply application circuit is shown in Figure 10. 1. Set the ramp rate of the master signal. Solve for the value of CGATE, the capacitor on the GATE pin, based on the desired ramp rate (V/s) of the master supply, SM. CGATE = IGATE where IGATE ≈ 10µA SM (1) If the external FET has a gate capacitance comparable to CGATE, then the external capacitor’s value should be reduced to compensate for the FET’s gate capacitance. If no external FET is used, tie the GATE and RAMP pins together, connect SENSEN and SENSEP to VCC, and connect SCTMR to GND. 2. Solve for the pair of resistors that provide the desired ramp rate of the slave supply, assuming no delay. RSENSE VIN Q1 MASTER RONB 154k CGATE RAMP GATE ON RST VIN PGI RONA 100k SD1 REMOTE FB1 VIN RUN/SS IN DC/DC FB OUT 10k RFA1 STATUS SD2 10k FB2 RTB1 SLAVE2 RTB2 SD3 RTB3 FB3 RUN/SS IN DC/DC FB OUT TRACK3 RTA3 GND SCTMR SDTMR VFB RFB (3) where VTRACK ≈ 0.8V. Note that large ratios of slave ramp rate to master ramp rate, SS/SM, may result in negative values for RTA´. If a sufficiently large delay is used in step 3, RTA will be positive, otherwise SS/SM must be reduced. PGTMR RFA3 2925 F10 RFB3 VTRACK • RTB tD • SM RTA = RTA ′ || RTA ′′ (4) (5) the parallel combination of RTA´ and RTA´´ RFB2 VIN TRACK2 RTA2 IN RUN/SS DC/DC FB OUT RFA2 TRACK1 RTA1 VTRACK V V + FB – TRACK RFA RTB RTA ′′ = RFB1 VIN FAULT RAMPBUF RTA ′ = (2) SLAVE1 VIN LTC2925 SM SS If no delay is required, such as in coincident and ratiometric tracking, then simply set RTA = RTA´. If a delay is desired, as in offset tracking and supply sequencing, calculate RTA´´ to determine the value of RTA where tD is the desired delay. SUPPLY MONITOR VCC SENSEP SENSEN RTB = RFB • 3. Choose RTA to obtain the desired delay. 0.1µF 10Ω Choose a ramp rate for the slave supply, SS. If the slave supply ramps up coincident with the master supply or with a fixed voltage offset, then the ramp rate equals the master supply’s ramp rate. Be sure to use a fast enough ramp rate for the slave supply so that it will finish ramping before the master supply has reached its final supply value. If not, the slave supply will be held below the intended regulation value by the master supply. Use the following formulas to determine the resistor values for the desired ramp rate, where RFB and RFA are the feedback resistors in the slave supply and VFB is the feedback reference voltage of the slave supply: SLAVE3 As noted in step 2, small delays and large ratios of slave ramp rate to master ramp rate (usually only seen in sequencing) may result in solutions with negative values for RTA. In such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. Figure 10. Four Supply Application 2925f 12 LTC2925 U W U U APPLICATIO S I FOR ATIO MASTER SLAVE2 SLAVE1 SLAVE3 1V/DIV 10ms/DIV 1V/DIV 10ms/DIV 2925 F11a 2925 F11b Figure 11. Coincident Tracking from Figure 12 Coincident Tracking Example A typical four supply application is shown in Figure 12. The master signal is a 3.3V module. The slave 1 supply is a 1.8V switching power supply, the slave 2 supply is a 2.5V switching power supply, and the slave 3 supply is a 1.5V supply. All three slave supplies track coincidently with the 3.3V supply that is controlled with an external FET. The ramp rate of the supplies is 100V/s. The 3-step design procedure detailed previously can be used to determine component values. Only the slave 1 supply is considered here as the procedure is the same for the other supplies. 1. Set the ramp rate of the master signal. is held below 1.23V. When the ON pin rises above 1.23V, 10µA pulls up CGATE and the gate of the FET at 100V/s. As the gate of the FET rises, the source follows and pulls up the output to 3.3V at 100V/s. This output serves as the master signal and is buffered from the RAMP pin to the RAMPBUF pin. As this output and the RAMPBUF pin rise, the current from the TRACKx pins is reduced. Consequently, the voltages at the slave supplies’ outputs increase, and the slave supplies track the master supply. When the ON pin is again pulled below 1.23V, 10µA will pull down CGATE and the gate of the FET at 100V/s. If the loads on the outputs are sufficient, all outputs will track down coincidently at 100V/s. From Equation 1: Q1 Si4412ADY 0.015Ω 3.3V VIN CGATE = MASTER 10µA = 0.1µF 100 V s 0.1µF 10Ω RONB 154k 2. Solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. CGATE 0.1µF SUPPLY MONITOR VCC SENSEP SENSEN GATE RAMP ON RONA 100k REMOTE From Equation 2: 3.3V SD1 RUN/SS IN DC/DC FB = 1.235V OUT FB1 VIN 10k 100V s RTB = 16.5k • = 16.5k 100V s RFA1 35.7k STATUS LTC2925 SD2 RTA ′ = 0.8 V ≈ 13k 1.235V 1.235V 0.8 V + – 16.5k 35.7k 16.5k 3. Choose RTA to obtain the desired delay. Since no delay is desired, RTA = RTA´ In this example, all supplies remain low while the ON pin FB2 FAULT RAMPBUF RTB1 16.5k 3.3V RTA1 13k RTB2 88.7k RTA2 41.2k RTB3 86.6k IN RUN/SS DC/DC FB = 0.8V OUT RFA2 41.2k TRACK1 SD3 TRACK2 FB3 RFB2 88.7k GND SCTMR CSCTMR 0.47µF SDTMR CSDTMR 0.082µF PGTMR CPGTMR 0.82µF RFA3 100k 2.5V SLAVE2 3.3V RUN/SS IN DC/DC FB = 0.8V OUT TRACK3 RTA3 100k 1.8V SLAVE1 RFB1 16.5k VIN 10k From Equation 3: RST PGI 1.5V SLAVE3 RFB3 86.6k 2925 F12 Figure 12. Coincident Tracking Example 2925f 13 LTC2925 U U W U APPLICATIO S I FOR ATIO SLAVE2 SLAVE1 SLAVE3 1V/DIV 10ms/DIV 1V/DIV 10ms/DIV 2925 F13a 2925 F13b Figure 13. Ratiometric Tracking from Figure 14 Ratiometric Tracking Example This example converts the coincident tracking example to the ratiometric tracking profile shown in Figure 13, using three supplies without an external FET. The ramp rate of the master signal remains unchanged (Step 1) and there is no delay in ratiometric tracking (Step 3), so only the result of step 2 in the 3-step design procedure needs to be considered. In this example, the ramp rate of the 1.8V slave 1 supply ramps up at 60V/s, the 2.5V slave 2 supply ramps up at 85V/s, and the 1.5V slave 3 supply ramps up at 50V/s. Always verify that the chosen ramp rate will allow the supplies to ramp-up completely before RAMPBUF reaches VCC. If the 1.8V supply were to ramp-up at 50V/s it would only reach 1.65V because the RAMPBUF signal would reach its final value of VCC = 3.3V before the slave supply reached 1.8V. From Equation 3: RTA ′ = 0.8 V ≈ 10k 1.235V 1.235V 0.8 V + – 16.5k 35.7k 27.5k Step 3 is unnecessary because there is no delay, so RTA = RTA´. 3.3V VIN CGATE 0.1µF 0.1µF RONB 154k VCC SENSEP SENSEN GATE RAMP ON RONA 100k REMOTE 3.3V SD1 RUN/SS IN DC/DC FB = 1.235V OUT 10k 2. Solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. RFA1 35.7k STATUS LTC2925 SD2 10k RTB1 27.4k RTA1 10k RTA2 38.3k FB2 FAULT RAMPBUF RTB2 100k 3.3V RTB3 174k IN RUN/SS DC/DC FB = 0.8V OUT RFA2 41.2k TRACK1 SD3 TRACK2 FB3 RFB2 88.7k GND SCTMR CSCTMR 0.41µF SDTMR CSDTMR 0.082µF PGTMR CPGTMR 0.82µF RFA3 100k 2.5V SLAVE2 3.3V RUN/SS IN DC/DC FB = 0.8V OUT TRACK3 RTA3 63.4k 1.8V SLAVE1 RFB1 16.5k VIN From Equation 2: 100 V s RTB = 16.5k • ≈ 27.4k 60 V s RST PGI FB1 VIN SUPPLY MONITOR 1.5V SLAVE3 RFB3 86.6k 2925 F14 Figure 14. Ratiometric Tracking Example 2925f 14 LTC2925 U W U U APPLICATIO S I FOR ATIO MASTER SLAVE2 SLAVE1 SLAVE3 1V/DIV 10ms/DIV 1V/DIV 10ms/DIV 2925 F15a 2925 F15b Figure 15. Offset Tracking from Figure 16 Offset Tracking Example From Equation 4: Converting the circuit in the coincident tracking example to the offset tracking shown in Figure 15 is relatively simple. Here the 1.8V slave 1 supply ramps up 1V below the master. The ramp rate remains the same (100V/s), so there are no changes necessary to steps 1 and 2 of the 3-step design procedure. Only step 3 must be considered. Be sure to verify that the chosen voltage offsets will allow the slave supplies to ramp up completely. In this example, if the voltage offset were 2V, the slave supply would only ramp up to 3.3V – 2V = 1.3V. RTA ″ = 0.8 V • 16.5k = 13.2k 1ms • 100 V s From Equation 5: RTA = 13.1k || 13.2k ≈ 6.65k Q1 Si4412ADY 0.015Ω 3.3V VIN MASTER 0.1µF 10Ω 3. Choose RTA to obtain the desired delay. RONB 154k First, convert the desired voltage offset, VOS, to a delay, tD, using the ramp rate: CGATE 0.1µF SUPPLY MONITOR VCC SENSEP SENSEN GATE RAMP ON RONA 100k REMOTE V 1V tD = OS = = 10ms SS 100 V s (6) 3.3V SD1 RUN/SS IN DC/DC FB = 1.235V OUT FB1 VIN RST PGI 10k RFA1 35.7k STATUS RFB1 16.5k 3.3V VIN LTC2925 SD2 10k FB2 FAULT RAMPBUF RTB1 16.5k RTA1 6.65k RTB2 88.7k RTA2 31.6k RTB3 86.6k IN RUN/SS DC/DC FB = 0.8V OUT RFA2 41.2k TRACK1 SD3 TRACK2 FB3 RFB2 88.7k GND SCTMR CSCTMR 0.41µF SDTMR CSDTMR 0.082µF PGTMR CPGTMR 0.82µF RFA3 100k 2.5V SLAVE2 3.3V RUN/SS IN DC/DC FB = 0.8V OUT TRACK3 RTA3 31.6k 1.8V SLAVE1 1.5V SLAVE3 RFB3 86.6k 2925 F16 Figure 16. Offset Tracking Example 2925f 15 LTC2925 U W U U APPLICATIO S I FOR ATIO MASTER SLAVE2 SLAVE1 SLAVE3 1V/DIV 10ms/DIV 1V/DIV 10ms/DIV 2925 F17a 2925 F17b Figure 17. Supply Sequencing from Figure 18 Supply Sequencing Example 3. Choose RTA to obtain the desired delay. In Figure 17, the three slave supplies are sequenced instead of tracking. As in the coincident tracking example, the 3.3V master supply ramps up at 100V/s through an external FET, so step 1 remains the same. The 1.8V slave 1 supply ramps up at 1000V/s beginning 10ms after the master signal starts to ramp up. The 2.5V slave 2 supply ramps up at 1000V/s beginning 20ms after the master signal begins to ramp up. The 1.5V slave 3 supply ramps up at 1000V/s beginning 25ms after the master signal begins to ramp up. Note that not every combination of ramp rates and delays is possible. Small delays and large ratios of slave ramp rate to master ramp rate may result in solutions that require negative resistors. In such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. In this example, solving for the slave 1 supply yields: From Equation 4: RTA ″ = 0.8 V • 1.65k = 1.32k 10ms • 100 V s From Equation 5: RTA = –2.13k || 1.32k ≈ 3.48k Q1 Si4412ADY 0.015Ω 3.3V VIN MASTER 0.1µF 10Ω RONB 154k CGATE 0.1µF SUPPLY MONITOR VCC SENSEP SENSEN GATE RAMP ON RONA 100k REMOTE 3.3V SD1 RUN/SS IN DC/DC FB = 1.235V OUT FB1 VIN 2. Solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. RST PGI 10k RFA1 35.7k STATUS RFB1 16.5k 3.3V VIN LTC2925 From Equation 2: RTB = 16.5k • SD2 10k 100 V s ≈ 1.65k 1000 V s From Equation 3: 0.8 V RTA ′ = ≈ –2.13k 1.235V 1.235V 0.8 V + – 16.5k 35.7k 1.65k FB2 FAULT RAMPBUF RTB1 1.65k RTA1 3.48k RTB2 8.87k RTA2 4.87k RTB3 8.66k IN RUN/SS DC/DC FB = 0.8V OUT RFA2 41.2k TRACK1 SD3 TRACK2 FB3 RFB2 88.7k GND SCTMR CSCTMR 0.41µF SDTMR CSDTMR 0.082µF PGTMR CPGTMR 0.82µF RFA3 100k 2.5V SLAVE2 3.3V RUN/SS IN DC/DC FB = 0.8V OUT TRACK3 RTA3 3.74k 1.8V SLAVE1 1.5V SLAVE3 RFB3 86.6k 2925 F18 Figure 18. Supply Sequencing Example 2925f 16 LTC2925 U W U U APPLICATIO S I FOR ATIO Final Sanity Checks The collection of equations below is useful for identifying unrealizable solutions. As stated in step 2, the slave supply must finish ramping before the master signal has reached its final voltage. This can be verified by the following equation: R VTRACK 1+ TB < VMASTER RTA Here, VTRACK = 0.8V. VMASTER is the final voltage of the master signal, either the supply voltage ramped up through the optional external FET or VCC when no FET is present. It is possible to choose resistor values that require the LTC2925 to supply more current than the Electrical Characteristics table guarantees. To avoid this condition, check that ITRACKx does not exceed 1mA and IRAMPBUF does not exceed ±3mA. To confirm that ITRACKx < 1mA, the TRACKx pin(s) maximum guaranteed current, verify that: VTRACK < 1mA RTA RTB Finally, check that the RAMPBUF pin will not be forced to sink more than 3mA when it is at 0V or be forced to source more than 3mA when it is at VMASTER. VTRACK V V + TRACK + TRACK < 3mA and RTA1 RTB1 RTA2 RTB2 RTA3 RTB3 VMASTER V V + MASTER + MASTER < 3mA RTA1 + RTB1 RTA2 + RTB2 RTA3 + RTB3 Therefore, the LTC2925’s tracking cell will not effectively drive the supply’s output below the input. Special caution should be taken when considering the use of linear regulators. Three-terminal linear regulators have a reference voltage that is referred to the output supply rather than to ground. In this case, driving current into the regulator’s feedback node will cause its output to rise rather than fall. Even linear regulators that have their reference voltage referred to ground, including low-dropout regulators (LDOs), may be problematic. Linear regulators commonly contain circuitry that prevents driving their outputs below their reference voltage. This may not be obvious from the datasheets, so lab testing is recommended whenever the LTC2925’s tracking cell is used to control linear regulators. Load Requirements When the supplies are ramped down quickly, either the load or the supply itself must be capable of sinking enough current to support the ramp rate. For example, if there is a large output capacitance on the supply and a weak resistive load, supplies that do not sink current will have their falling ramp rate limited by the RC time constant of the load and the output capacitance. Figure 19 shows the case when the 2.5V supply does not track the 1.8V and 3.3V supplies near ground. Start-Up Delays Often power supplies do not start-up immediatley when their input supplies are applied. If the LTC2925 tries to ramp-up these power supplies as soon as the input supply is present, the start-up of the outputs may be delayed Caution with Boost Regulators and Linear Regulators Note that the LTC2925’s tracking cell is not able to control the outputs of all types of power supplies. If it is necessary to control a supply, where the output is not controllable through its feedback node, the series FET can be used to control its output. For example, boost regulators commonly contain an inductor and diode between the input supply and the output supply providing a DC current path when the output voltage falls below the input voltage. MASTER SLAVE2 SLAVE1 1V/DIV 1ms/DIV 2925 F19 Figure 19. Weak Resistive Load 2925f 17 LTC2925 U W U U APPLICATIO S I FOR ATIO defeating the tracking circuit (Figure 20). Often this delay is intentionally configured by a soft-start capacacitor. This can be remedied either by reducing the soft-start capacitor on the slave supply or by increasing the shutdown timer cycle configured by CSDTMR. Layout Considerations Be sure to place a 0.1µF bypass capacitor as near as possible to the supply pin of the LTC2925. To minimize the noise on the slave supplies’ outputs, keep the traces connecting the FBx pins of the LTC2925 and the feedback nodes of the slave supplies as short as possible. In addition, do not route those traces next to signals with fast transition times. In some circumstances it might be MASTER SLAVE1 1V/DIV SLAVE2 ON This resistor must not exceed: RSERIES = 1.6 V – VFB 1.6 V = – 1 (RFA || RFB) VFB IMAX This resistor is most effective if there is already a capacitor at the feedback node of the slave supply (often a compensation component). Increasing the capacitance on a slave supply’s feedback node will further improve the noise immunity, but could affect the stability and transient response of the supply. For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC2925’s SENSEP and SENSEN pins are strongly recommended. The drawing in Figure 22 illustrates the correct way of making connections between the LTC2925 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. The power rating of the sense resistor should accommodate steady-state fault current levels so that the component is not damaged before the circuit breaker trips. 2925 F20 1ms/DIV advantageous to add a resistor near the feedback node of the slave supply in series with the FBx pin of the LTC2925. Figure 20. Power Supply Start-Ups Delayed CURRENT FLOW TO LOAD VCC LTC2925 RSERIES FB1 GND MINIMIZE TRACE LENGTH DC/DC FB OUT RFA RFB TRACK WIDTH W: 0.03' PER AMP ON 1 OZ COPPER IRC-TT SENSE RESISTOR LR251201R010F OR EQUIVALENT 0.01Ω, 1%, 1W CURRENT FLOW TO LOAD W 2925 F23 0.1µF 2925 F22 TO SENSEP TO SENSEN Figure 21. Layout Considerations Figure 22. Making PCB Connections to the Sense Resistor 2925f 18 LTC2925 U PACKAGE DESCRIPTIO GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .337 – .344* (8.560 – 8.738) 24 23 22 21 20 19 18 17 16 15 1413 .045 ±.005 .229 – .244 (5.817 – 6.198) .254 MIN .033 (0.838) REF .150 – .157** (3.810 – 3.988) .150 – .165 1 .0165 ± .0015 2 3 4 5 6 7 8 9 10 11 12 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) .008 – .012 (0.203 – 0.305) TYP NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .0250 (0.635) BSC GN24 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 4.00 ± 0.10 (4 SIDES) 0.70 ±0.05 BOTTOM VIEW—EXPOSED PAD 0.23 TYP (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP 23 24 0.38 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 4.50 ± 0.05 2.45 ± 0.05 (4 SIDES) 2.45 ± 0.10 (4-SIDES) 3.10 ± 0.05 PACKAGE OUTLINE (UF24) QFN 1103 0.25 ±0.05 0.50 BSC 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2925f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2925 U TYPICAL APPLICATIO S External FET Controls 1V Supply 0.015Ω 1V Electronic Circuit Breaker Monitors Slave Output Q1 Si4412ADY Q1 Si4412ADY VIN MASTER 0.1µF 10Ω 3.3V RONB 154k CGATE 0.1µF 10Ω SUPPLY MONITOR VCC SENSEP SENSEN GATE RAMP ON RONA 100k REMOTE PGI 3.3V SD1 RUN/SS IN DC/DC FB = 1.235V OUT 10k RFA1 35.7k STATUS SD2 FB2 FAULT RAMPBUF RTA1 48.7k RTB2 32.4k RTA2 215k RTB3 53.6k RFA2 41.2k TRACK1 SD3 TRACK2 GND SCTMR CSCTMR 0.41µF SDTMR CSDTMR 0.082µF PGTMR RFA3 100k CPGTMR 0.82µF RST PGI 3.3V SD1 RUN/SS IN DC/DC FB = 1.235VOUT FB1 VIN RFA1 RFB1 35.7k 16.5k STATUS VIN SD2 10k 2.5V SLAVE2 3.3V TRACK3 RTA3 348k REMOTE 1.8V SLAVE1 1.5V SLAVE3 RFB3 86.6k FB2 FAULT RAMPBUF RTB1 16.5k RUN/SS IN DC/DC FB = 0.8V OUT FB3 RAMP GATE ON 3.3V RFB2 88.7k SUPPLY MONITOR VCC 10k IN RUN/SS DC/DC FB = 0.8V OUT 10k CGATE 0.1µF RONA 100k RFB1 16.5k VIN LTC2925 RONB 154k RST FB1 VIN RTB1 8.66k MASTER 0.1µF RTA1 13k RTB2 88.7k RTA2 41.2k RTB3 86.6k 1.8V SLAVE1 3.3V IN RUN/SS DC/DC FB = 0.8V OUT LTC2925 2.5V SLAVE2 RFA2 RFB2 41.2k 88.7k TRACK1 3.3V SD3 TRACK2 FB3 TRACK3 RTA3 100k RUN/SS IN DC/DC FB = 0.8V OUT 0.015Ω 1.5V SLAVE3 RFA3 RFB3 100k 86.6k SENSEP 2925 TA03a SENSEN GND SCTMR SDTMR CSCTMR 0.41µF PGTMR CSDTMR 0.082µF 2925 TA03b CPGTMR 0.82µF RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2900 Quad Voltage Monitor in MSOP and DFN 16 User Selectable Combinations, ±1.5% Threshold Accuracy LTC2901 Quad Voltage Monitor with Watchdog 16 User Selectable Combinations, Adjustable Timers LTC2902 Quad Voltage Monitor with Adjustable Reset 5%, 2.5%, 10% and 12.5% Selectable Supply Tolerances LTC2920 Power Supply Margining Controller Single or Dual, Symmetric/Asymmetric High and Low Margining LTC2921/LTC2922 Power Supply Tracker with Input Monitors Includes Three (LTC2921) or Five (LTC2922) Remote Sense Switches LTC2923 Power Supply Sequencing/Tracking Controller Controls Two Supplies Without FETs, MSOP-10 and DFN-12 Packages 2925f 20 Linear Technology Corporation LT/TP 0404 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2004