TI SN74HC14N

 SCLS085E − DECEMBER 1982 − REVISED NOVEMBER 2004
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 20-µA Max ICC
D Typical tpd = 11 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
SN54HC14 . . . J OR W PACKAGE
SN74HC14 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
1Y
1A
NC
VCC
6A
VCC
6A
6Y
5A
5Y
4A
4Y
2A
NC
2Y
NC
3A
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
6Y
NC
5A
NC
5Y
3Y
GND
NC
4Y
4A
1A
1Y
2A
2Y
3A
3Y
GND
SN54HC14 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
description/ordering information
These Schmitt-trigger devices contain six independent inverters. They perform the Boolean function
Y = A in positive logic.
ORDERING INFORMATION
PACKAGE†
TA
PDIP − N
SN74HC14N
Tube of 50
SN74HC14D
Reel of 2500
SN74HC14DR
Reel of 250
SN74HC14DT
SOP − NS
Reel of 2000
SN74HC14NSR
HC14
SSOP − DB
Reel of 2000
SN74HC14DBR
HC14
Tube of 90
SN74HC14PW
Reel of 2000
SN74HC14PWR
Reel of 250
SN74HC14PWT
CDIP − J
Tube
SNJ54HC14J
SNJ54HC14J
CFP − W
Tube
SNJ54HC14W
SNJ54HC14W
LCCC − FK
Tube
SNJ54HC14FK
TSSOP − PW
−55°C
−55
C to 125
125°C
C
TOP-SIDE
MARKING
Tube of 25
SOIC − D
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
SN74HC14N
HC14
HC14
SNJ54HC14FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
%(#"! "%' /0121 '' %$$! $ $!$(
#'$!! *$,!$ $() '' *$ %(#"! %(#"
%"$!!. ($! $"$!!'- "'#($ $!. '' %$$!)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS085E − DECEMBER 1982 − REVISED NOVEMBER 2004
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
L
H
logic diagram (positive logic)
A
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC14
SN74HC14
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
5
6
2
5
6
V
VCC
VI
Supply voltage
2
Input voltage
0
0
0
VCC
VCC
V
Output voltage
VCC
VCC
0
VO
TA
−55
125
−40
85
°C
Operating free-air temperature
V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS085E − DECEMBER 1982 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VT+
VT−
MIN
MAX
MAX
2V
0.7
1.2
1.5
0.7
1.5
0.7
1.5
4.5 V
1.55
2.5
3.15
1.55
3.15
1.55
3.15
6V
2.1
3.3
4.2
2.1
4.2
2.1
4.2
2V
0.3
0.6
1
0.3
1
0.3
1
4.5 V
0.9
1.6
2.45
0.9
2.45
0.9
2.45
6V
1.2
2
3.2
1.2
3.2
1.2
3.2
UNIT
V
V
0.6
1.2
0.2
1.2
0.2
1.2
0.4
0.9
2.1
0.4
2.1
0.4
2.1
6V
0.5
1.3
2.5
0.5
2.5
0.5
2.5
2V
1.9
1.998
1.9
1.9
IOH = −20 µA
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
IOH = −4 mA
IOH = −5.2 mA
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 µA
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
2
40
20
µA
10
10
10
pF
IOL = 4 mA
IOL = 5.2 mA
VI = VCC or 0
VI = VCC or 0,
SN74HC14
MIN
0.2
VI = VIH or VIL
II
ICC
SN54HC14
2V
VI = VIH or VIL
VOL
TA = 25°C
TYP
MAX
4.5 V
VT+ − VT−
VOH
MIN
IO = 0
6V
Ci
2 V to 6 V
3
V
V
V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
TYP
MAX
SN54HC14
SN74HC14
MIN
MIN
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
55
125
190
155
tpd
A
Y
4.5 V
12
25
38
31
6V
11
21
32
26
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
tt
Y
MAX
MAX
UNIT
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per inverter
POST OFFICE BOX 655303
No load
• DALLAS, TEXAS 75265
TYP
20
UNIT
pF
3
SCLS085E − DECEMBER 1982 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
Input
VCC
50%
50%
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
50%
10%
tPHL
90%
90%
tr
Input
50%
10%
90%
90%
tr
VCC
50%
10% 0 V
tPHL
Out-of-Phase
Output
90%
tf
VOH
50%
10%
VOL
tf
tPLH
50%
10%
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
5962-8409101VCA
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
5962-8409101VDA
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
84091012A
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
8409101CA
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
8409101DA
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
JM38510/65702BCA
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
JM38510/65702BDA
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
SN54HC14J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
SN74HC14D
ACTIVE
SOIC
D
14
50
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC14DBR
ACTIVE
SSOP
DB
14
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC14DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HC14DT
ACTIVE
SOIC
D
14
250
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC14N
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN74HC14N3
OBSOLETE
PDIP
N
14
None
Call TI
SN74HC14NS
ACTIVE
SO
NS
14
Pb-Free
(RoHS)
CU NIPDAU
Call TI
SN74HC14NSLE
OBSOLETE
SO
NS
14
None
Call TI
SN74HC14NSR
ACTIVE
SO
NS
14
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC14PW
ACTIVE
TSSOP
PW
14
90
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74HC14PWLE
OBSOLETE
TSSOP
PW
14
None
Call TI
SN74HC14PWR
ACTIVE
TSSOP
PW
14
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74HC14PWT
ACTIVE
TSSOP
PW
14
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SNJ54HC14FK
ACTIVE
LCCC
FK
20
1
None
Call TI
Level-NC-NC-NC
SNJ54HC14J
ACTIVE
CDIP
J
14
1
None
Call TI
Level-NC-NC-NC
SNJ54HC14W
ACTIVE
CFP
W
14
1
None
Call TI
Level-NC-NC-NC
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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