TI SN74HC4040N

 SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 12 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
QF
QL
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
QK
QJ
QH
QI
CLR
CLK
QA
QE
QG
NC
QD
QC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
QJ
QH
NC
QI
CLR
QB
GND
NC
QA
CLK
QL
QF
QE
QG
QD
QC
QB
GND
NC
VCC
QK
SN54HC4040 . . . FK PACKAGE
(TOP VIEW)
SN54HC4040 . . . J OR W PACKAGE
SN74HC4040 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
description/ordering information
The ’HC4040 devices are 12-stage asynchronous binary counters, with the outputs of all stages available
externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low.
The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay
circuits, counter controls, and frequency-dividing circuits.
ORDERING INFORMATION
TA
PACKAGE†
PDIP − N
TOP-SIDE
MARKING
SN74HC4040N
Tube of 40
SN74HC4040D
Reel of 2500
SN74HC4040DR
Reel of 250
SN74HC4040DT
SOP − NS
Reel of 2000
SN74HC4040NSR
HC4040
SSOP − DB
Reel of 2000
SN74HC4040DBR
HC4040
Tube of 90
SN74HC4040PW
Reel of 2000
SN74HC4040PWR
Reel of 250
SN74HC4040PWT
CDIP − J
Tube of 25
SNJ54HC4040J
SNJ54HC4040J
CFP − W
Tube of 150
SNJ54HC4040W
SNJ54HC4040W
LCCC − FK
Tube of 55
SNJ54HC4040FK
TSSOP − PW
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
Tube of 25
SOIC − D
−40°C
−40
C to 85
85°C
C
PACKAGE†
SN74HC4040N
HC4040
HC4040
SNJ54HC4040FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
%(#"! "%' /01232 '' %$$! $ $!$(
#'$!! *$,!$ $() '' *$ %(#"! %(#"
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1
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
FUNCTION TABLE
(each buffer)
INPUTS
FUNCTION
CLK
CLR
↑
L
No change
↓
L
Advance to next stage
X
H
All outputs L
logic diagram (positive logic)
CLR
11
R
CLK
10
R
T
R
R
T
T
4
QF
QG
T
R
T
T
7
6
5
3
QA
QB
QC
QD
QE
R
T
2
R
9
R
T
R
R
T
13
QH
R
T
12
QI
R
T
14
QJ
T
15
QK
1
QL
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC4040
VCC
Supply voltage
VIH
VCC = 2 V
VCC = 4.5 V
High-level input voltage
VCC = 6 V
VCC = 2 V
VIL
VI
VO
Input voltage
NOM
MAX
2
5
6
NOM
MAX
2
5
6
1.5
3.15
3.15
4.2
4.2
0
VCC = 6 V
UNIT
V
V
0.5
0.5
1.35
1.35
1.8
1.8
VCC
VCC
VCC = 2 V
VCC = 4.5 V
Input transition rise/fall time
MIN
1.5
0
Output voltage
∆t/∆v†
MIN
VCC = 4.5 V
VCC = 6 V
Low-level input voltage
SN74HC4040
0
VCC
VCC
0
1000
1000
500
500
400
400
V
V
V
ns
TA
Operating free-air temperature
−55
125
−40
85
°C
† If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −20 µA
VOH
VI = VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
IOL = 20 µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
Ci
VI = VCC or 0
VI = VCC or 0,
IO = 0
TA = 25°C
TYP
MAX
SN54HC4040
SN74HC4040
VCC
MIN
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
MIN
MAX
5.2
MIN
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
µA
10
10
10
pF
6V
2 V to 6 V
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V
3
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
CLK high or low
tw
Pulse duration
CLR high
tsu
Setup time, CLR inactive before CLK↓
TA = 25°C
MIN
MAX
SN54HC4040
MIN
MAX
SN74HC4040
MIN
MAX
2V
5.5
3.7
4.3
4.5 V
28
19
22
6V
33
22
25
2V
90
135
115
4.5 V
18
27
23
6V
15
23
20
2V
70
105
90
4.5 V
14
21
18
6V
12
18
15
2V
60
90
75
4.5 V
12
18
15
6V
10
15
13
UNIT
MHz
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
tPHL
CLR
tt
QA
Any
Any
VCC
TA = 25°C
MIN
TYP
MAX
SN54HC4040
MIN
MAX
SN74HC4040
MIN
2V
5.5
10
3.7
4.3
4.5 V
28
45
19
22
6V
33
53
22
25
MAX
UNIT
MHz
2V
62
150
225
190
4.5 V
16
30
45
38
6V
12
26
38
32
2V
63
140
210
175
4.5 V
17
28
42
35
6V
13
24
36
30
2V
28
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
TEST CONDITIONS
Power dissipation capacitance
No load
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
88
UNIT
pF
SCLS160D − DECEMBER 1982 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
VCC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL = 50 pF
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
VCC
50%
50%
0V
tPLH
Reference
Input
VCC
50%
In-Phase
Output
50%
10%
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
90%
90%
tr
th
90%
tPHL
Out-of-Phase
Output
90%
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
tPLH
50%
10%
tf
tf
VOH
50%
10%
VOL
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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5
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
85004012A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
8500401EA
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
8500401FA
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
SN54HC4040J
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SN74HC4040D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
SN74HC4040DBLE
OBSOLETE
SSOP
DB
16
TBD
Call TI
SN74HC4040DBR
ACTIVE
SSOP
DB
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC4040DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC4040DT
ACTIVE
SOIC
D
16
250
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC4040DWR
OBSOLETE
SOIC
DW
16
TBD
Call TI
SN74HC4040N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Call TI
Call TI
Level-NC-NC-NC
SN74HC4040N3
OBSOLETE
PDIP
N
16
TBD
Call TI
SN74HC4040NSR
ACTIVE
SO
NS
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Call TI
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74HC4040PW
ACTIVE
TSSOP
PW
16
90
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74HC4040PWLE
OBSOLETE
TSSOP
PW
16
TBD
Call TI
SN74HC4040PWR
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SN74HC4040PWT
ACTIVE
TSSOP
PW
16
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
SNJ54HC4040FK
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Level-NC-NC-NC
SNJ54HC4040J
ACTIVE
CDIP
J
16
1
TBD
Call TI
Level-NC-NC-NC
SNJ54HC4040W
ACTIVE
CFP
W
16
1
TBD
Call TI
Level-NC-NC-NC
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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