UCC5630A Multimode SCSI 9 Line Terminator FEATURES DESCRIPTION • Auto Selection Single Ended (SE) or Low Voltage Differential (LVD) Termination The UCC5630A Multimode SCSI Terminator provides a smooth transition into the LVD SCSI Parallel Interface (SPI-2, SPI-3, SPI-4). It automatically senses the bus, via DIFFB, and switches the termination to either single ended (SE) or low voltage differential (LVD) SCSI, dependent on which type of devices are connected to the bus. The UCC5630A can not be used on a HVD, EIA485, differential SCSI bus. If the UCC5630A detects a HVD SCSI device, it switches to a high impedance state. • Meets SCSI-1, SCSI-2, Ultra2 (SPI-2 LVD), Ultra3, Ultra160 (SPI-3) and Ultra320 (SPI-4) Standards • 2.7V to 5.25V Operation The Multimode terminator contains all functions required to terminate and auto detect and switch modes for SPI-2, SPI-3 and SPI-4 bus architectures. Single Ended and Differential impedances and currents are trimmed for maximum effectiveness. Fail Safe biasing is provided to insure signal integrity. Device/Bus type detection circuitry is integrated into the terminator to provide automatic switching of termination between single ended and LVD SCSI and a high impedance for HVD SCSI. The multimode function provides all the performance analog functions necessary to implement SPI-2 termination in a single monolithic device. • Differential Failsafe Bias • Thermal packaging for low junction temperature and better MTBF • Master/Slave Input • Supports Active Negation • 3pF Channel Capacitance The UCC5630A is offered in a 36 pin SSOP package, as well as a 48 pin LQFP package for a temperature range of 0°C to 70°C. BLOCK DIAGRAM HIPD LVD SE 35 34 33 (NOISE LOAD) HIPD 2.15V DIFFB 20 DIFSENS 5 L1– 4 L1+ 32 L9– 31 L9+ LVD 0.6V MSTR/SLV 1.3V REF 1.3V 21 –15mA ≤ ISOURCE ≤ –5mA 50µA ≤ ISINK ≤ 200µA SE 19 110 SOURCE/SINK REGULATOR SE REF 2.7V 124 56mV 52.5 – + LVD REF 1.25V 56mV 52.5 + – MODE ALL SWITCHES SE UP 10µA ENABLE SWITCHES DISCNCT 17 LVD DOWN HIPD OPEN DISCNCT OPEN SE GND SWITCH 110 124 56mV 52.5 – + 56mV 52.5 + – TRMPWR 36 SE GND SWITCH 18 GND 8 9 10 26 27 28 HS/GND 1 REG Note: Indicated pinout is for 36 pin SSOP package. SLUS322C - SEPTEMBER 1999 - REVISED MARCH 2002 PATENTED CIRCUIT DESIGN UDG-98192 UCC5630A ABSOLUTE MAXIMUM RATINGS TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to TRMPWR Package Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 2W Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C AVAILABLE OPTIONS TA 0 C to 70°C Packaged Devices UCC5630AMWP UCC5630AFQP All voltages are with respect to pin 18. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Databook for thermal limitations and considerations of packages. CONNECTION DIAGRAM RECOMMENDED OPERATING CONDITIONS TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V QSOP-36 (Top View) MWP Package LQFP-48 (Top View) FQP Package HS/GND HS/GND L4– L4+ L3– L3+ NC HS/GND L5+ L5– DISCNCT GND 48 47 46 40 39 38 1 37 36 L2– DIFSENS 2 35 L2+ DIFFB 3 34 L1– 45 44 43 42 MSTR/SLV 41 N/C 4 33 L1+ HS/GND 5 32 HS/GND HS/GND 6 31 HS/GND HS/GND 7 30 HS/GND HS/GND 8 29 HS/GND L6+ 9 28 NC L6– 10 27 NC L7+ 11 26 REG L7– 12 13 14 25 NC L8+ L8– 15 16 17 18 19 20 21 22 23 24 NC TERMPWR L9+ L9– HS/GND HIPD LVD HS/GND HS/GND SE 2 TRMPWR REG 1 36 N/C 2 35 HIPD N/C 3 34 LVD L1+ 4 33 SE L1– 5 32 L9– L2+ 6 31 L9+ L2– 7 30 L8– HS/GND 8 29 L8+ HS/GND 9 28 HS/GND HS/GND 10 27 HS/GND L3+ 11 26 HS/GND L3– 12 25 L7– L4+ 13 24 L7+ L4– 14 23 L6– L5+ 15 22 L6+ L5– 16 21 DIFF B DISCNCT 17 20 DIFSENS GND 18 19 MSTR/SLV UCC5630A ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = 0°C to 70°C, TRMPWR = 2.7V to 5.25V. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TRMPWR Supply Current Section TRMPWR Supply Current LVD Mode (No Load) 13 20 mA SE Mode (No Load) 1.6 10 mA Disabled 250 400 A 1.25 1.35 V Regulator Section REG Output Voltage (LVD Mode) 0.5V ≤ VCM ≤ 2.0V (Note1) 1.15 REG Output Voltage (SE Mode) 0V ≤ VL– ≤ 4.2V (Note2) 2.5 2.7 3.0 V REG Short-Circuit Source Current (LVD and SE Modes) VREG= 0V –800 –420 –225 mA REG Short-Circuit Sink Current (LVD and SE Modes) VREG= 3.0V 100 180 800 mA –5mA ≤ IDIFSENS ≤ 50µA 1.2 1.3 1.4 V Short-Circuit Source Current VDIFSENS = 0V –15 –8 –5 mA Short-Circuit Sink Current VDIFSENS = 2.75V 50 80 200 µA 100 105 110 110 140 DIFSENS Output Section Output Voltage Differential Termination Section (Applies to each line pair, 1-9, in LVD mode) Differential Impedance Common Mode Impedance L+ and L– shorted together. (Note 3) Differential Bias Voltage 100 Common Mode Bias Voltage L+ and L– shorted together. Output Capacitance Single ended measurement to ground. (Note 4) 1.15 1.25 165 125 mV 1.35 V 3 pF Single Ended Termination Section (Applies to each line pair, 1-9, in SE mode) Impedance (Note 5) 102.3 Termination Current Signal Level 0.2V –25.4 –21 mA Signal Level 0.5V –22.4 –18 mA 3 pF Output Capacitance Single ended measurement to ground. (Note 4) Single Ended GND Switch Impedance I = 10mA 110 20 117.7 60 Disconnected Termination Section (Applies to each line pair, 1-9, in DISCNCT or HIPD mode) Output Leakage Output Capacitance Single ended measurement to ground. (Note 4) 400 nA 3 pF 2.0 V DISCNCT and DIFFB Input Section DISCNCT Threshold DISCNCT Input Current 0.8 VDISCNCT = 0V –30 DIFFB Single Ended to LVD Threshold DIFFB LVD to HIPD Threshold DIFFB Input Current 0V ≤ VDIFFB ≤ 2.75V 3 –3 A 0.5 –10 0.7 V 1.9 2.4 V –1 1 A UCC5630A ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = 0°C to 70°C, TRMPWR = 2.7V to 5.25V. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Master/Slave (MSTR/SLV) Input Section MSTR/SLV Threshold VTRMPWR = 2.7V 0.8 1.9 V VTRMPWR = 3.3V 1 2.4 V VTRMPWR = 5.25V 1.5 3.7 V –1 1 A MSTR/SLV Input Current Status Bits (SE, LVD, HIPD) Output Section ISOURCE VLOAD = 2.4V ISINK VLOAD = 0.5V 3 –8.7 6 –4 mA mA VLOAD = 0.4V 2 5 mA Note 1: VCM is applied to all L+ and L– lines simultaneously. Note 2: VL– is applied to all L– lines simultaneously. Note 3: Z CM = (2 . 0V − 0. 5V ) I ( at V CM = 2V )− I ( at V CM = 0 . 5V ) ; Note 4: Ensured by design. Not 100% tested in production. Note 5: Z = (V ( L X) − 0 . 2V I L( X ) ); where VL(X)= Output voltage for each terminator minus output pin (L1– through L9–) with each pin unloaded. IL(X )= Output current for each terminator minus output pin (L1– through L9–) with the minus output pin forced to 0.2V. PIN DESCRIPTIONS DIFFB: Input pin for the comparators that select SE, LVD, or HIPD modes of operation. This pin should be decoupled with a 4.7 F capacitor to ground and then coupled to the DIFSENS pin through a 50k resistor. L1– thru L9–: Termination lines. These are the active lines in SE mode and are the negative lines for LVD mode. In HIPD mode, these lines are high impedance. L1+ thru L9+: Termination lines. These lines switch to ground in SE mode and are the positive lines for LVD mode. In HIPD mode, these lines are high impedance. DIFSENS: Connects to the Diff Sense line of the SCSI bus. The bus mode is controlled by the voltage level on this pin. MSTR/SLV: If the terminator is enabled, this input pin enables / disables the DIFSENS driver, when connected to TRMPWR or ground respectively. When the terminator is disabled, the DIFSENS driver is off, independent of this input. DISCNCT: Input pin used to shut down the terminator if the terminator is not connected at the end of the bus. Connect this pin to ground to activate the terminator or open pin to disable the terminator. LVD: TTL compatible status bit. This output pin is high when the SCSI bus is in LVD mode. HIPD: TTL compatible status bit. This output pin is high when a high voltage differential device is detected on the bus. REG: Regulator output bypass pin. This pin must be connected to a 4.7 F capacitor to ground. HS/GND: Heat sink ground pins. These should be connected to large area PC board traces to increase the power dissipation capability. SE: TTL compatible status bit. This output pin is high when the SCSI bus is in SE mode. GND: Power Supply return. TRMPWR: 2.7V to 5.25V power input pin, bypass near the terminators with a 4.7 F capacitor to ground. 4 UCC5630A APPLICATION INFORMATION TERMPWR 36 TERMPWR TERMPWR 36 CONTROL LINES 19 MSTR/SLV 17 DISCNCT DIFSENS 20 20 DIFSENS DIFFB DIFF B REG 1 21 21 1 50k 50k 4.7µF . 4.7µF . 36 TERMPWR 4.7µF TERMPWR 36 DATA LINES (9) 19 MSTR/SLV 4.7µF . DISCNCT 17 REG 4.7µF . TERMPWR CONTROL LINES MSTR/SLV 19 17 DISCNCT DATA LINES (9) MSTR/SLV 19 NC 20 20 NC DISCNCT 17 REG DIFF B DIFFB REG 1 21 21 1 4.7µF . 4.7µF . 4.7µF 36 TERMPWR TERMPWR 36 DATA LINES (9) 19 MSTR/SLV 17 DISCNCT DATA LINES (9) MSTR/SLV 19 NC 20 20 NC DISCNCT 17 REG DIFFB DIFFB REG 1 21 21 1 4.7µF . 4.7µF UDG-98193 Figure 2. Application diagram. All SCSI buses require a termination network at each end to function properly. Specific termination requirements differ, depending on which types of SCSI devices are present on the bus. The SCSI bus DIFSENS signal line is used to identify which types of SCSI devices are present on the bus. On power-up, the UCC5630A DIFSENS drivers will try to deliver 1.3V to the DIFSENS line. If only LVD devices are present, the DIFSENS line will be successfully driven to 1.3V and the terminators will configure for LVD operation. If any single ended devices are present, they will present a short to ground on the DIFSENS line, signaling the UCC5630A(s) to configure into the SE mode, accommodating the SE devices. Or, if any high voltage differential (HVD) devices are present, the DIFSENS line is pulled high and the terminator will enter a high impedance state, effectively disconnecting from the bus. The UCC5630A is used in multi-mode active termination applications, where single ended (SE) and low voltage differential (LVD) devices might coexist. The UCC5630A has both SE and LVD termination networks integrated into a single monolithic component. The correct termination network is automatically determined by the SCSI bus "DIFSENS" signal. 5 UCC5630A APPLICATION INFORMATION (cont.) The DIFSENS line is monitored by each terminator through a 100ms to 300ms noise filter at the DIFFB input pin. A set of comparators detect and select the appropriate termination for the bus as follows. If the DIFSENS signal is below 0.5V, the termination network is SE. Between 0.7V and 1.9V, the termination network switches to LVD, and above 2.4V is HVD, causing the terminators to disconnect from the bus. The thresholds accommodate differences in ground potential that can occur with long lines. negative signal lines of each pair to ground. An additional requirement is a maximum difference of 2pF when comparing pair to pair. These requirements apply to differential bus termination circuitry that is not part of a SCSI device. If the termination circuitry is included as part of a device, then the corresponding balance requirements are 2.25pF maximum difference within a pair, and 3pF from pair to pair. Feed-throughs, through-hole connections, and etch lengths need to be carefully balanced. Standard multi-layer power and ground plane spacing add about 1pF to each plane. Each feed-through will add about 2.5pF to 3.5pF. Enlarging the clearance holes on both power and ground planes will reduce the capacitance. Similarly, opening up the power and ground planes under the connector will reduce the capacitance for through-hole connector applications. Capacitance will also be affected by components, in close proximity, above and below the circuit board. Three UCC5630A multi-mode parts are required at each end of the bus to terminate 27 (18 data, plus 9 control) lines. Each part includes a DIFSENS driver, but only one is necessary to drive the line. A MSTR/SLV input pin is provided to disable the other two. The "master" part must have its' MSTR/SLV pin connected to TRMPWR and the two "slave" parts must have the MSTR/SLV inputs grounded. Only the "master" is connected directly to the SCSI bus DIFSENS line. The DIFFB inputs on all three parts are connected together, allowing them to share the same 50Hz noise filter. This multi-mode terminator operates in full specification down to 2.7V TRMPWR voltage. This accommodates 3.3V systems, with allowance for the 3.3V supply tolerance (+/- 10%), a unidirectional fusing device and cable drop. In 3.3V TRMPWR systems, the UCC3912 is recommended in place of the fuse and diode. The UCC3912's lower voltage drop allows additional margin over the fuse and diode, for the far end terminator. Unitrode multi-mode terminators are designed with very tight balance, typically 0.1pF between pins in a pair and 0.3pF between pairs. At each L+ pin, a ground driver drives the pin to ground, while in single ended mode. The ground driver is specially designed to not effect the capacitive balance of the bus when the device is in LVD or disconnect mode. Multi-layer boards need to adhere to the 120 impedance standard, including the connectors and feedthroughs. This is normally done on the outer layers with 4 mil etch and 4 mil spacing between runs within a pair, and a minimum of 8 mil spacing to the adjacent pairs to reduce crosstalk. Microstrip technology is normally too low of impedance and should not be used. It is designed for 50 rather than 120 differential systems. Careful consideration must be given to the issue of heat management. A multi-mode terminator, operating in SE mode, will dissipate as much as 130mW of instantaneous power per active line with TRMPWR = 5.25V. The UCC5630A is offered in a 36 pin SSOP and a 48 lead LFQP. Both packages include heat sink ground pins. These heat sink/ground pins are directly connected to the die mount paddle under the die and conduct heat from the die to reduce the junction temperature. All of the HS/GND pins need to be connected to etch area or a feed-through per pin connecting to the ground plane layer on a multi-layer board. Layout is critical for Ultra2, Ultra3, Ultra160 and Ultra320 systems. The SPI-2 standard for capacitance loading is 10pF maximum from each positive and negative signal line to ground, and a maximum of 5pF between the positive and negative signal lines of each pair is allowed. These maximum capacitances apply to differential bus termination circuitry that is not part of a SCSI device, (e.g. a cable terminator). If the termination circuitry is included as part of a SCSI device, (e.g., a host adaptor, disk or tape drive), then the corresponding requirements are 30pF maximum from each positive and negative signal line to ground and 15pF maximum between the positive and negative signal lines of each pair. The SPI-2 standard for capacitance balance of each pair and balance between pairs is more stringent. The standard is 0.75pF maximum difference from the positive and 6 PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UCC5630AFQP ACTIVE LQFP PT 48 250 None CU SNPB Level-1-220C-UNLIM UCC5630AFQPTR ACTIVE LQFP PT 48 1000 None CU SNPB Level-1-220C-UNLIM 25 Level-1-220C-UNLIM Lead/Ball Finish MSL Peak Temp (3) UCC5630AMWP ACTIVE SSOP DCE 36 None CU SNPB UCC5630AMWP/81535 OBSOLETE SSOP DCE 36 None Call TI Call TI UCC5630AMWPR/81535 OBSOLETE SSOP DCE 36 None Call TI Call TI UCC5630AMWPTR ACTIVE SSOP DCE 36 1000 UCC5630AMWPTRG4 ACTIVE SSOP DCE 36 1000 Green (RoHS & no Sb/Br) None CU SNPB Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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